include/configs/PK1C20.h

   1 /*
   2  * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
   3  * Scott McNutt <smcnutt@psyent.com>
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #ifndef __CONFIG_H
  25 #define __CONFIG_H
  26
  27 /*------------------------------------------------------------------------
  28  * BOARD/CPU
  29  *----------------------------------------------------------------------*/
  30 #define CONFIG_PK1C20           1               /* PK1C20 board         */
  31 #define CONFIG_SYS_CLK_FREQ     50000000        /* 50 MHz core clk      */
  32
  33 #define CFG_RESET_ADDR          0x00000000      /* Hard-reset address   */
  34 #define CFG_EXCEPTION_ADDR      0x01000020      /* Exception entry point*/
  35 #define CFG_NIOS_SYSID_BASE     0x021208b8      /* System id address    */
  36 #define CONFIG_BOARD_EARLY_INIT_F 1     /* enable early board-spec. init*/
  37
  38 /*------------------------------------------------------------------------
  39  * CACHE -- the following will support II/s and II/f. The II/s does not
  40  * have dcache, so the cache instructions will behave as NOPs.
  41  *----------------------------------------------------------------------*/
  42 #define CFG_ICACHE_SIZE         4096            /* 4 KByte total        */
  43 #define CFG_ICACHELINE_SIZE     32              /* 32 bytes/line        */
  44 #define CFG_DCACHE_SIZE         2048            /* 2 KByte (II/f)       */
  45 #define CFG_DCACHELINE_SIZE     4               /* 4 bytes/line (II/f)  */
  46
  47 /*------------------------------------------------------------------------
  48  * MEMORY BASE ADDRESSES
  49  *----------------------------------------------------------------------*/
  50 #define CFG_FLASH_BASE          0x00000000      /* FLASH base addr      */
  51 #define CFG_FLASH_SIZE          0x00800000      /* 8 MByte              */
  52 #define CFG_SDRAM_BASE          0x01000000      /* SDRAM base addr      */
  53 #define CFG_SDRAM_SIZE          0x01000000      /* 16 MByte             */
  54 #define CFG_SRAM_BASE           0x02000000      /* SRAM base addr       */
  55 #define CFG_SRAM_SIZE           0x00100000      /* 1 MB (only 1M mapped)*/
  56
  57 /*------------------------------------------------------------------------
  58  * MEMORY ORGANIZATION
  59  *      -Monitor at top.
  60  *      -The heap is placed below the monitor.
  61  *      -Global data is placed below the heap.
  62  *      -The stack is placed below global data (&grows down).
  63  *----------------------------------------------------------------------*/
  64 #define CFG_MONITOR_LEN         (256 * 1024)    /* Reserve 128k         */
  65 #define CFG_GBL_DATA_SIZE       128             /* Global data size rsvd*/
  66 #define CFG_MALLOC_LEN          (CFG_ENV_SIZE + 128*1024)
  67
  68 #define CFG_MONITOR_BASE        TEXT_BASE
  69 #define CFG_MALLOC_BASE         (CFG_MONITOR_BASE - CFG_MALLOC_LEN)
  70 #define CFG_GBL_DATA_OFFSET     (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
  71 #define CFG_INIT_SP             CFG_GBL_DATA_OFFSET
  72
  73 /*------------------------------------------------------------------------
  74  * FLASH (AM29LV065D)
  75  *----------------------------------------------------------------------*/
  76 #define CFG_MAX_FLASH_SECT      128             /* Max # sects per bank */
  77 #define CFG_MAX_FLASH_BANKS     1               /* Max # of flash banks */
  78 #define CFG_FLASH_ERASE_TOUT    8000            /* Erase timeout (msec) */
  79 #define CFG_FLASH_WRITE_TOUT    100             /* Write timeout (msec) */
  80 #define CFG_FLASH_WORD_SIZE     unsigned char   /* flash word size      */
  81
  82 /*------------------------------------------------------------------------
  83  * ENVIRONMENT -- Put environment in sector CFG_MONITOR_LEN above
  84  * CFG_RESET_ADDR, since we assume the monitor is stored at the
  85  * reset address, no? This will keep the environment in user region
  86  * of flash. NOTE: the monitor length must be multiple of sector size
  87  * (which is common practice).
  88  *----------------------------------------------------------------------*/
  89 #define CFG_ENV_IS_IN_FLASH     1               /* Environment in flash */
  90 #define CFG_ENV_SIZE            (64 * 1024)     /* 64 KByte (1 sector)  */
  91 #define CONFIG_ENV_OVERWRITE                    /* Serial change Ok     */
  92 #define CFG_ENV_ADDR    (CFG_RESET_ADDR + CFG_MONITOR_LEN)
  93
  94 /*------------------------------------------------------------------------
  95  * CONSOLE
  96  *----------------------------------------------------------------------*/
  97 #if defined(CONFIG_CONSOLE_JTAG)
  98 #define CFG_NIOS_CONSOLE        0x021208b0      /* JTAG UART base addr  */
  99 #else
 100 #define CFG_NIOS_CONSOLE        0x02120840      /* UART base addr       */
 101 #endif
 102
 103 #define CFG_NIOS_FIXEDBAUD      1               /* Baudrate is fixed    */
 104 #define CONFIG_BAUDRATE         115200          /* Initial baudrate     */
 105 #define CFG_BAUDRATE_TABLE      {115200}        /* It's fixed ;-)       */
 106
 107 #define CFG_CONSOLE_INFO_QUIET  1               /* Suppress console info*/
 108
 109 /*------------------------------------------------------------------------
 110  * EPCS Device -- wne CFG_NIOS_EPCSBASE is defined code/commands for
 111  * epcs device access is enabled. The base address is the epcs
 112  * _register_ base address, NOT THE ADDRESS OF THE MEMORY BLOCK.
 113  * The register base is currently at offset 0x600 from the memory base.
 114  *----------------------------------------------------------------------*/
 115 #define CFG_NIOS_EPCSBASE       0x02100200      /* EPCS register base   */
 116
 117 /*------------------------------------------------------------------------
 118  * DEBUG
 119  *----------------------------------------------------------------------*/
 120 #undef CONFIG_ROM_STUBS                         /* Stubs not in ROM     */
 121
 122 /*------------------------------------------------------------------------
 123  * TIMEBASE --
 124  *
 125  * The high res timer defaults to 1 msec. Since it includes the period
 126  * registers, we can slow it down to 10 msec using TMRCNT. If the default
 127  * period is acceptable, TMRCNT can be left undefined.
 128  *----------------------------------------------------------------------*/
 129 #define CFG_NIOS_TMRBASE        0x02120820      /* Tick timer base addr */
 130 #define CFG_NIOS_TMRIRQ         3               /* Timer IRQ num        */
 131 #define CFG_NIOS_TMRMS          10              /* 10 msec per tick     */
 132 #define CFG_NIOS_TMRCNT (CFG_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000))
 133 #define CFG_HZ          (CONFIG_SYS_CLK_FREQ/(CFG_NIOS_TMRCNT + 1))
 134
 135 /*------------------------------------------------------------------------
 136  * STATUS LED -- Provides a simple blinking led. For Nios2 each board
 137  * must implement its own led routines -- leds are, after all,
 138  * board-specific, no?
 139  *----------------------------------------------------------------------*/
 140 #define CFG_LEDPIO_ADDR         0x02120870      /* LED PIO base addr    */
 141 #define CONFIG_STATUS_LED                       /* Enable status driver */
 142
 143 #define STATUS_LED_BIT          1               /* Bit-0 on PIO         */
 144 #define STATUS_LED_STATE        1               /* Blinking             */
 145 #define STATUS_LED_PERIOD       (500/CFG_NIOS_TMRMS) /* Every 500 msec  */
 146
 147 /*------------------------------------------------------------------------
 148  * ETHERNET -- The header file for the SMC91111 driver hurts my eyes ...
 149  * and really doesn't need any additional clutter. So I choose the lazy
 150  * way out to avoid changes there -- define the base address to ensure
 151  * cache bypass so there's no need to monkey with inx/outx macros.
 152  *----------------------------------------------------------------------*/
 153 #define CONFIG_SMC91111_BASE    0x82110300      /* Base addr (bypass)   */
 154 #define CONFIG_DRIVER_SMC91111                  /* Using SMC91c111      */
 155 #undef  CONFIG_SMC91111_EXT_PHY                 /* Internal PHY         */
 156 #define CONFIG_SMC_USE_32_BIT                   /* 32-bit interface     */
 157
 158 #define CONFIG_ETHADDR          08:00:3e:26:0a:5b
 159 #define CONFIG_NETMASK          255.255.255.0
 160 #define CONFIG_IPADDR           192.168.2.21
 161 #define CONFIG_SERVERIP         192.168.2.16
 162
 163
 164 /*
 165  * BOOTP options
 166  */
 167 #define CONFIG_BOOTP_BOOTFILESIZE
 168 #define CONFIG_BOOTP_BOOTPATH
 169 #define CONFIG_BOOTP_GATEWAY
 170 #define CONFIG_BOOTP_HOSTNAME
 171
 172
 173 /*
 174  * Command line configuration.
 175  */
 176
 177 #define CONFIG_CMD_BDI
 178 #define CONFIG_CMD_DHCP
 179 #define CONFIG_CMD_ECHO
 180 #define CONFIG_CMD_ENV
 181 #define CONFIG_CMD_FLASH
 182 #define CONFIG_CMD_IMI
 183 #define CONFIG_CMD_IRQ
 184 #define CONFIG_CMD_LOADS
 185 #define CONFIG_CMD_LOADB
 186 #define CONFIG_CMD_MEMORY
 187 #define CONFIG_CMD_MISC
 188 #define CONFIG_CMD_NET
 189 #define CONFIG_CMD_PING
 190 #define CONFIG_CMD_RUN
 191 #define CONFIG_CMD_SAVES
 192
 193
 194 /*------------------------------------------------------------------------
 195  * COMPACT FLASH
 196  *----------------------------------------------------------------------*/
 197 #if defined(CONFIG_CMD_IDE)
 198 #define CONFIG_IDE_PREINIT                      /* Implement id_preinit */
 199 #define CFG_IDE_MAXBUS          1               /* 1 IDE bus            */
 200 #define CFG_IDE_MAXDEVICE       1               /* 1 drive per IDE bus  */
 201
 202 #define CFG_ATA_BASE_ADDR       0x00900800      /* ATA base addr        */
 203 #define CFG_ATA_IDE0_OFFSET     0x0000          /* IDE0 offset          */
 204 #define CFG_ATA_DATA_OFFSET     0x0040          /* Data IO offset       */
 205 #define CFG_ATA_REG_OFFSET      0x0040          /* Register offset      */
 206 #define CFG_ATA_ALT_OFFSET      0x0100          /* Alternate reg offset */
 207 #define CFG_ATA_STRIDE          4               /* Width betwix addrs   */
 208 #define CONFIG_DOS_PARTITION
 209
 210 /* Board-specific cf regs */
 211 #define CFG_CF_PRESENT          0x00900880      /* CF Present PIO base  */
 212 #define CFG_CF_POWER            0x00900890      /* CF Power FET PIO base*/
 213 #define CFG_CF_ATASEL           0x009008a0      /* CF ATASEL PIO base   */
 214
 215 #endif
 216
 217 /*------------------------------------------------------------------------
 218  * JFFS2
 219  *----------------------------------------------------------------------*/
 220 #if defined(CONFIG_CMD_JFFS2)
 221 #define CFG_JFFS_CUSTOM_PART                    /* board defined part   */
 222 #endif
 223
 224 /*------------------------------------------------------------------------
 225  * MISC
 226  *----------------------------------------------------------------------*/
 227 #define CFG_LONGHELP                            /* Provide extended help*/
 228 #define CFG_PROMPT              "==> "          /* Command prompt       */
 229 #define CFG_CBSIZE              256             /* Console I/O buf size */
 230 #define CFG_MAXARGS             16              /* Max command args     */
 231 #define CFG_BARGSIZE            CFG_CBSIZE      /* Boot arg buf size    */
 232 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print buf size */
 233 #define CFG_LOAD_ADDR           CFG_SDRAM_BASE  /* Default load address */
 234 #define CFG_MEMTEST_START       CFG_SDRAM_BASE  /* Start addr for test  */
 235 #define CFG_MEMTEST_END         CFG_INIT_SP - 0x00020000
 236
 237 #define CFG_HUSH_PARSER
 238 #define CFG_PROMPT_HUSH_PS2     "> "
 239
 240 #endif  /* __CONFIG_H */