include/configs/PCI5441.h

   1 /*
   2  * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
   3  * Scott McNutt <smcnutt@psyent.com>
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #ifndef __CONFIG_H
  25 #define __CONFIG_H
  26
  27 /*------------------------------------------------------------------------
  28  * BOARD/CPU
  29  *----------------------------------------------------------------------*/
  30 #define CONFIG_PCI5441          1               /* PCI-5441 board       */
  31 #define CONFIG_SYS_CLK_FREQ     50000000        /* 50 MHz core clk      */
  32
  33 #define CFG_RESET_ADDR          0x00000000      /* Hard-reset address   */
  34 #define CFG_EXCEPTION_ADDR      0x01000020      /* Exception entry point*/
  35 #define CFG_NIOS_SYSID_BASE     0x00920828      /* System id address    */
  36 #define CONFIG_BOARD_EARLY_INIT_F 1     /* enable early board-spec. init*/
  37
  38 /*------------------------------------------------------------------------
  39  * CACHE -- the following will support II/s and II/f. The II/s does not
  40  * have dcache, so the cache instructions will behave as NOPs.
  41  *----------------------------------------------------------------------*/
  42 #define CFG_ICACHE_SIZE         4096            /* 4 KByte total        */
  43 #define CFG_ICACHELINE_SIZE     32              /* 32 bytes/line        */
  44 #define CFG_DCACHE_SIZE         2048            /* 2 KByte (II/f)       */
  45 #define CFG_DCACHELINE_SIZE     4               /* 4 bytes/line (II/f)  */
  46
  47 /*------------------------------------------------------------------------
  48  * MEMORY BASE ADDRESSES
  49  *----------------------------------------------------------------------*/
  50 #define CFG_FLASH_BASE          0x00000000      /* FLASH base addr      */
  51 #define CFG_FLASH_SIZE          0x00800000      /* 8 MByte              */
  52 #define CFG_SDRAM_BASE          0x01000000      /* SDRAM base addr      */
  53 #define CFG_SDRAM_SIZE          0x01000000      /* 16 MByte             */
  54
  55 /*------------------------------------------------------------------------
  56  * MEMORY ORGANIZATION
  57  *      -Monitor at top.
  58  *      -The heap is placed below the monitor.
  59  *      -Global data is placed below the heap.
  60  *      -The stack is placed below global data (&grows down).
  61  *----------------------------------------------------------------------*/
  62 #define CFG_MONITOR_LEN         (128 * 1024)    /* Reserve 128k         */
  63 #define CFG_GBL_DATA_SIZE       128             /* Global data size rsvd*/
  64 #define CFG_MALLOC_LEN          (CFG_ENV_SIZE + 128*1024)
  65
  66 #define CFG_MONITOR_BASE        TEXT_BASE
  67 #define CFG_MALLOC_BASE         (CFG_MONITOR_BASE - CFG_MALLOC_LEN)
  68 #define CFG_GBL_DATA_OFFSET     (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
  69 #define CFG_INIT_SP             CFG_GBL_DATA_OFFSET
  70
  71 /*------------------------------------------------------------------------
  72  * FLASH (AM29LV065D)
  73  *----------------------------------------------------------------------*/
  74 #define CFG_MAX_FLASH_SECT      128             /* Max # sects per bank */
  75 #define CFG_MAX_FLASH_BANKS     1               /* Max # of flash banks */
  76 #define CFG_FLASH_ERASE_TOUT    8000            /* Erase timeout (msec) */
  77 #define CFG_FLASH_WRITE_TOUT    100             /* Write timeout (msec) */
  78 #define CFG_FLASH_WORD_SIZE     unsigned char   /* flash word size      */
  79
  80 /*------------------------------------------------------------------------
  81  * ENVIRONMENT -- Put environment in sector CFG_MONITOR_LEN above
  82  * CFG_RESET_ADDR, since we assume the monitor is stored at the
  83  * reset address, no? This will keep the environment in user region
  84  * of flash. NOTE: the monitor length must be multiple of sector size
  85  * (which is common practice).
  86  *----------------------------------------------------------------------*/
  87 #define CFG_ENV_IS_IN_FLASH     1               /* Environment in flash */
  88 #define CFG_ENV_SIZE            (64 * 1024)     /* 64 KByte (1 sector)  */
  89 #define CONFIG_ENV_OVERWRITE                    /* Serial change Ok     */
  90 #define CFG_ENV_ADDR    (CFG_RESET_ADDR + CFG_MONITOR_LEN)
  91
  92 /*------------------------------------------------------------------------
  93  * CONSOLE
  94  *----------------------------------------------------------------------*/
  95 #if defined(CONFIG_CONSOLE_JTAG)
  96 #define CFG_NIOS_CONSOLE        0x00920820      /* JTAG UART base addr  */
  97 #else
  98 #define CFG_NIOS_CONSOLE        0x009208a0      /* UART base addr       */
  99 #endif
 100
 101 #define CFG_NIOS_FIXEDBAUD      1               /* Baudrate is fixed    */
 102 #define CONFIG_BAUDRATE         115200          /* Initial baudrate     */
 103 #define CFG_BAUDRATE_TABLE      {115200}        /* It's fixed ;-)       */
 104
 105 #define CFG_CONSOLE_INFO_QUIET  1               /* Suppress console info*/
 106
 107 /*------------------------------------------------------------------------
 108  * DEBUG
 109  *----------------------------------------------------------------------*/
 110 #undef CONFIG_ROM_STUBS                         /* Stubs not in ROM     */
 111
 112 /*------------------------------------------------------------------------
 113  * TIMEBASE --
 114  *
 115  * The high res timer defaults to 1 msec. Since it includes the period
 116  * registers, we can slow it down to 10 msec using TMRCNT. If the default
 117  * period is acceptable, TMRCNT can be left undefined.
 118  *----------------------------------------------------------------------*/
 119 #define CFG_NIOS_TMRBASE        0x00920860      /* Tick timer base addr */
 120 #define CFG_NIOS_TMRIRQ         3               /* Timer IRQ num        */
 121 #define CFG_NIOS_TMRMS          10              /* 10 msec per tick     */
 122 #define CFG_NIOS_TMRCNT (CFG_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000))
 123 #define CFG_HZ          (CONFIG_SYS_CLK_FREQ/(CFG_NIOS_TMRCNT + 1))
 124
 125
 126 /*
 127  * BOOTP options
 128  */
 129 #define CONFIG_BOOTP_BOOTFILESIZE
 130 #define CONFIG_BOOTP_BOOTPATH
 131 #define CONFIG_BOOTP_GATEWAY
 132 #define CONFIG_BOOTP_HOSTNAME
 133
 134
 135 /*
 136  * Command line configuration.
 137  */
 138 #define CONFIG_CMD_BDI
 139 #define CONFIG_CMD_ECHO
 140 #define CONFIG_CMD_ENV
 141 #define CONFIG_CMD_FLASH
 142 #define CONFIG_CMD_IMI
 143 #define CONFIG_CMD_IRQ
 144 #define CONFIG_CMD_LOADS
 145 #define CONFIG_CMD_LOADB
 146 #define CONFIG_CMD_MEMORY
 147 #define CONFIG_CMD_MISC
 148 #define CONFIG_CMD_RUN
 149 #define CONFIG_CMD_SAVES
 150
 151
 152 /*------------------------------------------------------------------------
 153  * MISC
 154  *----------------------------------------------------------------------*/
 155 #define CFG_LONGHELP                            /* Provide extended help*/
 156 #define CFG_PROMPT              "==> "          /* Command prompt       */
 157 #define CFG_CBSIZE              256             /* Console I/O buf size */
 158 #define CFG_MAXARGS             16              /* Max command args     */
 159 #define CFG_BARGSIZE            CFG_CBSIZE      /* Boot arg buf size    */
 160 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print buf size */
 161 #define CFG_LOAD_ADDR           CFG_SDRAM_BASE  /* Default load address */
 162 #define CFG_MEMTEST_START       CFG_SDRAM_BASE  /* Start addr for test  */
 163 #define CFG_MEMTEST_END         CFG_INIT_SP - 0x00020000
 164
 165 #endif  /* __CONFIG_H */