include/configs/MPC8544DS.h

   1 /*
   2  * Copyright 2007 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 /*
  24  * mpc8544ds board configuration file
  25  *
  26  */
  27 #ifndef __CONFIG_H
  28 #define __CONFIG_H
  29
  30 /* High Level Configuration Options */
  31 #define CONFIG_BOOKE            1       /* BOOKE */
  32 #define CONFIG_E500             1       /* BOOKE e500 family */
  33 #define CONFIG_MPC85xx          1       /* MPC8540/60/55/41/48 */
  34 #define CONFIG_MPC8544          1
  35 #define CONFIG_MPC8544DS        1
  36
  37 #define CONFIG_PCI              1       /* Enable PCI/PCIE */
  38 #define CONFIG_PCI1             1       /* PCI controller 1 */
  39 #define CONFIG_PCIE1            1       /* PCIE controler 1 (slot 1) */
  40 #define CONFIG_PCIE2            1       /* PCIE controler 2 (slot 2) */
  41 #define CONFIG_PCIE3            1       /* PCIE controler 3 (ULI bridge) */
  42 #define CONFIG_FSL_PCI_INIT     1       /* Use common FSL init code */
  43 #define CONFIG_FSL_PCIE_RESET   1       /* need PCIe reset errata */
  44
  45 #define CONFIG_FSL_LAW          1       /* Use common FSL init code */
  46
  47 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
  48 #define CONFIG_ENV_OVERWRITE
  49 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup */
  50 #undef CONFIG_DDR_DLL
  51 #define CONFIG_DDR_2T_TIMING            /* Sets the 2T timing bit */
  52
  53 #define CONFIG_DDR_ECC                  /* only for ECC DDR module */
  54 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER       /* DDR controller or DMA? */
  55 #define CONFIG_MEM_INIT_VALUE           0xDeadBeef
  56
  57 #define CONFIG_DDR_ECC_CMD
  58 #define CONFIG_INTERRUPTS               /* enable pci, srio, ddr interrupts */
  59
  60 /*
  61  * When initializing flash, if we cannot find the manufacturer ID,
  62  * assume this is the AMD flash associated with the CDS board.
  63  * This allows booting from a promjet.
  64  */
  65 #define CONFIG_ASSUME_AMD_FLASH
  66
  67 #define MPC85xx_DDR_SDRAM_CLK_CNTL      /* 85xx has clock control reg */
  68
  69 #ifndef __ASSEMBLY__
  70 extern unsigned long get_board_sys_clk(unsigned long dummy);
  71 #endif
  72 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk(0) /* sysclk for MPC85xx */
  73
  74 /*
  75  * These can be toggled for performance analysis, otherwise use default.
  76  */
  77 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
  78 #define CONFIG_BTB                      /* toggle branch predition */
  79 #define CONFIG_ADDR_STREAMING           /* toggle addr streaming */
  80 #define CONFIG_CLEAR_LAW0               /* Clear LAW0 in cpu_init_r */
  81
  82 /*
  83  * Only possible on E500 Version 2 or newer cores.
  84  */
  85 #define CONFIG_ENABLE_36BIT_PHYS        1
  86
  87 #define CONFIG_BOARD_EARLY_INIT_F       1       /* Call board_pre_init */
  88
  89 #undef  CFG_DRAM_TEST                   /* memory test, takes time */
  90 #define CFG_MEMTEST_START       0x00200000      /* memtest works on */
  91 #define CFG_MEMTEST_END         0x00400000
  92 #define CFG_ALT_MEMTEST
  93 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
  94
  95 /*
  96  * Base addresses -- Note these are effective addresses where the
  97  * actual resources get mapped (not physical addresses)
  98  */
  99 #define CFG_CCSRBAR_DEFAULT     0xff700000      /* CCSRBAR Default */
 100 #define CFG_CCSRBAR             0xe0000000      /* relocated CCSRBAR */
 101 #define CFG_CCSRBAR_PHYS        CFG_CCSRBAR     /* physical addr of CCSRBAR */
 102 #define CFG_IMMR                CFG_CCSRBAR     /* PQII uses CFG_IMMR */
 103
 104 #define CFG_PCI1_ADDR           (CFG_CCSRBAR+0x8000)
 105 #define CFG_PCIE1_ADDR          (CFG_CCSRBAR+0xa000)
 106 #define CFG_PCIE2_ADDR          (CFG_CCSRBAR+0x9000)
 107 #define CFG_PCIE3_ADDR          (CFG_CCSRBAR+0xb000)
 108
 109 /*
 110  * DDR Setup
 111  */
 112 #define CFG_DDR_SDRAM_BASE      0x00000000      /* DDR is system memory*/
 113 #define CFG_SDRAM_BASE          CFG_DDR_SDRAM_BASE
 114
 115 #define SPD_EEPROM_ADDRESS      0x51            /* DDR DIMM */
 116
 117 /*
 118  * Make sure required options are set
 119  */
 120 #ifndef CONFIG_SPD_EEPROM
 121 #error ("CONFIG_SPD_EEPROM is required")
 122 #endif
 123
 124 #undef CONFIG_CLOCKS_IN_MHZ
 125
 126 /*
 127  * Memory map
 128  *
 129  * 0x0000_0000  0x7fff_ffff     DDR                     2G Cacheable
 130  *
 131  * 0x8000_0000  0xbfff_ffff     PCI Express Mem         1G non-cacheable
 132  *
 133  * 0xc000_0000  0xdfff_ffff     PCI                     512M non-cacheable
 134  *
 135  * 0xe000_0000  0xe00f_ffff     CCSR                    1M non-cacheable
 136  * 0xe100_0000  0xe3ff_ffff     PCI IO range            4M non-cacheable
 137  *
 138  * Localbus cacheable
 139  *
 140  * 0xf000_0000  0xf3ff_ffff     SDRAM                   64M Cacheable
 141  * 0xf401_0000  0xf401_3fff     L1 for stack            4K Cacheable TLB0
 142  *
 143  * Localbus non-cacheable
 144  *
 145  * 0xf800_0000  0xf80f_ffff     NVRAM/CADMUS (*)        1M non-cacheable
 146  * 0xff00_0000  0xff7f_ffff     FLASH (2nd bank)        8M non-cacheable
 147  * 0xff80_0000  0xffff_ffff     FLASH (boot bank)       8M non-cacheable
 148  *
 149  */
 150
 151 /*
 152  * Local Bus Definitions
 153  */
 154 #define CFG_BOOT_BLOCK          0xfc000000      /* boot TLB */
 155
 156 #define CFG_LBC_CACHE_BASE      0xf0000000      /* Localbus cacheable */
 157
 158 #define CFG_FLASH_BASE          0xff800000      /* start of FLASH 8M */
 159
 160 #define CFG_BR0_PRELIM          0xff801001
 161 #define CFG_BR1_PRELIM          0xfe801001
 162
 163 #define CFG_OR0_PRELIM          0xff806e65
 164 #define CFG_OR1_PRELIM          0xff806e65
 165
 166 #define CFG_FLASH_BANKS_LIST    {0xfe800000,CFG_FLASH_BASE}
 167
 168 #define CFG_MAX_FLASH_BANKS     2               /* number of banks */
 169 #define CFG_MAX_FLASH_SECT      128             /* sectors per device */
 170 #undef  CFG_FLASH_CHECKSUM
 171 #define CFG_FLASH_ERASE_TOUT    60000           /* Flash Erase Timeout (ms) */
 172 #define CFG_FLASH_WRITE_TOUT    500             /* Flash Write Timeout (ms) */
 173
 174 #define CFG_MONITOR_BASE        TEXT_BASE       /* start of monitor */
 175
 176 #define CFG_FLASH_CFI_DRIVER
 177 #define CFG_FLASH_CFI
 178 #define CFG_FLASH_EMPTY_INFO
 179
 180 #define CFG_LBC_NONCACHE_BASE   0xf8000000
 181
 182 #define CFG_BR2_PRELIM          0xf8201001      /* port size 16bit */
 183 #define CFG_OR2_PRELIM          0xfff06ff7      /* 1MB Compact Flash area*/
 184
 185 #define CFG_BR3_PRELIM          0xf8100801      /* port size 8bit */
 186 #define CFG_OR3_PRELIM          0xfff06ff7      /* 1MB PIXIS area*/
 187
 188 #define CONFIG_FSL_PIXIS        1       /* use common PIXIS code */
 189 #define PIXIS_BASE      0xf8100000      /* PIXIS registers */
 190 #define PIXIS_ID                0x0     /* Board ID at offset 0 */
 191 #define PIXIS_VER               0x1     /* Board version at offset 1 */
 192 #define PIXIS_PVER              0x2     /* PIXIS FPGA version at offset 2 */
 193 #define PIXIS_RST               0x4     /* PIXIS Reset Control register */
 194 #define PIXIS_AUX               0x6     /* PIXIS Auxiliary register; Scratch
 195                                          * register */
 196 #define PIXIS_SPD               0x7     /* Register for SYSCLK speed */
 197 #define PIXIS_VCTL              0x10    /* VELA Control Register */
 198 #define PIXIS_VCFGEN0           0x12    /* VELA Config Enable 0 */
 199 #define PIXIS_VCFGEN1           0x13    /* VELA Config Enable 1 */
 200 #define PIXIS_VBOOT             0x16    /* VELA VBOOT Register */
 201 #define PIXIS_VSPEED0           0x17    /* VELA VSpeed 0 */
 202 #define PIXIS_VSPEED1           0x18    /* VELA VSpeed 1 */
 203 #define PIXIS_VCLKH             0x19    /* VELA VCLKH register */
 204 #define PIXIS_VCLKL             0x1A    /* VELA VCLKL register */
 205 #define CFG_PIXIS_VBOOT_MASK    0x40    /* Reset altbank mask*/
 206
 207
 208 /* define to use L1 as initial stack */
 209 #define CONFIG_L1_INIT_RAM      1
 210 #define CFG_INIT_L1_LOCK        1
 211 #define CFG_INIT_L1_ADDR        0xf4010000      /* Initial L1 address */
 212 #define CFG_INIT_L1_END         0x00004000      /* End of used area in RAM */
 213
 214 /* define to use L2SRAM as initial stack */
 215 #undef CONFIG_L2_INIT_RAM
 216 #define CFG_INIT_L2_ADDR        0xf8fc0000
 217 #define CFG_INIT_L2_END         0x00040000      /* End of used area in RAM */
 218
 219 #ifdef CONFIG_L1_INIT_RAM
 220 #define CFG_INIT_RAM_ADDR       CFG_INIT_L1_ADDR
 221 #define CFG_INIT_RAM_END        CFG_INIT_L1_END
 222 #else
 223 #define CFG_INIT_RAM_ADDR       CFG_INIT_L2_ADDR
 224 #define CFG_INIT_RAM_END        CFG_INIT_L2_END
 225 #endif
 226
 227 #define CFG_GBL_DATA_SIZE       128     /* num bytes initial data */
 228 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 229 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 230
 231 #define CFG_MONITOR_LEN         (256 * 1024) /* Reserve 256 kB for Mon */
 232 #define CFG_MALLOC_LEN          (128 * 1024)    /* Reserved for malloc */
 233
 234 /* Serial Port - controlled on board with jumper J8
 235  * open - index 2
 236  * shorted - index 1
 237  */
 238 #define CONFIG_CONS_INDEX       1
 239 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
 240 #define CFG_NS16550
 241 #define CFG_NS16550_SERIAL
 242 #define CFG_NS16550_REG_SIZE    1
 243 #define CFG_NS16550_CLK         get_bus_freq(0)
 244
 245 #define CFG_BAUDRATE_TABLE      \
 246         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 247
 248 #define CFG_NS16550_COM1        (CFG_CCSRBAR+0x4500)
 249 #define CFG_NS16550_COM2        (CFG_CCSRBAR+0x4600)
 250
 251 /* Use the HUSH parser */
 252 #define CFG_HUSH_PARSER
 253 #ifdef  CFG_HUSH_PARSER
 254 #define CFG_PROMPT_HUSH_PS2 "> "
 255 #endif
 256
 257 /* pass open firmware flat tree */
 258 #define CONFIG_OF_LIBFDT                1
 259 #define CONFIG_OF_BOARD_SETUP           1
 260 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 261
 262 /* I2C */
 263 #define CONFIG_FSL_I2C          /* Use FSL common I2C driver */
 264 #define CONFIG_HARD_I2C         /* I2C with hardware support */
 265 #undef  CONFIG_SOFT_I2C         /* I2C bit-banged */
 266 #define CFG_I2C_SPEED           400000  /* I2C speed and slave address */
 267 #define CFG_I2C_EEPROM_ADDR     0x57
 268 #define CFG_I2C_SLAVE           0x7F
 269 #define CFG_I2C_NOPROBES        {0x69}  /* Don't probe these addrs */
 270 #define CFG_I2C_OFFSET          0x3100
 271
 272 /*
 273  * General PCI
 274  * Memory space is mapped 1-1, but I/O space must start from 0.
 275  */
 276 #define CFG_PCIE_PHYS           0x80000000      /* 1G PCIE TLB */
 277 #define CFG_PCI_PHYS            0xc0000000      /* 512M PCI TLB */
 278
 279 #define CFG_PCI1_MEM_BASE       0xc0000000
 280 #define CFG_PCI1_MEM_PHYS       CFG_PCI1_MEM_BASE
 281 #define CFG_PCI1_MEM_SIZE       0x20000000      /* 512M */
 282 #define CFG_PCI1_IO_BASE        0x00000000
 283 #define CFG_PCI1_IO_PHYS        0xe1000000
 284 #define CFG_PCI1_IO_SIZE        0x00010000      /* 64k */
 285
 286 /* PCI view of System Memory */
 287 #define CFG_PCI_MEMORY_BUS      0x00000000
 288 #define CFG_PCI_MEMORY_PHYS     0x00000000
 289 #define CFG_PCI_MEMORY_SIZE     0x80000000
 290
 291 /* controller 2, Slot 1, tgtid 1, Base address 9000 */
 292 #define CFG_PCIE2_MEM_BASE      0x80000000
 293 #define CFG_PCIE2_MEM_PHYS      CFG_PCIE2_MEM_BASE
 294 #define CFG_PCIE2_MEM_SIZE      0x20000000      /* 512M */
 295 #define CFG_PCIE2_IO_BASE       0x00000000
 296 #define CFG_PCIE2_IO_PHYS       0xe1010000
 297 #define CFG_PCIE2_IO_SIZE       0x00010000      /* 64k */
 298
 299 /* controller 1, Slot 2,tgtid 2, Base address a000 */
 300 #define CFG_PCIE1_MEM_BASE      0xa0000000
 301 #define CFG_PCIE1_MEM_PHYS      CFG_PCIE1_MEM_BASE
 302 #define CFG_PCIE1_MEM_SIZE      0x10000000      /* 256M */
 303 #define CFG_PCIE1_IO_BASE       0x00000000
 304 #define CFG_PCIE1_IO_PHYS       0xe1020000
 305 #define CFG_PCIE1_IO_SIZE       0x00010000      /* 64k */
 306
 307 /* controller 3, direct to uli, tgtid 3, Base address b000 */
 308 #define CFG_PCIE3_MEM_BASE      0xb0000000
 309 #define CFG_PCIE3_MEM_PHYS      CFG_PCIE3_MEM_BASE
 310 #define CFG_PCIE3_MEM_SIZE      0x00100000      /* 1M */
 311 #define CFG_PCIE3_IO_BASE       0x00000000
 312 #define CFG_PCIE3_IO_PHYS       0xb0100000      /* reuse mem LAW */
 313 #define CFG_PCIE3_IO_SIZE       0x00100000      /* 1M */
 314 #define CFG_PCIE3_MEM_BASE2     0xb0200000
 315 #define CFG_PCIE3_MEM_PHYS2     CFG_PCIE3_MEM_BASE2
 316 #define CFG_PCIE3_MEM_SIZE2     0x00200000      /* 1M */
 317
 318 #if defined(CONFIG_PCI)
 319
 320 #define CONFIG_NET_MULTI
 321 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 322
 323 #undef CONFIG_EEPRO100
 324 #undef CONFIG_TULIP
 325 #define CONFIG_RTL8139
 326
 327 #ifdef CONFIG_RTL8139
 328 /* This macro is used by RTL8139 but not defined in PPC architecture */
 329 #define KSEG1ADDR(x)            (x)
 330 #define _IO_BASE        0x00000000
 331 #endif
 332
 333 #ifndef CONFIG_PCI_PNP
 334         #define PCI_ENET0_IOADDR        CFG_PCI1_IO_BASE
 335         #define PCI_ENET0_MEMADDR       CFG_PCI1_IO_BASE
 336         #define PCI_IDSEL_NUMBER        0x11    /* IDSEL = AD11 */
 337 #endif
 338
 339 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 340 #define CONFIG_DOS_PARTITION
 341 #define CONFIG_SCSI_AHCI
 342
 343 #ifdef CONFIG_SCSI_AHCI
 344 #define CONFIG_SATA_ULI5288
 345 #define CFG_SCSI_MAX_SCSI_ID    4
 346 #define CFG_SCSI_MAX_LUN        1
 347 #define CFG_SCSI_MAX_DEVICE     (CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN)
 348 #define CFG_SCSI_MAXDEVICE      CFG_SCSI_MAX_DEVICE
 349 #endif /* SCSCI */
 350
 351 #endif  /* CONFIG_PCI */
 352
 353
 354 #if defined(CONFIG_TSEC_ENET)
 355
 356 #ifndef CONFIG_NET_MULTI
 357 #define CONFIG_NET_MULTI        1
 358 #endif
 359
 360 #define CONFIG_MII              1       /* MII PHY management */
 361 #define CONFIG_MII_DEFAULT_TSEC 1       /* Allow unregistered phys */
 362 #define CONFIG_TSEC1    1
 363 #define CONFIG_TSEC1_NAME       "eTSEC1"
 364 #define CONFIG_TSEC3    1
 365 #define CONFIG_TSEC3_NAME       "eTSEC3"
 366
 367 #define TSEC1_PHY_ADDR          0
 368 #define TSEC3_PHY_ADDR          1
 369
 370 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 371 #define TSEC3_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 372
 373 #define TSEC1_PHYIDX            0
 374 #define TSEC3_PHYIDX            0
 375
 376 #define CONFIG_ETHPRIME         "eTSEC1"
 377
 378 #define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 379 #endif  /* CONFIG_TSEC_ENET */
 380
 381 /*
 382  * Environment
 383  */
 384 #define CFG_ENV_IS_IN_FLASH     1
 385 #if CFG_MONITOR_BASE > 0xfff80000
 386 #define CFG_ENV_ADDR            0xfff80000
 387 #else
 388 #define CFG_ENV_ADDR            (CFG_MONITOR_BASE + 0x40000)
 389 #endif
 390 #define CFG_ENV_SIZE            0x2000
 391 #define CFG_ENV_SECT_SIZE       0x10000 /* 64K (one sector) */
 392
 393 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 394 #define CFG_LOADS_BAUD_CHANGE   1       /* allow baudrate change */
 395
 396 /*
 397  * BOOTP options
 398  */
 399 #define CONFIG_BOOTP_BOOTFILESIZE
 400 #define CONFIG_BOOTP_BOOTPATH
 401 #define CONFIG_BOOTP_GATEWAY
 402 #define CONFIG_BOOTP_HOSTNAME
 403
 404
 405 /*
 406  * Command line configuration.
 407  */
 408 #include <config_cmd_default.h>
 409
 410 #define CONFIG_CMD_PING
 411 #define CONFIG_CMD_I2C
 412 #define CONFIG_CMD_MII
 413 #define CONFIG_CMD_ELF
 414
 415 #if defined(CONFIG_PCI)
 416     #define CONFIG_CMD_PCI
 417     #define CONFIG_CMD_BEDBUG
 418     #define CONFIG_CMD_NET
 419     #define CONFIG_CMD_SCSI
 420     #define CONFIG_CMD_EXT2
 421 #endif
 422
 423
 424 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 425
 426 /*
 427  * Miscellaneous configurable options
 428  */
 429 #define CFG_LONGHELP                    /* undef to save memory */
 430 #define CONFIG_CMDLINE_EDITING          /* Command-line editing */
 431 #define CFG_LOAD_ADDR   0x2000000       /* default load address */
 432 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt */
 433 #if defined(CONFIG_CMD_KGDB)
 434 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size */
 435 #else
 436 #define CFG_CBSIZE      256             /* Console I/O Buffer Size */
 437 #endif
 438 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 439 #define CFG_MAXARGS     16              /* max number of command args */
 440 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size */
 441 #define CFG_HZ          1000            /* decrementer freq: 1ms ticks */
 442
 443 /*
 444  * For booting Linux, the board info and command line data
 445  * have to be in the first 8 MB of memory, since this is
 446  * the maximum mapped by the Linux kernel during initialization.
 447  */
 448 #define CFG_BOOTMAPSZ   (8 << 20)       /* Initial Memory map for Linux*/
 449
 450 /*
 451  * Internal Definitions
 452  *
 453  * Boot Flags
 454  */
 455 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH */
 456 #define BOOTFLAG_WARM   0x02            /* Software reboot */
 457
 458 #if defined(CONFIG_CMD_KGDB)
 459 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 460 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 461 #endif
 462
 463 /*
 464  * Environment Configuration
 465  */
 466
 467 /* The mac addresses for all ethernet interface */
 468 #if defined(CONFIG_TSEC_ENET)
 469 #define CONFIG_HAS_ETH0
 470 #define CONFIG_ETHADDR  00:E0:0C:02:00:FD
 471 #define CONFIG_HAS_ETH1
 472 #define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD
 473 #endif
 474
 475 #define CONFIG_IPADDR   192.168.1.251
 476
 477 #define CONFIG_HOSTNAME 8544ds_unknown
 478 #define CONFIG_ROOTPATH /nfs/mpc85xx
 479 #define CONFIG_BOOTFILE 8544ds/uImage.uboot
 480 #define CONFIG_UBOOTPATH        8544ds/u-boot.bin       /* TFTP server */
 481
 482 #define CONFIG_SERVERIP 192.168.1.1
 483 #define CONFIG_GATEWAYIP 192.168.1.1
 484 #define CONFIG_NETMASK  255.255.0.0
 485
 486 #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
 487
 488 #define CONFIG_BOOTDELAY 10     /* -1 disables auto-boot */
 489 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs*/
 490
 491 #define CONFIG_BAUDRATE 115200
 492
 493 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 494  "netdev=eth0\0"                                                \
 495  "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"                         \
 496  "tftpflash=tftpboot $loadaddr $uboot; "                        \
 497         "protect off " MK_STR(TEXT_BASE) " +$filesize; "        \
 498         "erase " MK_STR(TEXT_BASE) " +$filesize; "              \
 499         "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; "      \
 500         "protect on " MK_STR(TEXT_BASE) " +$filesize; "         \
 501         "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0"     \
 502  "consoledev=ttyS0\0"                           \
 503  "ramdiskaddr=2000000\0"                        \
 504  "ramdiskfile=8544ds/ramdisk.uboot\0"           \
 505  "fdtaddr=c00000\0"                             \
 506  "fdtfile=8544ds/mpc8544ds.dtb\0"               \
 507  "bdev=sda3\0"
 508
 509 #define CONFIG_NFSBOOTCOMMAND           \
 510  "setenv bootargs root=/dev/nfs rw "    \
 511  "nfsroot=$serverip:$rootpath "         \
 512  "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 513  "console=$consoledev,$baudrate $othbootargs;"  \
 514  "tftp $loadaddr $bootfile;"            \
 515  "tftp $fdtaddr $fdtfile;"              \
 516  "bootm $loadaddr - $fdtaddr"
 517
 518 #define CONFIG_RAMBOOTCOMMAND           \
 519  "setenv bootargs root=/dev/ram rw "    \
 520  "console=$consoledev,$baudrate $othbootargs;"  \
 521  "tftp $ramdiskaddr $ramdiskfile;"      \
 522  "tftp $loadaddr $bootfile;"            \
 523  "tftp $fdtaddr $fdtfile;"              \
 524  "bootm $loadaddr $ramdiskaddr $fdtaddr"
 525
 526 #define CONFIG_BOOTCOMMAND              \
 527  "setenv bootargs root=/dev/$bdev rw "  \
 528  "console=$consoledev,$baudrate $othbootargs;"  \
 529  "tftp $loadaddr $bootfile;"            \
 530  "tftp $fdtaddr $fdtfile;"              \
 531  "bootm $loadaddr - $fdtaddr"
 532
 533 #endif  /* __CONFIG_H */