include/configs/MPC8540EVAL.h

   1 /*
   2  * (C) Copyright 2002,2003 Motorola,Inc.
   3  * Modified by Lunsheng Wang, lunsheng@sohu.com
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /* mpc8540eval board configuration file */
  25 /* please refer to doc/README.mpc85xxads for more info */
  26 /* make sure you change the MAC address and other network params first,
  27  * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file
  28  */
  29
  30 #ifndef __CONFIG_H
  31 #define __CONFIG_H
  32 /* High Level Configuration Options */
  33 #define CONFIG_BOOKE            1           /* BOOKE                    */
  34 #define CONFIG_E500             1           /* BOOKE e500 family        */
  35 #define CONFIG_MPC85xx          1           /* MPC8540/MPC8560          */
  36 #define CONFIG_MPC8540          1           /* MPC8540 specific         */
  37 #define CONFIG_MPC8540EVAL      1           /* MPC8540EVAL board specific */
  38
  39 #undef  CONFIG_PCI                          /* pci ethernet support     */
  40 #define CONFIG_TSEC_ENET                    /* tsec ethernet support  */
  41 #define CONFIG_ENV_OVERWRITE
  42 #define CONFIG_SPD_EEPROM                   /* Use SPD EEPROM for DDR setup */
  43 #undef  CONFIG_DDR_ECC                      /* only for ECC DDR module */
  44 #define CONFIG_DDR_DLL                      /* possible DLL fix needed */
  45
  46 #define CONFIG_FSL_LAW          1       /* Use common FSL init code */
  47
  48 /* Using Localbus SDRAM to emulate flash before we can program the flash,
  49  * normally you only need a flash-boot image(u-boot.bin),if unsure undef this.
  50  * Not availabe for EVAL board
  51  */
  52 #undef CONFIG_RAM_AS_FLASH
  53
  54 /* sysclk for MPC8540EVAL */
  55 #if defined(CONFIG_SYSCLK_66M)
  56         /*
  57          * the oscillator on board is 66Mhz
  58          * can also get 66M clock from external PCI
  59          */
  60         #define CONFIG_SYS_CLK_FREQ   66000000
  61 #else
  62         #define CONFIG_SYS_CLK_FREQ   33000000   /* most pci cards are 33Mhz */
  63 #endif
  64
  65 /* below can be toggled for performance analysis. otherwise use default */
  66 #define CONFIG_L2_CACHE                     /* toggle L2 cache  */
  67 #undef  CONFIG_BTB                          /* toggle branch predition */
  68 #undef  CONFIG_ADDR_STREAMING               /* toggle addr streaming   */
  69
  70 #define CONFIG_BOARD_PRE_INIT   1           /* Call board_pre_init      */
  71
  72 #undef  CFG_DRAM_TEST                       /* memory test, takes time  */
  73 #define CFG_MEMTEST_START       0x00200000      /* memtest works on     */
  74 #define CFG_MEMTEST_END         0x00400000
  75
  76 #if defined(CONFIG_PCI) && defined(CONFIG_TSEC_ENET)
  77 #error "You can only use either PCI Ethernet Card or TSEC Ethernet, not both."
  78 #endif
  79
  80 /*
  81  * Base addresses -- Note these are effective addresses where the
  82  * actual resources get mapped (not physical addresses)
  83  */
  84 #define CFG_CCSRBAR_DEFAULT     0xff700000      /* CCSRBAR Default      */
  85 #define CFG_CCSRBAR             0xe0000000      /* relocated CCSRBAR    */
  86 #define CFG_CCSRBAR_PHYS        CFG_CCSRBAR     /* physical addr of CCSRBAR */
  87 #define CFG_IMMR                CFG_CCSRBAR     /* PQII uses CFG_IMMR   */
  88
  89 #define CFG_DDR_SDRAM_BASE      0x00000000      /* DDR is system memory  */
  90 #define CFG_SDRAM_BASE          CFG_DDR_SDRAM_BASE
  91 #define CFG_SDRAM_SIZE          256             /* DDR is now 256MB     */
  92
  93 #if defined(CONFIG_RAM_AS_FLASH)
  94 #define CFG_LBC_SDRAM_BASE      0xfc000000      /* Localbus SDRAM */
  95 #else
  96 #define CFG_LBC_SDRAM_BASE      0xf0000000      /* Localbus SDRAM */
  97 #endif
  98 #define CFG_LBC_SDRAM_SIZE      64              /* LBC SDRAM is 0MB     */
  99
 100 #if defined(CONFIG_RAM_AS_FLASH)
 101 #define CFG_FLASH_BASE          0xf8000000      /* start of FLASH  16M  */
 102 #define CFG_BR0_PRELIM          0xf8001801      /* port size 32bit */
 103 #else /* Boot from real Flash */
 104 #define CFG_FLASH_BASE          0xff800000      /* start of FLASH 8M    */
 105 #define CFG_BR0_PRELIM          0xff801001      /* port size 16bit      */
 106 #endif
 107
 108 #define CFG_OR0_PRELIM          0xff806f67      /* 8MB Flash            */
 109 #define CFG_MAX_FLASH_BANKS     1               /* number of banks      */
 110 #define CFG_MAX_FLASH_SECT      64              /* sectors per device   */
 111 #undef  CFG_FLASH_CHECKSUM
 112 #define CFG_FLASH_ERASE_TOUT    60000   /* Timeout for Flash Erase (in ms)*/
 113 #define CFG_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms)*/
 114 #define CFG_FLASH_CFI           1
 115
 116 #define CFG_MONITOR_BASE        TEXT_BASE       /* start of monitor */
 117
 118 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
 119 #define CFG_RAMBOOT
 120 #else
 121 #undef  CFG_RAMBOOT
 122 #endif
 123
 124 #define SPD_EEPROM_ADDRESS      0x51            /* DDR DIMM */
 125
 126 /* Here some DDR setting should be added */
 127
 128
 129 #undef CONFIG_CLOCKS_IN_MHZ
 130
 131 /* local bus definitions */
 132 #define CFG_BR2_PRELIM          0xf0001861      /* 64MB localbus SDRAM  */
 133 #define CFG_OR2_PRELIM          0xfc006901
 134 #define CFG_LBC_LCRR            0x00030004      /* local bus freq divider*/
 135 #define CFG_LBC_LBCR            0x00000000
 136 #define CFG_LBC_LSRT            0x20000000
 137 #define CFG_LBC_MRTPR           0x20000000
 138 #define CFG_LBC_LSDMR_1         0x2861b723
 139 #define CFG_LBC_LSDMR_2         0x0861b723
 140 #define CFG_LBC_LSDMR_3         0x0861b723
 141 #define CFG_LBC_LSDMR_4         0x1861b723
 142 #define CFG_LBC_LSDMR_5         0x4061b723
 143
 144 #if defined(CONFIG_RAM_AS_FLASH)
 145 #define CFG_BR4_PRELIM          0xf8000801      /* 32KB, 8-bit wide for ADS config reg */
 146 #else
 147 #define CFG_BR4_PRELIM          0xf8000801      /* 32KB, 8-bit wide for ADS config reg */
 148 #endif
 149 #define CFG_OR4_PRELIM          0xffffe1f1
 150 #define CFG_BCSR                (CFG_BR4_PRELIM & 0xffff8000)
 151
 152 #define CONFIG_L1_INIT_RAM
 153 #define CFG_INIT_RAM_LOCK       1
 154 #define CFG_INIT_RAM_ADDR       0x40000000      /* Initial RAM address  */
 155 #define CFG_INIT_RAM_END        0x4000          /* End of used area in RAM */
 156
 157 #define CFG_GBL_DATA_SIZE       128             /* num bytes initial data */
 158 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 159 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 160
 161 #define CFG_MONITOR_LEN         (256 * 1024)    /* Reserve 256 kB for Mon */
 162 #define CFG_MALLOC_LEN          (128 * 1024)    /* Reserved for malloc */
 163
 164 /* Serial Port */
 165 #define CONFIG_CONS_INDEX     1
 166 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
 167 #define CFG_NS16550
 168 #define CFG_NS16550_SERIAL
 169 #define CFG_NS16550_REG_SIZE    1
 170 #define CFG_NS16550_CLK         get_bus_freq(0)
 171 #define CONFIG_BAUDRATE         115200
 172
 173 #define CFG_BAUDRATE_TABLE  \
 174         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 175
 176 #define CFG_NS16550_COM1        (CFG_CCSRBAR+0x4500)
 177 #define CFG_NS16550_COM2        (CFG_CCSRBAR+0x4600)
 178
 179 /* Use the HUSH parser */
 180 #define CFG_HUSH_PARSER
 181 #ifdef  CFG_HUSH_PARSER
 182 #define CFG_PROMPT_HUSH_PS2 "> "
 183 #endif
 184
 185 /*
 186  * I2C
 187  */
 188 #define CONFIG_FSL_I2C          /* Use FSL common I2C driver */
 189 #define CONFIG_HARD_I2C         /* I2C with hardware support*/
 190 #undef  CONFIG_SOFT_I2C                 /* I2C bit-banged               */
 191 #define CFG_I2C_SPEED           400000  /* I2C speed and slave address  */
 192 #define CFG_I2C_SLAVE           0x7F
 193 #define CFG_I2C_NOPROBES        {0x69}  /* Don't probe these addrs */
 194 #define CFG_I2C_OFFSET          0x3000
 195
 196 /* General PCI */
 197 #define CFG_PCI_MEM_BASE        0x80000000
 198 #define CFG_PCI_MEM_PHYS        0x80000000
 199 #define CFG_PCI_MEM_SIZE        0x20000000
 200 #define CFG_PCI_IO_BASE         0xe2000000
 201
 202 #if defined(CONFIG_PCI)
 203 #define CONFIG_NET_MULTI
 204 #undef CONFIG_EEPRO100
 205 #define CONFIG_TULIP
 206 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 207 #if !defined(CONFIG_PCI_PNP)
 208 #define PCI_ENET0_IOADDR      0xe0000000
 209 #define PCI_ENET0_MEMADDR     0xe0000000
 210 #define PCI_IDSEL_NUMBER      0x0c      /*slot0->3(IDSEL)=12->15*/
 211 #endif
 212 #define CONFIG_PCI_SCAN_SHOW    1       /* show pci devices on startup  */
 213 #define CFG_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
 214 #define CFG_PCI_SUBSYS_DEVICEID 0x0008
 215 #elif defined(CONFIG_TSEC_ENET)
 216 #define CONFIG_NET_MULTI        1
 217 #define CONFIG_MII              1       /* MII PHY management   */
 218 #define CONFIG_TSEC1    1
 219 #define CONFIG_HAS_ETH0
 220 #define CONFIG_TSEC1_NAME      "TSEC0"
 221 #define CONFIG_TSEC2    1
 222 #define CONFIG_HAS_ETH1
 223 #define CONFIG_TSEC2_NAME      "TSEC1"
 224 #define CONFIG_MPC85XX_FEC      1
 225 #define CONFIG_HAS_ETH2
 226 #define CONFIG_MPC85XX_FEC_NAME                "FEC"
 227 #define TSEC1_PHY_ADDR          7
 228 #define TSEC2_PHY_ADDR          4
 229 #define FEC_PHY_ADDR            2
 230 #define TSEC1_PHYIDX            0
 231 #define TSEC2_PHYIDX            0
 232 #define FEC_PHYIDX              0
 233 #define TSEC1_FLAGS             TSEC_GIGABIT
 234 #define TSEC2_FLAGS             TSEC_GIGABIT
 235 #define FEC_FLAGS               0
 236
 237 /* Options are: TSEC[0-1], FEC */
 238 #define CONFIG_ETHPRIME                "TSEC0"
 239
 240 #define CONFIG_PHY_M88E1011     1       /* GigaBit Ether PHY    */
 241 #define INTEL_LXT971_PHY        1
 242 #endif
 243
 244 /* Environment */
 245 #ifndef CFG_RAMBOOT
 246 #if defined(CONFIG_RAM_AS_FLASH)
 247 #define CFG_ENV_IS_NOWHERE
 248 #define CFG_ENV_ADDR            (CFG_FLASH_BASE + 0x100000)
 249 #define CFG_ENV_SIZE            0x2000
 250 #else
 251 #define CFG_ENV_IS_IN_FLASH     1
 252 #define CFG_ENV_ADDR            (CFG_MONITOR_BASE + 0x40000)
 253 #define CFG_ENV_SECT_SIZE       0x40000 /* 256K(one sector) for env */
 254 #endif
 255 #define CFG_ENV_SIZE            0x2000
 256 #else
 257 /* #define CFG_NO_FLASH         1 */    /* Flash is not usable now      */
 258 #define CFG_ENV_IS_NOWHERE      1       /* Store ENV in memory only     */
 259 #define CFG_ENV_ADDR            (CFG_MONITOR_BASE - 0x1000)
 260 #define CFG_ENV_SIZE            0x2000
 261 #endif
 262
 263 #define CONFIG_BOOTARGS "root=/dev/ram rw console=ttyS0,115200"
 264 #define CONFIG_BOOTCOMMAND      "bootm 0xff800000 0xffa00000"
 265 #define CONFIG_BOOTDELAY        3       /* -1 disable autoboot */
 266
 267 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 268 #define CFG_LOADS_BAUD_CHANGE   1       /* allow baudrate change        */
 269
 270
 271 /*
 272  * BOOTP options
 273  */
 274 #define CONFIG_BOOTP_BOOTFILESIZE
 275 #define CONFIG_BOOTP_BOOTPATH
 276 #define CONFIG_BOOTP_GATEWAY
 277 #define CONFIG_BOOTP_HOSTNAME
 278
 279
 280 /*
 281  * Command line configuration.
 282  */
 283 #include <config_cmd_default.h>
 284
 285 #define CONFIG_CMD_PING
 286 #define CONFIG_CMD_I2C
 287
 288 #if defined(CONFIG_PCI)
 289     #define CONFIG_CMD_PCI
 290 #endif
 291
 292 #if defined(CFG_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH)
 293     #undef CONFIG_CMD_ENV
 294     #undef CONFIG_CMD_LOADS
 295 #endif
 296
 297
 298 #undef CONFIG_WATCHDOG                  /* watchdog disabled            */
 299
 300 /*
 301  * Miscellaneous configurable options
 302  */
 303 #define CFG_LONGHELP                    /* undef to save memory         */
 304 #define CFG_LOAD_ADDR   0x2000000       /* default load address */
 305 #define CFG_PROMPT      "MPC8540EVAL=> "/* Monitor Command Prompt       */
 306 #if defined(CONFIG_CMD_KGDB)
 307 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size      */
 308 #else
 309 #define CFG_CBSIZE      256             /* Console I/O Buffer Size      */
 310 #endif
 311 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 312 #define CFG_MAXARGS     16              /* max number of command args   */
 313 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 314 #define CFG_HZ          1000            /* decrementer freq: 1 ms ticks */
 315
 316 /*
 317  * For booting Linux, the board info and command line data
 318  * have to be in the first 8 MB of memory, since this is
 319  * the maximum mapped by the Linux kernel during initialization.
 320  */
 321 #define CFG_BOOTMAPSZ   (8 << 20)       /* Initial Memory map for Linux */
 322
 323 /*
 324  * Internal Definitions
 325  *
 326  * Boot Flags
 327  */
 328 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH */
 329 #define BOOTFLAG_WARM   0x02            /* Software reboot              */
 330
 331 #if defined(CONFIG_CMD_KGDB)
 332 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 333 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 334 #endif
 335
 336 /*****************************/
 337 /* Environment Configuration */
 338 /*****************************/
 339 /* The mac addresses for all ethernet interface */
 340 /* NOTE: change below for your network setting!!! */
 341 #if defined(CONFIG_TSEC_ENET)
 342 #define CONFIG_ETHADDR  00:01:af:07:9b:8a
 343 #define CONFIG_ETH1ADDR  00:01:af:07:9b:8b
 344 #define CONFIG_ETH2ADDR  00:01:af:07:9b:8c
 345 #endif
 346
 347 #define CONFIG_ROOTPATH  /nfsroot
 348 #define CONFIG_BOOTFILE  your.uImage
 349
 350 #define CONFIG_SERVERIP         192.168.101.1
 351 #define CONFIG_IPADDR           192.168.101.11
 352 #define CONFIG_GATEWAYIP        192.168.101.0
 353 #define CONFIG_NETMASK          255.255.255.0
 354
 355 #define CONFIG_LOADADDR  200000   /* default location for tftp and bootm */
 356
 357 #define CONFIG_HOSTNAME         MPC8540EVAL
 358
 359 #endif  /* __CONFIG_H */