include/configs/MPC837XERDB.h

   1 /*
   2  * Copyright (C) 2007 Freescale Semiconductor, Inc.
   3  * Kevin Lam <kevin.lam@freescale.com>
   4  * Joe D'Abbraccio <joe.d'abbraccio@freescale.com>
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; either version 2 of
   9  * the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  19  * MA 02111-1307 USA
  20  */
  21
  22 #ifndef __CONFIG_H
  23 #define __CONFIG_H
  24
  25 /*
  26  * High Level Configuration Options
  27  */
  28 #define CONFIG_E300             1 /* E300 family */
  29 #define CONFIG_MPC83XX          1 /* MPC83XX family */
  30 #define CONFIG_MPC837X          1 /* MPC837X CPU specific */
  31 #define CONFIG_MPC837XERDB      1
  32
  33 #define CONFIG_PCI      1
  34
  35 #define CONFIG_BOARD_EARLY_INIT_F
  36 #define CONFIG_MISC_INIT_R
  37
  38 /*
  39  * On-board devices
  40  */
  41 #define CONFIG_TSEC_ENET                /* TSEC Ethernet support */
  42 #define CONFIG_VSC7385_ENET
  43
  44 /*
  45  * System Clock Setup
  46  */
  47 #ifdef CONFIG_PCISLAVE
  48 #define CONFIG_83XX_PCICLK      66666667 /* in HZ */
  49 #else
  50 #define CONFIG_83XX_CLKIN       66666667 /* in Hz */
  51 #define CONFIG_83XX_GENERIC_PCI 1
  52 #endif
  53
  54 #ifndef CONFIG_SYS_CLK_FREQ
  55 #define CONFIG_SYS_CLK_FREQ     CONFIG_83XX_CLKIN
  56 #endif
  57
  58 /*
  59  * Hardware Reset Configuration Word
  60  */
  61 #define CFG_HRCW_LOW (\
  62         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  63         HRCWL_DDR_TO_SCB_CLK_1X1 |\
  64         HRCWL_SVCOD_DIV_2 |\
  65         HRCWL_CSB_TO_CLKIN_5X1 |\
  66         HRCWL_CORE_TO_CSB_2X1)
  67
  68 #ifdef CONFIG_PCISLAVE
  69 #define CFG_HRCW_HIGH (\
  70         HRCWH_PCI_AGENT |\
  71         HRCWH_PCI1_ARBITER_DISABLE |\
  72         HRCWH_CORE_ENABLE |\
  73         HRCWH_FROM_0XFFF00100 |\
  74         HRCWH_BOOTSEQ_DISABLE |\
  75         HRCWH_SW_WATCHDOG_DISABLE |\
  76         HRCWH_ROM_LOC_LOCAL_16BIT |\
  77         HRCWH_RL_EXT_LEGACY |\
  78         HRCWH_TSEC1M_IN_RGMII |\
  79         HRCWH_TSEC2M_IN_RGMII |\
  80         HRCWH_BIG_ENDIAN |\
  81         HRCWH_LDP_CLEAR)
  82 #else
  83 #define CFG_HRCW_HIGH (\
  84         HRCWH_PCI_HOST |\
  85         HRCWH_PCI1_ARBITER_ENABLE |\
  86         HRCWH_CORE_ENABLE |\
  87         HRCWH_FROM_0X00000100 |\
  88         HRCWH_BOOTSEQ_DISABLE |\
  89         HRCWH_SW_WATCHDOG_DISABLE |\
  90         HRCWH_ROM_LOC_LOCAL_16BIT |\
  91         HRCWH_RL_EXT_LEGACY |\
  92         HRCWH_TSEC1M_IN_RGMII |\
  93         HRCWH_TSEC2M_IN_RGMII |\
  94         HRCWH_BIG_ENDIAN |\
  95         HRCWH_LDP_CLEAR)
  96 #endif
  97
  98 /* System performance - define the value i.e. CFG_XXX
  99 */
 100
 101 /* Arbiter Configuration Register */
 102 #define CFG_ACR_PIPE_DEP        3       /* Arbiter pipeline depth (0-3) */
 103 #define CFG_ACR_RPTCNT          3       /* Arbiter repeat count (0-7) */
 104
 105 /* System Priority Control Regsiter */
 106 #define CFG_SPCR_TSECEP         3       /* eTSEC1&2 emergency priority (0-3) */
 107
 108 /* System Clock Configuration Register */
 109 #define CFG_SCCR_TSEC1CM        1               /* eTSEC1 clock mode (0-3) */
 110 #define CFG_SCCR_TSEC2CM        1               /* eTSEC2 clock mode (0-3) */
 111 #define CFG_SCCR_SATACM         SCCR_SATACM_1   /* SATA1-4 clock mode (0-3) */
 112
 113 /*
 114  * System IO Config
 115  */
 116 #define CFG_SICRH               0x08200000
 117 #define CFG_SICRL               0x00000000
 118
 119 /*
 120  * Output Buffer Impedance
 121  */
 122 #define CFG_OBIR                0x30100000
 123
 124 /*
 125  * IMMR new address
 126  */
 127 #define CFG_IMMR                0xE0000000
 128
 129 /*
 130  * Device configurations
 131  */
 132
 133 /* Vitesse 7385 */
 134
 135 #ifdef CONFIG_VSC7385_ENET
 136
 137 #define CONFIG_TSEC2
 138
 139 /* The flash address and size of the VSC7385 firmware image */
 140 #define CONFIG_VSC7385_IMAGE            0xFE7FE000
 141 #define CONFIG_VSC7385_IMAGE_SIZE       8192
 142
 143 #endif
 144
 145 /*
 146  * DDR Setup
 147  */
 148 #define CFG_DDR_BASE            0x00000000 /* DDR is system memory */
 149 #define CFG_SDRAM_BASE          CFG_DDR_BASE
 150 #define CFG_DDR_SDRAM_BASE      CFG_DDR_BASE
 151 #define CFG_DDR_SDRAM_CLK_CNTL  0x03000000
 152 #define CFG_83XX_DDR_USES_CS0
 153
 154 #define CFG_DDRCDR_VALUE        (DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN)
 155
 156 #undef CONFIG_DDR_ECC           /* support DDR ECC function */
 157 #undef CONFIG_DDR_ECC_CMD       /* Use DDR ECC user commands */
 158
 159 #undef CONFIG_NEVER_ASSERT_ODT_TO_CPU   /* Never assert ODT to internal IOs */
 160
 161 /*
 162  * Manually set up DDR parameters
 163  */
 164 #define CFG_DDR_SIZE            256             /* MB */
 165 #define CFG_DDR_CS0_BNDS        0x0000000f
 166 #define CFG_DDR_CS0_CONFIG      (CSCONFIG_EN | CSCONFIG_ODT_WR_ACS \
 167                                 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
 168
 169 #define CFG_DDR_TIMING_3        0x00000000
 170 #define CFG_DDR_TIMING_0        ((0 << TIMING_CFG0_RWT_SHIFT) \
 171                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
 172                                 | (0 << TIMING_CFG0_RRT_SHIFT) \
 173                                 | (0 << TIMING_CFG0_WWT_SHIFT) \
 174                                 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
 175                                 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
 176                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
 177                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
 178                                 /* 0x00220802 */
 179                                 /* 0x00260802 */ /* DDR400 */
 180 #define CFG_DDR_TIMING_1        ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
 181                                 | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
 182                                 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
 183                                 | (7 << TIMING_CFG1_CASLAT_SHIFT) \
 184                                 | (13 << TIMING_CFG1_REFREC_SHIFT) \
 185                                 | (3 << TIMING_CFG1_WRREC_SHIFT) \
 186                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
 187                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
 188                                 /* 0x3935d322 */
 189                                 /* 0x3937d322 */
 190 #define CFG_DDR_TIMING_2        0x02984cc8
 191
 192 #define CFG_DDR_INTERVAL        ((1545 << SDRAM_INTERVAL_REFINT_SHIFT) \
 193                                 | (256 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
 194                                 /* 0x06090100 */
 195
 196 #if defined(CONFIG_DDR_2T_TIMING)
 197 #define CFG_DDR_SDRAM_CFG               (SDRAM_CFG_SREN \
 198                                 | 3 << SDRAM_CFG_SDRAM_TYPE_SHIFT \
 199                                 | SDRAM_CFG_2T_EN \
 200                                 | SDRAM_CFG_DBW_32)
 201 #else
 202 #define CFG_DDR_SDRAM_CFG               (SDRAM_CFG_SREN \
 203                                 | 3 << SDRAM_CFG_SDRAM_TYPE_SHIFT)
 204                                 /* 0x43000000 */
 205 #endif
 206 #define CFG_DDR_SDRAM_CFG2      0x00001000 /* 1 posted refresh */
 207 #define CFG_DDR_MODE            ((0x0440 << SDRAM_MODE_ESD_SHIFT) \
 208                                 | (0x0442 << SDRAM_MODE_SD_SHIFT))
 209                                 /* 0x04400442 */ /* DDR400 */
 210 #define CFG_DDR_MODE2           0x00000000;
 211
 212 /*
 213  * Memory test
 214  */
 215 #undef CFG_DRAM_TEST            /* memory test, takes time */
 216 #define CFG_MEMTEST_START       0x00040000 /* memtest region */
 217 #define CFG_MEMTEST_END         0x0ef70010
 218
 219 /*
 220  * The reserved memory
 221  */
 222 #define CFG_MONITOR_BASE        TEXT_BASE /* start of monitor */
 223
 224 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
 225 #define CFG_RAMBOOT
 226 #else
 227 #undef  CFG_RAMBOOT
 228 #endif
 229
 230 #define CFG_MONITOR_LEN         (256 * 1024) /* Reserve 256 kB for Mon */
 231 #define CFG_MALLOC_LEN          (512 * 1024) /* Reserved for malloc */
 232
 233 /*
 234  * Initial RAM Base Address Setup
 235  */
 236 #define CFG_INIT_RAM_LOCK       1
 237 #define CFG_INIT_RAM_ADDR       0xE6000000 /* Initial RAM address */
 238 #define CFG_INIT_RAM_END        0x1000 /* End of used area in RAM */
 239 #define CFG_GBL_DATA_SIZE       0x100 /* num bytes initial data */
 240 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 241
 242 /*
 243  * Local Bus Configuration & Clock Setup
 244  */
 245 #define CFG_LCRR                (LCRR_DBYP | LCRR_CLKDIV_8)
 246 #define CFG_LBC_LBCR            0x00000000
 247
 248 /*
 249  * FLASH on the Local Bus
 250  */
 251 #define CFG_FLASH_CFI           /* use the Common Flash Interface */
 252 #define CFG_FLASH_CFI_DRIVER    /* use the CFI driver */
 253 #define CFG_FLASH_BASE          0xFE000000 /* FLASH base address */
 254 #define CFG_FLASH_SIZE          8 /* max FLASH size is 32M */
 255
 256 #define CFG_FLASH_EMPTY_INFO                    /* display empty sectors */
 257 #define CFG_FLASH_USE_BUFFER_WRITE              /* buffer up multiple bytes */
 258
 259 #define CFG_LBLAWBAR0_PRELIM    CFG_FLASH_BASE /* Window base at flash base */
 260 #define CFG_LBLAWAR0_PRELIM     0x80000016      /* 8 MB window size */
 261
 262 #define CFG_BR0_PRELIM          (CFG_FLASH_BASE | /* Flash Base address */ \
 263                                 (2 << BR_PS_SHIFT) | /* 16 bit port size */ \
 264                                 BR_V) /* valid */
 265 #define CFG_OR0_PRELIM          (0xFF800000             /* 8 MByte */ \
 266                                 | OR_GPCM_XACS \
 267                                 | OR_GPCM_SCY_9 \
 268                                 | OR_GPCM_EHTR \
 269                                 | OR_GPCM_EAD)
 270                                 /* 0xFF806FF7   TODO SLOW 8 MB flash size */
 271
 272 #define CFG_MAX_FLASH_BANKS     1 /* number of banks */
 273 #define CFG_MAX_FLASH_SECT      256 /* max sectors per device */
 274
 275 #undef  CFG_FLASH_CHECKSUM
 276 #define CFG_FLASH_ERASE_TOUT    60000   /* Flash Erase Timeout (ms) */
 277 #define CFG_FLASH_WRITE_TOUT    500     /* Flash Write Timeout (ms) */
 278
 279 /*
 280  * NAND Flash on the Local Bus
 281  */
 282 #define CFG_NAND_BASE           0xE0600000      /* 0xE0600000 */
 283 #define CFG_BR1_PRELIM          (CFG_NAND_BASE | \
 284                                  (2 << BR_DECC_SHIFT) | /* Use HW ECC */ \
 285                                  BR_PS_8 |              /* Port Size = 8 bit */ \
 286                                  BR_MS_FCM |            /* MSEL = FCM */ \
 287                                  BR_V)                  /* valid */
 288 #define CFG_OR1_PRELIM          (0xFFFF8000 |           /* length 32K */ \
 289                                  OR_FCM_CSCT | \
 290                                  OR_FCM_CST | \
 291                                  OR_FCM_CHT | \
 292                                  OR_FCM_SCY_1 | \
 293                                  OR_FCM_TRLX | \
 294                                  OR_FCM_EHTR)
 295 #define CFG_LBLAWBAR1_PRELIM    CFG_NAND_BASE
 296 #define CFG_LBLAWAR1_PRELIM     0x8000000E      /* 32KB  */
 297
 298 /* Vitesse 7385 */
 299
 300 #define CFG_VSC7385_BASE        0xF0000000
 301
 302 #ifdef CONFIG_VSC7385_ENET
 303
 304 #define CFG_BR2_PRELIM          0xf0000801              /* Base address */
 305 #define CFG_OR2_PRELIM          0xfffe09ff              /* 128K bytes*/
 306 #define CFG_LBLAWBAR2_PRELIM    CFG_VSC7385_BASE        /* Access Base */
 307 #define CFG_LBLAWAR2_PRELIM     0x80000010              /* Access Size 128K */
 308
 309 #endif
 310
 311 /*
 312  * Serial Port
 313  */
 314 #define CONFIG_CONS_INDEX       1
 315 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
 316 #define CFG_NS16550
 317 #define CFG_NS16550_SERIAL
 318 #define CFG_NS16550_REG_SIZE    1
 319 #define CFG_NS16550_CLK         get_bus_freq(0)
 320
 321 #define CFG_BAUDRATE_TABLE \
 322         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 323
 324 #define CFG_NS16550_COM1        (CFG_IMMR+0x4500)
 325 #define CFG_NS16550_COM2        (CFG_IMMR+0x4600)
 326
 327 /* SERDES */
 328 #define CONFIG_FSL_SERDES
 329 #define CONFIG_FSL_SERDES1      0xe3000
 330 #define CONFIG_FSL_SERDES2      0xe3100
 331
 332 /* Use the HUSH parser */
 333 #define CFG_HUSH_PARSER
 334 #ifdef  CFG_HUSH_PARSER
 335 #define CFG_PROMPT_HUSH_PS2 "> "
 336 #endif
 337
 338 /* Pass open firmware flat tree */
 339 #define CONFIG_OF_LIBFDT        1
 340 #define CONFIG_OF_BOARD_SETUP   1
 341 #define CONFIG_OF_STDOUT_VIA_ALIAS 1
 342
 343 /* I2C */
 344 #define CONFIG_HARD_I2C         /* I2C with hardware support */
 345 #undef  CONFIG_SOFT_I2C         /* I2C bit-banged */
 346 #define CONFIG_FSL_I2C
 347 #define CFG_I2C_SPEED           400000 /* I2C speed and slave address */
 348 #define CFG_I2C_SLAVE           0x7F
 349 #define CFG_I2C_NOPROBES        {0x51} /* Don't probe these addrs */
 350 #define CFG_I2C_OFFSET          0x3000
 351 #define CFG_I2C2_OFFSET         0x3100
 352
 353 /*
 354  * Config on-board RTC
 355  */
 356 #define CONFIG_RTC_DS1374       /* use ds1374 rtc via i2c */
 357 #define CFG_I2C_RTC_ADDR        0x68 /* at address 0x68 */
 358
 359 /*
 360  * General PCI
 361  * Addresses are mapped 1-1.
 362  */
 363 #define CFG_PCI_MEM_BASE        0x80000000
 364 #define CFG_PCI_MEM_PHYS        CFG_PCI_MEM_BASE
 365 #define CFG_PCI_MEM_SIZE        0x10000000 /* 256M */
 366 #define CFG_PCI_MMIO_BASE       0x90000000
 367 #define CFG_PCI_MMIO_PHYS       CFG_PCI_MMIO_BASE
 368 #define CFG_PCI_MMIO_SIZE       0x10000000 /* 256M */
 369 #define CFG_PCI_IO_BASE         0x00000000
 370 #define CFG_PCI_IO_PHYS         0xE0300000
 371 #define CFG_PCI_IO_SIZE         0x100000 /* 1M */
 372
 373 #define CFG_PCI_SLV_MEM_LOCAL   CFG_SDRAM_BASE
 374 #define CFG_PCI_SLV_MEM_BUS     0x00000000
 375 #define CFG_PCI_SLV_MEM_SIZE    0x80000000
 376
 377 #ifdef CONFIG_PCI
 378 #define CONFIG_NET_MULTI
 379 #define CONFIG_PCI_PNP          /* do pci plug-and-play */
 380
 381 #undef CONFIG_PCI_SCAN_SHOW     /* show pci devices on startup */
 382 #define CFG_PCI_SUBSYS_VENDORID 0x1957  /* Freescale */
 383 #endif  /* CONFIG_PCI */
 384
 385 /*
 386  * TSEC
 387  */
 388 #ifdef CONFIG_TSEC_ENET
 389
 390 #define CONFIG_NET_MULTI
 391 #define CONFIG_GMII                     /* MII PHY management */
 392
 393 #define CONFIG_TSEC1
 394
 395 #ifdef CONFIG_TSEC1
 396 #define CONFIG_HAS_ETH0
 397 #define CONFIG_TSEC1_NAME               "TSEC0"
 398 #define CFG_TSEC1_OFFSET                0x24000
 399 #define TSEC1_PHY_ADDR                  2
 400 #define TSEC1_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 401 #define TSEC1_PHYIDX                    0
 402 #endif
 403
 404 #ifdef CONFIG_TSEC2
 405 #define CONFIG_HAS_ETH1
 406 #define CONFIG_TSEC2_NAME               "TSEC1"
 407 #define CFG_TSEC2_OFFSET                0x25000
 408 #define TSEC2_PHY_ADDR                  0x1c
 409 #define TSEC2_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 410 #define TSEC2_PHYIDX                    0
 411 #endif
 412
 413 /* Options are: TSEC[0-1] */
 414 #define CONFIG_ETHPRIME                 "TSEC0"
 415
 416 #endif
 417
 418 /*
 419  * SATA
 420  */
 421 #define CONFIG_LIBATA
 422 #define CONFIG_FSL_SATA
 423
 424 #define CFG_SATA_MAX_DEVICE     2
 425 #define CONFIG_SATA1
 426 #define CFG_SATA1_OFFSET        0x18000
 427 #define CFG_SATA1               (CFG_IMMR + CFG_SATA1_OFFSET)
 428 #define CFG_SATA1_FLAGS         FLAGS_DMA
 429 #define CONFIG_SATA2
 430 #define CFG_SATA2_OFFSET        0x19000
 431 #define CFG_SATA2               (CFG_IMMR + CFG_SATA2_OFFSET)
 432 #define CFG_SATA2_FLAGS         FLAGS_DMA
 433
 434 #ifdef CONFIG_FSL_SATA
 435 #define CONFIG_LBA48
 436 #define CONFIG_CMD_SATA
 437 #define CONFIG_DOS_PARTITION
 438 #define CONFIG_CMD_EXT2
 439 #endif
 440
 441 /*
 442  * Environment
 443  */
 444 #ifndef CFG_RAMBOOT
 445         #define CFG_ENV_IS_IN_FLASH     1
 446         #define CFG_ENV_ADDR            (CFG_MONITOR_BASE+CFG_MONITOR_LEN)
 447         #define CFG_ENV_SECT_SIZE       0x10000 /* 64K (one sector) for env */
 448         #define CFG_ENV_SIZE            0x4000
 449 #else
 450         #define CFG_NO_FLASH            1       /* Flash is not usable now */
 451         #define CFG_ENV_IS_NOWHERE      1       /* Store ENV in memory only */
 452         #define CFG_ENV_ADDR            (CFG_MONITOR_BASE-0x1000)
 453         #define CFG_ENV_SIZE            0x2000
 454 #endif
 455
 456 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 457 #define CFG_LOADS_BAUD_CHANGE   1       /* allow baudrate change */
 458
 459 /*
 460  * BOOTP options
 461  */
 462 #define CONFIG_BOOTP_BOOTFILESIZE
 463 #define CONFIG_BOOTP_BOOTPATH
 464 #define CONFIG_BOOTP_GATEWAY
 465 #define CONFIG_BOOTP_HOSTNAME
 466
 467
 468 /*
 469  * Command line configuration.
 470  */
 471 #include <config_cmd_default.h>
 472
 473 #define CONFIG_CMD_PING
 474 #define CONFIG_CMD_I2C
 475 #define CONFIG_CMD_MII
 476 #define CONFIG_CMD_DATE
 477
 478 #if defined(CONFIG_PCI)
 479 #define CONFIG_CMD_PCI
 480 #endif
 481
 482 #if defined(CFG_RAMBOOT)
 483 #undef CONFIG_CMD_ENV
 484 #undef CONFIG_CMD_LOADS
 485 #endif
 486
 487 #define CONFIG_CMDLINE_EDITING  1       /* add command line history */
 488
 489 #undef CONFIG_WATCHDOG          /* watchdog disabled */
 490
 491 /*
 492  * Miscellaneous configurable options
 493  */
 494 #define CFG_LONGHELP            /* undef to save memory */
 495 #define CFG_LOAD_ADDR           0x2000000 /* default load address */
 496 #define CFG_PROMPT              "=> "   /* Monitor Command Prompt */
 497
 498 #if defined(CONFIG_CMD_KGDB)
 499         #define CFG_CBSIZE      1024 /* Console I/O Buffer Size */
 500 #else
 501         #define CFG_CBSIZE      256 /* Console I/O Buffer Size */
 502 #endif
 503
 504 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 505 #define CFG_MAXARGS     16              /* max number of command args */
 506 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size */
 507 #define CFG_HZ          1000            /* decrementer freq: 1ms ticks */
 508
 509 /*
 510  * For booting Linux, the board info and command line data
 511  * have to be in the first 8 MB of memory, since this is
 512  * the maximum mapped by the Linux kernel during initialization.
 513  */
 514 #define CFG_BOOTMAPSZ           (8 << 20) /* Initial Memory map for Linux */
 515
 516 /*
 517  * Core HID Setup
 518  */
 519 #define CFG_HID0_INIT           0x000000000
 520 #define CFG_HID0_FINAL          HID0_ENABLE_MACHINE_CHECK
 521 #define CFG_HID2                HID2_HBE
 522
 523 /*
 524  * MMU Setup
 525  */
 526
 527 /* DDR: cache cacheable */
 528 #define CFG_SDRAM_LOWER         CFG_SDRAM_BASE
 529 #define CFG_SDRAM_UPPER         (CFG_SDRAM_BASE + 0x10000000)
 530
 531 #define CFG_IBAT0L      (CFG_SDRAM_LOWER | BATL_PP_10 | BATL_MEMCOHERENCE)
 532 #define CFG_IBAT0U      (CFG_SDRAM_LOWER | BATU_BL_256M | BATU_VS | BATU_VP)
 533 #define CFG_DBAT0L      CFG_IBAT0L
 534 #define CFG_DBAT0U      CFG_IBAT0U
 535
 536 #define CFG_IBAT1L      (CFG_SDRAM_UPPER | BATL_PP_10 | BATL_MEMCOHERENCE)
 537 #define CFG_IBAT1U      (CFG_SDRAM_UPPER | BATU_BL_256M | BATU_VS | BATU_VP)
 538 #define CFG_DBAT1L      CFG_IBAT1L
 539 #define CFG_DBAT1U      CFG_IBAT1U
 540
 541 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
 542 #define CFG_IBAT2L      (CFG_IMMR | BATL_PP_10 | \
 543                         BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 544 #define CFG_IBAT2U      (CFG_IMMR | BATU_BL_8M | BATU_VS | BATU_VP)
 545 #define CFG_DBAT2L      CFG_IBAT2L
 546 #define CFG_DBAT2U      CFG_IBAT2U
 547
 548 /* L2 Switch: cache-inhibit and guarded */
 549 #define CFG_IBAT3L      (CFG_VSC7385_BASE | BATL_PP_10 | \
 550                         BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 551 #define CFG_IBAT3U      (CFG_VSC7385_BASE | BATU_BL_128K | BATU_VS | BATU_VP)
 552 #define CFG_DBAT3L      CFG_IBAT3L
 553 #define CFG_DBAT3U      CFG_IBAT3U
 554
 555 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
 556 #define CFG_IBAT4L      (CFG_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 557 #define CFG_IBAT4U      (CFG_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
 558 #define CFG_DBAT4L      (CFG_FLASH_BASE | BATL_PP_10 | \
 559                         BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 560 #define CFG_DBAT4U      CFG_IBAT4U
 561
 562 /* Stack in dcache: cacheable, no memory coherence */
 563 #define CFG_IBAT5L      (CFG_INIT_RAM_ADDR | BATL_PP_10)
 564 #define CFG_IBAT5U      (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
 565 #define CFG_DBAT5L      CFG_IBAT5L
 566 #define CFG_DBAT5U      CFG_IBAT5U
 567
 568 #ifdef CONFIG_PCI
 569 /* PCI MEM space: cacheable */
 570 #define CFG_IBAT6L      (CFG_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
 571 #define CFG_IBAT6U      (CFG_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
 572 #define CFG_DBAT6L      CFG_IBAT6L
 573 #define CFG_DBAT6U      CFG_IBAT6U
 574 /* PCI MMIO space: cache-inhibit and guarded */
 575 #define CFG_IBAT7L      (CFG_PCI_MMIO_PHYS | BATL_PP_10 | \
 576                         BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 577 #define CFG_IBAT7U      (CFG_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
 578 #define CFG_DBAT7L      CFG_IBAT7L
 579 #define CFG_DBAT7U      CFG_IBAT7U
 580 #else
 581 #define CFG_IBAT6L      (0)
 582 #define CFG_IBAT6U      (0)
 583 #define CFG_IBAT7L      (0)
 584 #define CFG_IBAT7U      (0)
 585 #define CFG_DBAT6L      CFG_IBAT6L
 586 #define CFG_DBAT6U      CFG_IBAT6U
 587 #define CFG_DBAT7L      CFG_IBAT7L
 588 #define CFG_DBAT7U      CFG_IBAT7U
 589 #endif
 590
 591 /*
 592  * Internal Definitions
 593  *
 594  * Boot Flags
 595  */
 596 #define BOOTFLAG_COLD   0x01 /* Normal Power-On: Boot from FLASH */
 597 #define BOOTFLAG_WARM   0x02 /* Software reboot */
 598
 599 #if defined(CONFIG_CMD_KGDB)
 600 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 601 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 602 #endif
 603
 604 /*
 605  * Environment Configuration
 606  */
 607 #define CONFIG_ENV_OVERWRITE
 608
 609 #ifdef CONFIG_HAS_ETH0
 610 #define CONFIG_ETHADDR          00:04:9f:ef:04:01
 611 #endif
 612
 613 #ifdef CONFIG_HAS_ETH1
 614 #define CONFIG_ETH1ADDR         00:04:9f:ef:04:02
 615 #endif
 616
 617 #define CONFIG_HAS_FSL_DR_USB
 618
 619 #define CONFIG_IPADDR           10.0.0.2
 620 #define CONFIG_SERVERIP         10.0.0.1
 621 #define CONFIG_GATEWAYIP        10.0.0.1
 622 #define CONFIG_NETMASK          255.0.0.0
 623 #define CONFIG_NETDEV           eth1
 624
 625 #define CONFIG_HOSTNAME         mpc837x_rdb
 626 #define CONFIG_ROOTPATH         /nfsroot
 627 #define CONFIG_RAMDISKFILE      rootfs.ext2.gz.uboot
 628 #define CONFIG_BOOTFILE         uImage
 629 #define CONFIG_UBOOTPATH        u-boot.bin      /* U-Boot image on TFTP server */
 630 #define CONFIG_FDTFILE          mpc8379_rdb.dtb
 631
 632 #define CONFIG_LOADADDR         200000  /* default location for tftp and bootm */
 633 #define CONFIG_BOOTDELAY        -1      /* -1 disables auto-boot */
 634 #define CONFIG_BAUDRATE         115200
 635
 636 #define XMK_STR(x)      #x
 637 #define MK_STR(x)       XMK_STR(x)
 638
 639 #define CONFIG_EXTRA_ENV_SETTINGS \
 640         "netdev=" MK_STR(CONFIG_NETDEV) "\0"                            \
 641         "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"                          \
 642         "tftpflash=tftp $loadaddr $uboot;"                              \
 643                 "protect off " MK_STR(TEXT_BASE) " +$filesize; "        \
 644                 "erase " MK_STR(TEXT_BASE) " +$filesize; "              \
 645                 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; "      \
 646                 "protect on " MK_STR(TEXT_BASE) " +$filesize; "         \
 647                 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0"     \
 648         "fdtaddr=400000\0"                                              \
 649         "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0"                          \
 650         "ramdiskaddr=1000000\0"                                         \
 651         "ramdiskfile=" MK_STR(CONFIG_RAMDISKFILE) "\0"                  \
 652         "console=ttyS0\0"                                               \
 653         "setbootargs=setenv bootargs "                                  \
 654                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
 655         "setipargs=setenv bootargs nfsroot=$serverip:$rootpath "        \
 656                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 657                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
 658
 659 #define CONFIG_NFSBOOTCOMMAND                                           \
 660         "setenv rootdev /dev/nfs;"                                      \
 661         "run setbootargs;"                                              \
 662         "run setipargs;"                                                \
 663         "tftp $loadaddr $bootfile;"                                     \
 664         "tftp $fdtaddr $fdtfile;"                                       \
 665         "bootm $loadaddr - $fdtaddr"
 666
 667 #define CONFIG_RAMBOOTCOMMAND                                           \
 668         "setenv rootdev /dev/ram;"                                      \
 669         "run setbootargs;"                                              \
 670         "tftp $ramdiskaddr $ramdiskfile;"                               \
 671         "tftp $loadaddr $bootfile;"                                     \
 672         "tftp $fdtaddr $fdtfile;"                                       \
 673         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 674
 675 #undef MK_STR
 676 #undef XMK_STR
 677
 678 #endif  /* __CONFIG_H */