include/configs/DP405.h

   1 /*
   2  * (C) Copyright 2001-2003
   3  * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * board/config.h - configuration options, board specific
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /*
  32  * High Level Configuration Options
  33  * (easy to change)
  34  */
  35
  36 #define CONFIG_405EP            1       /* This is a PPC405 CPU         */
  37 #define CONFIG_4xx              1       /* ...member of PPC4xx family   */
  38 #define CONFIG_DP405            1       /* ...on a DP405 board          */
  39
  40 #define CONFIG_BOARD_EARLY_INIT_F 1     /* call board_early_init_f()    */
  41 #define CONFIG_MISC_INIT_R      1       /* call misc_init_r()           */
  42
  43 #define CONFIG_SYS_CLK_FREQ     33333300 /* external frequency to pll   */
  44
  45 #define CONFIG_BAUDRATE         9600
  46 #define CONFIG_BOOTDELAY        3       /* autoboot after 3 seconds     */
  47
  48 #undef  CONFIG_BOOTARGS
  49 #undef  CONFIG_BOOTCOMMAND
  50
  51 #define CONFIG_PREBOOT                  /* enable preboot variable      */
  52
  53 #define CFG_LOADS_BAUD_CHANGE   1       /* allow baudrate change        */
  54
  55 #define CONFIG_MII              1       /* MII PHY management           */
  56 #define CONFIG_PHY_ADDR         0       /* PHY address                  */
  57
  58
  59 /*
  60  * BOOTP options
  61  */
  62 #define CONFIG_BOOTP_BOOTFILESIZE
  63 #define CONFIG_BOOTP_BOOTPATH
  64 #define CONFIG_BOOTP_GATEWAY
  65 #define CONFIG_BOOTP_HOSTNAME
  66
  67
  68 /*
  69  * Command line configuration.
  70  */
  71 #include <config_cmd_default.h>
  72
  73 #define CONFIG_CMD_BSP
  74 #define CONFIG_CMD_DHCP
  75 #define CONFIG_CMD_IRQ
  76 #define CONFIG_CMD_ELF
  77 #define CONFIG_CMD_DATE
  78 #define CONFIG_CMD_I2C
  79 #define CONFIG_CMD_EEPROM
  80
  81
  82 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  83
  84 #define CONFIG_RTC_MC146818             /* DS1685 is MC146818 compatible*/
  85 #define CFG_RTC_REG_BASE_ADDR    0xF0000500 /* RTC Base Address         */
  86
  87 #define CONFIG_SDRAM_BANK0      1       /* init onboard SDRAM bank 0    */
  88
  89 #define CONFIG_PRAM             2       /* reserve 2 kB "protected RAM" */
  90
  91 /*
  92  * Miscellaneous configurable options
  93  */
  94 #define CFG_LONGHELP                    /* undef to save memory         */
  95 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt       */
  96
  97 #undef  CFG_HUSH_PARSER                 /* use "hush" command parser    */
  98 #ifdef  CFG_HUSH_PARSER
  99 #define CFG_PROMPT_HUSH_PS2     "> "
 100 #endif
 101
 102 #if defined(CONFIG_CMD_KGDB)
 103 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size      */
 104 #else
 105 #define CFG_CBSIZE      256             /* Console I/O Buffer Size      */
 106 #endif
 107 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 108 #define CFG_MAXARGS     16              /* max number of command args   */
 109 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 110
 111 #define CFG_DEVICE_NULLDEV      1       /* include nulldev device       */
 112
 113 #define CFG_CONSOLE_INFO_QUIET  1       /* don't print console @ startup*/
 114
 115 #define CFG_MEMTEST_START       0x0400000       /* memtest works on     */
 116 #define CFG_MEMTEST_END         0x0C00000       /* 4 ... 12 MB in DRAM  */
 117
 118 #undef  CFG_EXT_SERIAL_CLOCK           /* no external serial clock used */
 119 #define CFG_IGNORE_405_UART_ERRATA_59   /* ignore ppc405gp errata #59   */
 120 #define CFG_BASE_BAUD       691200
 121 #undef  CONFIG_UART1_CONSOLE            /* define for uart1 as console  */
 122
 123 /* The following table includes the supported baudrates */
 124 #define CFG_BAUDRATE_TABLE      \
 125         { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 126          57600, 115200, 230400, 460800, 921600 }
 127
 128 #define CFG_LOAD_ADDR   0x100000        /* default load address */
 129 #define CFG_EXTBDINFO   1               /* To use extended board_into (bd_t) */
 130
 131 #define CFG_HZ          1000            /* decrementer freq: 1 ms ticks */
 132
 133 #define CONFIG_ZERO_BOOTDELAY_CHECK     /* check for keypress on bootdelay==0 */
 134
 135 #define CONFIG_VERSION_VARIABLE 1       /* include version env variable */
 136
 137 #define CFG_RX_ETH_BUFFER       16      /* use 16 rx buffer on 405 emac */
 138
 139 /*-----------------------------------------------------------------------
 140  * PCI stuff
 141  *-----------------------------------------------------------------------
 142  */
 143 #define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
 144 #define PCI_HOST_FORCE  1               /* configure as pci host        */
 145 #define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
 146
 147 #define CONFIG_PCI                      /* include pci support          */
 148 #define CONFIG_PCI_HOST PCI_HOST_HOST   /* select pci host function     */
 149 #undef  CONFIG_PCI_PNP                  /* do pci plug-and-play         */
 150                                         /* resource configuration       */
 151
 152 #undef  CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
 153
 154 #define CFG_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
 155 #define CFG_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
 156 #define CFG_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
 157 #define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
 158 #define CFG_PCI_PTM1MS  0xfc000001      /* 64MB, enable hard-wired to 1 */
 159 #define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
 160 #define CFG_PCI_PTM2LA  0xffc00000      /* point to flash               */
 161 #define CFG_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
 162 #define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
 163
 164 /*
 165  * For booting Linux, the board info and command line data
 166  * have to be in the first 8 MB of memory, since this is
 167  * the maximum mapped by the Linux kernel during initialization.
 168  */
 169 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 170 /*-----------------------------------------------------------------------
 171  * FLASH organization
 172  */
 173 #define FLASH_BASE0_PRELIM      0xFFC00000      /* FLASH bank #0        */
 174
 175 #define CFG_MAX_FLASH_BANKS     1       /* max number of memory banks           */
 176 #define CFG_MAX_FLASH_SECT      256     /* max number of sectors on one chip    */
 177
 178 #define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)      */
 179 #define CFG_FLASH_WRITE_TOUT    1000    /* Timeout for Flash Write (in ms)      */
 180
 181 #define CFG_FLASH_WORD_SIZE     unsigned short  /* flash word size (width)      */
 182 #define CFG_FLASH_ADDR0         0x5555  /* 1st address for flash config cycles  */
 183 #define CFG_FLASH_ADDR1         0x2AAA  /* 2nd address for flash config cycles  */
 184 /*
 185  * The following defines are added for buggy IOP480 byte interface.
 186  * All other boards should use the standard values (CPCI405 etc.)
 187  */
 188 #define CFG_FLASH_READ0         0x0000  /* 0 is standard                        */
 189 #define CFG_FLASH_READ1         0x0001  /* 1 is standard                        */
 190 #define CFG_FLASH_READ2         0x0002  /* 2 is standard                        */
 191
 192 #define CFG_FLASH_EMPTY_INFO            /* print 'E' for empty sector on flinfo */
 193
 194 #if 0 /* test-only */
 195 #define CFG_JFFS2_FIRST_BANK    0           /* use for JFFS2 */
 196 #define CFG_JFFS2_NUM_BANKS     1           /* ! second bank contains U-Boot */
 197 #endif
 198
 199 /*-----------------------------------------------------------------------
 200  * Start addresses for the final memory configuration
 201  * (Set up by the startup code)
 202  * Please note that CFG_SDRAM_BASE _must_ start at 0
 203  */
 204 #define CFG_SDRAM_BASE          0x00000000
 205 #define CFG_FLASH_BASE          0xFFFC0000
 206 #define CFG_MONITOR_BASE        TEXT_BASE
 207 #define CFG_MONITOR_LEN         (256 * 1024)    /* Reserve 256 kB for Monitor   */
 208 #define CFG_MALLOC_LEN          (256 * 1024)    /* Reserve 256 kB for malloc()  */
 209
 210 #if (CFG_MONITOR_BASE < FLASH_BASE0_PRELIM)
 211 # define CFG_RAMBOOT            1
 212 #else
 213 # undef CFG_RAMBOOT
 214 #endif
 215
 216 /*-----------------------------------------------------------------------
 217  * Environment Variable setup
 218  */
 219 #define CFG_ENV_IS_IN_EEPROM    1       /* use EEPROM for environment vars */
 220 #define CFG_ENV_OFFSET          0x100   /* environment starts at the beginning of the EEPROM */
 221 #define CFG_ENV_SIZE            0x700   /* 2048 bytes may be used for env vars*/
 222                                    /* total size of a CAT24WC16 is 2048 bytes */
 223
 224 #define CFG_NVRAM_BASE_ADDR     0xF0000500              /* NVRAM base address   */
 225 #define CFG_NVRAM_SIZE          242                     /* NVRAM size           */
 226
 227 /*-----------------------------------------------------------------------
 228  * I2C EEPROM (CAT24WC16) for environment
 229  */
 230 #define CONFIG_HARD_I2C                 /* I2c with hardware support */
 231 #define CFG_I2C_SPEED           400000  /* I2C speed and slave address */
 232 #define CFG_I2C_SLAVE           0x7F
 233
 234 #define CFG_I2C_EEPROM_ADDR     0x50    /* EEPROM CAT28WC08             */
 235 #define CFG_I2C_EEPROM_ADDR_LEN 1       /* Bytes of address             */
 236 /* mask of address bits that overflow into the "EEPROM chip address"    */
 237 #define CFG_I2C_EEPROM_ADDR_OVERFLOW    0x07
 238 #define CFG_EEPROM_PAGE_WRITE_BITS 4    /* The Catalyst CAT24WC08 has   */
 239                                         /* 16 byte page write mode using*/
 240                                         /* last 4 bits of the address   */
 241 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS  10   /* and takes up to 10 msec */
 242 #define CFG_EEPROM_PAGE_WRITE_ENABLE
 243
 244 /*-----------------------------------------------------------------------
 245  * External Bus Controller (EBC) Setup
 246  */
 247
 248 #define CAN_BA          0xF0000000          /* CAN Base Address                 */
 249 #define RTC_BA          0xF0000500          /* RTC Base Address                 */
 250
 251 /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization                       */
 252 #define CFG_EBC_PB0AP           0x92015480
 253 #define CFG_EBC_PB0CR           0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
 254
 255 #if 0 /* test-only */
 256 /* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization                      */
 257 #define CFG_EBC_PB1AP           0x92015480
 258 #define CFG_EBC_PB1CR           0xF4018000  /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit  */
 259 #endif
 260
 261 /* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization              */
 262 #define CFG_EBC_PB2AP           0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
 263 #define CFG_EBC_PB2CR           0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
 264
 265 /*-----------------------------------------------------------------------
 266  * FPGA stuff
 267  */
 268 #define CFG_FPGA_XC95XL         1           /* using Xilinx XC95XL CPLD      */
 269 #define CFG_FPGA_MAX_SIZE       32*1024     /* 32kByte is enough for CPLD    */
 270
 271 /* FPGA program pin configuration */
 272 #define CFG_FPGA_PRG            0x04000000  /* JTAG TMS pin (ppc output)     */
 273 #define CFG_FPGA_CLK            0x02000000  /* JTAG TCK pin (ppc output)     */
 274 #define CFG_FPGA_DATA           0x01000000  /* JTAG TDO->TDI data pin (ppc output) */
 275 #define CFG_FPGA_INIT           0x00010000  /* unused (ppc input)            */
 276 #define CFG_FPGA_DONE           0x00008000  /* JTAG TDI->TDO pin (ppc input) */
 277
 278 /*-----------------------------------------------------------------------
 279  * Definitions for initial stack pointer and data area (in data cache)
 280  */
 281 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
 282 #define CFG_TEMP_STACK_OCM        1
 283
 284 /* On Chip Memory location */
 285 #define CFG_OCM_DATA_ADDR       0xF8000000
 286 #define CFG_OCM_DATA_SIZE       0x1000
 287 #define CFG_INIT_RAM_ADDR       CFG_OCM_DATA_ADDR /* inside of SDRAM            */
 288 #define CFG_INIT_RAM_END        CFG_OCM_DATA_SIZE /* End of used area in RAM    */
 289
 290 #define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
 291 #define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 292 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 293
 294 /*-----------------------------------------------------------------------
 295  * Definitions for GPIO setup (PPC405EP specific)
 296  *
 297  * GPIO0[0]     - External Bus Controller BLAST output
 298  * GPIO0[1-9]   - Instruction trace outputs -> GPIO
 299  * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
 300  * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
 301  * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
 302  * GPIO0[24-27] - UART0 control signal inputs/outputs
 303  * GPIO0[28-29] - UART1 data signal input/output
 304  * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
 305  */
 306 /* GPIO Input:          OSR=00, ISR=00, TSR=00, TCR=0 */
 307 /* GPIO Output:         OSR=00, ISR=00, TSR=00, TCR=1 */
 308 /* Alt. Funtion Input:  OSR=00, ISR=01, TSR=00, TCR=0 */
 309 /* Alt. Funtion Output: OSR=01, ISR=00, TSR=00, TCR=1 */
 310 #define CFG_GPIO0_OSRH          0x40000540  /*  0 ... 15 */
 311 #define CFG_GPIO0_OSRL          0x00000110  /* 16 ... 31 */
 312 #define CFG_GPIO0_ISR1H         0x00000000  /*  0 ... 15 */
 313 #define CFG_GPIO0_ISR1L         0x14000045  /* 16 ... 31 */
 314 #define CFG_GPIO0_TSRH          0x00000000  /*  0 ... 15 */
 315 #define CFG_GPIO0_TSRL          0x00000000  /* 16 ... 31 */
 316 #define CFG_GPIO0_TCR           0xF7FE0014  /*  0 ... 31 */
 317
 318 /*
 319  * Internal Definitions
 320  *
 321  * Boot Flags
 322  */
 323 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 324 #define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 325
 326 /*
 327  * Default speed selection (cpu_plb_opb_ebc) in mhz.
 328  * This value will be set if iic boot eprom is disabled.
 329  */
 330 #if 0
 331 #define PLLMR0_DEFAULT   PLLMR0_266_133_66_33
 332 #define PLLMR1_DEFAULT   PLLMR1_266_133_66_33
 333 #endif
 334 #if 0
 335 #define PLLMR0_DEFAULT   PLLMR0_200_100_50_33
 336 #define PLLMR1_DEFAULT   PLLMR1_200_100_50_33
 337 #endif
 338 #if 1
 339 #define PLLMR0_DEFAULT   PLLMR0_133_66_66_33
 340 #define PLLMR1_DEFAULT   PLLMR1_133_66_66_33
 341 #endif
 342
 343 #endif  /* __CONFIG_H */