include/configs/DK1S10_mtx_ldk_20.h

   1 /*
   2  * (C) Copyright 2003, Li-Pro.Net <www.li-pro.net>
   3  * Stephan Linz <linz@li-pro.net>
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #ifndef __CONFIG_DK1S10_MTX_LDK_20_H
  25 #define __CONFIG_DK1S10_MTX_LDK_20_H
  26
  27 /*
  28  * NIOS CPU configuration. (PART OF configs/DK1S10.h)
  29  *
  30  * Here we must define CPU dependencies. Any unsupported option have to
  31  * be defined with zero, example CPU without data cache / OCI:
  32  *
  33  *      #define CFG_NIOS_CPU_ICACHE     4096
  34  *      #define CFG_NIOS_CPU_DCACHE     0
  35  *      #define CFG_NIOS_CPU_OCI_BASE   0
  36  *      #define CFG_NIOS_CPU_OCI_SIZE   0
  37  */
  38
  39 /* CPU core */
  40 #define CFG_NIOS_CPU_CLK        75000000        /* NIOS CPU clock       */
  41 #define CFG_NIOS_CPU_ICACHE     (0)             /* instruction cache    */
  42 #define CFG_NIOS_CPU_DCACHE     (0)             /* data cache           */
  43 #define CFG_NIOS_CPU_REG_NUMS   512             /* number of register   */
  44 #define CFG_NIOS_CPU_MUL        0               /* 16x16 MUL:   no(0)   */
  45                                                 /*              yes(1)  */
  46 #define CFG_NIOS_CPU_MSTEP      1               /* 16x16 MSTEP: no(0)   */
  47                                                 /*              yes(1)  */
  48 #define CFG_NIOS_CPU_STACK      0x02000000      /* stack top    addr    */
  49 #define CFG_NIOS_CPU_VEC_BASE   0x01000000      /* IRQ vectors  addr    */
  50 #define CFG_NIOS_CPU_VEC_SIZE   256             /*              size    */
  51 #define CFG_NIOS_CPU_VEC_NUMS   64              /*              numbers */
  52 #define CFG_NIOS_CPU_RST_VECT   0x00000000      /* RESET vector addr    */
  53 #define CFG_NIOS_CPU_DBG_CORE   0               /* CPU debug:   no(0)   */
  54                                                 /*              yes(1)  */
  55
  56 /* The offset address in flash to check for the Nios signature "Ni".
  57  * (see GM_FlashExec in germs_monitor.s) */
  58 #define CFG_NIOS_CPU_EXES_OFFS  0x0C
  59
  60 /* on-chip extensions */
  61 #undef  CFG_NIOS_CPU_RAM_BASE                   /* on chip RAM  addr    */
  62 #undef  CFG_NIOS_CPU_RAM_SIZE                   /* 64 KB        size    */
  63
  64 #define CFG_NIOS_CPU_ROM_BASE   0x00000000      /* on chip ROM  addr    */
  65 #define CFG_NIOS_CPU_ROM_SIZE   (2 * 1024)      /*  2 KB        size    */
  66
  67 #undef  CFG_NIOS_CPU_OCI_BASE                   /* OCI core     addr    */
  68 #undef  CFG_NIOS_CPU_OCI_SIZE                   /*              size    */
  69
  70 /* timer */
  71 #define CFG_NIOS_CPU_TIMER_NUMS 1               /* number of timer      */
  72
  73 #define CFG_NIOS_CPU_TIMER0     0x00000840      /* TIMER0       addr    */
  74 #define CFG_NIOS_CPU_TIMER0_IRQ 16              /*              IRQ     */
  75 #define CFG_NIOS_CPU_TIMER0_PER 1000            /*  periode     usec    */
  76 #define CFG_NIOS_CPU_TIMER0_AR  0               /*  always run: no(0)   */
  77                                                 /*              yes(1)  */
  78 #define CFG_NIOS_CPU_TIMER0_FP  0               /*  fixed per:  no(0)   */
  79                                                 /*              yes(1)  */
  80 #define CFG_NIOS_CPU_TIMER0_SS  1               /*  snaphot:    no(0)   */
  81                                                 /*              yes(1)  */
  82
  83 /* serial i/o */
  84 #define CFG_NIOS_CPU_UART_NUMS  2               /* number of uarts      */
  85
  86 #define CFG_NIOS_CPU_UART0      0x00000800      /* UART0        addr    */
  87 #define CFG_NIOS_CPU_UART0_IRQ  17              /*              IRQ     */
  88 #define CFG_NIOS_CPU_UART0_BR   115200          /*  baudrate    var(0)  */
  89 #define CFG_NIOS_CPU_UART0_DB   8               /*  data bit            */
  90 #define CFG_NIOS_CPU_UART0_SB   2               /*  stop bit            */
  91 #define CFG_NIOS_CPU_UART0_PA   0               /*  parity      none(0) */
  92                                                 /*              odd(1)  */
  93                                                 /*              even(2) */
  94 #define CFG_NIOS_CPU_UART0_HS   0               /*  handshake:  no(0)   */
  95                                                 /*              crts(1) */
  96 #define CFG_NIOS_CPU_UART0_EOP  0               /*  eop reg:    no(0)   */
  97                                                 /*              yes(1)  */
  98
  99 #define CFG_NIOS_CPU_UART1      0x000008a0      /* UART1        addr    */
 100 #define CFG_NIOS_CPU_UART1_IRQ  18              /*              IRQ     */
 101 #define CFG_NIOS_CPU_UART1_BR   115200          /*  baudrate    var(0)  */
 102 #define CFG_NIOS_CPU_UART1_DB   8               /*  data bit            */
 103 #define CFG_NIOS_CPU_UART1_SB   1               /*  stop bit            */
 104 #define CFG_NIOS_CPU_UART1_PA   0               /*  parity      none(0) */
 105                                                 /*              odd(1)  */
 106                                                 /*              even(2) */
 107 #define CFG_NIOS_CPU_UART1_HS   0               /*  handshake:  no(0)   */
 108                                                 /*              crts(1) */
 109 #define CFG_NIOS_CPU_UART1_EOP  0               /*  eop reg:    no(0)   */
 110                                                 /*              yes(1)  */
 111
 112 /* parallel i/o */
 113 #define CFG_NIOS_CPU_PIO_NUMS   2               /* number of parports   */
 114
 115 #define CFG_NIOS_CPU_PIO0       0x00000860      /* PIO0         addr    */
 116 #undef  CFG_NIOS_CPU_PIO0_IRQ                   /*              w/o IRQ */
 117 #define CFG_NIOS_CPU_PIO0_BITS  1               /*  number  of  bits    */
 118 #define CFG_NIOS_CPU_PIO0_TYPE  1               /*  io type:    tris(0) */
 119                                                 /*              out(1)  */
 120                                                 /*              in(2)   */
 121 #define CFG_NIOS_CPU_PIO0_CAP   0               /*  capture:    no(0)   */
 122                                                 /*              yes(1)  */
 123 #define CFG_NIOS_CPU_PIO0_EDGE  0               /*  edge type:  none(0) */
 124                                                 /*              fall(1) */
 125                                                 /*              rise(2) */
 126                                                 /*              any(3)  */
 127 #define CFG_NIOS_CPU_PIO0_ITYPE 0               /*  IRQ type:   none(0) */
 128                                                 /*              level(1)*/
 129                                                 /*              edge(2) */
 130
 131 #define CFG_NIOS_CPU_PIO1       0x00000870      /* PIO1         addr    */
 132 #undef  CFG_NIOS_CPU_PIO1_IRQ                   /*              w/o IRQ */
 133 #define CFG_NIOS_CPU_PIO1_BITS  4               /*  number  of  bits    */
 134 #define CFG_NIOS_CPU_PIO1_TYPE  2               /*  io type:    tris(0) */
 135                                                 /*              out(1)  */
 136                                                 /*              in(2)   */
 137 #define CFG_NIOS_CPU_PIO1_CAP   0               /*  capture:    no(0)   */
 138                                                 /*              yes(1)  */
 139 #define CFG_NIOS_CPU_PIO1_EDGE  0               /*  edge type:  none(0) */
 140                                                 /*              fall(1) */
 141                                                 /*              rise(2) */
 142                                                 /*              any(3)  */
 143 #define CFG_NIOS_CPU_PIO1_ITYPE 0               /*  IRQ type:   none(0) */
 144                                                 /*              level(1)*/
 145                                                 /*              edge(2) */
 146
 147 /* IDE i/f */
 148 #define CFG_NIOS_CPU_IDE_NUMS   1               /* number of IDE contr. */
 149 #define CFG_NIOS_CPU_IDE0       0x00000900      /* IDE0         addr    */
 150 #define CFG_NIOS_CPU_IDE0_IRQ   25              /*              IRQ     */
 151
 152 /* memory accessibility */
 153 #undef  CFG_NIOS_CPU_SRAM_BASE                  /* board SRAM   addr    */
 154 #undef  CFG_NIOS_CPU_SRAM_SIZE                  /*  1 MB        size    */
 155
 156 #define CFG_NIOS_CPU_SDRAM_BASE 0x01000000      /* board SDRAM  addr    */
 157 #define CFG_NIOS_CPU_SDRAM_SIZE (16*1024*1024)  /* 16 MB        size    */
 158
 159 #define CFG_NIOS_CPU_FLASH_BASE 0x00800000      /* board Flash  addr    */
 160 #define CFG_NIOS_CPU_FLASH_SIZE (8*1024*1024)   /*  8 MB        size    */
 161
 162 /* LAN */
 163 #define CFG_NIOS_CPU_LAN_NUMS   1               /* number of LAN i/f    */
 164
 165 #define CFG_NIOS_CPU_LAN0_BASE  0x00010000      /* LAN0         addr    */
 166 #define CFG_NIOS_CPU_LAN0_OFFS  0x0300          /*              offset  */
 167 #define CFG_NIOS_CPU_LAN0_IRQ   20              /*              IRQ     */
 168 #define CFG_NIOS_CPU_LAN0_BUSW  32              /*              buswidth*/
 169 #define CFG_NIOS_CPU_LAN0_TYPE  0               /*      smc91111(0)     */
 170                                                 /*      cs8900(1)       */
 171                                                 /* ex:  openmac(2)      */
 172                                                 /* ex:  alteramac(3)    */
 173
 174 /* symbolic redefinition (undef, if not present) */
 175 #define CFG_NIOS_CPU_TICK_TIMER         0       /* TIMER0: tick (needed)*/
 176 #undef  CFG_NIOS_CPU_USER_TIMER                 /* TIMERx: users choice */
 177
 178 #define CFG_NIOS_CPU_CFPOWER_PIO        0       /* PIO0: CF power/sw.   */
 179 #define CFG_NIOS_CPU_BUTTON_PIO         1       /* PIO1: buttons        */
 180 #undef  CFG_NIOS_CPU_LCD_PIO                    /* PIOx: ASCII LCD      */
 181 #undef  CFG_NIOS_CPU_LED_PIO                    /* PIOx: LED bar        */
 182 #undef  CFG_NIOS_CPU_SEVENSEG_PIO               /* PIOx: 7-seg. display */
 183 #undef  CFG_NIOS_CPU_RECONF_PIO                 /* PIOx: reconf pin     */
 184 #undef  CFG_NIOS_CPU_CFPRESENT_PIO              /* PIOx: CF present IRQ */
 185 #undef  CFG_NIOS_CPU_CFATASEL_PIO               /* PIOx: CF ATA select  */
 186
 187 #endif  /* __CONFIG_DK1S10_MTX_LDK_20_H */