include/configs/CPCI750.h

   1 /*
   2  * (C) Copyright 2001
   3  * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * board/config.h - configuration options, board specific
  26  */
  27
  28 /*************************************************************************
  29  * (c) 2004 esd gmbh Hannover
  30  *
  31  *
  32  * from db64360.h file
  33  * by Reinhard Arlt reinhard.arlt@esd-electronics.com
  34  *
  35   ************************************************************************/
  36
  37
  38 #ifndef __CONFIG_H
  39 #define __CONFIG_H
  40
  41 /* This define must be before the core.h include */
  42 #define CONFIG_CPCI750          1       /* this is an CPCI750 board     */
  43
  44 #ifndef __ASSEMBLY__
  45 #include <../board/Marvell/include/core.h>
  46 #endif
  47 /*-----------------------------------------------------*/
  48
  49 #include "../board/esd/cpci750/local.h"
  50
  51 /*
  52  * High Level Configuration Options
  53  * (easy to change)
  54  */
  55
  56 #define CONFIG_750FX                    /* we have a 750FX (override local.h) */
  57
  58 #define CONFIG_CPCI750          1       /* this is an CPCI750 board     */
  59
  60 #define CONFIG_BAUDRATE         9600    /* console baudrate = 9600      */
  61
  62 #undef  CONFIG_ECC                      /* enable ECC support */
  63
  64 /* which initialization functions to call for this board */
  65 #define CONFIG_MISC_INIT_R
  66 #define CONFIG_BOARD_PRE_INIT
  67 #define CONFIG_BOARD_EARLY_INIT_F 1
  68
  69 #define CFG_BOARD_NAME          "CPCI750"
  70 #define CONFIG_IDENT_STRING     "Marvell 64360 + IBM750FX"
  71
  72 /*#define CFG_HUSH_PARSER*/
  73 #define CFG_HUSH_PARSER
  74
  75 #define CFG_PROMPT_HUSH_PS2     "> "
  76
  77 #define CONFIG_AUTO_COMPLETE 1
  78
  79 /* Define which ETH port will be used for connecting the network */
  80 #define CFG_ETH_PORT            ETH_0
  81
  82 /*
  83  * The following defines let you select what serial you want to use
  84  * for your console driver.
  85  *
  86  * what to do:
  87  * to use the DUART, undef CONFIG_MPSC.  If you have hacked a serial
  88  * cable onto the second DUART channel, change the CFG_DUART port from 1
  89  * to 0 below.
  90  *
  91  * to use the MPSC, #define CONFIG_MPSC.  If you have wired up another
  92  * mpsc channel, change CONFIG_MPSC_PORT to the desired value.
  93  */
  94 #define CONFIG_MPSC
  95 #define CONFIG_MPSC_PORT        0
  96
  97 /* to change the default ethernet port, use this define (options: 0, 1, 2) */
  98 #define CONFIG_NET_MULTI
  99 #define MV_ETH_DEVS             1
 100 #define CONFIG_ETHER_PORT       0
 101
 102 #undef CONFIG_ETHER_PORT_MII    /* use RMII */
 103
 104 #define CONFIG_BOOTDELAY        5       /* autoboot disabled            */
 105
 106 #define CONFIG_RTC_M48T35A      1       /* ST Electronics M48 timekeeper */
 107
 108 #define CONFIG_ZERO_BOOTDELAY_CHECK
 109
 110
 111 #undef  CONFIG_BOOTARGS
 112
 113 /* -----------------------------------------------------------------------------
 114  * New bootcommands for Marvell CPCI750 c 2002 Ingo Assmus
 115  */
 116
 117 #define CONFIG_IPADDR           "192.168.0.185"
 118
 119 #define CONFIG_SERIAL           "AA000001"
 120 #define CONFIG_SERVERIP         "10.0.0.79"
 121 #define CONFIG_ROOTPATH         "/export/nfs_cpci750/%s"
 122
 123 #define CONFIG_TESTDRAMDATA     y
 124 #define CONFIG_TESTDRAMADDRESS  n
 125 #define CONFIG_TESETDRAMWALK    n
 126
 127 /* ----------------------------------------------------------------------------- */
 128
 129
 130 #define CONFIG_LOADS_ECHO       0       /* echo off for serial download */
 131 #define CFG_LOADS_BAUD_CHANGE           /* allow baudrate changes       */
 132
 133 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
 134 #undef  CONFIG_ALTIVEC                  /* undef to disable             */
 135
 136 /*
 137  * BOOTP options
 138  */
 139 #define CONFIG_BOOTP_SUBNETMASK
 140 #define CONFIG_BOOTP_GATEWAY
 141 #define CONFIG_BOOTP_HOSTNAME
 142 #define CONFIG_BOOTP_BOOTPATH
 143 #define CONFIG_BOOTP_BOOTFILESIZE
 144
 145
 146 /*
 147  * Command line configuration.
 148  */
 149 #include <config_cmd_default.h>
 150
 151 #define CONFIG_CMD_ASKENV
 152 #define CONFIG_CMD_I2C
 153 #define CONFIG_CMD_CACHE
 154 #define CONFIG_CMD_EEPROM
 155 #define CONFIG_CMD_PCI
 156 #define CONFIG_CMD_ELF
 157 #define CONFIG_CMD_DATE
 158 #define CONFIG_CMD_NET
 159 #define CONFIG_CMD_PING
 160 #define CONFIG_CMD_IDE
 161 #define CONFIG_CMD_FAT
 162 #define CONFIG_CMD_EXT2
 163
 164
 165 #define CONFIG_DOS_PARTITION
 166
 167 #define CONFIG_USE_CPCIDVI
 168
 169 #ifdef  CONFIG_USE_CPCIDVI
 170 #define CONFIG_VIDEO
 171 #define CONFIG_VIDEO_CT69000
 172 #define CONFIG_CFB_CONSOLE
 173 #define CONFIG_VIDEO_SW_CURSOR
 174 #define CONFIG_VIDEO_LOGO
 175 #define CONFIG_I8042_KBD
 176 #define CFG_ISA_IO 0
 177 #endif
 178
 179 /*
 180  * Miscellaneous configurable options
 181  */
 182 #define CFG_I2C_EEPROM_ADDR_LEN 2
 183 #define CFG_I2C_MULTI_EEPROMS
 184 #define CFG_I2C_SPEED   80000           /* I2C speed default */
 185
 186 #define CFG_GT_DUAL_CPU                 /* also for JTAG even with one cpu */
 187 #define CFG_LONGHELP                    /* undef to save memory         */
 188 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt       */
 189 #if defined(CONFIG_CMD_KGDB)
 190 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size      */
 191 #else
 192 #define CFG_CBSIZE      256             /* Console I/O Buffer Size      */
 193 #endif
 194 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 195 #define CFG_MAXARGS     16              /* max number of command args   */
 196 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 197
 198 /*#define CFG_MEMTEST_START     0x00400000*/    /* memtest works on     */
 199 /*#define CFG_MEMTEST_END               0x00C00000*/    /* 4 ... 12 MB in DRAM  */
 200 /*#define CFG_MEMTEST_END               0x07c00000*/    /* 4 ... 124 MB in DRAM */
 201
 202 /*
 203 #define CFG_DRAM_TEST
 204  * DRAM tests
 205  *   CFG_DRAM_TEST - enables the following tests.
 206  *
 207  *   CFG_DRAM_TEST_DATA - Enables test for shorted or open data lines
 208  *                        Environment variable 'test_dram_data' must be
 209  *                        set to 'y'.
 210  *   CFG_DRAM_TEST_DATA - Enables test to verify that each word is uniquely
 211  *                        addressable. Environment variable
 212  *                        'test_dram_address' must be set to 'y'.
 213  *   CFG_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test.
 214  *                        This test takes about 6 minutes to test 64 MB.
 215  *                        Environment variable 'test_dram_walk' must be
 216  *                        set to 'y'.
 217  */
 218 #define CFG_DRAM_TEST
 219 #if defined(CFG_DRAM_TEST)
 220 #define CFG_MEMTEST_START               0x00400000      /* memtest works on     */
 221 /*#define CFG_MEMTEST_END               0x00C00000*/    /* 4 ... 12 MB in DRAM  */
 222 #define CFG_MEMTEST_END         0x07c00000      /* 4 ... 124 MB in DRAM */
 223 #define CFG_DRAM_TEST_DATA
 224 #define CFG_DRAM_TEST_ADDRESS
 225 #define CFG_DRAM_TEST_WALK
 226 #endif /* CFG_DRAM_TEST */
 227
 228 #define CONFIG_DISPLAY_MEMMAP           /* at the end of the bootprocess show the memory map */
 229 #undef CFG_DISPLAY_DIMM_SPD_CONTENT     /* show SPD content during boot */
 230
 231 #define CFG_LOAD_ADDR           0x00300000      /* default load address */
 232
 233 #define CFG_HZ                  1000            /* decr freq: 1ms ticks */
 234 #define CFG_BUS_HZ              133000000       /* 133 MHz (CPU = 5*Bus = 666MHz)               */
 235 #define CFG_BUS_CLK             CFG_BUS_HZ
 236
 237 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200, 230400 }
 238
 239 #define CFG_TCLK                133000000
 240
 241 /*#define CFG_750FX_HID0                0x8000c084*/
 242 #define CFG_750FX_HID0          0x80008484
 243 #define CFG_750FX_HID1          0x54800000
 244 #define CFG_750FX_HID2          0x00000000
 245
 246 /*
 247  * Low Level Configuration Settings
 248  * (address mappings, register initial values, etc.)
 249  * You should know what you are doing if you make changes here.
 250  */
 251
 252 /*-----------------------------------------------------------------------
 253  * Definitions for initial stack pointer and data area
 254  */
 255
 256  /*
 257  * When locking data in cache you should point the CFG_INIT_RAM_ADDRESS
 258  * To an unused memory region. The stack will remain in cache until RAM
 259  * is initialized
 260 */
 261 #undef    CFG_INIT_RAM_LOCK
 262 /* #define CFG_INIT_RAM_ADDR    0x40000000*/ /* unused memory region */
 263 /* #define CFG_INIT_RAM_ADDR    0xfba00000*/ /* unused memory region */
 264 #define CFG_INIT_RAM_ADDR       0xf1080000 /* unused memory region */
 265 #define CFG_INIT_RAM_END        0x1000
 266 #define CFG_GBL_DATA_SIZE       128  /* size in bytes reserved for init data */
 267 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 268
 269 #define RELOCATE_INTERNAL_RAM_ADDR
 270 #ifdef RELOCATE_INTERNAL_RAM_ADDR
 271 /*#define CFG_INTERNAL_RAM_ADDR 0xfba00000*/
 272 #define CFG_INTERNAL_RAM_ADDR   0xf1080000
 273 #endif
 274
 275 /*-----------------------------------------------------------------------
 276  * Start addresses for the final memory configuration
 277  * (Set up by the startup code)
 278  * Please note that CFG_SDRAM_BASE _must_ start at 0
 279  */
 280 #define CFG_SDRAM_BASE          0x00000000
 281 /* Dummies for BAT 4-7 */
 282 #define CFG_SDRAM1_BASE         0x10000000      /* each 256 MByte */
 283 #define CFG_SDRAM2_BASE         0x20000000
 284 #define CFG_SDRAM3_BASE         0x30000000
 285 #define CFG_SDRAM4_BASE         0x40000000
 286 #define CFG_RESET_ADDRESS       0xfff00100
 287 #define CFG_MONITOR_LEN         (256 << 10)     /* Reserve 256 kB for Monitor */
 288 #define CFG_MONITOR_BASE        0xfff00000
 289 #define CFG_MALLOC_LEN          (128 << 10)     /* Reserve 256 kB for malloc */
 290
 291 /*-----------------------------------------------------------------------
 292  * FLASH related
 293  *----------------------------------------------------------------------*/
 294
 295 #define CFG_FLASH_CFI_DRIVER
 296 #define CFG_FLASH_CFI           1          /* Flash is CFI conformant           */
 297 #define CFG_FLASH_PROTECTION    1          /* use hardware protection           */
 298 #define CFG_FLASH_USE_BUFFER_WRITE 1       /* use buffered writes (20x faster)  */
 299 #define CFG_FLASH_BASE          0xfc000000 /* start of flash banks              */
 300 #define CFG_MAX_FLASH_BANKS     4          /* max number of memory banks        */
 301 #define CFG_FLASH_INCREMENT     0x01000000 /* size of  flash bank               */
 302 #define CFG_MAX_FLASH_SECT      128        /* max number of sectors on one chip */
 303 #define CFG_FLASH_BANKS_LIST  { CFG_FLASH_BASE,                            \
 304                                 CFG_FLASH_BASE + 1*CFG_FLASH_INCREMENT,    \
 305                                 CFG_FLASH_BASE + 2*CFG_FLASH_INCREMENT,    \
 306                                 CFG_FLASH_BASE + 3*CFG_FLASH_INCREMENT }
 307 #define CFG_FLASH_EMPTY_INFO    1          /* show if bank is empty             */
 308
 309 /* areas to map different things with the GT in physical space */
 310 #define CFG_DRAM_BANKS          4
 311
 312 /* What to put in the bats. */
 313 #define CFG_MISC_REGION_BASE    0xf0000000
 314
 315 /* Peripheral Device section */
 316
 317 /*******************************************************/
 318 /* We have on the cpci750 Board :                      */
 319 /* GT-Chipset Register Area                            */
 320 /* GT-Chipset internal SRAM 256k                       */
 321 /* SRAM on external device module                      */
 322 /* Real time clock on external device module           */
 323 /* dobble UART on external device module               */
 324 /* Data flash on external device module                */
 325 /* Boot flash on external device module                */
 326 /*******************************************************/
 327 #define CFG_DFL_GT_REGS         0x14000000                              /* boot time GT_REGS */
 328 #define  CFG_CPCI750_RESET_ADDR 0x14000000                              /* After power on Reset the CPCI750 is here */
 329
 330 #undef  MARVEL_STANDARD_CFG
 331 #ifndef         MARVEL_STANDARD_CFG
 332 /*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
 333 #define CFG_GT_REGS             0xf1000000                              /* GT Registers will be mapped here */
 334 /*#define CFG_DEV_BASE          0xfc000000*/                            /* GT Devices CS start here */
 335 #define CFG_INT_SRAM_BASE       0xf1080000                              /* GT offers 256k internal fast SRAM */
 336
 337 #define CFG_BOOT_SPACE          0xff000000                              /* BOOT_CS0 flash 0    */
 338 #define CFG_DEV0_SPACE          0xfc000000                              /* DEV_CS0 flash 1     */
 339 #define CFG_DEV1_SPACE          0xfd000000                              /* DEV_CS1 flash 2     */
 340 #define CFG_DEV2_SPACE          0xfe000000                              /* DEV_CS2 flash 3     */
 341 #define CFG_DEV3_SPACE          0xf0000000                              /* DEV_CS3 nvram/can   */
 342
 343 #define CFG_BOOT_SIZE           _16M                                    /* cpci750 flash 0     */
 344 #define CFG_DEV0_SIZE           _16M                                    /* cpci750 flash 1     */
 345 #define CFG_DEV1_SIZE           _16M                                    /* cpci750 flash 2     */
 346 #define CFG_DEV2_SIZE           _16M                                    /* cpci750 flash 3     */
 347 #define CFG_DEV3_SIZE           _16M                                    /* cpci750 nvram/can   */
 348
 349 /*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
 350 #endif
 351
 352 /* Reset values for Port behavior (8bit/ 32bit, etc.) only corrected by device width */
 353 #define CFG_DEV0_PAR            0x8FDFFFFF                              /* 16 bit flash */
 354 #define CFG_DEV1_PAR            0x8FDFFFFF                              /* 16 bit flash */
 355 #define CFG_DEV2_PAR            0x8FDFFFFF                              /* 16 bit flash */
 356 #define CFG_DEV3_PAR            0x8FCFFFFF                              /* nvram/can    */
 357 #define CFG_BOOT_PAR            0x8FDFFFFF                              /* 16 bit flash */
 358
 359         /*   c    4    a      8     2     4    1      c         */
 360         /* 33 22|2222|22 22|111 1|11 11|1 1  |    |             */
 361         /* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210       */
 362         /* 11|00|0100|10 10|100|0 00|10 0|100 0|001 1|100       */
 363         /*  3| 0|.... ..| 2| 4 |  0 |  4 |  8  |  3  | 4        */
 364
 365
 366 /* MPP Control MV64360 Appendix P P. 632*/
 367 #define CFG_MPP_CONTROL_0       0x00002222      /*                                   */
 368 #define CFG_MPP_CONTROL_1       0x11110000      /*                                   */
 369 #define CFG_MPP_CONTROL_2       0x11111111      /*                                   */
 370 #define CFG_MPP_CONTROL_3       0x00001111      /*                                   */
 371 /* #define CFG_SERIAL_PORT_MUX  0x00000102*/    /*                                   */
 372
 373
 374 #define CFG_GPP_LEVEL_CONTROL   0xffffffff      /* 1111 1111 1111 1111 1111 1111 1111 1111*/
 375
 376 /* setup new config_value for MV64360 DDR-RAM To_do !! */
 377 /*# define CFG_SDRAM_CONFIG     0xd8e18200*/    /* 0x448 */
 378 /*# define CFG_SDRAM_CONFIG     0xd8e14400*/    /* 0x1400 */
 379                                 /* GB has high prio.
 380                                    idma has low prio
 381                                    MPSC has low prio
 382                                    pci has low prio 1 and 2
 383                                    cpu has high prio
 384                                    Data DQS pins == eight (DQS[7:0] foe x8 and x16 devices
 385                                    ECC disable
 386                                    non registered DRAM */
 387                                 /* 31:26   25:22  21:20 19 18 17 16 */
 388                                 /* 100001 0000   010   0   0   0  0 */
 389                                 /* refresh_count=0x400
 390                                    phisical interleaving disable
 391                                    virtual interleaving enable */
 392                                 /* 15 14 13:0 */
 393                                 /* 0  1  0x400 */
 394 # define CFG_SDRAM_CONFIG       0x58200400      /* 0x1400  copied from Dink32 bzw. VxWorks*/
 395
 396
 397 /*-----------------------------------------------------------------------
 398  * PCI stuff
 399  *-----------------------------------------------------------------------
 400  */
 401
 402 #define PCI_HOST_ADAPTER 0              /* configure ar pci adapter     */
 403 #define PCI_HOST_FORCE  1               /* configure as pci host        */
 404 #define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
 405
 406 #define CONFIG_PCI                      /* include pci support          */
 407 #define CONFIG_PCI_HOST PCI_HOST_FORCE  /* select pci host function     */
 408 #define CONFIG_PCI_PNP                  /* do pci plug-and-play         */
 409 #define CONFIG_PCI_SCAN_SHOW            /* show devices on bus          */
 410
 411 /* PCI MEMORY MAP section */
 412 #define CFG_PCI0_MEM_BASE       0x80000000
 413 #define CFG_PCI0_MEM_SIZE       _128M
 414 #define CFG_PCI1_MEM_BASE       0x88000000
 415 #define CFG_PCI1_MEM_SIZE       _128M
 416
 417 #define CFG_PCI0_0_MEM_SPACE    (CFG_PCI0_MEM_BASE)
 418 #define CFG_PCI1_0_MEM_SPACE    (CFG_PCI1_MEM_BASE)
 419
 420 /* PCI I/O MAP section */
 421 #define CFG_PCI0_IO_BASE        0xfa000000
 422 #define CFG_PCI0_IO_SIZE        _16M
 423 #define CFG_PCI1_IO_BASE        0xfb000000
 424 #define CFG_PCI1_IO_SIZE        _16M
 425
 426 #define CFG_PCI0_IO_SPACE       (CFG_PCI0_IO_BASE)
 427 #define CFG_PCI0_IO_SPACE_PCI   0x00000000
 428 #define CFG_PCI1_IO_SPACE       (CFG_PCI1_IO_BASE)
 429 #define CFG_PCI1_IO_SPACE_PCI   0x00000000
 430
 431 #define CFG_ISA_IO_BASE_ADDRESS (CFG_PCI0_IO_BASE)
 432
 433 #if defined (CONFIG_750CX)
 434 #define CFG_PCI_IDSEL 0x0
 435 #else
 436 #define CFG_PCI_IDSEL 0x30
 437 #endif
 438
 439 /*-----------------------------------------------------------------------
 440  * IDE/ATA stuff
 441  *-----------------------------------------------------------------------
 442  */
 443 #undef  CONFIG_IDE_8xx_DIRECT           /* no pcmcia interface required */
 444 #undef  CONFIG_IDE_LED                  /* no led for ide supported     */
 445 #define CONFIG_IDE_RESET                /* no reset for ide supported   */
 446 #define CONFIG_IDE_PREINIT              /* check for units              */
 447
 448 #define CFG_IDE_MAXBUS          2               /* max. 1 IDE busses    */
 449 #define CFG_IDE_MAXDEVICE       (CFG_IDE_MAXBUS*2) /* max. 1 drives per IDE bus */
 450
 451 #define CFG_ATA_BASE_ADDR       0
 452 #define CFG_ATA_IDE0_OFFSET     0
 453 #define CFG_ATA_IDE1_OFFSET     0
 454
 455 #define CFG_ATA_DATA_OFFSET     0x0000  /* Offset for data I/O                  */
 456 #define CFG_ATA_REG_OFFSET      0x0000  /* Offset for normal register accesses  */
 457 #define CFG_ATA_ALT_OFFSET      0x0000  /* Offset for alternate registers       */
 458
 459
 460 /*----------------------------------------------------------------------
 461  * Initial BAT mappings
 462  */
 463
 464 /* NOTES:
 465  * 1) GUARDED and WRITE_THRU not allowed in IBATS
 466  * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT
 467  */
 468
 469 /* SDRAM */
 470 #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
 471 #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 472 #define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 473 #define CFG_DBAT0U CFG_IBAT0U
 474
 475 /* init ram */
 476 #define CFG_IBAT1L  (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
 477 #define CFG_IBAT1U  (CFG_INIT_RAM_ADDR | BATU_BL_256K | BATU_VS | BATU_VP)
 478 #define CFG_DBAT1L  CFG_IBAT1L
 479 #define CFG_DBAT1U  CFG_IBAT1U
 480
 481 /* PCI0, PCI1 in one BAT */
 482 #define CFG_IBAT2L BATL_NO_ACCESS
 483 #define CFG_IBAT2U CFG_DBAT2U
 484 #define CFG_DBAT2L (CFG_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
 485 #define CFG_DBAT2U (CFG_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 486
 487 /* GT regs, bootrom, all the devices, PCI I/O */
 488 #define CFG_IBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)
 489 #define CFG_IBAT3U (CFG_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)
 490 #define CFG_DBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
 491 #define CFG_DBAT3U CFG_IBAT3U
 492
 493 /*
 494  * 750FX IBAT and DBAT pairs (To_do: define regins for I(D)BAT4 - I(D)BAT7)
 495  * IBAT4 and DBAT4
 496  * FIXME: ingo disable BATs for Linux Kernel
 497  */
 498 #undef SETUP_HIGH_BATS_FX750            /* don't initialize BATS 4-7 */
 499 /*#define SETUP_HIGH_BATS_FX750*/               /* initialize BATS 4-7 */
 500
 501 #ifdef SETUP_HIGH_BATS_FX750
 502 #define CFG_IBAT4L (CFG_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
 503 #define CFG_IBAT4U (CFG_SDRAM1_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 504 #define CFG_DBAT4L (CFG_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 505 #define CFG_DBAT4U CFG_IBAT4U
 506
 507 /* IBAT5 and DBAT5 */
 508 #define CFG_IBAT5L (CFG_SDRAM2_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
 509 #define CFG_IBAT5U (CFG_SDRAM2_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 510 #define CFG_DBAT5L (CFG_SDRAM2_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 511 #define CFG_DBAT5U CFG_IBAT5U
 512
 513 /* IBAT6 and DBAT6 */
 514 #define CFG_IBAT6L (CFG_SDRAM3_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
 515 #define CFG_IBAT6U (CFG_SDRAM3_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 516 #define CFG_DBAT6L (CFG_SDRAM3_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 517 #define CFG_DBAT6U CFG_IBAT6U
 518
 519 /* IBAT7 and DBAT7 */
 520 #define CFG_IBAT7L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
 521 #define CFG_IBAT7U (CFG_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 522 #define CFG_DBAT7L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 523 #define CFG_DBAT7U CFG_IBAT7U
 524
 525 #else           /* set em out of range for Linux !!!!!!!!!!! */
 526 #define CFG_IBAT4L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
 527 #define CFG_IBAT4U (CFG_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 528 #define CFG_DBAT4L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 529 #define CFG_DBAT4U CFG_IBAT4U
 530
 531 /* IBAT5 and DBAT5 */
 532 #define CFG_IBAT5L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
 533 #define CFG_IBAT5U (CFG_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 534 #define CFG_DBAT5L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 535 #define CFG_DBAT5U CFG_IBAT4U
 536
 537 /* IBAT6 and DBAT6 */
 538 #define CFG_IBAT6L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
 539 #define CFG_IBAT6U (CFG_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 540 #define CFG_DBAT6L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 541 #define CFG_DBAT6U CFG_IBAT4U
 542
 543 /* IBAT7 and DBAT7 */
 544 #define CFG_IBAT7L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
 545 #define CFG_IBAT7U (CFG_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 546 #define CFG_DBAT7L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 547 #define CFG_DBAT7U CFG_IBAT4U
 548
 549 #endif
 550 /* FIXME: ingo end: disable BATs for Linux Kernel */
 551
 552 /* I2C addresses for the two DIMM SPD chips */
 553 #define DIMM0_I2C_ADDR  0x51
 554 #define DIMM1_I2C_ADDR  0x52
 555
 556 /*
 557  * For booting Linux, the board info and command line data
 558  * have to be in the first 8 MB of memory, since this is
 559  * the maximum mapped by the Linux kernel during initialization.
 560  */
 561 #define CFG_BOOTMAPSZ           (8<<20) /* Initial Memory map for Linux */
 562
 563 /*-----------------------------------------------------------------------
 564  * FLASH organization
 565  */
 566 #define CFG_BOOT_FLASH_WIDTH    2       /* 16 bit */
 567
 568 #define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms) */
 569 #define CFG_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms) */
 570 #define CFG_FLASH_LOCK_TOUT     500     /* Timeout for Flash Lock (in ms) */
 571
 572 #if 0
 573 #define CFG_ENV_IS_IN_FLASH     0
 574 #define CFG_ENV_SIZE            0x1000  /* Total Size of Environment Sector */
 575 #define CFG_ENV_SECT_SIZE       0x10000
 576 #define CFG_ENV_ADDR            0xFFF78000 /* Marvell 8-Bit Bootflash last sector */
 577 /* #define CFG_ENV_ADDR    (CFG_FLASH_BASE+CFG_MONITOR_LEN-CFG_ENV_SECT_SIZE) */
 578 #endif
 579
 580 #define CFG_ENV_IS_IN_EEPROM    1       /* use EEPROM for environment vars */
 581 #define CFG_EEPROM_PAGE_WRITE_BITS 5
 582 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20
 583 #define CFG_I2C_EEPROM_ADDR     0x050
 584 #define CFG_ENV_OFFSET          0x200   /* environment starts at the beginning of the EEPROM */
 585 #define CFG_ENV_SIZE            0x600   /* 2048 bytes may be used for env vars*/
 586
 587 #define CFG_NVRAM_BASE_ADDR     0xf0000000              /* NVRAM base address   */
 588 #define CFG_NVRAM_SIZE          (32*1024)               /* NVRAM size           */
 589 #define CFG_VXWORKS_MAC_PTR     (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-0x40)
 590
 591 /*-----------------------------------------------------------------------
 592  * Cache Configuration
 593  */
 594 #define CFG_CACHELINE_SIZE      32      /* For all MPC74xx CPUs          */
 595 #if defined(CONFIG_CMD_KGDB)
 596 #define CFG_CACHELINE_SHIFT     5       /* log base 2 of the above value */
 597 #endif
 598
 599 /*-----------------------------------------------------------------------
 600  * L2CR setup -- make sure this is right for your board!
 601  * look in include/mpc74xx.h for the defines used here
 602  */
 603
 604 /*#define CFG_L2*/
 605 #undef CFG_L2
 606
 607 /*    #ifdef CONFIG_750CX*/
 608 #if defined (CONFIG_750CX) || defined (CONFIG_750FX)
 609 #define L2_INIT 0
 610 #else
 611 #define L2_INIT         (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
 612                         L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
 613 #endif
 614
 615 #define L2_ENABLE       (L2_INIT | L2CR_L2E)
 616
 617 /*
 618  * Internal Definitions
 619  *
 620  * Boot Flags
 621  */
 622 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH */
 623 #define BOOTFLAG_WARM   0x02            /* Software reboot                  */
 624
 625 #define CFG_BOARD_ASM_INIT      1
 626
 627 #endif  /* __CONFIG_H */