include/configs/Adder.h

   1 /*
   2  * Copyright (C) 2004-2005 Arabella Software Ltd.
   3  * Yuli Barcohen <yuli@arabellasw.com>
   4  *
   5  * Support for Analogue&Micro Adder boards family.
   6  * Tested on AdderII and Adder87x.
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26 #ifndef __CONFIG_H
  27 #define __CONFIG_H
  28
  29 #if !defined(CONFIG_MPC875) && !defined(CONFIG_MPC852T)
  30 #define CONFIG_MPC875
  31 #endif
  32
  33 #define CONFIG_ADDER                            /* Analogue&Micro Adder board   */
  34
  35 #define CONFIG_8xx_CONS_SMC1    1               /* Console is on SMC1           */
  36 #define CONFIG_BAUDRATE         38400
  37
  38 #define CONFIG_ETHER_ON_FEC1
  39 #define CONFIG_ETHER_ON_FEC2
  40 #define CONFIG_HAS_ETH0
  41 #define CONFIG_HAS_ETH1
  42
  43 #if defined(CONFIG_ETHER_ON_FEC1) || defined(CONFIG_ETHER_ON_FEC2)
  44 #define CFG_DISCOVER_PHY
  45 #define FEC_ENET
  46 #endif /* CONFIG_ETHER_ON_FEC || CONFIG_ETHER_ON_FEC2 */
  47
  48 #define CONFIG_8xx_OSCLK                10000000 /* 10 MHz oscillator on EXTCLK */
  49 #define CONFIG_8xx_CPUCLK_DEFAULT       50000000
  50 #define CFG_8xx_CPUCLK_MIN              40000000
  51 #ifdef CONFIG_MPC852T
  52 #define CFG_8xx_CPUCLK_MAX              50000000
  53 #else
  54 #define CFG_8xx_CPUCLK_MAX              133000000
  55 #endif /* CONFIG_MPC852T */
  56
  57
  58 /*
  59  * BOOTP options
  60  */
  61 #define CONFIG_BOOTP_BOOTFILESIZE
  62 #define CONFIG_BOOTP_BOOTPATH
  63 #define CONFIG_BOOTP_GATEWAY
  64 #define CONFIG_BOOTP_HOSTNAME
  65
  66
  67 /*
  68  * Command line configuration.
  69  */
  70 #include <config_cmd_default.h>
  71
  72 #define CONFIG_CMD_DHCP
  73 #define CONFIG_CMD_IMMAP
  74 #define CONFIG_CMD_MII
  75 #define CONFIG_CMD_PING
  76
  77
  78 #define CONFIG_BOOTDELAY        5               /* Autoboot after 5 seconds     */
  79 #define CONFIG_BOOTCOMMAND      "bootm fe040000"        /* Autoboot command     */
  80 #define CONFIG_BOOTARGS         "root=/dev/mtdblock1 rw mtdparts=1M(ROM)ro,-(root)"
  81
  82 #define CONFIG_BZIP2            /* Include support for bzip2 compressed images  */
  83 #undef  CONFIG_WATCHDOG         /* Disable platform specific watchdog           */
  84
  85 /*-----------------------------------------------------------------------
  86  * Miscellaneous configurable options
  87  */
  88 #define CFG_PROMPT              "=> "           /* Monitor Command Prompt       */
  89 #define CFG_HUSH_PARSER
  90 #define CFG_PROMPT_HUSH_PS2     "> "
  91 #define CFG_LONGHELP                            /* #undef to save memory        */
  92 #define CFG_CBSIZE              256             /* Console I/O Buffer Size      */
  93 #define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)  /* Print Buffer Size */
  94 #define CFG_MAXARGS             16              /* Max number of command args   */
  95 #define CFG_BARGSIZE            CFG_CBSIZE      /* Boot Argument Buffer Size    */
  96
  97 #define CFG_LOAD_ADDR           0x400000        /* Default load address         */
  98
  99 #define CFG_HZ                  1000            /* Decrementer freq: 1 ms ticks */
 100
 101 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 102
 103 /*-----------------------------------------------------------------------
 104  * RAM configuration (note that CFG_SDRAM_BASE must be zero)
 105  */
 106 #define CFG_SDRAM_BASE          0x00000000
 107 #define CFG_SDRAM_MAX_SIZE      0x01000000      /* Up to 16 Mbyte               */
 108
 109 #define CFG_MAMR                0x00002114
 110
 111 /*
 112  * 4096 Up to 4096 SDRAM rows
 113  * 1000 factor s -> ms
 114  * 32   PTP (pre-divider from MPTPR)
 115  * 4    Number of refresh cycles per period
 116  * 64   Refresh cycle in ms per number of rows
 117  */
 118 #define CFG_PTA_PER_CLK         ((4096 * 32 * 1000) / (4 * 64))
 119
 120 #define CFG_MEMTEST_START       0x00100000      /* memtest works on             */
 121 #define CFG_MEMTEST_END         0x00500000      /* 1 ... 5 MB in SDRAM          */
 122
 123 #define CFG_RESET_ADDRESS       0x09900000
 124
 125 /*-----------------------------------------------------------------------
 126  * For booting Linux, the board info and command line data
 127  * have to be in the first 8 MB of memory, since this is
 128  * the maximum mapped by the Linux kernel during initialization.
 129  */
 130 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 131
 132 #define CFG_MONITOR_BASE        TEXT_BASE
 133 #define CFG_MONITOR_LEN         (192 << 10)     /* Reserve 192 KB for Monitor   */
 134 #ifdef CONFIG_BZIP2
 135 #define CFG_MALLOC_LEN          (2500 << 10)    /* Reserve ~2.5 MB for malloc() */
 136 #else
 137 #define CFG_MALLOC_LEN          (128 << 10)     /* Reserve 128 KB for malloc()  */
 138 #endif /* CONFIG_BZIP2 */
 139
 140 /*-----------------------------------------------------------------------
 141  * Flash organisation
 142  */
 143 #define CFG_FLASH_BASE          0xFE000000
 144 #define CFG_FLASH_CFI                           /* The flash is CFI compatible  */
 145 #define CFG_FLASH_CFI_DRIVER                    /* Use common CFI driver        */
 146 #define CFG_MAX_FLASH_BANKS     1               /* Max number of flash banks    */
 147 #define CFG_MAX_FLASH_SECT      128             /* Max num of sects on one chip */
 148
 149 /* Environment is in flash */
 150 #define CFG_ENV_IS_IN_FLASH
 151 #define CFG_ENV_SECT_SIZE       0x10000         /* We use one complete sector   */
 152 #define CFG_ENV_ADDR            (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
 153
 154 #define CONFIG_ENV_OVERWRITE
 155
 156 #define CFG_OR0_PRELIM          0xFF000774
 157 #define CFG_BR0_PRELIM          (CFG_FLASH_BASE | BR_PS_16 | BR_MS_GPCM | BR_V)
 158
 159 #define CFG_DIRECT_FLASH_TFTP
 160
 161 /*-----------------------------------------------------------------------
 162  * Internal Memory Map Register
 163  */
 164 #define CFG_IMMR                0xFF000000
 165
 166 /*-----------------------------------------------------------------------
 167  * Definitions for initial stack pointer and data area (in DPRAM)
 168  */
 169 #define CFG_INIT_RAM_ADDR       CFG_IMMR
 170 #define CFG_INIT_RAM_END        0x2F00          /* End of used area in DPRAM    */
 171 #define CFG_GBL_DATA_SIZE       128  /* Size in bytes reserved for initial data */
 172 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 173 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 174
 175 /*-----------------------------------------------------------------------
 176  * Configuration registers
 177  */
 178 #ifdef CONFIG_WATCHDOG
 179 #define CFG_SYPCR               (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME  | \
 180                                  SYPCR_SWF  | SYPCR_SWE | SYPCR_SWRI | \
 181                                  SYPCR_SWP)
 182 #else
 183 #define CFG_SYPCR               (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME  | \
 184                                  SYPCR_SWF  | SYPCR_SWP)
 185 #endif /* CONFIG_WATCHDOG */
 186
 187 #define CFG_SIUMCR              (SIUMCR_MLRC01 | SIUMCR_DBGC11)
 188
 189 /* TBSCR - Time Base Status and Control Register */
 190 #define CFG_TBSCR               (TBSCR_TBF | TBSCR_TBE)
 191
 192 /* PISCR - Periodic Interrupt Status and Control */
 193 #define CFG_PISCR               (PISCR_PS | PISCR_PITF)
 194
 195 /* PLPRCR - PLL, Low-Power, and Reset Control Register */
 196 /* #define CFG_PLPRCR           PLPRCR_TEXPS */
 197
 198 /* SCCR - System Clock and reset Control Register */
 199 #define SCCR_MASK               SCCR_EBDF11
 200 #define CFG_SCCR                SCCR_RTSEL
 201
 202 #define CFG_DER                 0
 203
 204 /*-----------------------------------------------------------------------
 205  * Cache Configuration
 206  */
 207 #define CFG_CACHELINE_SIZE      16      /* For all MPC8xx chips                 */
 208
 209 /*-----------------------------------------------------------------------
 210  * Internal Definitions
 211  *
 212  * Boot Flags
 213  */
 214 #define BOOTFLAG_COLD           0x01    /* Normal Power-On: Boot from flash     */
 215 #define BOOTFLAG_WARM           0x02    /* Software reboot                      */
 216
 217 /* pass open firmware flat tree */
 218 #define CONFIG_OF_LIBFDT        1
 219 #define CONFIG_OF_BOARD_SETUP   1
 220
 221 #endif /* __CONFIG_H */