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add SDHC support in mmc driver
[u-boot-openmoko/mini2440.git] / include / configs / ADNPESC1_base_32.h
blob55210ebd3ae49f4dd4a161c8a0ebbe8d40992c48
1 /*
2 * (C) Copyright 2004, Li-Pro.Net <www.li-pro.net>
3 * Stephan Linz <linz@li-pro.net>
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24 #ifndef __CONFIG_ADNPESC1_BASE_32_H
25 #define __CONFIG_ADNPESC1_BASE_32_H
26
27 /*
28 * NIOS CPU configuration. (PART OF configs/ADNPESC1.h)
29 *
30 * Here we must define CPU dependencies. Any unsupported option have to
31 * be undefined or defined with zero, example CPU without data cache / OCI:
32 *
33 * #define CFG_NIOS_CPU_ICACHE 4096
34 * #define CFG_NIOS_CPU_DCACHE 0
35 * #undef CFG_NIOS_CPU_OCI_BASE
36 * #undef CFG_NIOS_CPU_OCI_SIZE
37 */
38
39 /* CPU core */
40 #define CFG_NIOS_CPU_CLK 50000000 /* NIOS CPU clock */
41 #define CFG_NIOS_CPU_ICACHE (0) /* instruction cache */
42 #define CFG_NIOS_CPU_DCACHE (0) /* data cache */
43 #define CFG_NIOS_CPU_REG_NUMS 512 /* number of register */
44 #define CFG_NIOS_CPU_MUL 0 /* 16x16 MUL: no(0) */
45 /* yes(1) */
46 #define CFG_NIOS_CPU_MSTEP 1 /* 16x16 MSTEP: no(0) */
47 /* yes(1) */
48 #define CFG_NIOS_CPU_STACK 0x03000000 /* stack top addr */
49 #define CFG_NIOS_CPU_VEC_BASE 0x02000000 /* IRQ vectors addr */
50 #define CFG_NIOS_CPU_VEC_SIZE 256 /* size */
51 #define CFG_NIOS_CPU_VEC_NUMS 64 /* numbers */
52 #define CFG_NIOS_CPU_RST_VECT 0x00000000 /* RESET vector addr */
53 #define CFG_NIOS_CPU_DBG_CORE 0 /* CPU debug: no(0) */
54 /* yes(1) */
55
56 /* The offset address in flash to check for the Nios signature "Ni".
57 * (see GM_FlashExec in germs_monitor.s) */
58 #define CFG_NIOS_CPU_EXES_OFFS 0x0C
59
60 /* on-chip extensions */
61 #undef CFG_NIOS_CPU_RAM_BASE /* on chip RAM addr */
62 #undef CFG_NIOS_CPU_RAM_SIZE /* 64 KB size */
63
64 #define CFG_NIOS_CPU_ROM_BASE 0x00000000 /* on chip ROM addr */
65 #define CFG_NIOS_CPU_ROM_SIZE (2 * 1024) /* 2 KB size */
66
67 #undef CFG_NIOS_CPU_OCI_BASE /* OCI core addr */
68 #undef CFG_NIOS_CPU_OCI_SIZE /* size */
69
70 /* timer */
71 #define CFG_NIOS_CPU_TIMER_NUMS 1 /* number of timer */
72
73 #define CFG_NIOS_CPU_TIMER0 0x00000840 /* TIMER0 addr */
74 #define CFG_NIOS_CPU_TIMER0_IRQ 16 /* IRQ */
75 #define CFG_NIOS_CPU_TIMER0_PER 1000 /* periode usec */
76 #define CFG_NIOS_CPU_TIMER0_AR 0 /* always run: no(0) */
77 /* yes(1) */
78 #define CFG_NIOS_CPU_TIMER0_FP 0 /* fixed per: no(0) */
79 /* yes(1) */
80 #define CFG_NIOS_CPU_TIMER0_SS 1 /* snaphot: no(0) */
81 /* yes(1) */
82
83 /* serial i/o */
84 #define CFG_NIOS_CPU_UART_NUMS 2 /* number of uarts */
85
86 #define CFG_NIOS_CPU_UART0 0x00000800 /* UART0 addr */
87 #define CFG_NIOS_CPU_UART0_IRQ 17 /* IRQ */
88 #define CFG_NIOS_CPU_UART0_BR 115200 /* baudrate var(0) */
89 #define CFG_NIOS_CPU_UART0_DB 8 /* data bit */
90 #define CFG_NIOS_CPU_UART0_SB 1 /* stop bit */
91 #define CFG_NIOS_CPU_UART0_PA 0 /* parity none(0) */
92 /* odd(1) */
93 /* even(2) */
94 #define CFG_NIOS_CPU_UART0_HS 1 /* handshake: no(0) */
95 /* crts(1) */
96 #define CFG_NIOS_CPU_UART0_EOP 0 /* eop reg: no(0) */
97 /* yes(1) */
98
99 #define CFG_NIOS_CPU_UART1 0x00000820 /* UART1 addr */
100 #define CFG_NIOS_CPU_UART1_IRQ 18 /* IRQ */
101 #define CFG_NIOS_CPU_UART1_BR 115200 /* baudrate var(0) */
102 #define CFG_NIOS_CPU_UART1_DB 8 /* data bit */
103 #define CFG_NIOS_CPU_UART1_SB 1 /* stop bit */
104 #define CFG_NIOS_CPU_UART1_PA 0 /* parity none(0) */
105 /* odd(1) */
106 /* even(2) */
107 #define CFG_NIOS_CPU_UART1_HS 0 /* handshake: no(0) */
108 /* crts(1) */
109 #define CFG_NIOS_CPU_UART1_EOP 0 /* eop reg: no(0) */
110 /* yes(1) */
111
112 /* serial peripheral i/o */
113 #define CFG_NIOS_CPU_SPI_NUMS 1 /* number of spis */
114
115 #define CFG_NIOS_CPU_SPI0 0x000008c0 /* SPI0 addr */
116 #define CFG_NIOS_CPU_SPI0_IRQ 25 /* IRQ */
117 #define CFG_NIOS_CPU_SPI0_BITS 16 /* data bit */
118 #define CFG_NIOS_CPU_SPI0_MA 1 /* is master: no(0) */
119 /* yes(1) */
120 #define CFG_NIOS_CPU_SPI0_SLN 1 /* num slaves */
121 #define CFG_NIOS_CPU_SPI0_TCLK 250000 /* clock (Hz) */
122 #define CFG_NIOS_CPU_SPI0_TDELAY 2 /* delay (usec) */
123 #define CFG_NIOS_CPU_SPI0_FB 0 /* first bit msb(0) */
124 /* lsb(1) */
125
126 /* parallel i/o */
127 #define CFG_NIOS_CPU_PIO_NUMS 14 /* number of parports */
128
129 #define CFG_NIOS_CPU_PIO0 0x00000860 /* PIO0 addr */
130 #undef CFG_NIOS_CPU_PIO0_IRQ /* w/o IRQ */
131 #define CFG_NIOS_CPU_PIO0_BITS 8 /* number of bits */
132 #define CFG_NIOS_CPU_PIO0_TYPE 0 /* io type: tris(0) */
133 /* out(1) */
134 /* in(2) */
135 #define CFG_NIOS_CPU_PIO0_CAP 0 /* capture: no(0) */
136 /* yes(1) */
137 #define CFG_NIOS_CPU_PIO0_EDGE 0 /* edge type: none(0) */
138 /* fall(1) */
139 /* rise(2) */
140 /* any(3) */
141 #define CFG_NIOS_CPU_PIO0_ITYPE 0 /* IRQ type: none(0) */
142 /* level(1)*/
143 /* edge(2) */
144
145 #define CFG_NIOS_CPU_PIO1 0x00000870 /* PIO1 addr */
146 #undef CFG_NIOS_CPU_PIO1_IRQ /* w/o IRQ */
147 #define CFG_NIOS_CPU_PIO1_BITS 8 /* number of bits */
148 #define CFG_NIOS_CPU_PIO1_TYPE 0 /* io type: tris(0) */
149 /* out(1) */
150 /* in(2) */
151 #define CFG_NIOS_CPU_PIO1_CAP 0 /* capture: no(0) */
152 /* yes(1) */
153 #define CFG_NIOS_CPU_PIO1_EDGE 0 /* edge type: none(0) */
154 /* fall(1) */
155 /* rise(2) */
156 /* any(3) */
157 #define CFG_NIOS_CPU_PIO1_ITYPE 0 /* IRQ type: none(0) */
158 /* level(1)*/
159 /* edge(2) */
160
161 #define CFG_NIOS_CPU_PIO2 0x00000880 /* PIO2 addr */
162 #undef CFG_NIOS_CPU_PIO2_IRQ /* w/o IRQ */
163 #define CFG_NIOS_CPU_PIO2_BITS 4 /* number of bits */
164 #define CFG_NIOS_CPU_PIO2_TYPE 0 /* io type: tris(0) */
165 /* out(1) */
166 /* in(2) */
167 #define CFG_NIOS_CPU_PIO2_CAP 0 /* capture: no(0) */
168 /* yes(1) */
169 #define CFG_NIOS_CPU_PIO2_EDGE 0 /* edge type: none(0) */
170 /* fall(1) */
171 /* rise(2) */
172 /* any(3) */
173 #define CFG_NIOS_CPU_PIO2_ITYPE 0 /* IRQ type: none(0) */
174 /* level(1)*/
175 /* edge(2) */
176
177 #define CFG_NIOS_CPU_PIO3 0x00000890 /* PIO3 addr */
178 #undef CFG_NIOS_CPU_PIO3_IRQ /* w/o IRQ */
179 #define CFG_NIOS_CPU_PIO3_BITS 1 /* number of bits */
180 #define CFG_NIOS_CPU_PIO3_TYPE 2 /* io type: tris(0) */
181 /* out(1) */
182 /* in(2) */
183 #define CFG_NIOS_CPU_PIO3_CAP 0 /* capture: no(0) */
184 /* yes(1) */
185 #define CFG_NIOS_CPU_PIO3_EDGE 0 /* edge type: none(0) */
186 /* fall(1) */
187 /* rise(2) */
188 /* any(3) */
189 #define CFG_NIOS_CPU_PIO3_ITYPE 0 /* IRQ type: none(0) */
190 /* level(1)*/
191 /* edge(2) */
192
193 #define CFG_NIOS_CPU_PIO3 0x00000890 /* PIO3 addr */
194 #undef CFG_NIOS_CPU_PIO3_IRQ /* w/o IRQ */
195 #define CFG_NIOS_CPU_PIO3_BITS 1 /* number of bits */
196 #define CFG_NIOS_CPU_PIO3_TYPE 2 /* io type: tris(0) */
197 /* out(1) */
198 /* in(2) */
199 #define CFG_NIOS_CPU_PIO3_CAP 0 /* capture: no(0) */
200 /* yes(1) */
201 #define CFG_NIOS_CPU_PIO3_EDGE 0 /* edge type: none(0) */
202 /* fall(1) */
203 /* rise(2) */
204 /* any(3) */
205 #define CFG_NIOS_CPU_PIO3_ITYPE 0 /* IRQ type: none(0) */
206 /* level(1)*/
207 /* edge(2) */
208
209 #define CFG_NIOS_CPU_PIO4 0x000008a0 /* PIO4 addr */
210 #undef CFG_NIOS_CPU_PIO4_IRQ /* w/o IRQ */
211 #define CFG_NIOS_CPU_PIO4_BITS 1 /* number of bits */
212 #define CFG_NIOS_CPU_PIO4_TYPE 1 /* io type: tris(0) */
213 /* out(1) */
214 /* in(2) */
215 #define CFG_NIOS_CPU_PIO4_CAP 0 /* capture: no(0) */
216 /* yes(1) */
217 #define CFG_NIOS_CPU_PIO4_EDGE 0 /* edge type: none(0) */
218 /* fall(1) */
219 /* rise(2) */
220 /* any(3) */
221 #define CFG_NIOS_CPU_PIO4_ITYPE 0 /* IRQ type: none(0) */
222 /* level(1)*/
223 /* edge(2) */
224
225 #define CFG_NIOS_CPU_PIO5 0x000008b0 /* PIO5 addr */
226 #undef CFG_NIOS_CPU_PIO5_IRQ /* w/o IRQ */
227 #define CFG_NIOS_CPU_PIO5_BITS 1 /* number of bits */
228 #define CFG_NIOS_CPU_PIO5_TYPE 1 /* io type: tris(0) */
229 /* out(1) */
230 /* in(2) */
231 #define CFG_NIOS_CPU_PIO5_CAP 0 /* capture: no(0) */
232 /* yes(1) */
233 #define CFG_NIOS_CPU_PIO5_EDGE 0 /* edge type: none(0) */
234 /* fall(1) */
235 /* rise(2) */
236 /* any(3) */
237 #define CFG_NIOS_CPU_PIO5_ITYPE 0 /* IRQ type: none(0) */
238 /* level(1)*/
239 /* edge(2) */
240
241 #define CFG_NIOS_CPU_PIO6 0x00000900 /* PIO6 addr */
242 #define CFG_NIOS_CPU_PIO6_IRQ 20 /* IRQ */
243 #define CFG_NIOS_CPU_PIO6_BITS 1 /* number of bits */
244 #define CFG_NIOS_CPU_PIO6_TYPE 2 /* io type: tris(0) */
245 /* out(1) */
246 /* in(2) */
247 #define CFG_NIOS_CPU_PIO6_CAP 1 /* capture: no(0) */
248 /* yes(1) */
249 #define CFG_NIOS_CPU_PIO6_EDGE 2 /* edge type: none(0) */
250 /* fall(1) */
251 /* rise(2) */
252 /* any(3) */
253 #define CFG_NIOS_CPU_PIO6_ITYPE 1 /* IRQ type: none(0) */
254 /* level(1)*/
255 /* edge(2) */
256
257 #define CFG_NIOS_CPU_PIO7 0x00000910 /* PIO7 addr */
258 #define CFG_NIOS_CPU_PIO7_IRQ 31 /* IRQ */
259 #define CFG_NIOS_CPU_PIO7_BITS 1 /* number of bits */
260 #define CFG_NIOS_CPU_PIO7_TYPE 2 /* io type: tris(0) */
261 /* out(1) */
262 /* in(2) */
263 #define CFG_NIOS_CPU_PIO7_CAP 1 /* capture: no(0) */
264 /* yes(1) */
265 #define CFG_NIOS_CPU_PIO7_EDGE 2 /* edge type: none(0) */
266 /* fall(1) */
267 /* rise(2) */
268 /* any(3) */
269 #define CFG_NIOS_CPU_PIO7_ITYPE 1 /* IRQ type: none(0) */
270 /* level(1)*/
271 /* edge(2) */
272
273 #define CFG_NIOS_CPU_PIO8 0x00000920 /* PIO8 addr */
274 #define CFG_NIOS_CPU_PIO8_IRQ 32 /* IRQ */
275 #define CFG_NIOS_CPU_PIO8_BITS 1 /* number of bits */
276 #define CFG_NIOS_CPU_PIO8_TYPE 2 /* io type: tris(0) */
277 /* out(1) */
278 /* in(2) */
279 #define CFG_NIOS_CPU_PIO8_CAP 1 /* capture: no(0) */
280 /* yes(1) */
281 #define CFG_NIOS_CPU_PIO8_EDGE 2 /* edge type: none(0) */
282 /* fall(1) */
283 /* rise(2) */
284 /* any(3) */
285 #define CFG_NIOS_CPU_PIO8_ITYPE 1 /* IRQ type: none(0) */
286 /* level(1)*/
287 /* edge(2) */
288
289 #define CFG_NIOS_CPU_PIO9 0x00000930 /* PIO9 addr */
290 #define CFG_NIOS_CPU_PIO9_IRQ 33 /* IRQ */
291 #define CFG_NIOS_CPU_PIO9_BITS 1 /* number of bits */
292 #define CFG_NIOS_CPU_PIO9_TYPE 2 /* io type: tris(0) */
293 /* out(1) */
294 /* in(2) */
295 #define CFG_NIOS_CPU_PIO9_CAP 1 /* capture: no(0) */
296 /* yes(1) */
297 #define CFG_NIOS_CPU_PIO9_EDGE 2 /* edge type: none(0) */
298 /* fall(1) */
299 /* rise(2) */
300 /* any(3) */
301 #define CFG_NIOS_CPU_PIO9_ITYPE 1 /* IRQ type: none(0) */
302 /* level(1)*/
303 /* edge(2) */
304
305 #define CFG_NIOS_CPU_PIO10 0x00000940 /* PIO10 addr */
306 #define CFG_NIOS_CPU_PIO10_IRQ 34 /* IRQ */
307 #define CFG_NIOS_CPU_PIO10_BITS 1 /* number of bits */
308 #define CFG_NIOS_CPU_PIO10_TYPE 2 /* io type: tris(0) */
309 /* out(1) */
310 /* in(2) */
311 #define CFG_NIOS_CPU_PIO10_CAP 1 /* capture: no(0) */
312 /* yes(1) */
313 #define CFG_NIOS_CPU_PIO10_EDGE 2 /* edge type: none(0) */
314 /* fall(1) */
315 /* rise(2) */
316 /* any(3) */
317 #define CFG_NIOS_CPU_PIO10_ITYPE 1 /* IRQ type: none(0) */
318 /* level(1)*/
319 /* edge(2) */
320
321 #define CFG_NIOS_CPU_PIO11 0x00000950 /* PIO11 addr */
322 #define CFG_NIOS_CPU_PIO11_IRQ 35 /* IRQ */
323 #define CFG_NIOS_CPU_PIO11_BITS 1 /* number of bits */
324 #define CFG_NIOS_CPU_PIO11_TYPE 2 /* io type: tris(0) */
325 /* out(1) */
326 /* in(2) */
327 #define CFG_NIOS_CPU_PIO11_CAP 1 /* capture: no(0) */
328 /* yes(1) */
329 #define CFG_NIOS_CPU_PIO11_EDGE 2 /* edge type: none(0) */
330 /* fall(1) */
331 /* rise(2) */
332 /* any(3) */
333 #define CFG_NIOS_CPU_PIO11_ITYPE 1 /* IRQ type: none(0) */
334 /* level(1)*/
335 /* edge(2) */
336
337 #define CFG_NIOS_CPU_PIO12 0x00000960 /* PIO12 addr */
338 #define CFG_NIOS_CPU_PIO12_IRQ 36 /* IRQ */
339 #define CFG_NIOS_CPU_PIO12_BITS 1 /* number of bits */
340 #define CFG_NIOS_CPU_PIO12_TYPE 2 /* io type: tris(0) */
341 /* out(1) */
342 /* in(2) */
343 #define CFG_NIOS_CPU_PIO12_CAP 1 /* capture: no(0) */
344 /* yes(1) */
345 #define CFG_NIOS_CPU_PIO12_EDGE 2 /* edge type: none(0) */
346 /* fall(1) */
347 /* rise(2) */
348 /* any(3) */
349 #define CFG_NIOS_CPU_PIO12_ITYPE 1 /* IRQ type: none(0) */
350 /* level(1)*/
351 /* edge(2) */
352
353 #define CFG_NIOS_CPU_PIO13 0x00000970 /* PIO113 addr */
354 #define CFG_NIOS_CPU_PIO13_IRQ 37 /* IRQ */
355 #define CFG_NIOS_CPU_PIO13_BITS 1 /* number of bits */
356 #define CFG_NIOS_CPU_PIO13_TYPE 2 /* io type: tris(0) */
357 /* out(1) */
358 /* in(2) */
359 #define CFG_NIOS_CPU_PIO13_CAP 1 /* capture: no(0) */
360 /* yes(1) */
361 #define CFG_NIOS_CPU_PIO13_EDGE 2 /* edge type: none(0) */
362 /* fall(1) */
363 /* rise(2) */
364 /* any(3) */
365 #define CFG_NIOS_CPU_PIO13_ITYPE 1 /* IRQ type: none(0) */
366 /* level(1)*/
367 /* edge(2) */
368
369 /* IDE i/f */
370 #define CFG_NIOS_CPU_IDE_NUMS 2 /* number of IDE contr. */
371
372 #define CFG_NIOS_CPU_IDE0 0x00001000 /* IDE0 addr */
373 #define CFG_NIOS_CPU_IDE0_IRQ 36 /* IRQ */
374
375 #define CFG_NIOS_CPU_IDE1 0x00001020 /* IDE1 addr */
376 #define CFG_NIOS_CPU_IDE1_IRQ 37 /* IRQ */
377
378 /* memory accessibility */
379 #undef CFG_NIOS_CPU_SRAM_BASE /* board SRAM addr */
380 #undef CFG_NIOS_CPU_SRAM_SIZE /* 1 MB size */
381
382 #define CFG_NIOS_CPU_SDRAM_BASE 0x02000000 /* board SDRAM addr */
383 #define CFG_NIOS_CPU_SDRAM_SIZE (16*1024*1024) /* 16 MB size */
384
385 #define CFG_NIOS_CPU_FLASH_BASE 0x01000000 /* board Flash addr */
386 #define CFG_NIOS_CPU_FLASH_SIZE (8*1024*1024) /* 8 MB size */
387
388 /* LAN */
389 #define CFG_NIOS_CPU_LAN_NUMS 1 /* number of LAN i/f */
390
391 #define CFG_NIOS_CPU_LAN0_BASE 0x00010000 /* LAN0 addr */
392 #define CFG_NIOS_CPU_LAN0_OFFS (0) /* offset */
393 #define CFG_NIOS_CPU_LAN0_IRQ 20 /* IRQ */
394 #define CFG_NIOS_CPU_LAN0_BUSW 16 /* buswidth*/
395 #define CFG_NIOS_CPU_LAN0_TYPE 0 /* smc91111(0) */
396 /* cs8900(1) */
397 /* ex: openmac(2) */
398 /* ex: alteramac(3) */
399
400 /* external extension */
401 #define CFG_NIOS_CPU_CS0_BASE 0x40000000 /* board EXT0 addr */
402 #define CFG_NIOS_CPU_CS0_SIZE (16*1024*1024) /* max. 16 MB size */
403
404 #define CFG_NIOS_CPU_CS1_BASE 0x41000000 /* board EXT1 addr */
405 #define CFG_NIOS_CPU_CS1_SIZE (16*1024*1024) /* max. 16 MB size */
406
407 #define CFG_NIOS_CPU_CS2_BASE 0x42000000 /* board EXT2 addr */
408 #define CFG_NIOS_CPU_CS2_SIZE (16*1024*1024) /* max. 16 MB size */
409
410 #define CFG_NIOS_CPU_CS3_BASE 0x43000000 /* board EXT3 addr */
411 #define CFG_NIOS_CPU_CS3_SIZE (16*1024*1024) /* max. 16 MB size */
412
413 /* symbolic redefinition (undef, if not present) */
414 #define CFG_NIOS_CPU_TICK_TIMER 0 /* TIMER0: tick (needed)*/
415 #undef CFG_NIOS_CPU_USER_TIMER /* TIMERx: users choice */
416
417 #define CFG_NIOS_CPU_PORTA_PIO 0 /* PIO0: Port A */
418 #define CFG_NIOS_CPU_PORTB_PIO 1 /* PIO1: Port D */
419 #define CFG_NIOS_CPU_PORTC_PIO 2 /* PIO2: Port C */
420 #define CFG_NIOS_CPU_RCM_PIO 3 /* PIO3: RCM jumper */
421 #define CFG_NIOS_CPU_WDENA_PIO 4 /* PIO4: watchdog enable*/
422 #define CFG_NIOS_CPU_WDTOG_PIO 5 /* PIO5: watchdog trigg.*/
423
424 /* PIOx: LED bar */
425 #ifdef CONFIG_DNPEVA2 /* DNP/EVA2 base board */
426 #define CFG_NIOS_CPU_LED_PIO CFG_NIOS_CPU_PORTA_PIO
427 #else
428 #undef CFG_NIOS_CPU_LED_PIO /* no LED bar */
429 #endif
430
431 #endif /* __CONFIG_ADNPESC1_BASE_32_H */
Fork of the u-boot for for Samsung based MINI2440 board