include/asm-ppc/cache.h

   1 /*
   2  * include/asm-ppc/cache.h
   3  */
   4 #ifndef __ARCH_PPC_CACHE_H
   5 #define __ARCH_PPC_CACHE_H
   6
   7 #include <linux/config.h>
   8 #include <asm/processor.h>
   9
  10 /* bytes per L1 cache line */
  11 #if defined(CONFIG_8xx) || defined(CONFIG_IOP480)
  12 #define L1_CACHE_SHIFT  4
  13 #elif defined(CONFIG_PPC64BRIDGE)
  14 #define L1_CACHE_SHIFT  7
  15 #else
  16 #define L1_CACHE_SHIFT  5
  17 #endif
  18
  19 #define L1_CACHE_BYTES          (1 << L1_CACHE_SHIFT)
  20
  21 /*
  22  * For compatibility reasons support the CFG_CACHELINE_SIZE too
  23  */
  24 #ifndef CFG_CACHELINE_SIZE
  25 #define CFG_CACHELINE_SIZE      L1_CACHE_BYTES
  26 #endif
  27
  28 #define L1_CACHE_ALIGN(x)       (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1))
  29 #define L1_CACHE_PAGES          8
  30
  31 #define SMP_CACHE_BYTES L1_CACHE_BYTES
  32
  33 #ifdef MODULE
  34 #define __cacheline_aligned __attribute__((__aligned__(L1_CACHE_BYTES)))
  35 #else
  36 #define __cacheline_aligned                                     \
  37   __attribute__((__aligned__(L1_CACHE_BYTES),                   \
  38                  __section__(".data.cacheline_aligned")))
  39 #endif
  40
  41 #if defined(__KERNEL__) && !defined(__ASSEMBLY__)
  42 extern void flush_dcache_range(unsigned long start, unsigned long stop);
  43 extern void clean_dcache_range(unsigned long start, unsigned long stop);
  44 extern void invalidate_dcache_range(unsigned long start, unsigned long stop);
  45 extern void flush_dcache(void);
  46 extern void invalidate_dcache(void);
  47 #ifdef CFG_INIT_RAM_LOCK
  48 extern void unlock_ram_in_cache(void);
  49 #endif /* CFG_INIT_RAM_LOCK */
  50 #endif /* __ASSEMBLY__ */
  51
  52 /* prep registers for L2 */
  53 #define CACHECRBA       0x80000823      /* Cache configuration register address */
  54 #define L2CACHE_MASK    0x03    /* Mask for 2 L2 Cache bits */
  55 #define L2CACHE_512KB   0x00    /* 512KB */
  56 #define L2CACHE_256KB   0x01    /* 256KB */
  57 #define L2CACHE_1MB     0x02    /* 1MB */
  58 #define L2CACHE_NONE    0x03    /* NONE */
  59 #define L2CACHE_PARITY  0x08    /* Mask for L2 Cache Parity Protected bit */
  60
  61 #ifdef CONFIG_8xx
  62 /* Cache control on the MPC8xx is provided through some additional
  63  * special purpose registers.
  64  */
  65 #define IC_CST          560     /* Instruction cache control/status */
  66 #define IC_ADR          561     /* Address needed for some commands */
  67 #define IC_DAT          562     /* Read-only data register */
  68 #define DC_CST          568     /* Data cache control/status */
  69 #define DC_ADR          569     /* Address needed for some commands */
  70 #define DC_DAT          570     /* Read-only data register */
  71
  72 /* Commands.  Only the first few are available to the instruction cache.
  73 */
  74 #define IDC_ENABLE      0x02000000      /* Cache enable */
  75 #define IDC_DISABLE     0x04000000      /* Cache disable */
  76 #define IDC_LDLCK       0x06000000      /* Load and lock */
  77 #define IDC_UNLINE      0x08000000      /* Unlock line */
  78 #define IDC_UNALL       0x0a000000      /* Unlock all */
  79 #define IDC_INVALL      0x0c000000      /* Invalidate all */
  80
  81 #define DC_FLINE        0x0e000000      /* Flush data cache line */
  82 #define DC_SFWT         0x01000000      /* Set forced writethrough mode */
  83 #define DC_CFWT         0x03000000      /* Clear forced writethrough mode */
  84 #define DC_SLES         0x05000000      /* Set little endian swap mode */
  85 #define DC_CLES         0x07000000      /* Clear little endian swap mode */
  86
  87 /* Status.
  88 */
  89 #define IDC_ENABLED     0x80000000      /* Cache is enabled */
  90 #define IDC_CERR1       0x00200000      /* Cache error 1 */
  91 #define IDC_CERR2       0x00100000      /* Cache error 2 */
  92 #define IDC_CERR3       0x00080000      /* Cache error 3 */
  93
  94 #define DC_DFWT         0x40000000      /* Data cache is forced write through */
  95 #define DC_LES          0x20000000      /* Caches are little endian mode */
  96 #endif /* CONFIG_8xx */
  97
  98 #endif