include/asm-m68k/immap_5282.h

   1 /*
   2  * MCF5282 Internal Memory Map
   3  *
   4  * Copyright (c) 2003 Josef Baumgartner <josef.baumgartner@telex.de>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #ifndef __IMMAP_5282__
  26 #define __IMMAP_5282__
  27
  28 #define MMAP_SCM        (CFG_MBAR + 0x00000000)
  29 #define MMAP_SDRAMC     (CFG_MBAR + 0x00000040)
  30 #define MMAP_FBCS       (CFG_MBAR + 0x00000080)
  31 #define MMAP_DMA0       (CFG_MBAR + 0x00000100)
  32 #define MMAP_DMA1       (CFG_MBAR + 0x00000140)
  33 #define MMAP_DMA2       (CFG_MBAR + 0x00000180)
  34 #define MMAP_DMA3       (CFG_MBAR + 0x000001C0)
  35 #define MMAP_UART0      (CFG_MBAR + 0x00000200)
  36 #define MMAP_UART1      (CFG_MBAR + 0x00000240)
  37 #define MMAP_UART2      (CFG_MBAR + 0x00000280)
  38 #define MMAP_I2C        (CFG_MBAR + 0x00000300)
  39 #define MMAP_QSPI       (CFG_MBAR + 0x00000340)
  40 #define MMAP_DTMR0      (CFG_MBAR + 0x00000400)
  41 #define MMAP_DTMR1      (CFG_MBAR + 0x00000440)
  42 #define MMAP_DTMR2      (CFG_MBAR + 0x00000480)
  43 #define MMAP_DTMR3      (CFG_MBAR + 0x000004C0)
  44 #define MMAP_INTC0      (CFG_MBAR + 0x00000C00)
  45 #define MMAP_INTC1      (CFG_MBAR + 0x00000D00)
  46 #define MMAP_INTCACK    (CFG_MBAR + 0x00000F00)
  47 #define MMAP_FEC        (CFG_MBAR + 0x00001000)
  48 #define MMAP_FECFIFO    (CFG_MBAR + 0x00001400)
  49 #define MMAP_GPIO       (CFG_MBAR + 0x00100000)
  50 #define MMAP_CCM        (CFG_MBAR + 0x00110000)
  51 #define MMAP_PLL        (CFG_MBAR + 0x00120000)
  52 #define MMAP_EPORT      (CFG_MBAR + 0x00130000)
  53 #define MMAP_WDOG       (CFG_MBAR + 0x00140000)
  54 #define MMAP_PIT0       (CFG_MBAR + 0x00150000)
  55 #define MMAP_PIT1       (CFG_MBAR + 0x00160000)
  56 #define MMAP_PIT2       (CFG_MBAR + 0x00170000)
  57 #define MMAP_PIT3       (CFG_MBAR + 0x00180000)
  58 #define MMAP_QADC       (CFG_MBAR + 0x00190000)
  59 #define MMAP_GPTMRA     (CFG_MBAR + 0x001A0000)
  60 #define MMAP_GPTMRB     (CFG_MBAR + 0x001B0000)
  61 #define MMAP_CAN        (CFG_MBAR + 0x001C0000)
  62 #define MMAP_CFMC       (CFG_MBAR + 0x001D0000)
  63 #define MMAP_CFMMEM     (CFG_MBAR + 0x04000000)
  64
  65 /* System Control Module */
  66 typedef struct scm_ctrl {
  67         u32 ipsbar;
  68         u32 res1;
  69         u32 rambar;
  70         u32 res2;
  71         u8 crsr;
  72         u8 cwcr;
  73         u8 lpicr;
  74         u8 cwsr;
  75         u32 res3;
  76         u8 mpark;
  77         u8 res4[3];
  78         u8 pacr0;
  79         u8 pacr1;
  80         u8 pacr2;
  81         u8 pacr3;
  82         u8 pacr4;
  83         u8 res5;
  84         u8 pacr5;
  85         u8 pacr6;
  86         u8 pacr7;
  87         u8 res6;
  88         u8 pacr8;
  89         u8 res7;
  90         u8 gpacr0;
  91         u8 gpacr1;
  92         u16 res8;
  93 } scm_t;
  94
  95 /* Flexbus module Chip select registers */
  96 typedef struct fbcs_ctrl {
  97         u16 csar0;              /* 0x00 Chip-Select Address Register 0 */
  98         u16 res0;
  99         u32 csmr0;              /* 0x04 Chip-Select Mask Register 0 */
 100         u16 res1;               /* 0x08 */
 101         u16 cscr0;              /* 0x0A Chip-Select Control Register 0 */
 102
 103         u16 csar1;              /* 0x0C Chip-Select Address Register 1 */
 104         u16 res2;
 105         u32 csmr1;              /* 0x10 Chip-Select Mask Register 1 */
 106         u16 res3;               /* 0x14 */
 107         u16 cscr1;              /* 0x16 Chip-Select Control Register 1 */
 108
 109         u16 csar2;              /* 0x18 Chip-Select Address Register 2 */
 110         u16 res4;
 111         u32 csmr2;              /* 0x1C Chip-Select Mask Register 2 */
 112         u16 res5;               /* 0x20 */
 113         u16 cscr2;              /* 0x22 Chip-Select Control Register 2 */
 114
 115         u16 csar3;              /* 0x24 Chip-Select Address Register 3 */
 116         u16 res6;
 117         u32 csmr3;              /* 0x28 Chip-Select Mask Register 3 */
 118         u16 res7;               /* 0x2C */
 119         u16 cscr3;              /* 0x2E Chip-Select Control Register 3 */
 120
 121         u16 csar4;              /* 0x30 Chip-Select Address Register 4 */
 122         u16 res8;
 123         u32 csmr4;              /* 0x34 Chip-Select Mask Register 4 */
 124         u16 res9;               /* 0x38 */
 125         u16 cscr4;              /* 0x3A Chip-Select Control Register 4 */
 126
 127         u16 csar5;              /* 0x3C Chip-Select Address Register 5 */
 128         u16 res10;
 129         u32 csmr5;              /* 0x40 Chip-Select Mask Register 5 */
 130         u16 res11;              /* 0x44 */
 131         u16 cscr5;              /* 0x46 Chip-Select Control Register 5 */
 132
 133         u16 csar6;              /* 0x48 Chip-Select Address Register 5 */
 134         u16 res12;
 135         u32 csmr6;              /* 0x4C Chip-Select Mask Register 5 */
 136         u16 res13;              /* 0x50 */
 137         u16 cscr6;              /* 0x52 Chip-Select Control Register 5 */
 138
 139         u16 csar7;              /* 0x54 Chip-Select Address Register 5 */
 140         u16 res14;
 141         u32 csmr7;              /* 0x58 Chip-Select Mask Register 5 */
 142         u16 res15;              /* 0x5C */
 143         u16 cscr7;              /* 0x5E Chip-Select Control Register 5 */
 144 } fbcs_t;
 145
 146 /* Interrupt module registers */
 147 typedef struct int0_ctrl {
 148         /* Interrupt Controller 0 */
 149         u32 iprh0;              /* 0x00 Pending Register High */
 150         u32 iprl0;              /* 0x04 Pending Register Low */
 151         u32 imrh0;              /* 0x08 Mask Register High */
 152         u32 imrl0;              /* 0x0C Mask Register Low */
 153         u32 frch0;              /* 0x10 Force Register High */
 154         u32 frcl0;              /* 0x14 Force Register Low */
 155         u8 irlr;                /* 0x18 */
 156         u8 iacklpr;             /* 0x19 */
 157         u16 res1[19];           /* 0x1a - 0x3c */
 158         u8 icr0[64];            /* 0x40 - 0x7F Control registers */
 159         u32 res3[24];           /* 0x80 - 0xDF */
 160         u8 swiack0;             /* 0xE0 Software Interrupt Acknowledge */
 161         u8 res4[3];             /* 0xE1 - 0xE3 */
 162         u8 Lniack0_1;           /* 0xE4 Level n interrupt acknowledge resister */
 163         u8 res5[3];             /* 0xE5 - 0xE7 */
 164         u8 Lniack0_2;           /* 0xE8 Level n interrupt acknowledge resister */
 165         u8 res6[3];             /* 0xE9 - 0xEB */
 166         u8 Lniack0_3;           /* 0xEC Level n interrupt acknowledge resister */
 167         u8 res7[3];             /* 0xED - 0xEF */
 168         u8 Lniack0_4;           /* 0xF0 Level n interrupt acknowledge resister */
 169         u8 res8[3];             /* 0xF1 - 0xF3 */
 170         u8 Lniack0_5;           /* 0xF4 Level n interrupt acknowledge resister */
 171         u8 res9[3];             /* 0xF5 - 0xF7 */
 172         u8 Lniack0_6;           /* 0xF8 Level n interrupt acknowledge resister */
 173         u8 resa[3];             /* 0xF9 - 0xFB */
 174         u8 Lniack0_7;           /* 0xFC Level n interrupt acknowledge resister */
 175         u8 resb[3];             /* 0xFD - 0xFF */
 176 } int0_t;
 177
 178 /* Clock Module registers */
 179 typedef struct pll_ctrl {
 180         u16 syncr;              /* 0x00 synthesizer control register */
 181         u16 synsr;              /* 0x02 synthesizer status register */
 182 } pll_t;
 183
 184 /* Watchdog registers */
 185 typedef struct wdog_ctrl {
 186         ushort wcr;
 187         ushort wmr;
 188         ushort wcntr;
 189         ushort wsr;
 190 } wdog_t;
 191
 192 #endif                          /* __IMMAP_5282__ */