include/asm-arm/arch-ixp/ixp425pci.h

   1 /*
   2  * IXP PCI Init
   3  * (C) Copyright 2004 eslab.whut.edu.cn
   4  * Yue Hu(huyue_whut@yahoo.com.cn), Ligong Xue(lgxue@hotmail.com)
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #ifndef _IXP425PCI_H_
  26 #define _IXP425PCI_H_
  27
  28 #define TRUE    1
  29 #define FALSE   0
  30 #define OK      0
  31 #define ERROR   -1
  32 #define BOOL    int
  33
  34 #define IXP425_PCI_MAX_BAR_PER_FUNC  6
  35 #define IXP425_PCI_MAX_BAR (IXP425_PCI_MAX_BAR_PER_FUNC * \
  36                             IXP425_PCI_MAX_FUNC_ON_BUS)
  37
  38 enum PciBarId
  39 {
  40         CSR_BAR=0,
  41         IO_BAR,
  42         SD_BAR,
  43         NO_BAR
  44 };
  45
  46 /*Base address register descriptor*/
  47 typedef struct
  48 {
  49         unsigned int size;
  50         unsigned int address;
  51 } PciBar;
  52
  53 typedef struct
  54 {
  55         unsigned int bus;
  56         unsigned int device;
  57         unsigned int func;
  58         unsigned int irq;
  59         BOOL error;
  60         unsigned short vendor_id;
  61         unsigned short device_id;
  62         /*We need an extra entry in this array for dummy placeholder*/
  63         PciBar bar[IXP425_PCI_MAX_BAR_PER_FUNC + 1];
  64 } PciDevice;
  65
  66 /* Mask definitions*/
  67 #define IXP425_PCI_TOP_WORD_OF_LONG_MASK        0xffff0000
  68 #define IXP425_PCI_TOP_BYTE_OF_LONG_MASK        0xff000000
  69 #define IXP425_PCI_BOTTOM_WORD_OF_LONG_MASK     0x0000ffff
  70 #define IXP425_PCI_BOTTOM_TRIBYTES_OF_LONG_MASK 0x00ffffff
  71 #define IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK   0x0000000f
  72 #define IXP425_PCI_MAX_UINT32                   0xffffffff
  73
  74
  75 #define IXP425_PCI_BAR_QUERY                    0xffffffff
  76
  77 #define IXP425_PCI_BAR_MEM_BASE 0x100000
  78 #define IXP425_PCI_BAR_IO_BASE  0x000000
  79
  80 /*define the maximum number of bus segments - we support a single segment*/
  81 #define IXP425_PCI_MAX_BUS  1
  82 /*define the maximum number of cards per bus segment*/
  83 #define IXP425_PCI_MAX_DEV  4
  84 /*define the maximum number of functions per device*/
  85 #define IXP425_PCI_MAX_FUNC 8
  86 /* define the maximum number of separate functions that we can
  87    potentially have on the bus*/
  88 #define IXP425_PCI_MAX_FUNC_ON_BUS (1+ IXP425_PCI_MAX_FUNC *    \
  89                                     IXP425_PCI_MAX_DEV *        \
  90                                     IXP425_PCI_MAX_BUS)
  91 /*define the maximum number of BARs per function*/
  92 #define IXP425_PCI_MAX_BAR_PER_FUNC  6
  93 #define IXP425_PCI_MAX_BAR (IXP425_PCI_MAX_BAR_PER_FUNC *       \
  94                             IXP425_PCI_MAX_FUNC_ON_BUS)
  95
  96 #define PCI_NP_CBE_BESL  (4)
  97 #define PCI_NP_AD_FUNCSL (8)
  98
  99 #define REG_WRITE(b,o,v) (*(volatile unsigned int*)((b+o))=(v))
 100 #define REG_READ(b,o,v)  ((v)=(*(volatile unsigned int*)((b+o))))
 101
 102 #define PCI_DELAY       500
 103 #define USEC_LOOP_COUNT 533
 104 #define PCI_SETTLE_USEC 200
 105 #define PCI_MIN_RESET_ASSERT_USEC 2000
 106
 107 /*Register addressing definitions for PCI controller configuration
 108   and status registers*/
 109
 110 #define PCI_CSR_BASE (0xC0000000)
 111 /*
 112 #define PCI_NP_AD_OFFSET       (0x00)
 113 #define PCI_NP_CBE_OFFSET      (0x04)
 114 #define PCI_NP_WDATA_OFFSET    (0x08)
 115 #define PCI_NP_RDATA_OFFSET    (0x0C)
 116 #define PCI_CRP_OFFSET         (0x10)
 117 #define PCI_CRP_WDATA_OFFSET   (0x14)
 118 #define PCI_CRP_RDATA_OFFSET   (0x18)
 119 #define PCI_CSR_OFFSET         (0x1C)
 120 #define PCI_ISR_OFFSET         (0x20)
 121 #define PCI_INTEN_OFFSET       (0x24)
 122 #define PCI_DMACTRL_OFFSET     (0x28)
 123 #define PCI_AHBMEMBASE_OFFSET  (0x2C)
 124 #define PCI_AHBIOBASE_OFFSET   (0x30)
 125 #define PCI_PCIMEMBASE_OFFSET  (0x34)
 126 #define PCI_AHBDOORBELL_OFFSET (0x38)
 127 #define PCI_PCIDOORBELL_OFFSET (0x3C)
 128 #define PCI_ATPDMA0_AHBADDR    (0x40)
 129 #define PCI_ATPDMA0_PCIADDR    (0x44)
 130 #define PCI_ATPDMA0_LENADDR    (0x48)
 131 #define PCI_ATPDMA1_AHBADDR    (0x4C)
 132 #define PCI_ATPDMA1_PCIADDR    (0x50)
 133 #define PCI_ATPDMA1_LENADDR    (0x54)
 134 #define PCI_PTADMA0_AHBADDR    (0x58)
 135 #define PCI_PTADMA0_PCIADDR    (0x5C)
 136 #define PCI_PTADMA0_LENADDR    (0x60)
 137 #define PCI_PTADMA1_AHBADDR    (0x64)
 138 #define PCI_PTADMA1_PCIADDR    (0x68)
 139 #define PCI_PTADMA1_LENADDR    (0x6C)
 140 */
 141 /*Non prefetch registers bit definitions*/
 142 /*
 143 #define NP_CMD_INTACK      (0x0)
 144 #define NP_CMD_SPECIAL     (0x1)
 145 #define NP_CMD_IOREAD      (0x2)
 146 #define NP_CMD_IOWRITE     (0x3)
 147 #define NP_CMD_MEMREAD     (0x6)
 148 #define NP_CMD_MEMWRITE    (0x7)
 149 #define NP_CMD_CONFIGREAD  (0xa)
 150 #define NP_CMD_CONFIGWRITE (0xb)
 151 */
 152
 153 /*define the default setting of the AHB memory base reg*/
 154 #define IXP425_PCI_AHBMEMBASE_DEFAULT 0x00010203
 155 #define IXP425_PCI_AHBIOBASE_DEFAULT  0x0
 156 #define IXP425_PCI_PCIMEMBASE_DEFAULT 0x0
 157
 158 /*define the default settings for the controller's BARs*/
 159 #ifdef IXP425_PCI_SIMPLE_MAPPING
 160 #define IXP425_PCI_BAR_0_DEFAULT 0x00000000
 161 #define IXP425_PCI_BAR_1_DEFAULT 0x01000000
 162 #define IXP425_PCI_BAR_2_DEFAULT 0x02000000
 163 #define IXP425_PCI_BAR_3_DEFAULT 0x03000000
 164 #define IXP425_PCI_BAR_4_DEFAULT 0x00000000
 165 #define IXP425_PCI_BAR_5_DEFAULT 0x00000000
 166 #else
 167 #define IXP425_PCI_BAR_0_DEFAULT 0x40000000
 168 #define IXP425_PCI_BAR_1_DEFAULT 0x41000000
 169 #define IXP425_PCI_BAR_2_DEFAULT 0x42000000
 170 #define IXP425_PCI_BAR_3_DEFAULT 0x43000000
 171 #define IXP425_PCI_BAR_4_DEFAULT 0x00000000
 172 #define IXP425_PCI_BAR_5_DEFAULT 0x00000000
 173 #endif
 174
 175 /*Configuration Port register bit definitions*/
 176 #define PCI_CRP_WRITE BIT(16)
 177
 178 /*ISR (Interrupt status) Register bit definitions*/
 179 #define PCI_ISR_PSE   BIT(0)
 180 #define PCI_ISR_PFE   BIT(1)
 181 #define PCI_ISR_PPE   BIT(2)
 182 #define PCI_ISR_AHBE  BIT(3)
 183 #define PCI_ISR_APDC  BIT(4)
 184 #define PCI_ISR_PADC  BIT(5)
 185 #define PCI_ISR_ADB   BIT(6)
 186 #define PCI_ISR_PDB   BIT(7)
 187
 188 /*INTEN (Interrupt Enable) Register bit definitions*/
 189 #define PCI_INTEN_PSE   BIT(0)
 190 #define PCI_INTEN_PFE   BIT(1)
 191 #define PCI_INTEN_PPE   BIT(2)
 192 #define PCI_INTEN_AHBE  BIT(3)
 193 #define PCI_INTEN_APDC  BIT(4)
 194 #define PCI_INTEN_PADC  BIT(5)
 195 #define PCI_INTEN_ADB   BIT(6)
 196 #define PCI_INTEN_PDB   BIT(7)
 197
 198 /*PCI configuration regs.*/
 199
 200 #define PCI_CFG_VENDOR_ID       0x00
 201 #define PCI_CFG_DEVICE_ID       0x02
 202 #define PCI_CFG_COMMAND         0x04
 203 #define PCI_CFG_STATUS          0x06
 204 #define PCI_CFG_REVISION        0x08
 205 #define PCI_CFG_PROGRAMMING_IF  0x09
 206 #define PCI_CFG_SUBCLASS        0x0a
 207 #define PCI_CFG_CLASS           0x0b
 208 #define PCI_CFG_CACHE_LINE_SIZE 0x0c
 209 #define PCI_CFG_LATENCY_TIMER   0x0d
 210 #define PCI_CFG_HEADER_TYPE     0x0e
 211 #define PCI_CFG_BIST            0x0f
 212 #define PCI_CFG_BASE_ADDRESS_0  0x10
 213 #define PCI_CFG_BASE_ADDRESS_1  0x14
 214 #define PCI_CFG_BASE_ADDRESS_2  0x18
 215 #define PCI_CFG_BASE_ADDRESS_3  0x1c
 216 #define PCI_CFG_BASE_ADDRESS_4  0x20
 217 #define PCI_CFG_BASE_ADDRESS_5  0x24
 218 #define PCI_CFG_CIS             0x28
 219 #define PCI_CFG_SUB_VENDOR_ID   0x2c
 220 #define PCI_CFG_SUB_SYSTEM_ID   0x2e
 221 #define PCI_CFG_EXPANSION_ROM   0x30
 222 #define PCI_CFG_RESERVED_0      0x34
 223 #define PCI_CFG_RESERVED_1      0x38
 224 #define PCI_CFG_DEV_INT_LINE    0x3c
 225 #define PCI_CFG_DEV_INT_PIN     0x3d
 226 #define PCI_CFG_MIN_GRANT       0x3e
 227 #define PCI_CFG_MAX_LATENCY     0x3f
 228 #define PCI_CFG_SPECIAL_USE     0x41
 229 #define PCI_CFG_MODE            0x43
 230
 231 /*Specify the initial command we send to PCI devices*/
 232 #define INITIAL_PCI_CMD (PCI_CMD_IO_ENABLE         \
 233                          | PCI_CMD_MEM_ENABLE      \
 234                          | PCI_CMD_MASTER_ENABLE   \
 235                          | PCI_CMD_WI_ENABLE)
 236
 237 /*define the sub vendor and subsystem to be used */
 238 #define IXP425_PCI_SUB_VENDOR_SYSTEM 0x00000000
 239
 240 #define PCI_IRQ_LINES           4
 241
 242 #define PCI_CMD_IO_ENABLE       0x0001  /* IO access enable */
 243 #define PCI_CMD_MEM_ENABLE      0x0002  /* memory access enable */
 244 #define PCI_CMD_MASTER_ENABLE   0x0004  /* bus master enable */
 245 #define PCI_CMD_MON_ENABLE      0x0008  /* monitor special cycles enable */
 246 #define PCI_CMD_WI_ENABLE       0x0010  /* write and invalidate enable */
 247 #define PCI_CMD_SNOOP_ENABLE    0x0020  /* palette snoop enable */
 248 #define PCI_CMD_PERR_ENABLE     0x0040  /* parity error enable */
 249 #define PCI_CMD_WC_ENABLE       0x0080  /* wait cycle enable */
 250 #define PCI_CMD_SERR_ENABLE     0x0100  /* system error enable */
 251 #define PCI_CMD_FBTB_ENABLE     0x0200  /* fast back to back enable */
 252
 253
 254 /*CSR Register bit definitions*/
 255 #define PCI_CSR_HOST  BIT(0)
 256 #define PCI_CSR_ARBEN BIT(1)
 257 #define PCI_CSR_ADS   BIT(2)
 258 #define PCI_CSR_PDS   BIT(3)
 259 #define PCI_CSR_ABE   BIT(4)
 260 #define PCI_CSR_DBT   BIT(5)
 261 #define PCI_CSR_ASE   BIT(8)
 262 #define PCI_CSR_IC    BIT(15)
 263
 264 /*Configuration command bit definitions*/
 265 #define PCI_CFG_CMD_IOAE BIT(0)
 266 #define PCI_CFG_CMD_MAE  BIT(1)
 267 #define PCI_CFG_CMD_BME  BIT(2)
 268 #define PCI_CFG_CMD_MWIE BIT(4)
 269 #define PCI_CFG_CMD_SER  BIT(8)
 270 #define PCI_CFG_CMD_FBBE BIT(9)
 271 #define PCI_CFG_CMD_MDPE BIT(24)
 272 #define PCI_CFG_CMD_STA  BIT(27)
 273 #define PCI_CFG_CMD_RTA  BIT(28)
 274 #define PCI_CFG_CMD_RMA  BIT(29)
 275 #define PCI_CFG_CMD_SSE  BIT(30)
 276 #define PCI_CFG_CMD_DPE  BIT(31)
 277
 278 /*DMACTRL DMA Control and status Register*/
 279 #define PCI_DMACTRL_APDCEN  BIT(0)
 280 #define PCI_DMACTRL_APDC0   BIT(4)
 281 #define PCI_DMACTRL_APDE0   BIT(5)
 282 #define PCI_DMACTRL_APDC1   BIT(6)
 283 #define PCI_DMACTRL_APDE1   BIT(7)
 284 #define PCI_DMACTRL_PADCEN  BIT(8)
 285 #define PCI_DMACTRL_PADC0   BIT(12)
 286 #define PCI_DMACTRL_PADE0   BIT(13)
 287 #define PCI_DMACTRL_PADC1   BIT(14)
 288 #define PCI_DMACTRL_PADE1   BIT(15)
 289
 290 /* GPIO related register */
 291 #undef IXP425_GPIO_GPOUTR
 292 #undef IXP425_GPIO_GPOER
 293 #undef IXP425_GPIO_GPINR
 294 #undef IXP425_GPIO_GPISR
 295 #undef IXP425_GPIO_GPIT1R
 296 #undef IXP425_GPIO_GPIT2R
 297 #undef IXP425_GPIO_GPCLKR
 298
 299 #define IXP425_GPIO_GPOUTR      0xC8004000
 300 #define IXP425_GPIO_GPOER       0xC8004004
 301 #define IXP425_GPIO_GPINR       0xC8004008
 302 #define IXP425_GPIO_GPISR       0xC800400C
 303 #define IXP425_GPIO_GPIT1R      0xC8004010
 304 #define IXP425_GPIO_GPIT2R      0xC8004014
 305 #define IXP425_GPIO_GPCLKR      0xC8004018
 306
 307 #define READ_GPIO_REG(addr,val) \
 308                 (val) = *((volatile int *)(addr));
 309 #define WRITE_GPIO_REG(addr,val) \
 310                 *((volatile int *)(addr)) = (val);
 311
 312 #endif