cpu/arm920t/cpu.c

   1 /*
   2  * (C) Copyright 2002
   3  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
   4  * Marius Groeger <mgroeger@sysgo.de>
   5  *
   6  * (C) Copyright 2002
   7  * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
   8  *
   9  * See file CREDITS for list of people who contributed to this
  10  * project.
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License as
  14  * published by the Free Software Foundation; either version 2 of
  15  * the License, or (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25  * MA 02111-1307 USA
  26  */
  27
  28 /*
  29  * CPU specific code
  30  */
  31
  32 #include <common.h>
  33 #include <command.h>
  34 #include <arm920t.h>
  35
  36 #ifdef CONFIG_USE_IRQ
  37 DECLARE_GLOBAL_DATA_PTR;
  38 #endif
  39
  40 /* read co-processor 15, register #1 (control register) */
  41 static unsigned long read_p15_c1 (void)
  42 {
  43         unsigned long value;
  44
  45         __asm__ __volatile__(
  46                 "mrc    p15, 0, %0, c1, c0, 0   @ read control reg\n"
  47                 : "=r" (value)
  48                 :
  49                 : "memory");
  50
  51 #ifdef MMU_DEBUG
  52         printf ("p15/c1 is = %08lx\n", value);
  53 #endif
  54         return value;
  55 }
  56
  57 /* write to co-processor 15, register #1 (control register) */
  58 static void write_p15_c1 (unsigned long value)
  59 {
  60 #ifdef MMU_DEBUG
  61         printf ("write %08lx to p15/c1\n", value);
  62 #endif
  63         __asm__ __volatile__(
  64                 "mcr    p15, 0, %0, c1, c0, 0   @ write it back\n"
  65                 :
  66                 : "r" (value)
  67                 : "memory");
  68
  69         read_p15_c1 ();
  70 }
  71
  72 static void cp_delay (void)
  73 {
  74         volatile int i;
  75
  76         /* copro seems to need some delay between reading and writing */
  77         for (i = 0; i < 100; i++);
  78 }
  79
  80 /* See also ARM920T    Technical reference Manual */
  81 #define C1_MMU          (1<<0)          /* mmu off/on */
  82 #define C1_ALIGN        (1<<1)          /* alignment faults off/on */
  83 #define C1_DC           (1<<2)          /* dcache off/on */
  84
  85 #define C1_BIG_ENDIAN   (1<<7)          /* big endian off/on */
  86 #define C1_SYS_PROT     (1<<8)          /* system protection */
  87 #define C1_ROM_PROT     (1<<9)          /* ROM protection */
  88 #define C1_IC           (1<<12)         /* icache off/on */
  89 #define C1_HIGH_VECTORS (1<<13)         /* location of vectors: low/high addresses */
  90
  91
  92 int cpu_init (void)
  93 {
  94         /*
  95          * setup up stacks if necessary
  96          */
  97 #ifdef CONFIG_USE_IRQ
  98         IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4;
  99         FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
 100 #endif
 101         return 0;
 102 }
 103
 104 int cleanup_before_linux (void)
 105 {
 106         /*
 107          * this function is called just before we call linux
 108          * it prepares the processor for linux
 109          *
 110          * we turn off caches etc ...
 111          */
 112
 113         unsigned long i;
 114
 115         disable_interrupts ();
 116
 117         /* turn off I/D-cache */
 118         asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
 119         i &= ~(C1_DC | C1_IC);
 120         asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
 121
 122         /* flush I/D-cache */
 123         i = 0;
 124         asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i));
 125
 126         return (0);
 127 }
 128
 129 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 130 {
 131         disable_interrupts ();
 132         reset_cpu (0);
 133         /*NOTREACHED*/
 134         return (0);
 135 }
 136
 137 void icache_enable (void)
 138 {
 139         ulong reg;
 140
 141         reg = read_p15_c1 ();           /* get control reg. */
 142         cp_delay ();
 143         write_p15_c1 (reg | C1_IC);
 144 }
 145
 146 void icache_disable (void)
 147 {
 148         ulong reg;
 149
 150         reg = read_p15_c1 ();
 151         cp_delay ();
 152         write_p15_c1 (reg & ~C1_IC);
 153 }
 154
 155 int icache_status (void)
 156 {
 157         return (read_p15_c1 () & C1_IC) != 0;
 158 }
 159
 160 #ifdef USE_920T_MMU
 161 /* It makes no sense to use the dcache if the MMU is not enabled */
 162 void dcache_enable (void)
 163 {
 164         ulong reg;
 165
 166         reg = read_p15_c1 ();
 167         cp_delay ();
 168         write_p15_c1 (reg | C1_DC);
 169 }
 170
 171 void dcache_disable (void)
 172 {
 173         ulong reg;
 174
 175         reg = read_p15_c1 ();
 176         cp_delay ();
 177         reg &= ~C1_DC;
 178         write_p15_c1 (reg);
 179 }
 180
 181 int dcache_status (void)
 182 {
 183         return (read_p15_c1 () & C1_DC) != 0;
 184 }
 185 #endif