add SDHC support in mmc driver
[u-boot-openmoko/mini2440.git] / common / cmd_i2c.c
blobc60ec99dad9182245b932a1d488dbb81a57767f3
1 /*
2 * (C) Copyright 2001
3 * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com.
5 * See file CREDITS for list of people who contributed to this
6 * project.
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
25 * I2C Functions similar to the standard memory functions.
27 * There are several parameters in many of the commands that bear further
28 * explanations:
30 * Two of the commands (imm and imw) take a byte/word/long modifier
31 * (e.g. imm.w specifies the word-length modifier). This was done to
32 * allow manipulating word-length registers. It was not done on any other
33 * commands because it was not deemed useful.
35 * {i2c_chip} is the I2C chip address (the first byte sent on the bus).
36 * Each I2C chip on the bus has a unique address. On the I2C data bus,
37 * the address is the upper seven bits and the LSB is the "read/write"
38 * bit. Note that the {i2c_chip} address specified on the command
39 * line is not shifted up: e.g. a typical EEPROM memory chip may have
40 * an I2C address of 0x50, but the data put on the bus will be 0xA0
41 * for write and 0xA1 for read. This "non shifted" address notation
42 * matches at least half of the data sheets :-/.
44 * {addr} is the address (or offset) within the chip. Small memory
45 * chips have 8 bit addresses. Large memory chips have 16 bit
46 * addresses. Other memory chips have 9, 10, or 11 bit addresses.
47 * Many non-memory chips have multiple registers and {addr} is used
48 * as the register index. Some non-memory chips have only one register
49 * and therefore don't need any {addr} parameter.
51 * The default {addr} parameter is one byte (.1) which works well for
52 * memories and registers with 8 bits of address space.
54 * You can specify the length of the {addr} field with the optional .0,
55 * .1, or .2 modifier (similar to the .b, .w, .l modifier). If you are
56 * manipulating a single register device which doesn't use an address
57 * field, use "0.0" for the address and the ".0" length field will
58 * suppress the address in the I2C data stream. This also works for
59 * successive reads using the I2C auto-incrementing memory pointer.
61 * If you are manipulating a large memory with 2-byte addresses, use
62 * the .2 address modifier, e.g. 210.2 addresses location 528 (decimal).
64 * Then there are the unfortunate memory chips that spill the most
65 * significant 1, 2, or 3 bits of address into the chip address byte.
66 * This effectively makes one chip (logically) look like 2, 4, or
67 * 8 chips. This is handled (awkwardly) by #defining
68 * CFG_I2C_EEPROM_ADDR_OVERFLOW and using the .1 modifier on the
69 * {addr} field (since .1 is the default, it doesn't actually have to
70 * be specified). Examples: given a memory chip at I2C chip address
71 * 0x50, the following would happen...
72 * imd 50 0 10 display 16 bytes starting at 0x000
73 * On the bus: <S> A0 00 <E> <S> A1 <rd> ... <rd>
74 * imd 50 100 10 display 16 bytes starting at 0x100
75 * On the bus: <S> A2 00 <E> <S> A3 <rd> ... <rd>
76 * imd 50 210 10 display 16 bytes starting at 0x210
77 * On the bus: <S> A4 10 <E> <S> A5 <rd> ... <rd>
78 * This is awfully ugly. It would be nice if someone would think up
79 * a better way of handling this.
81 * Adapted from cmd_mem.c which is copyright Wolfgang Denk (wd@denx.de).
84 #include <common.h>
85 #include <command.h>
86 #include <i2c.h>
87 #include <asm/byteorder.h>
89 /* Display values from last command.
90 * Memory modify remembered values are different from display memory.
92 static uchar i2c_dp_last_chip;
93 static uint i2c_dp_last_addr;
94 static uint i2c_dp_last_alen;
95 static uint i2c_dp_last_length = 0x10;
97 static uchar i2c_mm_last_chip;
98 static uint i2c_mm_last_addr;
99 static uint i2c_mm_last_alen;
101 /* If only one I2C bus is present, the list of devices to ignore when
102 * the probe command is issued is represented by a 1D array of addresses.
103 * When multiple buses are present, the list is an array of bus-address
104 * pairs. The following macros take care of this */
106 #if defined(CFG_I2C_NOPROBES)
107 #if defined(CONFIG_I2C_MULTI_BUS)
108 static struct
110 uchar bus;
111 uchar addr;
112 } i2c_no_probes[] = CFG_I2C_NOPROBES;
113 #define GET_BUS_NUM i2c_get_bus_num()
114 #define COMPARE_BUS(b,i) (i2c_no_probes[(i)].bus == (b))
115 #define COMPARE_ADDR(a,i) (i2c_no_probes[(i)].addr == (a))
116 #define NO_PROBE_ADDR(i) i2c_no_probes[(i)].addr
117 #else /* single bus */
118 static uchar i2c_no_probes[] = CFG_I2C_NOPROBES;
119 #define GET_BUS_NUM 0
120 #define COMPARE_BUS(b,i) ((b) == 0) /* Make compiler happy */
121 #define COMPARE_ADDR(a,i) (i2c_no_probes[(i)] == (a))
122 #define NO_PROBE_ADDR(i) i2c_no_probes[(i)]
123 #endif /* CONFIG_MULTI_BUS */
125 #define NUM_ELEMENTS_NOPROBE (sizeof(i2c_no_probes)/sizeof(i2c_no_probes[0]))
126 #endif
128 static int
129 mod_i2c_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char *argv[]);
130 extern int cmd_get_data_size(char* arg, int default_size);
133 * Syntax:
134 * imd {i2c_chip} {addr}{.0, .1, .2} {len}
136 #define DISP_LINE_LEN 16
138 int do_i2c_md ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
140 u_char chip;
141 uint addr, alen, length;
142 int j, nbytes, linebytes;
144 /* We use the last specified parameters, unless new ones are
145 * entered.
147 chip = i2c_dp_last_chip;
148 addr = i2c_dp_last_addr;
149 alen = i2c_dp_last_alen;
150 length = i2c_dp_last_length;
152 if (argc < 3) {
153 printf ("Usage:\n%s\n", cmdtp->usage);
154 return 1;
157 if ((flag & CMD_FLAG_REPEAT) == 0) {
159 * New command specified.
161 alen = 1;
164 * I2C chip address
166 chip = simple_strtoul(argv[1], NULL, 16);
169 * I2C data address within the chip. This can be 1 or
170 * 2 bytes long. Some day it might be 3 bytes long :-).
172 addr = simple_strtoul(argv[2], NULL, 16);
173 alen = 1;
174 for (j = 0; j < 8; j++) {
175 if (argv[2][j] == '.') {
176 alen = argv[2][j+1] - '0';
177 if (alen > 4) {
178 printf ("Usage:\n%s\n", cmdtp->usage);
179 return 1;
181 break;
182 } else if (argv[2][j] == '\0')
183 break;
187 * If another parameter, it is the length to display.
188 * Length is the number of objects, not number of bytes.
190 if (argc > 3)
191 length = simple_strtoul(argv[3], NULL, 16);
195 * Print the lines.
197 * We buffer all read data, so we can make sure data is read only
198 * once.
200 nbytes = length;
201 do {
202 unsigned char linebuf[DISP_LINE_LEN];
203 unsigned char *cp;
205 linebytes = (nbytes > DISP_LINE_LEN) ? DISP_LINE_LEN : nbytes;
207 if (i2c_read(chip, addr, alen, linebuf, linebytes) != 0)
208 puts ("Error reading the chip.\n");
209 else {
210 printf("%04x:", addr);
211 cp = linebuf;
212 for (j=0; j<linebytes; j++) {
213 printf(" %02x", *cp++);
214 addr++;
216 puts (" ");
217 cp = linebuf;
218 for (j=0; j<linebytes; j++) {
219 if ((*cp < 0x20) || (*cp > 0x7e))
220 puts (".");
221 else
222 printf("%c", *cp);
223 cp++;
225 putc ('\n');
227 nbytes -= linebytes;
228 } while (nbytes > 0);
230 i2c_dp_last_chip = chip;
231 i2c_dp_last_addr = addr;
232 i2c_dp_last_alen = alen;
233 i2c_dp_last_length = length;
235 return 0;
238 int do_i2c_mm ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
240 return mod_i2c_mem (cmdtp, 1, flag, argc, argv);
244 int do_i2c_nm ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
246 return mod_i2c_mem (cmdtp, 0, flag, argc, argv);
249 /* Write (fill) memory
251 * Syntax:
252 * imw {i2c_chip} {addr}{.0, .1, .2} {data} [{count}]
254 int do_i2c_mw ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
256 uchar chip;
257 ulong addr;
258 uint alen;
259 uchar byte;
260 int count;
261 int j;
263 if ((argc < 4) || (argc > 5)) {
264 printf ("Usage:\n%s\n", cmdtp->usage);
265 return 1;
269 * Chip is always specified.
271 chip = simple_strtoul(argv[1], NULL, 16);
274 * Address is always specified.
276 addr = simple_strtoul(argv[2], NULL, 16);
277 alen = 1;
278 for (j = 0; j < 8; j++) {
279 if (argv[2][j] == '.') {
280 alen = argv[2][j+1] - '0';
281 if (alen > 4) {
282 printf ("Usage:\n%s\n", cmdtp->usage);
283 return 1;
285 break;
286 } else if (argv[2][j] == '\0')
287 break;
291 * Value to write is always specified.
293 byte = simple_strtoul(argv[3], NULL, 16);
296 * Optional count
298 if (argc == 5)
299 count = simple_strtoul(argv[4], NULL, 16);
300 else
301 count = 1;
303 while (count-- > 0) {
304 if (i2c_write(chip, addr++, alen, &byte, 1) != 0)
305 puts ("Error writing the chip.\n");
307 * Wait for the write to complete. The write can take
308 * up to 10mSec (we allow a little more time).
310 * On some chips, while the write is in progress, the
311 * chip doesn't respond. This apparently isn't a
312 * universal feature so we don't take advantage of it.
315 * No write delay with FRAM devices.
317 #if !defined(CFG_I2C_FRAM)
318 udelay(11000);
319 #endif
321 #if 0
322 for (timeout = 0; timeout < 10; timeout++) {
323 udelay(2000);
324 if (i2c_probe(chip) == 0)
325 break;
327 #endif
330 return (0);
334 /* Calculate a CRC on memory
336 * Syntax:
337 * icrc32 {i2c_chip} {addr}{.0, .1, .2} {count}
339 int do_i2c_crc (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
341 uchar chip;
342 ulong addr;
343 uint alen;
344 int count;
345 uchar byte;
346 ulong crc;
347 ulong err;
348 int j;
350 if (argc < 4) {
351 printf ("Usage:\n%s\n", cmdtp->usage);
352 return 1;
356 * Chip is always specified.
358 chip = simple_strtoul(argv[1], NULL, 16);
361 * Address is always specified.
363 addr = simple_strtoul(argv[2], NULL, 16);
364 alen = 1;
365 for (j = 0; j < 8; j++) {
366 if (argv[2][j] == '.') {
367 alen = argv[2][j+1] - '0';
368 if (alen > 4) {
369 printf ("Usage:\n%s\n", cmdtp->usage);
370 return 1;
372 break;
373 } else if (argv[2][j] == '\0')
374 break;
378 * Count is always specified
380 count = simple_strtoul(argv[3], NULL, 16);
382 printf ("CRC32 for %08lx ... %08lx ==> ", addr, addr + count - 1);
384 * CRC a byte at a time. This is going to be slooow, but hey, the
385 * memories are small and slow too so hopefully nobody notices.
387 crc = 0;
388 err = 0;
389 while (count-- > 0) {
390 if (i2c_read(chip, addr, alen, &byte, 1) != 0)
391 err++;
392 crc = crc32 (crc, &byte, 1);
393 addr++;
395 if (err > 0)
396 puts ("Error reading the chip,\n");
397 else
398 printf ("%08lx\n", crc);
400 return 0;
404 /* Modify memory.
406 * Syntax:
407 * imm{.b, .w, .l} {i2c_chip} {addr}{.0, .1, .2}
408 * inm{.b, .w, .l} {i2c_chip} {addr}{.0, .1, .2}
411 static int
412 mod_i2c_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char *argv[])
414 uchar chip;
415 ulong addr;
416 uint alen;
417 ulong data;
418 int size = 1;
419 int nbytes;
420 int j;
421 extern char console_buffer[];
423 if (argc != 3) {
424 printf ("Usage:\n%s\n", cmdtp->usage);
425 return 1;
428 #ifdef CONFIG_BOOT_RETRY_TIME
429 reset_cmd_timeout(); /* got a good command to get here */
430 #endif
432 * We use the last specified parameters, unless new ones are
433 * entered.
435 chip = i2c_mm_last_chip;
436 addr = i2c_mm_last_addr;
437 alen = i2c_mm_last_alen;
439 if ((flag & CMD_FLAG_REPEAT) == 0) {
441 * New command specified. Check for a size specification.
442 * Defaults to byte if no or incorrect specification.
444 size = cmd_get_data_size(argv[0], 1);
447 * Chip is always specified.
449 chip = simple_strtoul(argv[1], NULL, 16);
452 * Address is always specified.
454 addr = simple_strtoul(argv[2], NULL, 16);
455 alen = 1;
456 for (j = 0; j < 8; j++) {
457 if (argv[2][j] == '.') {
458 alen = argv[2][j+1] - '0';
459 if (alen > 4) {
460 printf ("Usage:\n%s\n", cmdtp->usage);
461 return 1;
463 break;
464 } else if (argv[2][j] == '\0')
465 break;
470 * Print the address, followed by value. Then accept input for
471 * the next value. A non-converted value exits.
473 do {
474 printf("%08lx:", addr);
475 if (i2c_read(chip, addr, alen, (uchar *)&data, size) != 0)
476 puts ("\nError reading the chip,\n");
477 else {
478 data = cpu_to_be32(data);
479 if (size == 1)
480 printf(" %02lx", (data >> 24) & 0x000000FF);
481 else if (size == 2)
482 printf(" %04lx", (data >> 16) & 0x0000FFFF);
483 else
484 printf(" %08lx", data);
487 nbytes = readline (" ? ");
488 if (nbytes == 0) {
490 * <CR> pressed as only input, don't modify current
491 * location and move to next.
493 if (incrflag)
494 addr += size;
495 nbytes = size;
496 #ifdef CONFIG_BOOT_RETRY_TIME
497 reset_cmd_timeout(); /* good enough to not time out */
498 #endif
500 #ifdef CONFIG_BOOT_RETRY_TIME
501 else if (nbytes == -2)
502 break; /* timed out, exit the command */
503 #endif
504 else {
505 char *endp;
507 data = simple_strtoul(console_buffer, &endp, 16);
508 if (size == 1)
509 data = data << 24;
510 else if (size == 2)
511 data = data << 16;
512 data = be32_to_cpu(data);
513 nbytes = endp - console_buffer;
514 if (nbytes) {
515 #ifdef CONFIG_BOOT_RETRY_TIME
517 * good enough to not time out
519 reset_cmd_timeout();
520 #endif
521 if (i2c_write(chip, addr, alen, (uchar *)&data, size) != 0)
522 puts ("Error writing the chip.\n");
523 #ifdef CFG_EEPROM_PAGE_WRITE_DELAY_MS
524 udelay(CFG_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
525 #endif
526 if (incrflag)
527 addr += size;
530 } while (nbytes);
532 chip = i2c_mm_last_chip;
533 addr = i2c_mm_last_addr;
534 alen = i2c_mm_last_alen;
536 return 0;
540 * Syntax:
541 * iprobe {addr}{.0, .1, .2}
543 int do_i2c_probe (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
545 int j;
546 #if defined(CFG_I2C_NOPROBES)
547 int k, skip;
548 uchar bus = GET_BUS_NUM;
549 #endif /* NOPROBES */
551 puts ("Valid chip addresses:");
552 for (j = 0; j < 128; j++) {
553 #if defined(CFG_I2C_NOPROBES)
554 skip = 0;
555 for (k=0; k < NUM_ELEMENTS_NOPROBE; k++) {
556 if (COMPARE_BUS(bus, k) && COMPARE_ADDR(j, k)) {
557 skip = 1;
558 break;
561 if (skip)
562 continue;
563 #endif
564 if (i2c_probe(j) == 0)
565 printf(" %02X", j);
567 putc ('\n');
569 #if defined(CFG_I2C_NOPROBES)
570 puts ("Excluded chip addresses:");
571 for (k=0; k < NUM_ELEMENTS_NOPROBE; k++) {
572 if (COMPARE_BUS(bus,k))
573 printf(" %02X", NO_PROBE_ADDR(k));
575 putc ('\n');
576 #endif
578 return 0;
583 * Syntax:
584 * iloop {i2c_chip} {addr}{.0, .1, .2} [{length}] [{delay}]
585 * {length} - Number of bytes to read
586 * {delay} - A DECIMAL number and defaults to 1000 uSec
588 int do_i2c_loop(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
590 u_char chip;
591 ulong alen;
592 uint addr;
593 uint length;
594 u_char bytes[16];
595 int delay;
596 int j;
598 if (argc < 3) {
599 printf ("Usage:\n%s\n", cmdtp->usage);
600 return 1;
604 * Chip is always specified.
606 chip = simple_strtoul(argv[1], NULL, 16);
609 * Address is always specified.
611 addr = simple_strtoul(argv[2], NULL, 16);
612 alen = 1;
613 for (j = 0; j < 8; j++) {
614 if (argv[2][j] == '.') {
615 alen = argv[2][j+1] - '0';
616 if (alen > 4) {
617 printf ("Usage:\n%s\n", cmdtp->usage);
618 return 1;
620 break;
621 } else if (argv[2][j] == '\0')
622 break;
626 * Length is the number of objects, not number of bytes.
628 length = 1;
629 length = simple_strtoul(argv[3], NULL, 16);
630 if (length > sizeof(bytes))
631 length = sizeof(bytes);
634 * The delay time (uSec) is optional.
636 delay = 1000;
637 if (argc > 3)
638 delay = simple_strtoul(argv[4], NULL, 10);
640 * Run the loop...
642 while (1) {
643 if (i2c_read(chip, addr, alen, bytes, length) != 0)
644 puts ("Error reading the chip.\n");
645 udelay(delay);
648 /* NOTREACHED */
649 return 0;
654 * The SDRAM command is separately configured because many
655 * (most?) embedded boards don't use SDRAM DIMMs.
657 #if defined(CONFIG_CMD_SDRAM)
658 static void print_ddr2_tcyc (u_char const b)
660 printf ("%d.", (b >> 4) & 0x0F);
661 switch (b & 0x0F) {
662 case 0x0:
663 case 0x1:
664 case 0x2:
665 case 0x3:
666 case 0x4:
667 case 0x5:
668 case 0x6:
669 case 0x7:
670 case 0x8:
671 case 0x9:
672 printf ("%d ns\n", b & 0x0F);
673 break;
674 case 0xA:
675 puts ("25 ns\n");
676 break;
677 case 0xB:
678 puts ("33 ns\n");
679 break;
680 case 0xC:
681 puts ("66 ns\n");
682 break;
683 case 0xD:
684 puts ("75 ns\n");
685 break;
686 default:
687 puts ("?? ns\n");
688 break;
692 static void decode_bits (u_char const b, char const *str[], int const do_once)
694 u_char mask;
696 for (mask = 0x80; mask != 0x00; mask >>= 1, ++str) {
697 if (b & mask) {
698 puts (*str);
699 if (do_once)
700 return;
706 * Syntax:
707 * sdram {i2c_chip}
709 int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
711 enum { unknown, EDO, SDRAM, DDR2 } type;
713 u_char chip;
714 u_char data[128];
715 u_char cksum;
716 int j;
718 static const char *decode_CAS_DDR2[] = {
719 " TBD", " 6", " 5", " 4", " 3", " 2", " TBD", " TBD"
722 static const char *decode_CAS_default[] = {
723 " TBD", " 7", " 6", " 5", " 4", " 3", " 2", " 1"
726 static const char *decode_CS_WE_default[] = {
727 " TBD", " 6", " 5", " 4", " 3", " 2", " 1", " 0"
730 static const char *decode_byte21_default[] = {
731 " TBD (bit 7)\n",
732 " Redundant row address\n",
733 " Differential clock input\n",
734 " Registerd DQMB inputs\n",
735 " Buffered DQMB inputs\n",
736 " On-card PLL\n",
737 " Registered address/control lines\n",
738 " Buffered address/control lines\n"
741 static const char *decode_byte22_DDR2[] = {
742 " TBD (bit 7)\n",
743 " TBD (bit 6)\n",
744 " TBD (bit 5)\n",
745 " TBD (bit 4)\n",
746 " TBD (bit 3)\n",
747 " Supports partial array self refresh\n",
748 " Supports 50 ohm ODT\n",
749 " Supports weak driver\n"
752 static const char *decode_row_density_DDR2[] = {
753 "512 MiB", "256 MiB", "128 MiB", "16 GiB",
754 "8 GiB", "4 GiB", "2 GiB", "1 GiB"
757 static const char *decode_row_density_default[] = {
758 "512 MiB", "256 MiB", "128 MiB", "64 MiB",
759 "32 MiB", "16 MiB", "8 MiB", "4 MiB"
762 if (argc < 2) {
763 printf ("Usage:\n%s\n", cmdtp->usage);
764 return 1;
767 * Chip is always specified.
769 chip = simple_strtoul (argv[1], NULL, 16);
771 if (i2c_read (chip, 0, 1, data, sizeof (data)) != 0) {
772 puts ("No SDRAM Serial Presence Detect found.\n");
773 return 1;
776 cksum = 0;
777 for (j = 0; j < 63; j++) {
778 cksum += data[j];
780 if (cksum != data[63]) {
781 printf ("WARNING: Configuration data checksum failure:\n"
782 " is 0x%02x, calculated 0x%02x\n", data[63], cksum);
784 printf ("SPD data revision %d.%d\n",
785 (data[62] >> 4) & 0x0F, data[62] & 0x0F);
786 printf ("Bytes used 0x%02X\n", data[0]);
787 printf ("Serial memory size 0x%02X\n", 1 << data[1]);
789 puts ("Memory type ");
790 switch (data[2]) {
791 case 2:
792 type = EDO;
793 puts ("EDO\n");
794 break;
795 case 4:
796 type = SDRAM;
797 puts ("SDRAM\n");
798 break;
799 case 8:
800 type = DDR2;
801 puts ("DDR2\n");
802 break;
803 default:
804 type = unknown;
805 puts ("unknown\n");
806 break;
809 puts ("Row address bits ");
810 if ((data[3] & 0x00F0) == 0)
811 printf ("%d\n", data[3] & 0x0F);
812 else
813 printf ("%d/%d\n", data[3] & 0x0F, (data[3] >> 4) & 0x0F);
815 puts ("Column address bits ");
816 if ((data[4] & 0x00F0) == 0)
817 printf ("%d\n", data[4] & 0x0F);
818 else
819 printf ("%d/%d\n", data[4] & 0x0F, (data[4] >> 4) & 0x0F);
821 switch (type) {
822 case DDR2:
823 printf ("Number of ranks %d\n",
824 (data[5] & 0x07) + 1);
825 break;
826 default:
827 printf ("Module rows %d\n", data[5]);
828 break;
831 switch (type) {
832 case DDR2:
833 printf ("Module data width %d bits\n", data[6]);
834 break;
835 default:
836 printf ("Module data width %d bits\n",
837 (data[7] << 8) | data[6]);
838 break;
841 puts ("Interface signal levels ");
842 switch(data[8]) {
843 case 0: puts ("TTL 5.0 V\n"); break;
844 case 1: puts ("LVTTL\n"); break;
845 case 2: puts ("HSTL 1.5 V\n"); break;
846 case 3: puts ("SSTL 3.3 V\n"); break;
847 case 4: puts ("SSTL 2.5 V\n"); break;
848 case 5: puts ("SSTL 1.8 V\n"); break;
849 default: puts ("unknown\n"); break;
852 switch (type) {
853 case DDR2:
854 printf ("SDRAM cycle time ");
855 print_ddr2_tcyc (data[9]);
856 break;
857 default:
858 printf ("SDRAM cycle time %d.%d ns\n",
859 (data[9] >> 4) & 0x0F, data[9] & 0x0F);
860 break;
863 switch (type) {
864 case DDR2:
865 printf ("SDRAM access time 0.%d%d ns\n",
866 (data[10] >> 4) & 0x0F, data[10] & 0x0F);
867 break;
868 default:
869 printf ("SDRAM access time %d.%d ns\n",
870 (data[10] >> 4) & 0x0F, data[10] & 0x0F);
871 break;
874 puts ("EDC configuration ");
875 switch (data[11]) {
876 case 0: puts ("None\n"); break;
877 case 1: puts ("Parity\n"); break;
878 case 2: puts ("ECC\n"); break;
879 default: puts ("unknown\n"); break;
882 if ((data[12] & 0x80) == 0)
883 puts ("No self refresh, rate ");
884 else
885 puts ("Self refresh, rate ");
887 switch(data[12] & 0x7F) {
888 case 0: puts ("15.625 us\n"); break;
889 case 1: puts ("3.9 us\n"); break;
890 case 2: puts ("7.8 us\n"); break;
891 case 3: puts ("31.3 us\n"); break;
892 case 4: puts ("62.5 us\n"); break;
893 case 5: puts ("125 us\n"); break;
894 default: puts ("unknown\n"); break;
897 switch (type) {
898 case DDR2:
899 printf ("SDRAM width (primary) %d\n", data[13]);
900 break;
901 default:
902 printf ("SDRAM width (primary) %d\n", data[13] & 0x7F);
903 if ((data[13] & 0x80) != 0) {
904 printf (" (second bank) %d\n",
905 2 * (data[13] & 0x7F));
907 break;
910 switch (type) {
911 case DDR2:
912 if (data[14] != 0)
913 printf ("EDC width %d\n", data[14]);
914 break;
915 default:
916 if (data[14] != 0) {
917 printf ("EDC width %d\n",
918 data[14] & 0x7F);
920 if ((data[14] & 0x80) != 0) {
921 printf (" (second bank) %d\n",
922 2 * (data[14] & 0x7F));
925 break;
928 if (DDR2 != type) {
929 printf ("Min clock delay, back-to-back random column addresses "
930 "%d\n", data[15]);
933 puts ("Burst length(s) ");
934 if (data[16] & 0x80) puts (" Page");
935 if (data[16] & 0x08) puts (" 8");
936 if (data[16] & 0x04) puts (" 4");
937 if (data[16] & 0x02) puts (" 2");
938 if (data[16] & 0x01) puts (" 1");
939 putc ('\n');
940 printf ("Number of banks %d\n", data[17]);
942 switch (type) {
943 case DDR2:
944 puts ("CAS latency(s) ");
945 decode_bits (data[18], decode_CAS_DDR2, 0);
946 putc ('\n');
947 break;
948 default:
949 puts ("CAS latency(s) ");
950 decode_bits (data[18], decode_CAS_default, 0);
951 putc ('\n');
952 break;
955 if (DDR2 != type) {
956 puts ("CS latency(s) ");
957 decode_bits (data[19], decode_CS_WE_default, 0);
958 putc ('\n');
961 if (DDR2 != type) {
962 puts ("WE latency(s) ");
963 decode_bits (data[20], decode_CS_WE_default, 0);
964 putc ('\n');
967 switch (type) {
968 case DDR2:
969 puts ("Module attributes:\n");
970 if (data[21] & 0x80)
971 puts (" TBD (bit 7)\n");
972 if (data[21] & 0x40)
973 puts (" Analysis probe installed\n");
974 if (data[21] & 0x20)
975 puts (" TBD (bit 5)\n");
976 if (data[21] & 0x10)
977 puts (" FET switch external enable\n");
978 printf (" %d PLLs on DIMM\n", (data[21] >> 2) & 0x03);
979 if (data[20] & 0x11) {
980 printf (" %d active registers on DIMM\n",
981 (data[21] & 0x03) + 1);
983 break;
984 default:
985 puts ("Module attributes:\n");
986 if (!data[21])
987 puts (" (none)\n");
988 else
989 decode_bits (data[21], decode_byte21_default, 0);
990 break;
993 switch (type) {
994 case DDR2:
995 decode_bits (data[22], decode_byte22_DDR2, 0);
996 break;
997 default:
998 puts ("Device attributes:\n");
999 if (data[22] & 0x80) puts (" TBD (bit 7)\n");
1000 if (data[22] & 0x40) puts (" TBD (bit 6)\n");
1001 if (data[22] & 0x20) puts (" Upper Vcc tolerance 5%\n");
1002 else puts (" Upper Vcc tolerance 10%\n");
1003 if (data[22] & 0x10) puts (" Lower Vcc tolerance 5%\n");
1004 else puts (" Lower Vcc tolerance 10%\n");
1005 if (data[22] & 0x08) puts (" Supports write1/read burst\n");
1006 if (data[22] & 0x04) puts (" Supports precharge all\n");
1007 if (data[22] & 0x02) puts (" Supports auto precharge\n");
1008 if (data[22] & 0x01) puts (" Supports early RAS# precharge\n");
1009 break;
1012 switch (type) {
1013 case DDR2:
1014 printf ("SDRAM cycle time (2nd highest CAS latency) ");
1015 print_ddr2_tcyc (data[23]);
1016 break;
1017 default:
1018 printf ("SDRAM cycle time (2nd highest CAS latency) %d."
1019 "%d ns\n", (data[23] >> 4) & 0x0F, data[23] & 0x0F);
1020 break;
1023 switch (type) {
1024 case DDR2:
1025 printf ("SDRAM access from clock (2nd highest CAS latency) 0."
1026 "%d%d ns\n", (data[24] >> 4) & 0x0F, data[24] & 0x0F);
1027 break;
1028 default:
1029 printf ("SDRAM access from clock (2nd highest CAS latency) %d."
1030 "%d ns\n", (data[24] >> 4) & 0x0F, data[24] & 0x0F);
1031 break;
1034 switch (type) {
1035 case DDR2:
1036 printf ("SDRAM cycle time (3rd highest CAS latency) ");
1037 print_ddr2_tcyc (data[25]);
1038 break;
1039 default:
1040 printf ("SDRAM cycle time (3rd highest CAS latency) %d."
1041 "%d ns\n", (data[25] >> 4) & 0x0F, data[25] & 0x0F);
1042 break;
1045 switch (type) {
1046 case DDR2:
1047 printf ("SDRAM access from clock (3rd highest CAS latency) 0."
1048 "%d%d ns\n", (data[26] >> 4) & 0x0F, data[26] & 0x0F);
1049 break;
1050 default:
1051 printf ("SDRAM access from clock (3rd highest CAS latency) %d."
1052 "%d ns\n", (data[26] >> 4) & 0x0F, data[26] & 0x0F);
1053 break;
1056 switch (type) {
1057 case DDR2:
1058 printf ("Minimum row precharge %d.%02d ns\n",
1059 (data[27] >> 2) & 0x3F, 25 * (data[27] & 0x03));
1060 break;
1061 default:
1062 printf ("Minimum row precharge %d ns\n", data[27]);
1063 break;
1066 switch (type) {
1067 case DDR2:
1068 printf ("Row active to row active min %d.%02d ns\n",
1069 (data[28] >> 2) & 0x3F, 25 * (data[28] & 0x03));
1070 break;
1071 default:
1072 printf ("Row active to row active min %d ns\n", data[28]);
1073 break;
1076 switch (type) {
1077 case DDR2:
1078 printf ("RAS to CAS delay min %d.%02d ns\n",
1079 (data[29] >> 2) & 0x3F, 25 * (data[29] & 0x03));
1080 break;
1081 default:
1082 printf ("RAS to CAS delay min %d ns\n", data[29]);
1083 break;
1086 printf ("Minimum RAS pulse width %d ns\n", data[30]);
1088 switch (type) {
1089 case DDR2:
1090 puts ("Density of each row ");
1091 decode_bits (data[31], decode_row_density_DDR2, 1);
1092 putc ('\n');
1093 break;
1094 default:
1095 puts ("Density of each row ");
1096 decode_bits (data[31], decode_row_density_default, 1);
1097 putc ('\n');
1098 break;
1101 switch (type) {
1102 case DDR2:
1103 puts ("Command and Address setup ");
1104 if (data[32] >= 0xA0) {
1105 printf ("1.%d%d ns\n",
1106 ((data[32] >> 4) & 0x0F) - 10, data[32] & 0x0F);
1107 } else {
1108 printf ("0.%d%d ns\n",
1109 ((data[32] >> 4) & 0x0F), data[32] & 0x0F);
1111 break;
1112 default:
1113 printf ("Command and Address setup %c%d.%d ns\n",
1114 (data[32] & 0x80) ? '-' : '+',
1115 (data[32] >> 4) & 0x07, data[32] & 0x0F);
1116 break;
1119 switch (type) {
1120 case DDR2:
1121 puts ("Command and Address hold ");
1122 if (data[33] >= 0xA0) {
1123 printf ("1.%d%d ns\n",
1124 ((data[33] >> 4) & 0x0F) - 10, data[33] & 0x0F);
1125 } else {
1126 printf ("0.%d%d ns\n",
1127 ((data[33] >> 4) & 0x0F), data[33] & 0x0F);
1129 break;
1130 default:
1131 printf ("Command and Address hold %c%d.%d ns\n",
1132 (data[33] & 0x80) ? '-' : '+',
1133 (data[33] >> 4) & 0x07, data[33] & 0x0F);
1134 break;
1137 switch (type) {
1138 case DDR2:
1139 printf ("Data signal input setup 0.%d%d ns\n",
1140 (data[34] >> 4) & 0x0F, data[34] & 0x0F);
1141 break;
1142 default:
1143 printf ("Data signal input setup %c%d.%d ns\n",
1144 (data[34] & 0x80) ? '-' : '+',
1145 (data[34] >> 4) & 0x07, data[34] & 0x0F);
1146 break;
1149 switch (type) {
1150 case DDR2:
1151 printf ("Data signal input hold 0.%d%d ns\n",
1152 (data[35] >> 4) & 0x0F, data[35] & 0x0F);
1153 break;
1154 default:
1155 printf ("Data signal input hold %c%d.%d ns\n",
1156 (data[35] & 0x80) ? '-' : '+',
1157 (data[35] >> 4) & 0x07, data[35] & 0x0F);
1158 break;
1161 puts ("Manufacturer's JEDEC ID ");
1162 for (j = 64; j <= 71; j++)
1163 printf ("%02X ", data[j]);
1164 putc ('\n');
1165 printf ("Manufacturing Location %02X\n", data[72]);
1166 puts ("Manufacturer's Part Number ");
1167 for (j = 73; j <= 90; j++)
1168 printf ("%02X ", data[j]);
1169 putc ('\n');
1170 printf ("Revision Code %02X %02X\n", data[91], data[92]);
1171 printf ("Manufacturing Date %02X %02X\n", data[93], data[94]);
1172 puts ("Assembly Serial Number ");
1173 for (j = 95; j <= 98; j++)
1174 printf ("%02X ", data[j]);
1175 putc ('\n');
1177 if (DDR2 != type) {
1178 printf ("Speed rating PC%d\n",
1179 data[126] == 0x66 ? 66 : data[126]);
1181 return 0;
1183 #endif
1185 #if defined(CONFIG_I2C_CMD_TREE)
1186 #if defined(CONFIG_I2C_MULTI_BUS)
1187 int do_i2c_bus_num(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
1189 int bus_idx, ret=0;
1191 if (argc == 1)
1192 /* querying current setting */
1193 printf("Current bus is %d\n", i2c_get_bus_num());
1194 else {
1195 bus_idx = simple_strtoul(argv[1], NULL, 10);
1196 printf("Setting bus to %d\n", bus_idx);
1197 ret = i2c_set_bus_num(bus_idx);
1198 if (ret)
1199 printf("Failure changing bus number (%d)\n", ret);
1201 return ret;
1203 #endif /* CONFIG_I2C_MULTI_BUS */
1205 int do_i2c_bus_speed(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
1207 int speed, ret=0;
1209 if (argc == 1)
1210 /* querying current speed */
1211 printf("Current bus speed=%d\n", i2c_get_bus_speed());
1212 else {
1213 speed = simple_strtoul(argv[1], NULL, 10);
1214 printf("Setting bus speed to %d Hz\n", speed);
1215 ret = i2c_set_bus_speed(speed);
1216 if (ret)
1217 printf("Failure changing bus speed (%d)\n", ret);
1219 return ret;
1222 int do_i2c(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
1224 #if defined(CONFIG_I2C_MULTI_BUS)
1225 if (!strncmp(argv[1], "de", 2))
1226 return do_i2c_bus_num(cmdtp, flag, --argc, ++argv);
1227 #endif /* CONFIG_I2C_MULTI_BUS */
1228 if (!strncmp(argv[1], "sp", 2))
1229 return do_i2c_bus_speed(cmdtp, flag, --argc, ++argv);
1230 if (!strncmp(argv[1], "md", 2))
1231 return do_i2c_md(cmdtp, flag, --argc, ++argv);
1232 if (!strncmp(argv[1], "mm", 2))
1233 return do_i2c_mm(cmdtp, flag, --argc, ++argv);
1234 if (!strncmp(argv[1], "mw", 2))
1235 return do_i2c_mw(cmdtp, flag, --argc, ++argv);
1236 if (!strncmp(argv[1], "nm", 2))
1237 return do_i2c_nm(cmdtp, flag, --argc, ++argv);
1238 if (!strncmp(argv[1], "cr", 2))
1239 return do_i2c_crc(cmdtp, flag, --argc, ++argv);
1240 if (!strncmp(argv[1], "pr", 2))
1241 return do_i2c_probe(cmdtp, flag, --argc, ++argv);
1242 if (!strncmp(argv[1], "lo", 2))
1243 return do_i2c_loop(cmdtp, flag, --argc, ++argv);
1244 #if defined(CONFIG_CMD_SDRAM)
1245 if (!strncmp(argv[1], "sd", 2))
1246 return do_sdram(cmdtp, flag, --argc, ++argv);
1247 #endif
1248 else
1249 printf ("Usage:\n%s\n", cmdtp->usage);
1250 return 0;
1252 #endif /* CONFIG_I2C_CMD_TREE */
1254 /***************************************************/
1256 #if defined(CONFIG_I2C_CMD_TREE)
1257 U_BOOT_CMD(
1258 i2c, 6, 1, do_i2c,
1259 "i2c - I2C sub-system\n",
1260 #if defined(CONFIG_I2C_MULTI_BUS)
1261 "dev [dev] - show or set current I2C bus\n"
1262 #endif /* CONFIG_I2C_MULTI_BUS */
1263 "i2c speed [speed] - show or set I2C bus speed\n"
1264 "i2c md chip address[.0, .1, .2] [# of objects] - read from I2C device\n"
1265 "i2c mm chip address[.0, .1, .2] - write to I2C device (auto-incrementing)\n"
1266 "i2c mw chip address[.0, .1, .2] value [count] - write to I2C device (fill)\n"
1267 "i2c nm chip address[.0, .1, .2] - write to I2C device (constant address)\n"
1268 "i2c crc32 chip address[.0, .1, .2] count - compute CRC32 checksum\n"
1269 "i2c probe - show devices on the I2C bus\n"
1270 "i2c loop chip address[.0, .1, .2] [# of objects] - looping read of device\n"
1271 #if defined(CONFIG_CMD_SDRAM)
1272 "i2c sdram chip - print SDRAM configuration information\n"
1273 #endif
1275 #endif /* CONFIG_I2C_CMD_TREE */
1276 U_BOOT_CMD(
1277 imd, 4, 1, do_i2c_md, \
1278 "imd - i2c memory display\n", \
1279 "chip address[.0, .1, .2] [# of objects]\n - i2c memory display\n" \
1282 U_BOOT_CMD(
1283 imm, 3, 1, do_i2c_mm,
1284 "imm - i2c memory modify (auto-incrementing)\n",
1285 "chip address[.0, .1, .2]\n"
1286 " - memory modify, auto increment address\n"
1288 U_BOOT_CMD(
1289 inm, 3, 1, do_i2c_nm,
1290 "inm - memory modify (constant address)\n",
1291 "chip address[.0, .1, .2]\n - memory modify, read and keep address\n"
1294 U_BOOT_CMD(
1295 imw, 5, 1, do_i2c_mw,
1296 "imw - memory write (fill)\n",
1297 "chip address[.0, .1, .2] value [count]\n - memory write (fill)\n"
1300 U_BOOT_CMD(
1301 icrc32, 5, 1, do_i2c_crc,
1302 "icrc32 - checksum calculation\n",
1303 "chip address[.0, .1, .2] count\n - compute CRC32 checksum\n"
1306 U_BOOT_CMD(
1307 iprobe, 1, 1, do_i2c_probe,
1308 "iprobe - probe to discover valid I2C chip addresses\n",
1309 "\n -discover valid I2C chip addresses\n"
1313 * Require full name for "iloop" because it is an infinite loop!
1315 U_BOOT_CMD(
1316 iloop, 5, 1, do_i2c_loop,
1317 "iloop - infinite loop on address range\n",
1318 "chip address[.0, .1, .2] [# of objects]\n"
1319 " - loop, reading a set of addresses\n"
1322 #if defined(CONFIG_CMD_SDRAM)
1323 U_BOOT_CMD(
1324 isdram, 2, 1, do_sdram,
1325 "isdram - print SDRAM configuration information\n",
1326 "chip\n - print SDRAM configuration information\n"
1327 " (valid chip values 50..57)\n"
1329 #endif