drivers/net/dm9000x.c

   1 /*
   2   dm9000.c: Version 1.2 12/15/2003
   3
   4         A Davicom DM9000 ISA NIC fast Ethernet driver for Linux.
   5         Copyright (C) 1997  Sten Wang
   6
   7         This program is free software; you can redistribute it and/or
   8         modify it under the terms of the GNU General Public License
   9         as published by the Free Software Foundation; either version 2
  10         of the License, or (at your option) any later version.
  11
  12         This program is distributed in the hope that it will be useful,
  13         but WITHOUT ANY WARRANTY; without even the implied warranty of
  14         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15         GNU General Public License for more details.
  16
  17   (C)Copyright 1997-1998 DAVICOM Semiconductor,Inc. All Rights Reserved.
  18
  19 V0.11   06/20/2001      REG_0A bit3=1, default enable BP with DA match
  20         06/22/2001      Support DM9801 progrmming
  21                         E3: R25 = ((R24 + NF) & 0x00ff) | 0xf000
  22                         E4: R25 = ((R24 + NF) & 0x00ff) | 0xc200
  23                 R17 = (R17 & 0xfff0) | NF + 3
  24                         E5: R25 = ((R24 + NF - 3) & 0x00ff) | 0xc200
  25                 R17 = (R17 & 0xfff0) | NF
  26
  27 v1.00                   modify by simon 2001.9.5
  28                         change for kernel 2.4.x
  29
  30 v1.1   11/09/2001       fix force mode bug
  31
  32 v1.2   03/18/2003       Weilun Huang <weilun_huang@davicom.com.tw>:
  33                         Fixed phy reset.
  34                         Added tx/rx 32 bit mode.
  35                         Cleaned up for kernel merge.
  36
  37 --------------------------------------
  38
  39        12/15/2003       Initial port to u-boot by
  40                         Sascha Hauer <saschahauer@web.de>
  41
  42        06/03/2008       Remy Bohmer <linux@bohmer.net>
  43                         - Fixed the driver to work with DM9000A.
  44                           (check on ISR receive status bit before reading the
  45                           FIFO as described in DM9000 programming guide and
  46                           application notes)
  47                         - Added autodetect of databus width.
  48                         - Made debug code compile again.
  49                         - Adapt eth_send such that it matches the DM9000*
  50                           application notes. Needed to make it work properly
  51                           for DM9000A.
  52                         - Adapted reset procedure to match DM9000 application
  53                           notes (i.e. double reset)
  54                         - some minor code cleanups
  55                         These changes are tested with DM9000{A,EP,E} together
  56                         with a 200MHz Atmel AT91SAM92161 core
  57
  58 TODO: external MII is not functional, only internal at the moment.
  59 */
  60
  61 #include <common.h>
  62 #include <command.h>
  63 #include <net.h>
  64 #include <asm/io.h>
  65
  66 #include "dm9000x.h"
  67
  68 /* Board/System/Debug information/definition ---------------- */
  69
  70 /* #define CONFIG_DM9000_DEBUG */
  71
  72 #ifdef CONFIG_DM9000_DEBUG
  73 #define DM9000_DBG(fmt,args...) printf(fmt, ##args)
  74 #define DM9000_DMP_PACKET(func,packet,length)  \
  75         do { \
  76                 int i;                                                  \
  77                 printf(func ": length: %d\n", length);                  \
  78                 for (i = 0; i < length; i++) {                          \
  79                         if (i % 8 == 0)                                 \
  80                                 printf("\n%s: %02x: ", func, i);        \
  81                         printf("%02x ", ((unsigned char *) packet)[i]); \
  82                 } printf("\n");                                         \
  83         } while(0)
  84 #else
  85 #define DM9000_DBG(fmt,args...)
  86 #define DM9000_DMP_PACKET(func,packet,length)
  87 #endif
  88
  89 /* Structure/enum declaration ------------------------------- */
  90 typedef struct board_info {
  91         u32 runt_length_counter;        /* counter: RX length < 64byte */
  92         u32 long_length_counter;        /* counter: RX length > 1514byte */
  93         u32 reset_counter;      /* counter: RESET */
  94         u32 reset_tx_timeout;   /* RESET caused by TX Timeout */
  95         u32 reset_rx_status;    /* RESET caused by RX Statsus wrong */
  96         u16 tx_pkt_cnt;
  97         u16 queue_start_addr;
  98         u16 dbug_cnt;
  99         u8 phy_addr;
 100         u8 device_wait_reset;   /* device state */
 101         unsigned char srom[128];
 102         void (*outblk)(volatile void *data_ptr, int count);
 103         void (*inblk)(void *data_ptr, int count);
 104         void (*rx_status)(u16 *RxStatus, u16 *RxLen);
 105 } board_info_t;
 106 static board_info_t dm9000_info;
 107
 108 /* function declaration ------------------------------------- */
 109 int eth_init(bd_t * bd);
 110 int eth_send(volatile void *, int);
 111 int eth_rx(void);
 112 void eth_halt(void);
 113 static int dm9000_probe(void);
 114 static u16 phy_read(int);
 115 static void phy_write(int, u16);
 116 u16 read_srom_word(int);
 117 static u8 DM9000_ior(int);
 118 static void DM9000_iow(int reg, u8 value);
 119
 120 /* DM9000 network board routine ---------------------------- */
 121
 122 #define DM9000_outb(d,r) ( *(volatile u8 *)r = d )
 123 #define DM9000_outw(d,r) ( *(volatile u16 *)r = d )
 124 #define DM9000_outl(d,r) ( *(volatile u32 *)r = d )
 125 #define DM9000_inb(r) (*(volatile u8 *)r)
 126 #define DM9000_inw(r) (*(volatile u16 *)r)
 127 #define DM9000_inl(r) (*(volatile u32 *)r)
 128
 129 #ifdef CONFIG_DM9000_DEBUG
 130 static void
 131 dump_regs(void)
 132 {
 133         DM9000_DBG("\n");
 134         DM9000_DBG("NCR   (0x00): %02x\n", DM9000_ior(0));
 135         DM9000_DBG("NSR   (0x01): %02x\n", DM9000_ior(1));
 136         DM9000_DBG("TCR   (0x02): %02x\n", DM9000_ior(2));
 137         DM9000_DBG("TSRI  (0x03): %02x\n", DM9000_ior(3));
 138         DM9000_DBG("TSRII (0x04): %02x\n", DM9000_ior(4));
 139         DM9000_DBG("RCR   (0x05): %02x\n", DM9000_ior(5));
 140         DM9000_DBG("RSR   (0x06): %02x\n", DM9000_ior(6));
 141         DM9000_DBG("ISR   (0xFE): %02x\n", DM9000_ior(DM9000_ISR));
 142         DM9000_DBG("\n");
 143 }
 144 #endif
 145
 146 static void dm9000_outblk_8bit(volatile void *data_ptr, int count)
 147 {
 148         int i;
 149         for (i = 0; i < count; i++)
 150                 DM9000_outb((((u8 *) data_ptr)[i] & 0xff), DM9000_DATA);
 151 }
 152
 153 static void dm9000_outblk_16bit(volatile void *data_ptr, int count)
 154 {
 155         int i;
 156         u32 tmplen = (count + 1) / 2;
 157
 158         for (i = 0; i < tmplen; i++)
 159                 DM9000_outw(((u16 *) data_ptr)[i], DM9000_DATA);
 160 }
 161 static void dm9000_outblk_32bit(volatile void *data_ptr, int count)
 162 {
 163         int i;
 164         u32 tmplen = (count + 3) / 4;
 165
 166         for (i = 0; i < tmplen; i++)
 167                 DM9000_outl(((u32 *) data_ptr)[i], DM9000_DATA);
 168 }
 169
 170 static void dm9000_inblk_8bit(void *data_ptr, int count)
 171 {
 172         int i;
 173         for (i = 0; i < count; i++)
 174                 ((u8 *) data_ptr)[i] = DM9000_inb(DM9000_DATA);
 175 }
 176
 177 static void dm9000_inblk_16bit(void *data_ptr, int count)
 178 {
 179         int i;
 180         u32 tmplen = (count + 1) / 2;
 181
 182         for (i = 0; i < tmplen; i++)
 183                 ((u16 *) data_ptr)[i] = DM9000_inw(DM9000_DATA);
 184 }
 185 static void dm9000_inblk_32bit(void *data_ptr, int count)
 186 {
 187         int i;
 188         u32 tmplen = (count + 3) / 4;
 189
 190         for (i = 0; i < tmplen; i++)
 191                 ((u32 *) data_ptr)[i] = DM9000_inl(DM9000_DATA);
 192 }
 193
 194 static void dm9000_rx_status_32bit(u16 *RxStatus, u16 *RxLen)
 195 {
 196         u32 tmpdata;
 197
 198         DM9000_outb(DM9000_MRCMD, DM9000_IO);
 199
 200         tmpdata = DM9000_inl(DM9000_DATA);
 201         *RxStatus = __le16_to_cpu(tmpdata);
 202         *RxLen = __le16_to_cpu(tmpdata >> 16);
 203 }
 204
 205 static void dm9000_rx_status_16bit(u16 *RxStatus, u16 *RxLen)
 206 {
 207         DM9000_outb(DM9000_MRCMD, DM9000_IO);
 208
 209         *RxStatus = __le16_to_cpu(DM9000_inw(DM9000_DATA));
 210         *RxLen = __le16_to_cpu(DM9000_inw(DM9000_DATA));
 211 }
 212
 213 static void dm9000_rx_status_8bit(u16 *RxStatus, u16 *RxLen)
 214 {
 215         DM9000_outb(DM9000_MRCMD, DM9000_IO);
 216
 217         *RxStatus =
 218             __le16_to_cpu(DM9000_inb(DM9000_DATA) +
 219                           (DM9000_inb(DM9000_DATA) << 8));
 220         *RxLen =
 221             __le16_to_cpu(DM9000_inb(DM9000_DATA) +
 222                           (DM9000_inb(DM9000_DATA) << 8));
 223 }
 224
 225 /*
 226   Search DM9000 board, allocate space and register it
 227 */
 228 int
 229 dm9000_probe(void)
 230 {
 231         u32 id_val;
 232         id_val = DM9000_ior(DM9000_VIDL);
 233         id_val |= DM9000_ior(DM9000_VIDH) << 8;
 234         id_val |= DM9000_ior(DM9000_PIDL) << 16;
 235         id_val |= DM9000_ior(DM9000_PIDH) << 24;
 236         if (id_val == DM9000_ID) {
 237                 printf("dm9000 i/o: 0x%x, id: 0x%x \n", CONFIG_DM9000_BASE,
 238                        id_val);
 239                 return 0;
 240         } else {
 241                 printf("dm9000 not found at 0x%08x id: 0x%08x\n",
 242                        CONFIG_DM9000_BASE, id_val);
 243                 return -1;
 244         }
 245 }
 246
 247 /* General Purpose dm9000 reset routine */
 248 static void
 249 dm9000_reset(void)
 250 {
 251         DM9000_DBG("resetting DM9000\n");
 252
 253         /* Reset DM9000,
 254            see DM9000 Application Notes V1.22 Jun 11, 2004 page 29 */
 255
 256         /* DEBUG: Make all GPIO0 outputs, all others inputs */
 257         DM9000_iow(DM9000_GPCR, GPCR_GPIO0_OUT);
 258         /* Step 1: Power internal PHY by writing 0 to GPIO0 pin */
 259         DM9000_iow(DM9000_GPR, 0);
 260         /* Step 2: Software reset */
 261         DM9000_iow(DM9000_NCR, (NCR_LBK_INT_MAC | NCR_RST));
 262
 263         do {
 264                 DM9000_DBG("resetting the DM9000, 1st reset\n");
 265                 udelay(25); /* Wait at least 20 us */
 266         } while (DM9000_ior(DM9000_NCR) & 1);
 267
 268         DM9000_iow(DM9000_NCR, 0);
 269         DM9000_iow(DM9000_NCR, (NCR_LBK_INT_MAC | NCR_RST)); /* Issue a second reset */
 270
 271         do {
 272                 DM9000_DBG("resetting the DM9000, 2nd reset\n");
 273                 udelay(25); /* Wait at least 20 us */
 274         } while (DM9000_ior(DM9000_NCR) & 1);
 275
 276         /* Check whether the ethernet controller is present */
 277         if ((DM9000_ior(DM9000_PIDL) != 0x0) ||
 278             (DM9000_ior(DM9000_PIDH) != 0x90))
 279                 printf("ERROR: resetting DM9000 -> not responding\n");
 280 }
 281
 282 /* Initilize dm9000 MAC, without reset
 283 */
 284 int
 285 eth_set_mac(bd_t * bd)
 286 {
 287         int i,oft;
 288         printf("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n", bd->bi_enetaddr[0],
 289                bd->bi_enetaddr[1], bd->bi_enetaddr[2], bd->bi_enetaddr[3],
 290                bd->bi_enetaddr[4], bd->bi_enetaddr[5]);
 291
 292         /* fill device MAC address registers */
 293         for (i = 0, oft = DM9000_PAR; i < 6; i++, oft++)
 294                 DM9000_iow(oft, bd->bi_enetaddr[i]);
 295         for (i = 0, oft = 0x16; i < 8; i++, oft++)
 296                 DM9000_iow(oft, 0xff);
 297
 298         /* read back mac, just to be sure */
 299         for (i = 0, oft = 0x10; i < 6; i++, oft++)
 300                 DM9000_DBG("%02x:", DM9000_ior(oft));
 301         DM9000_DBG("\n");
 302         return 0;
 303 }
 304
 305 /* Initilize dm9000 board
 306 */
 307 int
 308 eth_init(bd_t * bd)
 309 {
 310         int i, oft, lnk;
 311         u8 io_mode;
 312         struct board_info *db = &dm9000_info;
 313
 314         DM9000_DBG("eth_init()\n");
 315
 316         /* RESET device */
 317         dm9000_reset();
 318
 319         if (dm9000_probe() < 0)
 320                 return -1;
 321
 322         /* Auto-detect 8/16/32 bit mode, ISR Bit 6+7 indicate bus width */
 323         io_mode = DM9000_ior(DM9000_ISR) >> 6;
 324
 325         switch (io_mode) {
 326         case 0x0:  /* 16-bit mode */
 327                 printf("DM9000: running in 16 bit mode\n");
 328                 db->outblk    = dm9000_outblk_16bit;
 329                 db->inblk     = dm9000_inblk_16bit;
 330                 db->rx_status = dm9000_rx_status_16bit;
 331                 break;
 332         case 0x01:  /* 32-bit mode */
 333                 printf("DM9000: running in 32 bit mode\n");
 334                 db->outblk    = dm9000_outblk_32bit;
 335                 db->inblk     = dm9000_inblk_32bit;
 336                 db->rx_status = dm9000_rx_status_32bit;
 337                 break;
 338         case 0x02: /* 8 bit mode */
 339                 printf("DM9000: running in 8 bit mode\n");
 340                 db->outblk    = dm9000_outblk_8bit;
 341                 db->inblk     = dm9000_inblk_8bit;
 342                 db->rx_status = dm9000_rx_status_8bit;
 343                 break;
 344         default:
 345                 /* Assume 8 bit mode, will probably not work anyway */
 346                 printf("DM9000: Undefined IO-mode:0x%x\n", io_mode);
 347                 db->outblk    = dm9000_outblk_8bit;
 348                 db->inblk     = dm9000_inblk_8bit;
 349                 db->rx_status = dm9000_rx_status_8bit;
 350                 break;
 351         }
 352
 353         /* Program operating register, only internal phy supported */
 354         DM9000_iow(DM9000_NCR, 0x0);
 355         /* TX Polling clear */
 356         DM9000_iow(DM9000_TCR, 0);
 357         /* Less 3Kb, 200us */
 358         DM9000_iow(DM9000_BPTR, BPTR_BPHW(3) | BPTR_JPT_600US);
 359         /* Flow Control : High/Low Water */
 360         DM9000_iow(DM9000_FCTR, FCTR_HWOT(3) | FCTR_LWOT(8));
 361         /* SH FIXME: This looks strange! Flow Control */
 362         DM9000_iow(DM9000_FCR, 0x0);
 363         /* Special Mode */
 364         DM9000_iow(DM9000_SMCR, 0);
 365         /* clear TX status */
 366         DM9000_iow(DM9000_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END);
 367         /* Clear interrupt status */
 368         DM9000_iow(DM9000_ISR, ISR_ROOS | ISR_ROS | ISR_PTS | ISR_PRS);
 369
 370         /* Set Node address */
 371 #if !defined(CONFIG_AT91SAM9261EK) && !defined(CONFIG_DRIVER_DM9000_NO_EEPROM)
 372         for (i = 0; i < 6; i++)
 373                 ((u16 *) bd->bi_enetaddr)[i] = read_srom_word(i);
 374 #endif
 375
 376         if (is_zero_ether_addr(bd->bi_enetaddr) ||
 377             is_multicast_ether_addr(bd->bi_enetaddr)) {
 378                 /* try reading from environment */
 379                 u8 i;
 380                 char *s, *e;
 381                 s = getenv ("ethaddr");
 382                 for (i = 0; i < 6; ++i) {
 383                         bd->bi_enetaddr[i] = s ?
 384                                 simple_strtoul (s, &e, 16) : 0;
 385                         if (s)
 386                                 s = (*e) ? e + 1 : e;
 387                 }
 388         }
 389         eth_set_mac(bd);
 390
 391         /* Activate DM9000 */
 392         /* RX enable */
 393         DM9000_iow(DM9000_RCR, RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN);
 394         /* Enable TX/RX interrupt mask */
 395         DM9000_iow(DM9000_IMR, IMR_PAR);
 396
 397 #ifdef CONFIG_MINI2440
 398         // PHY read status doesn't work anyway
 399         return 0;
 400 #endif
 401         i = 0;
 402         while (!(phy_read(1) & 0x20)) { /* autonegation complete bit */
 403                 udelay(1000);
 404                 i++;
 405                 if (i == 10000) {
 406                         printf("could not establish link\n");
 407                         return 0;
 408                 }
 409         }
 410
 411         /* see what we've got */
 412         lnk = phy_read(17) >> 12;
 413         printf("operating at ");
 414         switch (lnk) {
 415         case 1:
 416                 printf("10M half duplex ");
 417                 break;
 418         case 2:
 419                 printf("10M full duplex ");
 420                 break;
 421         case 4:
 422                 printf("100M half duplex ");
 423                 break;
 424         case 8:
 425                 printf("100M full duplex ");
 426                 break;
 427         default:
 428                 printf("unknown: %d ", lnk);
 429                 break;
 430         }
 431         printf("mode\n");
 432         return 0;
 433 }
 434
 435 /*
 436   Hardware start transmission.
 437   Send a packet to media from the upper layer.
 438 */
 439 int
 440 eth_send(volatile void *packet, int length)
 441 {
 442         int tmo;
 443         struct board_info *db = &dm9000_info;
 444
 445         DM9000_DMP_PACKET("eth_send", packet, length);
 446
 447         DM9000_iow(DM9000_ISR, IMR_PTM); /* Clear Tx bit in ISR */
 448
 449         /* Move data to DM9000 TX RAM */
 450         DM9000_outb(DM9000_MWCMD, DM9000_IO); /* Prepare for TX-data */
 451
 452         /* push the data to the TX-fifo */
 453         (db->outblk)(packet, length);
 454
 455         /* Set TX length to DM9000 */
 456         DM9000_iow(DM9000_TXPLL, length & 0xff);
 457         DM9000_iow(DM9000_TXPLH, (length >> 8) & 0xff);
 458
 459         /* Issue TX polling command */
 460         DM9000_iow(DM9000_TCR, TCR_TXREQ); /* Cleared after TX complete */
 461
 462         /* wait for end of transmission */
 463         tmo = get_timer(0) + 5 * CFG_HZ;
 464         while ( !(DM9000_ior(DM9000_NSR) & (NSR_TX1END | NSR_TX2END)) ||
 465                 !(DM9000_ior(DM9000_ISR) & IMR_PTM) ) {
 466                 if (get_timer(0) >= tmo) {
 467                         printf("transmission timeout\n");
 468                         break;
 469                 }
 470         }
 471         DM9000_iow(DM9000_ISR, IMR_PTM); /* Clear Tx bit in ISR */
 472
 473         DM9000_DBG("transmit done\n\n");
 474         return 0;
 475 }
 476
 477 /*
 478   Stop the interface.
 479   The interface is stopped when it is brought.
 480 */
 481 void
 482 eth_halt(void)
 483 {
 484         DM9000_DBG("eth_halt\n");
 485
 486         /* RESET devie */
 487         phy_write(0, 0x8000);   /* PHY RESET */
 488         DM9000_iow(DM9000_GPR, 0x01);   /* Power-Down PHY */
 489         DM9000_iow(DM9000_IMR, 0x80);   /* Disable all interrupt */
 490         DM9000_iow(DM9000_RCR, 0x00);   /* Disable RX */
 491 }
 492
 493 /*
 494   Received a packet and pass to upper layer
 495 */
 496 int
 497 eth_rx(void)
 498 {
 499         u8 rxbyte, *rdptr = (u8 *) NetRxPackets[0];
 500         u16 RxStatus, RxLen = 0;
 501         struct board_info *db = &dm9000_info;
 502
 503         /* Check packet ready or not, we must check
 504            the ISR status first for DM9000A */
 505         if (!(DM9000_ior(DM9000_ISR) & 0x01)) /* Rx-ISR bit must be set. */
 506                 return 0;
 507
 508         DM9000_iow(DM9000_ISR, 0x01); /* clear PR status latched in bit 0 */
 509
 510         /* There is _at least_ 1 package in the fifo, read them all */
 511         for (;;) {
 512                 DM9000_ior(DM9000_MRCMDX);      /* Dummy read */
 513
 514                 /* Get most updated data,
 515                    only look at bits 0:1, See application notes DM9000 */
 516                 rxbyte = DM9000_inb(DM9000_DATA) & 0x03;
 517
 518                 /* Status check: this byte must be 0 or 1 */
 519                 if (rxbyte > DM9000_PKT_RDY) {
 520                         DM9000_iow(DM9000_RCR, 0x00);   /* Stop Device */
 521                         DM9000_iow(DM9000_ISR, 0x80);   /* Stop INT request */
 522                         printf("DM9000 error: status check fail: 0x%x\n",
 523                                 rxbyte);
 524                         return 0;
 525                 }
 526
 527                 if (rxbyte != DM9000_PKT_RDY)
 528                         return 0; /* No packet received, ignore */
 529
 530                 DM9000_DBG("receiving packet\n");
 531
 532                 /* A packet ready now  & Get status/length */
 533                 (db->rx_status)(&RxStatus, &RxLen);
 534
 535                 DM9000_DBG("rx status: 0x%04x rx len: %d\n", RxStatus, RxLen);
 536
 537                 /* Move data from DM9000 */
 538                 /* Read received packet from RX SRAM */
 539                 (db->inblk)(rdptr, RxLen);
 540
 541                 if ((RxStatus & 0xbf00) || (RxLen < 0x40)
 542                         || (RxLen > DM9000_PKT_MAX)) {
 543                         if (RxStatus & 0x100) {
 544                                 printf("rx fifo error\n");
 545                         }
 546                         if (RxStatus & 0x200) {
 547                                 printf("rx crc error\n");
 548                         }
 549                         if (RxStatus & 0x8000) {
 550                                 printf("rx length error\n");
 551                         }
 552                         if (RxLen > DM9000_PKT_MAX) {
 553                                 printf("rx length too big\n");
 554                                 dm9000_reset();
 555                         }
 556                 } else {
 557                         DM9000_DMP_PACKET("eth_rx", rdptr, RxLen);
 558
 559                         DM9000_DBG("passing packet to upper layer\n");
 560                         NetReceive(NetRxPackets[0], RxLen);
 561                 }
 562         }
 563         return 0;
 564 }
 565
 566 /*
 567   Read a word data from SROM
 568 */
 569 u16
 570 read_srom_word(int offset)
 571 {
 572         DM9000_iow(DM9000_EPAR, offset);
 573         DM9000_iow(DM9000_EPCR, 0x4);
 574         udelay(8000);
 575         DM9000_iow(DM9000_EPCR, 0x0);
 576         return (DM9000_ior(DM9000_EPDRL) + (DM9000_ior(DM9000_EPDRH) << 8));
 577 }
 578
 579 void
 580 write_srom_word(int offset, u16 val)
 581 {
 582         DM9000_iow(DM9000_EPAR, offset);
 583         DM9000_iow(DM9000_EPDRH, ((val >> 8) & 0xff));
 584         DM9000_iow(DM9000_EPDRL, (val & 0xff));
 585         DM9000_iow(DM9000_EPCR, 0x12);
 586         udelay(8000);
 587         DM9000_iow(DM9000_EPCR, 0);
 588 }
 589
 590
 591 /*
 592    Read a byte from I/O port
 593 */
 594 static u8
 595 DM9000_ior(int reg)
 596 {
 597         DM9000_outb(reg, DM9000_IO);
 598         return DM9000_inb(DM9000_DATA);
 599 }
 600
 601 /*
 602    Write a byte to I/O port
 603 */
 604 static void
 605 DM9000_iow(int reg, u8 value)
 606 {
 607         DM9000_outb(reg, DM9000_IO);
 608         DM9000_outb(value, DM9000_DATA);
 609 }
 610
 611 /*
 612    Read a word from phyxcer
 613 */
 614 static u16
 615 phy_read(int reg)
 616 {
 617         u16 val;
 618
 619         /* Fill the phyxcer register into REG_0C */
 620         DM9000_iow(DM9000_EPAR, DM9000_PHY | reg);
 621         DM9000_iow(DM9000_EPCR, 0xc);   /* Issue phyxcer read command */
 622         udelay(100);                    /* Wait read complete */
 623         DM9000_iow(DM9000_EPCR, 0x0);   /* Clear phyxcer read command */
 624         val = (DM9000_ior(DM9000_EPDRH) << 8) | DM9000_ior(DM9000_EPDRL);
 625
 626         /* The read data keeps on REG_0D & REG_0E */
 627         DM9000_DBG("phy_read(0x%x): 0x%x\n", reg, val);
 628         return val;
 629 }
 630
 631 /*
 632    Write a word to phyxcer
 633 */
 634 static void
 635 phy_write(int reg, u16 value)
 636 {
 637
 638         /* Fill the phyxcer register into REG_0C */
 639         DM9000_iow(DM9000_EPAR, DM9000_PHY | reg);
 640
 641         /* Fill the written data into REG_0D & REG_0E */
 642         DM9000_iow(DM9000_EPDRL, (value & 0xff));
 643         DM9000_iow(DM9000_EPDRH, ((value >> 8) & 0xff));
 644         DM9000_iow(DM9000_EPCR, 0xa);   /* Issue phyxcer write command */
 645         udelay(500);                    /* Wait write complete */
 646         DM9000_iow(DM9000_EPCR, 0x0);   /* Clear phyxcer write command */
 647         DM9000_DBG("phy_write(reg:0x%x, value:0x%x)\n", reg, value);
 648 }