21 * set the cpu to SVC32 mode
28 /* turn off the watchdog */
29 #define pWTCON 0x53000000
30 #define INTMSK 0x4A000008 /* Interupt-Controller base addresses */
31 #define INTSUBMSK 0x4A00001C
32 #define CLKDIVN 0x4C000014 /* clock divisor register */
45 /* FCLK:HCLK:PCLK = 1:2:4 */
46 /* default FCLK is 120 MHz ! */
60 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
61 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
64 * disable MMU stuff and caches
66 mrc p15, 0, r0, c1, c0, 0
67 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
68 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
69 orr r0, r0, #0x00000002 @ set bit 2 (A) Align
70 orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
71 mcr p15, 0, r0, c1, c0, 0
74 * before relocating, we have to setup RAM timing
75 * because memory timing is board-dependend, you will
76 * find a lowlevel_init.S in your board directory.