1 * Z:\trinary\code\circuits\tnand_test.asc
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2 VA A 0 PWL file=INPUT_A.txt
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3 XX1 A B TNAND_Out tnand
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4 VB B 0 PWL file=INPUT_B.txt
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5 XU1 $G_Vdd $G_Vss tpower
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7 * block symbol definitions
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8 .subckt tnand A B TNAND_Out
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11 MP1 NP B $G_Vdd $G_Vdd CD4007P
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12 MP2 NP A $G_Vdd $G_Vdd CD4007P
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13 MN2 NI B $G_Vss $G_Vss CD4007N
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14 MN1 NN A NI $G_Vss CD4007N
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17 .subckt tpower Vdd Vss
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24 .lib C:\PROGRA~1\LTC\SwCADIII\lib\cmp\standard.mos
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