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1 # NVRAM board text file for the BCM4703nr
2 # $Copyright (C) 2007 Broadcom Corporation$
3 # All Rights Reserved.
4 # $Id: bcm94703nr.txt,v 1.13 2007-10-25 21:21:54 mtanner Exp $
5 #
6 # THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7 # KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8 # SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
9 # FOR A SPECIFIC PURPOSE OR NON-INFRINGEMENT CONCERNING THIS SOFTWARE.
11 # boardtype describes what type of Broadcom reference board that the design resembles
12 # set a boardtype of BCM94703nr
13 boardtype=0x04c0
15 # boardnum is set by the nvserial program. Don't edit it here.
16 boardnum=${serno}
18 # Board revision is 1.1
19 boardrev=0x1101
21 # NOTE: This "boardflags" entry is ONLY for the 4704, not the 4321. See below for 4321 parameters.
22 # boardflags: (LSB on top, MSB on bottom)
23 # 0 = no Bluetooth coexistence
24 # 0 = GPIO 9 does not control the PA
25 # 0 = does not implement GPIO 13 radio disable indication
26 # 0 = NO RSSI divider
27 # 1 = YES board has RoboSwitch (the BCM5325F)
28 # 0 = OK to power down PLL and chip
29 # 0 = NO can't do high power CCK transmission (disables opo parameter
30 # for power offset between CCK and OFDM)
31 # 0 = NO board does not have ADMtek switch
32 # 0 = NO board does not have VLAN capability
33 # 0 = NO board does not support Afterburner
34 # 0 = NO board uses the PCI bus
35 # 0 = NO board does not have a FEM
36 # 0 = NO board does not have an external LNA
37 # 0 = NO board does not have high gain PA
38 # 0 = NO alternate Bluetooth coexistence
39 # 0 = NO do not use alternate IQ imbalance settings
40 #
41 boardflags=0x0010
43 # sromrev tells the software what "version" of NVRAM is used.
44 sromrev=2
46 # MIPS clock frequency in MHz
47 clkfreq=264
49 # 16MByte DDR SDRAM (4M x 16 x 1)
50 # The sdram_init value is the lower 16-bits of the memory controller's CONFIG register (offset 0x004)
51 # 64 MB DDR SDRAM (4 Meg x 16 x 2)
52 sdram_init=0x0149
53 # The sdram_config value is the lower 16-bits of the memory controller's MEMBuf register (offset 0x010)
54 # which is directly written to the SDRAM's mode register.
55 # Set burst length to 4, burst type to sequential, CAS latency to 2.5, normal mode, burst writes.
56 sdram_config=0x0062
57 # Always set sdram_refresh to 0x0000
58 sdram_refresh=0x0000
59 # Always set sdram_ncdl to 0x0000
60 sdram_ncdl=0x0000
62 # MII0 (et0) connects to the external Ethernet switch (5325F RoboSwitch) for the LAN
63 et0phyaddr=30
64 et0mdcport=0
65 # Set the MAC address of the LAN Ethernet ports
66 # The "maclo" part is filled in by the nvserial program.
67 et0macaddr=00:90:4c:f0:${maclo}
69 # MII1 (et1) connects directly to PHY 4 (not the switch) in the 5325F for the WAN
70 et1phyaddr=4
71 et1mdcport=0
72 # Set the MAC address of the WAN Ethernet port
73 # The "maclo" part is filled in by the nvserial program.
74 et1macaddr=00:90:4c:f1:${maclo}
76 # Set default IP address and net mask for the router.
77 lan_ipaddr=192.168.1.1
78 lan_netmask=255.255.255.0
80 # Set a short delay on boot so the CFE delays a bit before loading Linux. Allows easier S/W updates.
81 boot_wait=on
82 # If boot_wait is on, then "wait_time" sets the wait time from 3 to 20 seconds.
83 wait_time=3
85 # The reset button is on GPIO 7.
86 reset_gpio=7
88 # Bootloader variables for downloading new flash code - don't change!
89 dl_ram_addr=a0001000
90 os_ram_addr=80001000
91 os_flash_addr=bfc40000
92 scratch=a0180000
94 # Board has an external BCM5325 Ethernet switch (RoboSwitch) with the reset line
95 # controlled with GPIO_0 from the CPU chip.
96 gpio0=robo_reset
98 # SES Button on GPIO 6
99 gpio6=ses_button
101 # Watchdog timer in ms (0 will disable), 3000ms is minimum.
102 watchdog=3000
104 # The following section is to configure the on-board (WOMBO) 4322 when it does not have an SROM.
105 # These parameters take the place of the SROM contents.
106 # These parameters must have a special prefix. The format is:
107 # 'pci/<bus_#>/<slot_#>/<param>'
108 #
109 # where: <bus_#> is the PCI bus number – always "1" for current chips
110 # <slot_#> slot number of the WOMBo chip (i.e. the 4322)
111 # slot 0 is (usually) the CPU chip (i.e. the 4703)
112 # slot = 1 if PCI_AD17 connected to IDSEL pin of the WOMBo chip
113 # slot = 2 if PCI_AD18 connected to IDSEL pin of the WOMBo chip
114 # slot = 3 if PCI_AD19 connected to IDSEL pin of the WOMBo chip
115 # <param> is the parameter assignment. i.e. "boardflags=0x0200"
117 # This is the 4322 WOMBO section
119 # venid is the "vendor ID" of the 4321. 0x14E4 is Broadcom (Epigram)
120 pci/1/1/venid=0x14e4
122 # devid is the "device ID" to identify what type of wireless interface this is
123 # 0x432C sets 11n, single band 2.4GHz
124 pci/1/1/devid=0x432C
126 # sromrev tells the software what "version" of NVRAM/SROM is used.
127 pci/1/1/sromrev=8
129 # boardtype is the "type" of Broadcom reference board that the design resembles
130 # sets a board type of BCM94322mp
131 pci/1/1/boardtype=0x04a6
133 # boardvendor is the same as venid
134 pci/1/1/boardvendor=0x14e4
136 # set the rev of the 4322 part of the board
137 # set Rev 1.0
138 pci/1/1/boardrev=0x1101
140 # This is the 'boardflags' parameter for the 4322 only
141 # boardflags: (LSB on top, MSB on bottom)
142 # 0 = no Bluetooth coexistence
143 # 0 = GPIO 9 does not control the PA
144 # 0 = does not implement GPIO 13 radio disable indication
145 # 0 = NO RSSI divider
146 # 0 = NO board does not have a RoboSwitch (not applicable for a MAC/PHY only chip)
147 # 0 = OK to power down PLL and chip
148 # 0 = disables opo parameter for power offset between CCK and OFDM (not applicable for 4321)
149 # 0 = NO board does not have an ADMtek switch (not applicable for a MAC/PHY only chip)
150 # 0 = NO board does not have VLAN capability (not applicable for a MAC/PHY only chip)
151 # 1 = YES board supports Afterburner
152 # 0 = NO board does not disable the PCI bus, i.e. board uses the PCI bus
153 # 0 = NO board does no have a FEM
154 # 0 = NO board does not have an external LNA
155 # 0 = NO board does not have high gain PA
156 # 0 = NO alternate Bluetooth coexistence
157 # 0 = NO do not use alternate IQ imbalance settings
158 # 0 = No board has a PA
159 # 0 = NO board's RSSI does not use positive slope
160 # 0 = NO board does not use the PARef LDO
161 # 0 = NO board does not support phase shifter
162 # 0 = NO board does not have buck/booster
163 # 0 = NO board does not have FEM and switch to share antenna w/ BT
164 pci/1/1/boardflags=0x200
166 # This is the 'boardflags2' parameter for the 4321 only
167 # Awalys set zero for 4322
168 # boardflags2: (LSB on top, MSB on bottom)
169 # 0 = Board uses internal RX baseband regulators in 2055
170 # 0 = NO board does not have the RF superswitch for 2-of-3 antenna diversity
171 # 0 = NO board disables TX power control
172 # 0 = NO board does not support 2-of-4 antenna diversity
173 # 0 = NO board does not support the 5G band power boost
174 # 0 = NO board does not override ASPM and Clkreq settings
175 # 0 = NO board is not Caesers brd
176 # 0 = NO board does not use 3-wire BTC
177 # 0 = NO board does not use Skyworks FEM
178 # 0 = not defined yet
179 # 0 = not defined yet
180 # 0 = not defined yet
181 # 0 = not defined yet
182 # 0 = not defined yet
183 # 0 = not defined yet
184 # 0 = not defined yet
185 pci/1/1/boardflags2=0x0000
187 # macaddr sets the MAC address of the 4321 11n wireless interface
188 # The value of 00:90:4C:d6 is for a BCM94322mp reference design.
189 # The "maclo" part is filled in by the nvserial program.
190 pci/1/1/macaddr=00:90:4C:F2:${maclo}
192 # ccode is the "Country Code". 0 sets "all"
193 # This parameter should be changed depending upon where the board is shipped.
194 pci/1/1/ccode=0x0
196 # regrev is the regulatory revision number
197 pci/1/1/regrev=0x0
199 # ledbhX sets the LED behaviour of LEDs connected to the GPIO[3:0] pins of the 4322
200 # See app note "80211-AN500-RDS LED guide.pdf" for more details.
202 # GPIO 7 is wireless activity - 2 = WL_LED_ACTIVITY
203 pci/1/1/ledbh0=02
204 # don't control GPIOs 1-5
205 pci/1/1/ledbh1=11
206 pci/1/1/ledbh2=11
207 pci/1/1/ledbh3=11
208 # Driver can actually control more LEDs.
209 pci/1/1/ledbh4=11
210 pci/1/1/ledbh5=11
212 # leddc is the duty cycle for PWM control of the LEDs.
213 # 0xFFFF sets 100% duty cycle
214 pci/1/1/leddc=0xFFFF
216 # pci/1/1/aa2g sets which antennas are available for 2.4GHz. Value is a bit field:
217 # Bit 0 = 1 for antenna 0 is available, 0 for not.
218 # Bit 1 = 1 for antenna 1 is available, 0 for not.
219 # Bit 2 = 1 for antenna 2 is available, 0 for not.
220 # Bit 3 = 1 for antenna 3 is available, 0 for not.
222 pci/1/1/aa2g=0x3
225 # agX sets the antenna gain for antenna X. Lower 6 bits are interpreted as a signed number representing
226 # whole dB. Hi 2 bits represent number of quarter dBs. qdB's are ALWAYS POSITIVE and are
227 # added to whole dBs, so -1 whole dB and 1 qdB = 0x7F = -1dB + 0.25dB = -0.75dB. Range is
228 # -32dB to +31.75 dB.
229 # set 2dB gain for all available antennas
230 pci/1/1/ag0=0x2
231 pci/1/1/ag1=0x2
234 # txchain is a bit field that sets how many TX chains are implemented.
235 # Bit 0 = 1 for TX chain 0 is implemented, 0 for not.
236 # Bit 1 = 1 for TX chain 1 is implemented, 0 for not.
237 # Bit 2 = 1 for TX chain 2 is implemented, 0 for not.
238 # Bit 3 = 1 for TX chain 3 is implemented, 0 for not.
240 pci/1/1/txchain=0x3
242 # rxchain is a bit field that sets how many RX chains are implemented.
243 # Bit 0 = 1 for RX chain 0 is implemented, 0 for not.
244 # Bit 1 = 1 for RX chain 1 is implemented, 0 for not.
245 # Bit 2 = 1 for RX chain 2 is implemented, 0 for not.
246 # Bit 3 = 1 for RX chain 3 is implemented, 0 for not.
248 pci/1/1/rxchain=0x3
250 # antswitch sets the type of antenna diveristy switch used on the board
251 # 0 = no antenna switch
252 # 1 = antenna switch as on BCM94321cb2 2of3
253 # 2 = antenna switch as on BCM94321mp 2of3
254 # WNDR3300 uses the 4321cb2 switch design
255 pci/1/1/antswitch=0x0
259 # itt2ga0 is the TX chain 0 idle target TSSI value for 2.4GHz
260 pci/1/1/itt2ga0=0x20
262 # maxp2ga0 is the TX chain 0 maximum TX output power for 2.4GHz
263 # units of 0.25dB
264 # max TX power is 0x48=72qdBm=18dBm
265 pci/1/1/maxp2ga0=0x48
267 # The following four parameters are the PA parameters for the TX chain 0, 2.4GHz, PA
269 pci/1/1/pa2gw0a0=0xfe9e
270 pci/1/1/pa2gw1a0=0x15D5
271 pci/1/1/pa2gw2a0=0xfae9
273 # itt2ga1 is the TX chain 1 idle target TSSI value for 2.4GHz
274 pci/1/1/itt2ga1=0x20
276 # maxp2ga1 is the TX chain 1 maximum TX output power for 2.4GHz
277 # units of 0.25dB
278 # max TX power is 0x48=72qdBm=18dBm
279 pci/1/1/maxp2ga1=0x48
281 # The following four parameters are the PA parameters for the TX chain 1, 2.4GHz, PA
283 pci/1/1/pa2gw0a1=0xfeb3
284 pci/1/1/pa2gw1a1=0x15C9
285 pci/1/1/pa2gw2a1=0xfaf7
289 ######FEM parameters ###########
290 # TSSI positive slope (1 bit)
291 pci/1/1/tssipos2g=0x1
292 #External-PA gain-type: full-gain (0x0), pa-lite(0x1), no_pa(0x2)
293 pci/1/1/extpagain2g=0x0
294 #support 32 combinations of different Pdet dynamic ranges (5 bits)
295 pci/1/1/pdetrange2g=0x0
296 #TR switch isolation loss between RX0 <-> Ant0 (12:4:40 dB)
297 pci/1/1/triso2g=0x3
298 #AntswitchctrlLUT? configuration: 32 possible choices
299 pci/1/1/antswctl2g=0x0
302 ####used for lpphy only ? #########
303 pci/1/1/bxa2g=0x3
304 pci/1/1/rssisav2g=0x7
305 pci/1/1/rssismc2g=0xf
306 pci/1/1/rssismf2g=0xf
307 pci/1/1/rxpo2g=0xff
308 pci/1/1/tri2g=0xff
310 ##########PO parameters ########################
311 # cck2gpo is the 2.4GHz band CCK power offsets
312 pci/1/1/cck2gpo=0x0
314 # ofdm2gpo is the 2.4GHz band, legacy SISO, OFDM power offsets
315 pci/1/1/ofdm2gpo=0x0
318 # mcs2gpo0 is the 2.4GHz band, 11n MCS 0-3, SISO, power offsets
319 pci/1/1/mcs2gpo0=0x0
320 # mcs2gpo1 is the 2.4GHz band, 11n MCS 4-7, SISO, power offsets
321 pci/1/1/mcs2gpo1=0x0
322 # mcs2gpo2 is the 2.4GHz band, 11n MCS 8-11, SDM, power offsets
323 pci/1/1/mcs2gpo2=0x0
324 # mcs2gpo3 is the 2.4GHz band, 11n MCS 12-15, SDM, power offsets
325 pci/1/1/mcs2gpo3=0x0
326 # mcs2gpo4 is the 2.4GHz band, 11n MCS 16-19, SDM, power offsets
327 pci/1/1/mcs2gpo4=0x0
328 # mcs2gpo5 is the 2.4GHz band, 11n MCS 20-23, SDM, power offsets
329 pci/1/1/mcs2gpo5=0x0
330 # mcs2gpo6 is the 2.4GHz band, 11n MCS 24-27, SDM, power offsets
331 pci/1/1/mcs2gpo6=0x0
332 # mcs2gpo7 is the 2.4GHz band, 11n MCS 28-31, SDM, power offsets
333 pci/1/1/mcs2gpo7=0x0
334 # cddpo is the CDD power offsets, with regard to SISO
335 pci/1/1/cddpo=0x0
337 # stbcpo is the STBC power offsets, with regard to SISO
338 pci/1/1/stbcpo=0x0
340 # bw40po is the 40MHz power offsets, with regard to 20MHz BW
341 pci/1/1/bw40po=0x4
343 # bwduppo is the Dup in 40MHz power offsets, with regard to 20MHz BW
344 pci/1/1/bwduppo=0x0