release/src-rt-6.x.4708/linux/linux-2.6.36/include/sound/vx_core.h

   1 /*
   2  * Driver for Digigram VX soundcards
   3  *
   4  * Hardware core part
   5  *
   6  * Copyright (c) 2002 by Takashi Iwai <tiwai@suse.de>
   7  *
   8  *   This program is free software; you can redistribute it and/or modify
   9  *   it under the terms of the GNU General Public License as published by
  10  *   the Free Software Foundation; either version 2 of the License, or
  11  *   (at your option) any later version.
  12  *
  13  *   This program is distributed in the hope that it will be useful,
  14  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  *   GNU General Public License for more details.
  17  *
  18  *   You should have received a copy of the GNU General Public License
  19  *   along with this program; if not, write to the Free Software
  20  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  21  */
  22
  23 #ifndef __SOUND_VX_COMMON_H
  24 #define __SOUND_VX_COMMON_H
  25
  26 #include <sound/pcm.h>
  27 #include <sound/hwdep.h>
  28 #include <linux/interrupt.h>
  29
  30 #if defined(CONFIG_FW_LOADER) || defined(CONFIG_FW_LOADER_MODULE)
  31 #if !defined(CONFIG_USE_VXLOADER) && !defined(CONFIG_SND_VX_LIB)     /* built-in kernel \
  32         */
  33 #define SND_VX_FW_LOADER        /* use the standard firmware loader */
  34 #endif
  35 #endif
  36
  37 struct firmware;
  38 struct device;
  39
  40 #define VX_DRIVER_VERSION       0x010000        /* 1.0.0 */
  41
  42 /*
  43  */
  44 #define SIZE_MAX_CMD    0x10
  45 #define SIZE_MAX_STATUS 0x10
  46
  47 struct vx_rmh {
  48         u16     LgCmd;          /* length of the command to send (WORDs) */
  49         u16     LgStat;         /* length of the status received (WORDs) */
  50         u32     Cmd[SIZE_MAX_CMD];
  51         u32     Stat[SIZE_MAX_STATUS];
  52         u16     DspStat;        /* status type, RMP_SSIZE_XXX */
  53 };
  54
  55 typedef u64 pcx_time_t;
  56
  57 #define VX_MAX_PIPES    16
  58 #define VX_MAX_PERIODS  32
  59 #define VX_MAX_CODECS   2
  60
  61 struct vx_ibl_info {
  62         int size;       /* the current IBL size (0 = query) in bytes */
  63         int max_size;   /* max. IBL size in bytes */
  64         int min_size;   /* min. IBL size in bytes */
  65         int granularity;        /* granularity */
  66 };
  67
  68 struct vx_pipe {
  69         int number;
  70         unsigned int is_capture: 1;
  71         unsigned int data_mode: 1;
  72         unsigned int running: 1;
  73         unsigned int prepared: 1;
  74         int channels;
  75         unsigned int differed_type;
  76         pcx_time_t pcx_time;
  77         struct snd_pcm_substream *substream;
  78
  79         int hbuf_size;          /* H-buffer size in bytes */
  80         int buffer_bytes;       /* the ALSA pcm buffer size in bytes */
  81         int period_bytes;       /* the ALSA pcm period size in bytes */
  82         int hw_ptr;             /* the current hardware pointer in bytes */
  83         int position;           /* the current position in frames (playback only) */
  84         int transferred;        /* the transferred size (per period) in frames */
  85         int align;              /* size of alignment */
  86         u64 cur_count;          /* current sample position (for playback) */
  87
  88         unsigned int references;     /* an output pipe may be used for monitoring and/or playback */
  89         struct vx_pipe *monitoring_pipe;  /* pointer to the monitoring pipe (capture pipe only)*/
  90
  91         struct tasklet_struct start_tq;
  92 };
  93
  94 struct vx_core;
  95
  96 struct snd_vx_ops {
  97         /* low-level i/o */
  98         unsigned char (*in8)(struct vx_core *chip, int reg);
  99         unsigned int (*in32)(struct vx_core *chip, int reg);
 100         void (*out8)(struct vx_core *chip, int reg, unsigned char val);
 101         void (*out32)(struct vx_core *chip, int reg, unsigned int val);
 102         /* irq */
 103         int (*test_and_ack)(struct vx_core *chip);
 104         void (*validate_irq)(struct vx_core *chip, int enable);
 105         /* codec */
 106         void (*write_codec)(struct vx_core *chip, int codec, unsigned int data);
 107         void (*akm_write)(struct vx_core *chip, int reg, unsigned int data);
 108         void (*reset_codec)(struct vx_core *chip);
 109         void (*change_audio_source)(struct vx_core *chip, int src);
 110         void (*set_clock_source)(struct vx_core *chp, int src);
 111         /* chip init */
 112         int (*load_dsp)(struct vx_core *chip, int idx, const struct firmware *fw);
 113         void (*reset_dsp)(struct vx_core *chip);
 114         void (*reset_board)(struct vx_core *chip, int cold_reset);
 115         int (*add_controls)(struct vx_core *chip);
 116         /* pcm */
 117         void (*dma_write)(struct vx_core *chip, struct snd_pcm_runtime *runtime,
 118                           struct vx_pipe *pipe, int count);
 119         void (*dma_read)(struct vx_core *chip, struct snd_pcm_runtime *runtime,
 120                           struct vx_pipe *pipe, int count);
 121 };
 122
 123 struct snd_vx_hardware {
 124         const char *name;
 125         int type;       /* VX_TYPE_XXX */
 126
 127         /* hardware specs */
 128         unsigned int num_codecs;
 129         unsigned int num_ins;
 130         unsigned int num_outs;
 131         unsigned int output_level_max;
 132         const unsigned int *output_level_db_scale;
 133 };
 134
 135 /* hwdep id string */
 136 #define SND_VX_HWDEP_ID         "VX Loader"
 137
 138 /* hardware type */
 139 enum {
 140         /* VX222 PCI */
 141         VX_TYPE_BOARD,          /* old VX222 PCI */
 142         VX_TYPE_V2,             /* VX222 V2 PCI */
 143         VX_TYPE_MIC,            /* VX222 Mic PCI */
 144         /* VX-pocket */
 145         VX_TYPE_VXPOCKET,       /* VXpocket V2 */
 146         VX_TYPE_VXP440,         /* VXpocket 440 */
 147         VX_TYPE_NUMS
 148 };
 149
 150 /* chip status */
 151 enum {
 152         VX_STAT_XILINX_LOADED   = (1 << 0),     /* devices are registered */
 153         VX_STAT_DEVICE_INIT     = (1 << 1),     /* devices are registered */
 154         VX_STAT_CHIP_INIT       = (1 << 2),     /* all operational */
 155         VX_STAT_IN_SUSPEND      = (1 << 10),    /* in suspend phase */
 156         VX_STAT_IS_STALE        = (1 << 15)     /* device is stale */
 157 };
 158
 159 /* min/max values for analog output for old codecs */
 160 #define VX_ANALOG_OUT_LEVEL_MAX         0xe3
 161
 162 struct vx_core {
 163         /* ALSA stuff */
 164         struct snd_card *card;
 165         struct snd_pcm *pcm[VX_MAX_CODECS];
 166         int type;       /* VX_TYPE_XXX */
 167
 168         int irq;
 169         /* ports are defined externally */
 170
 171         /* low-level functions */
 172         struct snd_vx_hardware *hw;
 173         struct snd_vx_ops *ops;
 174
 175         spinlock_t lock;
 176         spinlock_t irq_lock;
 177         struct tasklet_struct tq;
 178
 179         unsigned int chip_status;
 180         unsigned int pcm_running;
 181
 182         struct device *dev;
 183         struct snd_hwdep *hwdep;
 184
 185         struct vx_rmh irq_rmh;  /* RMH used in interrupts */
 186
 187         unsigned int audio_info; /* see VX_AUDIO_INFO */
 188         unsigned int audio_ins;
 189         unsigned int audio_outs;
 190         struct vx_pipe **playback_pipes;
 191         struct vx_pipe **capture_pipes;
 192
 193         /* clock and audio sources */
 194         unsigned int audio_source;      /* current audio input source */
 195         unsigned int audio_source_target;
 196         unsigned int clock_mode;        /* clock mode (VX_CLOCK_MODE_XXX) */
 197         unsigned int clock_source;      /* current clock source (INTERNAL_QUARTZ or UER_SYNC) */
 198         unsigned int freq;              /* current frequency */
 199         unsigned int freq_detected;     /* detected frequency from digital in */
 200         unsigned int uer_detected;      /* VX_UER_MODE_XXX */
 201         unsigned int uer_bits;  /* IEC958 status bits */
 202         struct vx_ibl_info ibl; /* IBL information */
 203
 204         /* mixer setting */
 205         int output_level[VX_MAX_CODECS][2];     /* analog output level */
 206         int audio_gain[2][4];                   /* digital audio level (playback/capture) */
 207         unsigned char audio_active[4];          /* mute/unmute on digital playback */
 208         int audio_monitor[4];                   /* playback hw-monitor level */
 209         unsigned char audio_monitor_active[4];  /* playback hw-monitor mute/unmute */
 210
 211         struct mutex mixer_mutex;
 212
 213         const struct firmware *firmware[4]; /* loaded firmware data */
 214 };
 215
 216
 217 /*
 218  * constructor
 219  */
 220 struct vx_core *snd_vx_create(struct snd_card *card, struct snd_vx_hardware *hw,
 221                               struct snd_vx_ops *ops, int extra_size);
 222 int snd_vx_setup_firmware(struct vx_core *chip);
 223 int snd_vx_load_boot_image(struct vx_core *chip, const struct firmware *dsp);
 224 int snd_vx_dsp_boot(struct vx_core *chip, const struct firmware *dsp);
 225 int snd_vx_dsp_load(struct vx_core *chip, const struct firmware *dsp);
 226
 227 void snd_vx_free_firmware(struct vx_core *chip);
 228
 229 /*
 230  * interrupt handler; exported for pcmcia
 231  */
 232 irqreturn_t snd_vx_irq_handler(int irq, void *dev);
 233
 234 /*
 235  * lowlevel functions
 236  */
 237 static inline int vx_test_and_ack(struct vx_core *chip)
 238 {
 239         return chip->ops->test_and_ack(chip);
 240 }
 241
 242 static inline void vx_validate_irq(struct vx_core *chip, int enable)
 243 {
 244         chip->ops->validate_irq(chip, enable);
 245 }
 246
 247 static inline unsigned char snd_vx_inb(struct vx_core *chip, int reg)
 248 {
 249         return chip->ops->in8(chip, reg);
 250 }
 251
 252 static inline unsigned int snd_vx_inl(struct vx_core *chip, int reg)
 253 {
 254         return chip->ops->in32(chip, reg);
 255 }
 256
 257 static inline void snd_vx_outb(struct vx_core *chip, int reg, unsigned char val)
 258 {
 259         chip->ops->out8(chip, reg, val);
 260 }
 261
 262 static inline void snd_vx_outl(struct vx_core *chip, int reg, unsigned int val)
 263 {
 264         chip->ops->out32(chip, reg, val);
 265 }
 266
 267 #define vx_inb(chip,reg)        snd_vx_inb(chip, VX_##reg)
 268 #define vx_outb(chip,reg,val)   snd_vx_outb(chip, VX_##reg,val)
 269 #define vx_inl(chip,reg)        snd_vx_inl(chip, VX_##reg)
 270 #define vx_outl(chip,reg,val)   snd_vx_outl(chip, VX_##reg,val)
 271
 272 static inline void vx_reset_dsp(struct vx_core *chip)
 273 {
 274         chip->ops->reset_dsp(chip);
 275 }
 276
 277 int vx_send_msg(struct vx_core *chip, struct vx_rmh *rmh);
 278 int vx_send_msg_nolock(struct vx_core *chip, struct vx_rmh *rmh);
 279 int vx_send_rih(struct vx_core *chip, int cmd);
 280 int vx_send_rih_nolock(struct vx_core *chip, int cmd);
 281
 282 void vx_reset_codec(struct vx_core *chip, int cold_reset);
 283
 284 /*
 285  * check the bit on the specified register
 286  * returns zero if a bit matches, or a negative error code.
 287  * exported for vxpocket driver
 288  */
 289 int snd_vx_check_reg_bit(struct vx_core *chip, int reg, int mask, int bit, int time);
 290 #define vx_check_isr(chip,mask,bit,time) snd_vx_check_reg_bit(chip, VX_ISR, mask, bit, time)
 291 #define vx_wait_isr_bit(chip,bit) vx_check_isr(chip, bit, bit, 200)
 292 #define vx_wait_for_rx_full(chip) vx_wait_isr_bit(chip, ISR_RX_FULL)
 293
 294
 295 /*
 296  * pseudo-DMA transfer
 297  */
 298 static inline void vx_pseudo_dma_write(struct vx_core *chip, struct snd_pcm_runtime *runtime,
 299                                        struct vx_pipe *pipe, int count)
 300 {
 301         chip->ops->dma_write(chip, runtime, pipe, count);
 302 }
 303
 304 static inline void vx_pseudo_dma_read(struct vx_core *chip, struct snd_pcm_runtime *runtime,
 305                                       struct vx_pipe *pipe, int count)
 306 {
 307         chip->ops->dma_read(chip, runtime, pipe, count);
 308 }
 309
 310
 311
 312 /* error with hardware code,
 313  * the return value is -(VX_ERR_MASK | actual-hw-error-code)
 314  */
 315 #define VX_ERR_MASK     0x1000000
 316 #define vx_get_error(err)       (-(err) & ~VX_ERR_MASK)
 317
 318
 319 /*
 320  * pcm stuff
 321  */
 322 int snd_vx_pcm_new(struct vx_core *chip);
 323 void vx_pcm_update_intr(struct vx_core *chip, unsigned int events);
 324
 325 /*
 326  * mixer stuff
 327  */
 328 int snd_vx_mixer_new(struct vx_core *chip);
 329 void vx_toggle_dac_mute(struct vx_core *chip, int mute);
 330 int vx_sync_audio_source(struct vx_core *chip);
 331 int vx_set_monitor_level(struct vx_core *chip, int audio, int level, int active);
 332
 333 /*
 334  * IEC958 & clock stuff
 335  */
 336 void vx_set_iec958_status(struct vx_core *chip, unsigned int bits);
 337 int vx_set_clock(struct vx_core *chip, unsigned int freq);
 338 void vx_set_internal_clock(struct vx_core *chip, unsigned int freq);
 339 int vx_change_frequency(struct vx_core *chip);
 340
 341
 342 /*
 343  * PM
 344  */
 345 int snd_vx_suspend(struct vx_core *card, pm_message_t state);
 346 int snd_vx_resume(struct vx_core *card);
 347
 348 /*
 349  * hardware constants
 350  */
 351
 352 #define vx_has_new_dsp(chip)    ((chip)->type != VX_TYPE_BOARD)
 353 #define vx_is_pcmcia(chip)      ((chip)->type >= VX_TYPE_VXPOCKET)
 354
 355 /* audio input source */
 356 enum {
 357         VX_AUDIO_SRC_DIGITAL,
 358         VX_AUDIO_SRC_LINE,
 359         VX_AUDIO_SRC_MIC
 360 };
 361
 362 /* clock source */
 363 enum {
 364         INTERNAL_QUARTZ,
 365         UER_SYNC
 366 };
 367
 368 /* clock mode */
 369 enum {
 370         VX_CLOCK_MODE_AUTO,     /* depending on the current audio source */
 371         VX_CLOCK_MODE_INTERNAL, /* fixed to internal quartz */
 372         VX_CLOCK_MODE_EXTERNAL  /* fixed to UER sync */
 373 };
 374
 375 /* SPDIF/UER type */
 376 enum {
 377         VX_UER_MODE_CONSUMER,
 378         VX_UER_MODE_PROFESSIONAL,
 379         VX_UER_MODE_NOT_PRESENT,
 380 };
 381
 382 /* register indices */
 383 enum {
 384         VX_ICR,
 385         VX_CVR,
 386         VX_ISR,
 387         VX_IVR,
 388         VX_RXH,
 389         VX_TXH = VX_RXH,
 390         VX_RXM,
 391         VX_TXM = VX_RXM,
 392         VX_RXL,
 393         VX_TXL = VX_RXL,
 394         VX_DMA,
 395         VX_CDSP,
 396         VX_RFREQ,
 397         VX_RUER_V2,
 398         VX_GAIN,
 399         VX_DATA = VX_GAIN,
 400         VX_MEMIRQ,
 401         VX_ACQ,
 402         VX_BIT0,
 403         VX_BIT1,
 404         VX_MIC0,
 405         VX_MIC1,
 406         VX_MIC2,
 407         VX_MIC3,
 408         VX_PLX0,
 409         VX_PLX1,
 410         VX_PLX2,
 411
 412         VX_LOFREQ,  // V2: ACQ, VP: RFREQ
 413         VX_HIFREQ,  // V2: BIT0, VP: RUER_V2
 414         VX_CSUER,   // V2: BIT1, VP: BIT0
 415         VX_RUER,    // V2: RUER_V2, VP: BIT1
 416
 417         VX_REG_MAX,
 418
 419         /* aliases for VX board */
 420         VX_RESET_DMA = VX_ISR,
 421         VX_CFG = VX_RFREQ,
 422         VX_STATUS = VX_MEMIRQ,
 423         VX_SELMIC = VX_MIC0,
 424         VX_COMPOT = VX_MIC1,
 425         VX_SCOMPR = VX_MIC2,
 426         VX_GLIMIT = VX_MIC3,
 427         VX_INTCSR = VX_PLX0,
 428         VX_CNTRL = VX_PLX1,
 429         VX_GPIOC = VX_PLX2,
 430
 431         /* aliases for VXPOCKET board */
 432         VX_MICRO = VX_MEMIRQ,
 433         VX_CODEC2 = VX_MEMIRQ,
 434         VX_DIALOG = VX_ACQ,
 435
 436 };
 437
 438 /* RMH status type */
 439 enum {
 440         RMH_SSIZE_FIXED = 0,    /* status size given by the driver (in LgStat) */
 441         RMH_SSIZE_ARG = 1,      /* status size given in the LSB byte */
 442         RMH_SSIZE_MASK = 2,     /* status size given in bitmask */
 443 };
 444
 445
 446 /* bits for ICR register */
 447 #define ICR_HF1         0x10
 448 #define ICR_HF0         0x08
 449 #define ICR_TREQ        0x02    /* Interrupt mode + HREQ set on for transfer (->DSP) request */
 450 #define ICR_RREQ        0x01    /* Interrupt mode + RREQ set on for transfer (->PC) request */
 451
 452 /* bits for CVR register */
 453 #define CVR_HC          0x80
 454
 455 /* bits for ISR register */
 456 #define ISR_HF3         0x10
 457 #define ISR_HF2         0x08
 458 #define ISR_CHK         0x10
 459 #define ISR_ERR         0x08
 460 #define ISR_TX_READY    0x04
 461 #define ISR_TX_EMPTY    0x02
 462 #define ISR_RX_FULL     0x01
 463
 464 /* Constants used to access the DATA register */
 465 #define VX_DATA_CODEC_MASK      0x80
 466 #define VX_DATA_XICOR_MASK      0x80
 467
 468 /* Constants used to access the CSUER register (both for VX2 and VXP) */
 469 #define VX_SUER_FREQ_MASK               0x0c
 470 #define VX_SUER_FREQ_32KHz_MASK         0x0c
 471 #define VX_SUER_FREQ_44KHz_MASK         0x00
 472 #define VX_SUER_FREQ_48KHz_MASK         0x04
 473 #define VX_SUER_DATA_PRESENT_MASK       0x02
 474 #define VX_SUER_CLOCK_PRESENT_MASK      0x01
 475
 476 #define VX_CUER_HH_BITC_SEL_MASK        0x08
 477 #define VX_CUER_MH_BITC_SEL_MASK        0x04
 478 #define VX_CUER_ML_BITC_SEL_MASK        0x02
 479 #define VX_CUER_LL_BITC_SEL_MASK        0x01
 480
 481 #define XX_UER_CBITS_OFFSET_MASK        0x1f
 482
 483
 484 /* bits for audio_info */
 485 #define VX_AUDIO_INFO_REAL_TIME (1<<0)  /* real-time processing available */
 486 #define VX_AUDIO_INFO_OFFLINE   (1<<1)  /* offline processing available */
 487 #define VX_AUDIO_INFO_MPEG1     (1<<5)
 488 #define VX_AUDIO_INFO_MPEG2     (1<<6)
 489 #define VX_AUDIO_INFO_LINEAR_8  (1<<7)
 490 #define VX_AUDIO_INFO_LINEAR_16 (1<<8)
 491 #define VX_AUDIO_INFO_LINEAR_24 (1<<9)
 492
 493 /* DSP Interrupt Request values */
 494 #define VXP_IRQ_OFFSET          0x40 /* add 0x40 offset for vxpocket and vx222/v2 */
 495 /* call with vx_send_irq_dsp() */
 496 #define IRQ_MESS_WRITE_END          0x30
 497 #define IRQ_MESS_WRITE_NEXT         0x32
 498 #define IRQ_MESS_READ_NEXT          0x34
 499 #define IRQ_MESS_READ_END           0x36
 500 #define IRQ_MESSAGE                 0x38
 501 #define IRQ_RESET_CHK               0x3A
 502 #define IRQ_CONNECT_STREAM_NEXT     0x26
 503 #define IRQ_CONNECT_STREAM_END      0x28
 504 #define IRQ_PAUSE_START_CONNECT     0x2A
 505 #define IRQ_END_CONNECTION          0x2C
 506
 507 /* Is there async. events pending ( IT Source Test ) */
 508 #define ASYNC_EVENTS_PENDING            0x008000
 509 #define HBUFFER_EVENTS_PENDING          0x004000   // Not always accurate
 510 #define NOTIF_EVENTS_PENDING            0x002000
 511 #define TIME_CODE_EVENT_PENDING         0x001000
 512 #define FREQUENCY_CHANGE_EVENT_PENDING  0x000800
 513 #define END_OF_BUFFER_EVENTS_PENDING    0x000400
 514 #define FATAL_DSP_ERROR                 0xff0000
 515
 516 /* Stream Format Header Defines */
 517 #define HEADER_FMT_BASE                 0xFED00000
 518 #define HEADER_FMT_MONO                 0x000000C0
 519 #define HEADER_FMT_INTEL                0x00008000
 520 #define HEADER_FMT_16BITS               0x00002000
 521 #define HEADER_FMT_24BITS               0x00004000
 522 #define HEADER_FMT_UPTO11               0x00000200      /* frequency is less or equ. to 11k.*/
 523 #define HEADER_FMT_UPTO32               0x00000100      /* frequency is over 11k and less then 32k.*/
 524
 525 /* Constants used to access the Codec */
 526 #define XX_CODEC_SELECTOR               0x20
 527 /* codec commands */
 528 #define XX_CODEC_ADC_CONTROL_REGISTER   0x01
 529 #define XX_CODEC_DAC_CONTROL_REGISTER   0x02
 530 #define XX_CODEC_LEVEL_LEFT_REGISTER    0x03
 531 #define XX_CODEC_LEVEL_RIGHT_REGISTER   0x04
 532 #define XX_CODEC_PORT_MODE_REGISTER     0x05
 533 #define XX_CODEC_STATUS_REPORT_REGISTER 0x06
 534 #define XX_CODEC_CLOCK_CONTROL_REGISTER 0x07
 535
 536 /*
 537  * Audio-level control values
 538  */
 539 #define CVAL_M110DB             0x000   /* -110dB */
 540 #define CVAL_M99DB              0x02C
 541 #define CVAL_M21DB              0x163
 542 #define CVAL_M18DB              0x16F
 543 #define CVAL_M10DB              0x18F
 544 #define CVAL_0DB                0x1B7
 545 #define CVAL_18DB               0x1FF   /* +18dB */
 546 #define CVAL_MAX                0x1FF
 547
 548 #define AUDIO_IO_HAS_MUTE_LEVEL                 0x400000
 549 #define AUDIO_IO_HAS_MUTE_MONITORING_1          0x200000
 550 #define AUDIO_IO_HAS_MUTE_MONITORING_2          0x100000
 551 #define VALID_AUDIO_IO_DIGITAL_LEVEL            0x01
 552 #define VALID_AUDIO_IO_MONITORING_LEVEL         0x02
 553 #define VALID_AUDIO_IO_MUTE_LEVEL               0x04
 554 #define VALID_AUDIO_IO_MUTE_MONITORING_1        0x08
 555 #define VALID_AUDIO_IO_MUTE_MONITORING_2        0x10
 556
 557
 558 #endif /* __SOUND_VX_COMMON_H */