release/src-rt-6.x.4708/linux/linux-2.6.36/include/linux/spi/dw_spi.h

   1 #ifndef DW_SPI_HEADER_H
   2 #define DW_SPI_HEADER_H
   3 #include <linux/io.h>
   4
   5 /* Bit fields in CTRLR0 */
   6 #define SPI_DFS_OFFSET                  0
   7
   8 #define SPI_FRF_OFFSET                  4
   9 #define SPI_FRF_SPI                     0x0
  10 #define SPI_FRF_SSP                     0x1
  11 #define SPI_FRF_MICROWIRE               0x2
  12 #define SPI_FRF_RESV                    0x3
  13
  14 #define SPI_MODE_OFFSET                 6
  15 #define SPI_SCPH_OFFSET                 6
  16 #define SPI_SCOL_OFFSET                 7
  17
  18 #define SPI_TMOD_OFFSET                 8
  19 #define SPI_TMOD_MASK                   (0x3 << SPI_TMOD_OFFSET)
  20 #define SPI_TMOD_TR                     0x0             /* xmit & recv */
  21 #define SPI_TMOD_TO                     0x1             /* xmit only */
  22 #define SPI_TMOD_RO                     0x2             /* recv only */
  23 #define SPI_TMOD_EPROMREAD              0x3             /* eeprom read mode */
  24
  25 #define SPI_SLVOE_OFFSET                10
  26 #define SPI_SRL_OFFSET                  11
  27 #define SPI_CFS_OFFSET                  12
  28
  29 /* Bit fields in SR, 7 bits */
  30 #define SR_MASK                         0x7f            /* cover 7 bits */
  31 #define SR_BUSY                         (1 << 0)
  32 #define SR_TF_NOT_FULL                  (1 << 1)
  33 #define SR_TF_EMPT                      (1 << 2)
  34 #define SR_RF_NOT_EMPT                  (1 << 3)
  35 #define SR_RF_FULL                      (1 << 4)
  36 #define SR_TX_ERR                       (1 << 5)
  37 #define SR_DCOL                         (1 << 6)
  38
  39 /* Bit fields in ISR, IMR, RISR, 7 bits */
  40 #define SPI_INT_TXEI                    (1 << 0)
  41 #define SPI_INT_TXOI                    (1 << 1)
  42 #define SPI_INT_RXUI                    (1 << 2)
  43 #define SPI_INT_RXOI                    (1 << 3)
  44 #define SPI_INT_RXFI                    (1 << 4)
  45 #define SPI_INT_MSTI                    (1 << 5)
  46
  47 /* TX RX interrupt level threshhold, max can be 256 */
  48 #define SPI_INT_THRESHOLD               32
  49
  50 enum dw_ssi_type {
  51         SSI_MOTO_SPI = 0,
  52         SSI_TI_SSP,
  53         SSI_NS_MICROWIRE,
  54 };
  55
  56 struct dw_spi_reg {
  57         u32     ctrl0;
  58         u32     ctrl1;
  59         u32     ssienr;
  60         u32     mwcr;
  61         u32     ser;
  62         u32     baudr;
  63         u32     txfltr;
  64         u32     rxfltr;
  65         u32     txflr;
  66         u32     rxflr;
  67         u32     sr;
  68         u32     imr;
  69         u32     isr;
  70         u32     risr;
  71         u32     txoicr;
  72         u32     rxoicr;
  73         u32     rxuicr;
  74         u32     msticr;
  75         u32     icr;
  76         u32     dmacr;
  77         u32     dmatdlr;
  78         u32     dmardlr;
  79         u32     idr;
  80         u32     version;
  81         u32     dr;             /* Currently oper as 32 bits,
  82                                 though only low 16 bits matters */
  83 } __packed;
  84
  85 struct dw_spi {
  86         struct spi_master       *master;
  87         struct spi_device       *cur_dev;
  88         struct device           *parent_dev;
  89         enum dw_ssi_type        type;
  90
  91         void __iomem            *regs;
  92         unsigned long           paddr;
  93         u32                     iolen;
  94         int                     irq;
  95         u32                     fifo_len;       /* depth of the FIFO buffer */
  96         u32                     max_freq;       /* max bus freq supported */
  97
  98         u16                     bus_num;
  99         u16                     num_cs;         /* supported slave numbers */
 100
 101         /* Driver message queue */
 102         struct workqueue_struct *workqueue;
 103         struct work_struct      pump_messages;
 104         spinlock_t              lock;
 105         struct list_head        queue;
 106         int                     busy;
 107         int                     run;
 108
 109         /* Message Transfer pump */
 110         struct tasklet_struct   pump_transfers;
 111
 112         /* Current message transfer state info */
 113         struct spi_message      *cur_msg;
 114         struct spi_transfer     *cur_transfer;
 115         struct chip_data        *cur_chip;
 116         struct chip_data        *prev_chip;
 117         size_t                  len;
 118         void                    *tx;
 119         void                    *tx_end;
 120         void                    *rx;
 121         void                    *rx_end;
 122         int                     dma_mapped;
 123         dma_addr_t              rx_dma;
 124         dma_addr_t              tx_dma;
 125         size_t                  rx_map_len;
 126         size_t                  tx_map_len;
 127         u8                      n_bytes;        /* current is a 1/2 bytes op */
 128         u8                      max_bits_per_word;      /* maxim is 16b */
 129         u32                     dma_width;
 130         int                     cs_change;
 131         int                     (*write)(struct dw_spi *dws);
 132         int                     (*read)(struct dw_spi *dws);
 133         irqreturn_t             (*transfer_handler)(struct dw_spi *dws);
 134         void                    (*cs_control)(u32 command);
 135
 136         /* Dma info */
 137         int                     dma_inited;
 138         struct dma_chan         *txchan;
 139         struct dma_chan         *rxchan;
 140         int                     txdma_done;
 141         int                     rxdma_done;
 142         u64                     tx_param;
 143         u64                     rx_param;
 144         struct device           *dma_dev;
 145         dma_addr_t              dma_addr;
 146
 147         /* Bus interface info */
 148         void                    *priv;
 149 #ifdef CONFIG_DEBUG_FS
 150         struct dentry *debugfs;
 151 #endif
 152 };
 153
 154 #define dw_readl(dw, name) \
 155         __raw_readl(&(((struct dw_spi_reg *)dw->regs)->name))
 156 #define dw_writel(dw, name, val) \
 157         __raw_writel((val), &(((struct dw_spi_reg *)dw->regs)->name))
 158 #define dw_readw(dw, name) \
 159         __raw_readw(&(((struct dw_spi_reg *)dw->regs)->name))
 160 #define dw_writew(dw, name, val) \
 161         __raw_writew((val), &(((struct dw_spi_reg *)dw->regs)->name))
 162
 163 static inline void spi_enable_chip(struct dw_spi *dws, int enable)
 164 {
 165         dw_writel(dws, ssienr, (enable ? 1 : 0));
 166 }
 167
 168 static inline void spi_set_clk(struct dw_spi *dws, u16 div)
 169 {
 170         dw_writel(dws, baudr, div);
 171 }
 172
 173 static inline void spi_chip_sel(struct dw_spi *dws, u16 cs)
 174 {
 175         if (cs > dws->num_cs)
 176                 return;
 177
 178         if (dws->cs_control)
 179                 dws->cs_control(1);
 180
 181         dw_writel(dws, ser, 1 << cs);
 182 }
 183
 184 /* Disable IRQ bits */
 185 static inline void spi_mask_intr(struct dw_spi *dws, u32 mask)
 186 {
 187         u32 new_mask;
 188
 189         new_mask = dw_readl(dws, imr) & ~mask;
 190         dw_writel(dws, imr, new_mask);
 191 }
 192
 193 /* Enable IRQ bits */
 194 static inline void spi_umask_intr(struct dw_spi *dws, u32 mask)
 195 {
 196         u32 new_mask;
 197
 198         new_mask = dw_readl(dws, imr) | mask;
 199         dw_writel(dws, imr, new_mask);
 200 }
 201
 202 /*
 203  * Each SPI slave device to work with dw_api controller should
 204  * has such a structure claiming its working mode (PIO/DMA etc),
 205  * which can be save in the "controller_data" member of the
 206  * struct spi_device
 207  */
 208 struct dw_spi_chip {
 209         u8 poll_mode;   /* 0 for contoller polling mode */
 210         u8 type;        /* SPI/SSP/Micrwire */
 211         u8 enable_dma;
 212         void (*cs_control)(u32 command);
 213 };
 214
 215 extern int dw_spi_add_host(struct dw_spi *dws);
 216 extern void dw_spi_remove_host(struct dw_spi *dws);
 217 extern int dw_spi_suspend_host(struct dw_spi *dws);
 218 extern int dw_spi_resume_host(struct dw_spi *dws);
 219 #endif /* DW_SPI_HEADER_H */