release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/video/via/chip.h

   1 /*
   2  * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
   3  * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
   4
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public
   7  * License as published by the Free Software Foundation;
   8  * either version 2, or (at your option) any later version.
   9
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
  12  * the implied warranty of MERCHANTABILITY or FITNESS FOR
  13  * A PARTICULAR PURPOSE.See the GNU General Public License
  14  * for more details.
  15
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc.,
  19  * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  20  */
  21 #ifndef __CHIP_H__
  22 #define __CHIP_H__
  23
  24 #include "global.h"
  25
  26 /***************************************/
  27 /* Definition Graphic Chip Information */
  28 /***************************************/
  29
  30 #define     PCI_VIA_VENDOR_ID       0x1106
  31
  32 /* Define VIA Graphic Chip Name */
  33 #define     UNICHROME_CLE266        1
  34 #define     UNICHROME_CLE266_DID    0x3122
  35 #define     CLE266_REVISION_AX      0x0A
  36 #define     CLE266_REVISION_CX      0x0C
  37
  38 #define     UNICHROME_K400          2
  39 #define     UNICHROME_K400_DID      0x7205
  40
  41 #define     UNICHROME_K800          3
  42 #define     UNICHROME_K800_DID      0x3108
  43
  44 #define     UNICHROME_PM800         4
  45 #define     UNICHROME_PM800_DID     0x3118
  46
  47 #define     UNICHROME_CN700         5
  48 #define     UNICHROME_CN700_DID     0x3344
  49
  50 #define     UNICHROME_CX700         6
  51 #define     UNICHROME_CX700_DID     0x3157
  52 #define     CX700_REVISION_700      0x0
  53 #define     CX700_REVISION_700M     0x1
  54 #define     CX700_REVISION_700M2    0x2
  55
  56 #define     UNICHROME_CN750         7
  57 #define     UNICHROME_CN750_DID     0x3225
  58
  59 #define     UNICHROME_K8M890        8
  60 #define     UNICHROME_K8M890_DID    0x3230
  61
  62 #define     UNICHROME_P4M890        9
  63 #define     UNICHROME_P4M890_DID    0x3343
  64
  65 #define     UNICHROME_P4M900        10
  66 #define     UNICHROME_P4M900_DID    0x3371
  67
  68 #define     UNICHROME_VX800         11
  69 #define     UNICHROME_VX800_DID     0x1122
  70
  71 #define     UNICHROME_VX855         12
  72 #define     UNICHROME_VX855_DID     0x5122
  73
  74 /**************************************************/
  75 /* Definition TMDS Trasmitter Information         */
  76 /**************************************************/
  77
  78 /* Definition TMDS Trasmitter Index */
  79 #define     NON_TMDS_TRANSMITTER    0x00
  80 #define     VT1632_TMDS             0x01
  81 #define     INTEGRATED_TMDS         0x42
  82
  83 /* Definition TMDS Trasmitter I2C Slave Address */
  84 #define     VT1632_TMDS_I2C_ADDR    0x10
  85
  86 /**************************************************/
  87 /* Definition LVDS Trasmitter Information         */
  88 /**************************************************/
  89
  90 /* Definition LVDS Trasmitter Index */
  91 #define     NON_LVDS_TRANSMITTER    0x00
  92 #define     VT1631_LVDS             0x01
  93 #define     VT1636_LVDS             0x0E
  94 #define     INTEGRATED_LVDS         0x41
  95
  96 /* Definition Digital Transmitter Mode */
  97 #define     TX_DATA_12_BITS         0x01
  98 #define     TX_DATA_24_BITS         0x02
  99 #define     TX_DATA_DDR_MODE        0x04
 100 #define     TX_DATA_SDR_MODE        0x08
 101
 102 /* Definition LVDS Trasmitter I2C Slave Address */
 103 #define     VT1631_LVDS_I2C_ADDR    0x70
 104 #define     VT3271_LVDS_I2C_ADDR    0x80
 105 #define     VT1636_LVDS_I2C_ADDR    0x80
 106
 107 struct tmds_chip_information {
 108         int tmds_chip_name;
 109         int tmds_chip_slave_addr;
 110         int data_mode;
 111         int output_interface;
 112         int i2c_port;
 113         int device_type;
 114 };
 115
 116 struct lvds_chip_information {
 117         int lvds_chip_name;
 118         int lvds_chip_slave_addr;
 119         int data_mode;
 120         int output_interface;
 121         int i2c_port;
 122 };
 123
 124 /* The type of 2D engine */
 125 enum via_2d_engine {
 126         VIA_2D_ENG_H2,
 127         VIA_2D_ENG_H5,
 128         VIA_2D_ENG_M1,
 129 };
 130
 131 struct chip_information {
 132         int gfx_chip_name;
 133         int gfx_chip_revision;
 134         enum via_2d_engine twod_engine;
 135         struct tmds_chip_information tmds_chip_info;
 136         struct lvds_chip_information lvds_chip_info;
 137         struct lvds_chip_information lvds_chip_info2;
 138 };
 139
 140 struct crt_setting_information {
 141         int iga_path;
 142         int h_active;
 143         int v_active;
 144         int bpp;
 145         int refresh_rate;
 146 };
 147
 148 struct tmds_setting_information {
 149         int iga_path;
 150         int h_active;
 151         int v_active;
 152         int max_pixel_clock;
 153         int max_hres;
 154         int max_vres;
 155 };
 156
 157 struct lvds_setting_information {
 158         int iga_path;
 159         int h_active;
 160         int v_active;
 161         int bpp;
 162         int refresh_rate;
 163         int lcd_panel_id;
 164         int lcd_panel_hres;
 165         int lcd_panel_vres;
 166         int display_method;
 167         int device_lcd_dualedge;
 168         int LCDDithering;
 169         int lcd_mode;
 170         u32 vclk;               /*panel mode clock value */
 171 };
 172
 173 struct GFX_DPA_SETTING {
 174         int ClkRangeIndex;
 175         u8 DVP0;                /* CR96[3:0] */
 176         u8 DVP0DataDri_S1;      /* SR2A[5]   */
 177         u8 DVP0DataDri_S;       /* SR1B[1]   */
 178         u8 DVP0ClockDri_S1;     /* SR2A[4]   */
 179         u8 DVP0ClockDri_S;      /* SR1E[2]   */
 180         u8 DVP1;                /* CR9B[3:0] */
 181         u8 DVP1Driving;         /* SR65[3:0], Data and Clock driving */
 182         u8 DFPHigh;             /* CR97[3:0] */
 183         u8 DFPLow;              /* CR99[3:0] */
 184
 185 };
 186
 187 struct VT1636_DPA_SETTING {
 188         int PanelSizeID;
 189         u8 CLK_SEL_ST1;
 190         u8 CLK_SEL_ST2;
 191 };
 192 #endif /* __CHIP_H__ */