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GUI: Fix Tomato RAF theme for all builds. Compilation typo.
[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / drivers / video / via / accel.c
blobc2f4e6e166f11508b61a46236a68fa61f66ada4f
1 /*
2 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
3 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
4
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public
7 * License as published by the Free Software Foundation;
8 * either version 2, or (at your option) any later version.
9
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
12 * the implied warranty of MERCHANTABILITY or FITNESS FOR
13 * A PARTICULAR PURPOSE.See the GNU General Public License
14 * for more details.
15
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21 #include <linux/via-core.h>
22 #include "global.h"
23
24 /*
25 * Figure out an appropriate bytes-per-pixel setting.
26 */
27 static int viafb_set_bpp(void __iomem *engine, u8 bpp)
28 {
29 u32 gemode;
30
31 /* Preserve the reserved bits */
32 /* Lowest 2 bits to zero gives us no rotation */
33 gemode = readl(engine + VIA_REG_GEMODE) & 0xfffffcfc;
34 switch (bpp) {
35 case 8:
36 gemode |= VIA_GEM_8bpp;
37 break;
38 case 16:
39 gemode |= VIA_GEM_16bpp;
40 break;
41 case 32:
42 gemode |= VIA_GEM_32bpp;
43 break;
44 default:
45 printk(KERN_WARNING "viafb_set_bpp: Unsupported bpp %d\n", bpp);
46 return -EINVAL;
47 }
48 writel(gemode, engine + VIA_REG_GEMODE);
49 return 0;
50 }
51
52
53 static int hw_bitblt_1(void __iomem *engine, u8 op, u32 width, u32 height,
54 u8 dst_bpp, u32 dst_addr, u32 dst_pitch, u32 dst_x, u32 dst_y,
55 u32 *src_mem, u32 src_addr, u32 src_pitch, u32 src_x, u32 src_y,
56 u32 fg_color, u32 bg_color, u8 fill_rop)
57 {
58 u32 ge_cmd = 0, tmp, i;
59 int ret;
60
61 if (!op || op > 3) {
62 printk(KERN_WARNING "hw_bitblt_1: Invalid operation: %d\n", op);
63 return -EINVAL;
64 }
65
66 if (op != VIA_BITBLT_FILL && !src_mem && src_addr == dst_addr) {
67 if (src_x < dst_x) {
68 ge_cmd |= 0x00008000;
69 src_x += width - 1;
70 dst_x += width - 1;
71 }
72 if (src_y < dst_y) {
73 ge_cmd |= 0x00004000;
74 src_y += height - 1;
75 dst_y += height - 1;
76 }
77 }
78
79 if (op == VIA_BITBLT_FILL) {
80 switch (fill_rop) {
81 case 0x00: /* blackness */
82 case 0x5A: /* pattern inversion */
83 case 0xF0: /* pattern copy */
84 case 0xFF: /* whiteness */
85 break;
86 default:
87 printk(KERN_WARNING "hw_bitblt_1: Invalid fill rop: "
88 "%u\n", fill_rop);
89 return -EINVAL;
90 }
91 }
92
93 ret = viafb_set_bpp(engine, dst_bpp);
94 if (ret)
95 return ret;
96
97 if (op != VIA_BITBLT_FILL) {
98 if (src_x & (op == VIA_BITBLT_MONO ? 0xFFFF8000 : 0xFFFFF000)
99 || src_y & 0xFFFFF000) {
100 printk(KERN_WARNING "hw_bitblt_1: Unsupported source "
101 "x/y %d %d\n", src_x, src_y);
102 return -EINVAL;
103 }
104 tmp = src_x | (src_y << 16);
105 writel(tmp, engine + 0x08);
106 }
107
108 if (dst_x & 0xFFFFF000 || dst_y & 0xFFFFF000) {
109 printk(KERN_WARNING "hw_bitblt_1: Unsupported destination x/y "
110 "%d %d\n", dst_x, dst_y);
111 return -EINVAL;
112 }
113 tmp = dst_x | (dst_y << 16);
114 writel(tmp, engine + 0x0C);
115
116 if ((width - 1) & 0xFFFFF000 || (height - 1) & 0xFFFFF000) {
117 printk(KERN_WARNING "hw_bitblt_1: Unsupported width/height "
118 "%d %d\n", width, height);
119 return -EINVAL;
120 }
121 tmp = (width - 1) | ((height - 1) << 16);
122 writel(tmp, engine + 0x10);
123
124 if (op != VIA_BITBLT_COLOR)
125 writel(fg_color, engine + 0x18);
126
127 if (op == VIA_BITBLT_MONO)
128 writel(bg_color, engine + 0x1C);
129
130 if (op != VIA_BITBLT_FILL) {
131 tmp = src_mem ? 0 : src_addr;
132 if (dst_addr & 0xE0000007) {
133 printk(KERN_WARNING "hw_bitblt_1: Unsupported source "
134 "address %X\n", tmp);
135 return -EINVAL;
136 }
137 tmp >>= 3;
138 writel(tmp, engine + 0x30);
139 }
140
141 if (dst_addr & 0xE0000007) {
142 printk(KERN_WARNING "hw_bitblt_1: Unsupported destination "
143 "address %X\n", dst_addr);
144 return -EINVAL;
145 }
146 tmp = dst_addr >> 3;
147 writel(tmp, engine + 0x34);
148
149 if (op == VIA_BITBLT_FILL)
150 tmp = 0;
151 else
152 tmp = src_pitch;
153 if (tmp & 0xFFFFC007 || dst_pitch & 0xFFFFC007) {
154 printk(KERN_WARNING "hw_bitblt_1: Unsupported pitch %X %X\n",
155 tmp, dst_pitch);
156 return -EINVAL;
157 }
158 tmp = VIA_PITCH_ENABLE | (tmp >> 3) | (dst_pitch << (16 - 3));
159 writel(tmp, engine + 0x38);
160
161 if (op == VIA_BITBLT_FILL)
162 ge_cmd |= fill_rop << 24 | 0x00002000 | 0x00000001;
163 else {
164 ge_cmd |= 0xCC000000; /* ROP=SRCCOPY */
165 if (src_mem)
166 ge_cmd |= 0x00000040;
167 if (op == VIA_BITBLT_MONO)
168 ge_cmd |= 0x00000002 | 0x00000100 | 0x00020000;
169 else
170 ge_cmd |= 0x00000001;
171 }
172 writel(ge_cmd, engine);
173
174 if (op == VIA_BITBLT_FILL || !src_mem)
175 return 0;
176
177 tmp = (width * height * (op == VIA_BITBLT_MONO ? 1 : (dst_bpp >> 3)) +
178 3) >> 2;
179
180 for (i = 0; i < tmp; i++)
181 writel(src_mem[i], engine + VIA_MMIO_BLTBASE);
182
183 return 0;
184 }
185
186 static int hw_bitblt_2(void __iomem *engine, u8 op, u32 width, u32 height,
187 u8 dst_bpp, u32 dst_addr, u32 dst_pitch, u32 dst_x, u32 dst_y,
188 u32 *src_mem, u32 src_addr, u32 src_pitch, u32 src_x, u32 src_y,
189 u32 fg_color, u32 bg_color, u8 fill_rop)
190 {
191 u32 ge_cmd = 0, tmp, i;
192 int ret;
193
194 if (!op || op > 3) {
195 printk(KERN_WARNING "hw_bitblt_2: Invalid operation: %d\n", op);
196 return -EINVAL;
197 }
198
199 if (op != VIA_BITBLT_FILL && !src_mem && src_addr == dst_addr) {
200 if (src_x < dst_x) {
201 ge_cmd |= 0x00008000;
202 src_x += width - 1;
203 dst_x += width - 1;
204 }
205 if (src_y < dst_y) {
206 ge_cmd |= 0x00004000;
207 src_y += height - 1;
208 dst_y += height - 1;
209 }
210 }
211
212 if (op == VIA_BITBLT_FILL) {
213 switch (fill_rop) {
214 case 0x00: /* blackness */
215 case 0x5A: /* pattern inversion */
216 case 0xF0: /* pattern copy */
217 case 0xFF: /* whiteness */
218 break;
219 default:
220 printk(KERN_WARNING "hw_bitblt_2: Invalid fill rop: "
221 "%u\n", fill_rop);
222 return -EINVAL;
223 }
224 }
225
226 ret = viafb_set_bpp(engine, dst_bpp);
227 if (ret)
228 return ret;
229
230 if (op == VIA_BITBLT_FILL)
231 tmp = 0;
232 else
233 tmp = src_pitch;
234 if (tmp & 0xFFFFC007 || dst_pitch & 0xFFFFC007) {
235 printk(KERN_WARNING "hw_bitblt_2: Unsupported pitch %X %X\n",
236 tmp, dst_pitch);
237 return -EINVAL;
238 }
239 tmp = (tmp >> 3) | (dst_pitch << (16 - 3));
240 writel(tmp, engine + 0x08);
241
242 if ((width - 1) & 0xFFFFF000 || (height - 1) & 0xFFFFF000) {
243 printk(KERN_WARNING "hw_bitblt_2: Unsupported width/height "
244 "%d %d\n", width, height);
245 return -EINVAL;
246 }
247 tmp = (width - 1) | ((height - 1) << 16);
248 writel(tmp, engine + 0x0C);
249
250 if (dst_x & 0xFFFFF000 || dst_y & 0xFFFFF000) {
251 printk(KERN_WARNING "hw_bitblt_2: Unsupported destination x/y "
252 "%d %d\n", dst_x, dst_y);
253 return -EINVAL;
254 }
255 tmp = dst_x | (dst_y << 16);
256 writel(tmp, engine + 0x10);
257
258 if (dst_addr & 0xE0000007) {
259 printk(KERN_WARNING "hw_bitblt_2: Unsupported destination "
260 "address %X\n", dst_addr);
261 return -EINVAL;
262 }
263 tmp = dst_addr >> 3;
264 writel(tmp, engine + 0x14);
265
266 if (op != VIA_BITBLT_FILL) {
267 if (src_x & (op == VIA_BITBLT_MONO ? 0xFFFF8000 : 0xFFFFF000)
268 || src_y & 0xFFFFF000) {
269 printk(KERN_WARNING "hw_bitblt_2: Unsupported source "
270 "x/y %d %d\n", src_x, src_y);
271 return -EINVAL;
272 }
273 tmp = src_x | (src_y << 16);
274 writel(tmp, engine + 0x18);
275
276 tmp = src_mem ? 0 : src_addr;
277 if (dst_addr & 0xE0000007) {
278 printk(KERN_WARNING "hw_bitblt_2: Unsupported source "
279 "address %X\n", tmp);
280 return -EINVAL;
281 }
282 tmp >>= 3;
283 writel(tmp, engine + 0x1C);
284 }
285
286 if (op == VIA_BITBLT_FILL) {
287 writel(fg_color, engine + 0x58);
288 } else if (op == VIA_BITBLT_MONO) {
289 writel(fg_color, engine + 0x4C);
290 writel(bg_color, engine + 0x50);
291 }
292
293 if (op == VIA_BITBLT_FILL)
294 ge_cmd |= fill_rop << 24 | 0x00002000 | 0x00000001;
295 else {
296 ge_cmd |= 0xCC000000; /* ROP=SRCCOPY */
297 if (src_mem)
298 ge_cmd |= 0x00000040;
299 if (op == VIA_BITBLT_MONO)
300 ge_cmd |= 0x00000002 | 0x00000100 | 0x00020000;
301 else
302 ge_cmd |= 0x00000001;
303 }
304 writel(ge_cmd, engine);
305
306 if (op == VIA_BITBLT_FILL || !src_mem)
307 return 0;
308
309 tmp = (width * height * (op == VIA_BITBLT_MONO ? 1 : (dst_bpp >> 3)) +
310 3) >> 2;
311
312 for (i = 0; i < tmp; i++)
313 writel(src_mem[i], engine + VIA_MMIO_BLTBASE);
314
315 return 0;
316 }
317
318 int viafb_init_engine(struct fb_info *info)
319 {
320 struct viafb_par *viapar = info->par;
321 void __iomem *engine;
322 int highest_reg, i;
323 u32 vq_start_addr, vq_end_addr, vq_start_low, vq_end_low, vq_high,
324 vq_len, chip_name = viapar->shared->chip_info.gfx_chip_name;
325
326 engine = viapar->shared->vdev->engine_mmio;
327 if (!engine) {
328 printk(KERN_WARNING "viafb_init_accel: ioremap failed, "
329 "hardware acceleration disabled\n");
330 return -ENOMEM;
331 }
332
333 /* Initialize registers to reset the 2D engine */
334 switch (viapar->shared->chip_info.twod_engine) {
335 case VIA_2D_ENG_M1:
336 highest_reg = 0x5c;
337 break;
338 default:
339 highest_reg = 0x40;
340 break;
341 }
342 for (i = 0; i <= highest_reg; i += 4)
343 writel(0x0, engine + i);
344
345 switch (chip_name) {
346 case UNICHROME_CLE266:
347 case UNICHROME_K400:
348 case UNICHROME_K800:
349 case UNICHROME_PM800:
350 case UNICHROME_CN700:
351 case UNICHROME_CX700:
352 case UNICHROME_CN750:
353 case UNICHROME_K8M890:
354 case UNICHROME_P4M890:
355 case UNICHROME_P4M900:
356 viapar->shared->hw_bitblt = hw_bitblt_1;
357 break;
358 case UNICHROME_VX800:
359 case UNICHROME_VX855:
360 viapar->shared->hw_bitblt = hw_bitblt_2;
361 break;
362 default:
363 viapar->shared->hw_bitblt = NULL;
364 }
365
366 viapar->fbmem_free -= CURSOR_SIZE;
367 viapar->shared->cursor_vram_addr = viapar->fbmem_free;
368 viapar->fbmem_used += CURSOR_SIZE;
369
370 viapar->fbmem_free -= VQ_SIZE;
371 viapar->shared->vq_vram_addr = viapar->fbmem_free;
372 viapar->fbmem_used += VQ_SIZE;
373
374 #if defined(CONFIG_FB_VIA_CAMERA) || defined(CONFIG_FB_VIA_CAMERA_MODULE)
375 /*
376 * Set aside a chunk of framebuffer memory for the camera
377 * driver. Someday this driver probably needs a proper allocator
378 * for fbmem; for now, we just have to do this before the
379 * framebuffer initializes itself.
380 *
381 * As for the size: the engine can handle three frames,
382 * 16 bits deep, up to VGA resolution.
383 */
384 viapar->shared->vdev->camera_fbmem_size = 3*VGA_HEIGHT*VGA_WIDTH*2;
385 viapar->fbmem_free -= viapar->shared->vdev->camera_fbmem_size;
386 viapar->fbmem_used += viapar->shared->vdev->camera_fbmem_size;
387 viapar->shared->vdev->camera_fbmem_offset = viapar->fbmem_free;
388 #endif
389
390 /* Init AGP and VQ regs */
391 switch (chip_name) {
392 case UNICHROME_K8M890:
393 case UNICHROME_P4M900:
394 case UNICHROME_VX800:
395 case UNICHROME_VX855:
396 writel(0x00100000, engine + VIA_REG_CR_TRANSET);
397 writel(0x680A0000, engine + VIA_REG_CR_TRANSPACE);
398 writel(0x02000000, engine + VIA_REG_CR_TRANSPACE);
399 break;
400
401 default:
402 writel(0x00100000, engine + VIA_REG_TRANSET);
403 writel(0x00000000, engine + VIA_REG_TRANSPACE);
404 writel(0x00333004, engine + VIA_REG_TRANSPACE);
405 writel(0x60000000, engine + VIA_REG_TRANSPACE);
406 writel(0x61000000, engine + VIA_REG_TRANSPACE);
407 writel(0x62000000, engine + VIA_REG_TRANSPACE);
408 writel(0x63000000, engine + VIA_REG_TRANSPACE);
409 writel(0x64000000, engine + VIA_REG_TRANSPACE);
410 writel(0x7D000000, engine + VIA_REG_TRANSPACE);
411
412 writel(0xFE020000, engine + VIA_REG_TRANSET);
413 writel(0x00000000, engine + VIA_REG_TRANSPACE);
414 break;
415 }
416
417 /* Enable VQ */
418 vq_start_addr = viapar->shared->vq_vram_addr;
419 vq_end_addr = viapar->shared->vq_vram_addr + VQ_SIZE - 1;
420
421 vq_start_low = 0x50000000 | (vq_start_addr & 0xFFFFFF);
422 vq_end_low = 0x51000000 | (vq_end_addr & 0xFFFFFF);
423 vq_high = 0x52000000 | ((vq_start_addr & 0xFF000000) >> 24) |
424 ((vq_end_addr & 0xFF000000) >> 16);
425 vq_len = 0x53000000 | (VQ_SIZE >> 3);
426
427 switch (chip_name) {
428 case UNICHROME_K8M890:
429 case UNICHROME_P4M900:
430 case UNICHROME_VX800:
431 case UNICHROME_VX855:
432 vq_start_low |= 0x20000000;
433 vq_end_low |= 0x20000000;
434 vq_high |= 0x20000000;
435 vq_len |= 0x20000000;
436
437 writel(0x00100000, engine + VIA_REG_CR_TRANSET);
438 writel(vq_high, engine + VIA_REG_CR_TRANSPACE);
439 writel(vq_start_low, engine + VIA_REG_CR_TRANSPACE);
440 writel(vq_end_low, engine + VIA_REG_CR_TRANSPACE);
441 writel(vq_len, engine + VIA_REG_CR_TRANSPACE);
442 writel(0x74301001, engine + VIA_REG_CR_TRANSPACE);
443 writel(0x00000000, engine + VIA_REG_CR_TRANSPACE);
444 break;
445 default:
446 writel(0x00FE0000, engine + VIA_REG_TRANSET);
447 writel(0x080003FE, engine + VIA_REG_TRANSPACE);
448 writel(0x0A00027C, engine + VIA_REG_TRANSPACE);
449 writel(0x0B000260, engine + VIA_REG_TRANSPACE);
450 writel(0x0C000274, engine + VIA_REG_TRANSPACE);
451 writel(0x0D000264, engine + VIA_REG_TRANSPACE);
452 writel(0x0E000000, engine + VIA_REG_TRANSPACE);
453 writel(0x0F000020, engine + VIA_REG_TRANSPACE);
454 writel(0x1000027E, engine + VIA_REG_TRANSPACE);
455 writel(0x110002FE, engine + VIA_REG_TRANSPACE);
456 writel(0x200F0060, engine + VIA_REG_TRANSPACE);
457
458 writel(0x00000006, engine + VIA_REG_TRANSPACE);
459 writel(0x40008C0F, engine + VIA_REG_TRANSPACE);
460 writel(0x44000000, engine + VIA_REG_TRANSPACE);
461 writel(0x45080C04, engine + VIA_REG_TRANSPACE);
462 writel(0x46800408, engine + VIA_REG_TRANSPACE);
463
464 writel(vq_high, engine + VIA_REG_TRANSPACE);
465 writel(vq_start_low, engine + VIA_REG_TRANSPACE);
466 writel(vq_end_low, engine + VIA_REG_TRANSPACE);
467 writel(vq_len, engine + VIA_REG_TRANSPACE);
468 break;
469 }
470
471 /* Set Cursor Image Base Address */
472 writel(viapar->shared->cursor_vram_addr, engine + VIA_REG_CURSOR_MODE);
473 writel(0x0, engine + VIA_REG_CURSOR_POS);
474 writel(0x0, engine + VIA_REG_CURSOR_ORG);
475 writel(0x0, engine + VIA_REG_CURSOR_BG);
476 writel(0x0, engine + VIA_REG_CURSOR_FG);
477 return 0;
478 }
479
480 void viafb_show_hw_cursor(struct fb_info *info, int Status)
481 {
482 struct viafb_par *viapar = info->par;
483 u32 temp, iga_path = viapar->iga_path;
484
485 temp = readl(viapar->shared->vdev->engine_mmio + VIA_REG_CURSOR_MODE);
486 switch (Status) {
487 case HW_Cursor_ON:
488 temp |= 0x1;
489 break;
490 case HW_Cursor_OFF:
491 temp &= 0xFFFFFFFE;
492 break;
493 }
494 switch (iga_path) {
495 case IGA2:
496 temp |= 0x80000000;
497 break;
498 case IGA1:
499 default:
500 temp &= 0x7FFFFFFF;
501 }
502 writel(temp, viapar->shared->vdev->engine_mmio + VIA_REG_CURSOR_MODE);
503 }
504
505 void viafb_wait_engine_idle(struct fb_info *info)
506 {
507 struct viafb_par *viapar = info->par;
508 int loop = 0;
509 u32 mask;
510 void __iomem *engine = viapar->shared->vdev->engine_mmio;
511
512 switch (viapar->shared->chip_info.twod_engine) {
513 case VIA_2D_ENG_H5:
514 case VIA_2D_ENG_M1:
515 mask = VIA_CMD_RGTR_BUSY_M1 | VIA_2D_ENG_BUSY_M1 |
516 VIA_3D_ENG_BUSY_M1;
517 break;
518 default:
519 while (!(readl(engine + VIA_REG_STATUS) &
520 VIA_VR_QUEUE_BUSY) && (loop < MAXLOOP)) {
521 loop++;
522 cpu_relax();
523 }
524 mask = VIA_CMD_RGTR_BUSY | VIA_2D_ENG_BUSY | VIA_3D_ENG_BUSY;
525 break;
526 }
527
528 while ((readl(engine + VIA_REG_STATUS) & mask) && (loop < MAXLOOP)) {
529 loop++;
530 cpu_relax();
531 }
532
533 if (loop >= MAXLOOP)
534 printk(KERN_ERR "viafb_wait_engine_idle: not syncing\n");
535 }
Tomato firmware and modifications.