2 * linux/drivers/video/omap2/dss/dsi.c
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
20 #define DSS_SUBSYS_NAME "DSI"
22 #include <linux/kernel.h>
24 #include <linux/clk.h>
25 #include <linux/device.h>
26 #include <linux/err.h>
27 #include <linux/interrupt.h>
28 #include <linux/delay.h>
29 #include <linux/mutex.h>
30 #include <linux/semaphore.h>
31 #include <linux/seq_file.h>
32 #include <linux/platform_device.h>
33 #include <linux/regulator/consumer.h>
34 #include <linux/wait.h>
35 #include <linux/workqueue.h>
37 #include <plat/display.h>
38 #include <plat/clock.h>
42 /*#define VERBOSE_IRQ*/
43 #define DSI_CATCH_MISSING_TE
45 #define DSI_BASE 0x4804FC00
47 struct dsi_reg
{ u16 idx
; };
49 #define DSI_REG(idx) ((const struct dsi_reg) { idx })
51 #define DSI_SZ_REGS SZ_1K
52 /* DSI Protocol Engine */
54 #define DSI_REVISION DSI_REG(0x0000)
55 #define DSI_SYSCONFIG DSI_REG(0x0010)
56 #define DSI_SYSSTATUS DSI_REG(0x0014)
57 #define DSI_IRQSTATUS DSI_REG(0x0018)
58 #define DSI_IRQENABLE DSI_REG(0x001C)
59 #define DSI_CTRL DSI_REG(0x0040)
60 #define DSI_COMPLEXIO_CFG1 DSI_REG(0x0048)
61 #define DSI_COMPLEXIO_IRQ_STATUS DSI_REG(0x004C)
62 #define DSI_COMPLEXIO_IRQ_ENABLE DSI_REG(0x0050)
63 #define DSI_CLK_CTRL DSI_REG(0x0054)
64 #define DSI_TIMING1 DSI_REG(0x0058)
65 #define DSI_TIMING2 DSI_REG(0x005C)
66 #define DSI_VM_TIMING1 DSI_REG(0x0060)
67 #define DSI_VM_TIMING2 DSI_REG(0x0064)
68 #define DSI_VM_TIMING3 DSI_REG(0x0068)
69 #define DSI_CLK_TIMING DSI_REG(0x006C)
70 #define DSI_TX_FIFO_VC_SIZE DSI_REG(0x0070)
71 #define DSI_RX_FIFO_VC_SIZE DSI_REG(0x0074)
72 #define DSI_COMPLEXIO_CFG2 DSI_REG(0x0078)
73 #define DSI_RX_FIFO_VC_FULLNESS DSI_REG(0x007C)
74 #define DSI_VM_TIMING4 DSI_REG(0x0080)
75 #define DSI_TX_FIFO_VC_EMPTINESS DSI_REG(0x0084)
76 #define DSI_VM_TIMING5 DSI_REG(0x0088)
77 #define DSI_VM_TIMING6 DSI_REG(0x008C)
78 #define DSI_VM_TIMING7 DSI_REG(0x0090)
79 #define DSI_STOPCLK_TIMING DSI_REG(0x0094)
80 #define DSI_VC_CTRL(n) DSI_REG(0x0100 + (n * 0x20))
81 #define DSI_VC_TE(n) DSI_REG(0x0104 + (n * 0x20))
82 #define DSI_VC_LONG_PACKET_HEADER(n) DSI_REG(0x0108 + (n * 0x20))
83 #define DSI_VC_LONG_PACKET_PAYLOAD(n) DSI_REG(0x010C + (n * 0x20))
84 #define DSI_VC_SHORT_PACKET_HEADER(n) DSI_REG(0x0110 + (n * 0x20))
85 #define DSI_VC_IRQSTATUS(n) DSI_REG(0x0118 + (n * 0x20))
86 #define DSI_VC_IRQENABLE(n) DSI_REG(0x011C + (n * 0x20))
90 #define DSI_DSIPHY_CFG0 DSI_REG(0x200 + 0x0000)
91 #define DSI_DSIPHY_CFG1 DSI_REG(0x200 + 0x0004)
92 #define DSI_DSIPHY_CFG2 DSI_REG(0x200 + 0x0008)
93 #define DSI_DSIPHY_CFG5 DSI_REG(0x200 + 0x0014)
95 /* DSI_PLL_CTRL_SCP */
97 #define DSI_PLL_CONTROL DSI_REG(0x300 + 0x0000)
98 #define DSI_PLL_STATUS DSI_REG(0x300 + 0x0004)
99 #define DSI_PLL_GO DSI_REG(0x300 + 0x0008)
100 #define DSI_PLL_CONFIGURATION1 DSI_REG(0x300 + 0x000C)
101 #define DSI_PLL_CONFIGURATION2 DSI_REG(0x300 + 0x0010)
103 #define REG_GET(idx, start, end) \
104 FLD_GET(dsi_read_reg(idx), start, end)
106 #define REG_FLD_MOD(idx, val, start, end) \
107 dsi_write_reg(idx, FLD_MOD(dsi_read_reg(idx), val, start, end))
109 /* Global interrupts */
110 #define DSI_IRQ_VC0 (1 << 0)
111 #define DSI_IRQ_VC1 (1 << 1)
112 #define DSI_IRQ_VC2 (1 << 2)
113 #define DSI_IRQ_VC3 (1 << 3)
114 #define DSI_IRQ_WAKEUP (1 << 4)
115 #define DSI_IRQ_RESYNC (1 << 5)
116 #define DSI_IRQ_PLL_LOCK (1 << 7)
117 #define DSI_IRQ_PLL_UNLOCK (1 << 8)
118 #define DSI_IRQ_PLL_RECALL (1 << 9)
119 #define DSI_IRQ_COMPLEXIO_ERR (1 << 10)
120 #define DSI_IRQ_HS_TX_TIMEOUT (1 << 14)
121 #define DSI_IRQ_LP_RX_TIMEOUT (1 << 15)
122 #define DSI_IRQ_TE_TRIGGER (1 << 16)
123 #define DSI_IRQ_ACK_TRIGGER (1 << 17)
124 #define DSI_IRQ_SYNC_LOST (1 << 18)
125 #define DSI_IRQ_LDO_POWER_GOOD (1 << 19)
126 #define DSI_IRQ_TA_TIMEOUT (1 << 20)
127 #define DSI_IRQ_ERROR_MASK \
128 (DSI_IRQ_HS_TX_TIMEOUT | DSI_IRQ_LP_RX_TIMEOUT | DSI_IRQ_SYNC_LOST | \
130 #define DSI_IRQ_CHANNEL_MASK 0xf
132 /* Virtual channel interrupts */
133 #define DSI_VC_IRQ_CS (1 << 0)
134 #define DSI_VC_IRQ_ECC_CORR (1 << 1)
135 #define DSI_VC_IRQ_PACKET_SENT (1 << 2)
136 #define DSI_VC_IRQ_FIFO_TX_OVF (1 << 3)
137 #define DSI_VC_IRQ_FIFO_RX_OVF (1 << 4)
138 #define DSI_VC_IRQ_BTA (1 << 5)
139 #define DSI_VC_IRQ_ECC_NO_CORR (1 << 6)
140 #define DSI_VC_IRQ_FIFO_TX_UDF (1 << 7)
141 #define DSI_VC_IRQ_PP_BUSY_CHANGE (1 << 8)
142 #define DSI_VC_IRQ_ERROR_MASK \
143 (DSI_VC_IRQ_CS | DSI_VC_IRQ_ECC_CORR | DSI_VC_IRQ_FIFO_TX_OVF | \
144 DSI_VC_IRQ_FIFO_RX_OVF | DSI_VC_IRQ_ECC_NO_CORR | \
145 DSI_VC_IRQ_FIFO_TX_UDF)
147 /* ComplexIO interrupts */
148 #define DSI_CIO_IRQ_ERRSYNCESC1 (1 << 0)
149 #define DSI_CIO_IRQ_ERRSYNCESC2 (1 << 1)
150 #define DSI_CIO_IRQ_ERRSYNCESC3 (1 << 2)
151 #define DSI_CIO_IRQ_ERRESC1 (1 << 5)
152 #define DSI_CIO_IRQ_ERRESC2 (1 << 6)
153 #define DSI_CIO_IRQ_ERRESC3 (1 << 7)
154 #define DSI_CIO_IRQ_ERRCONTROL1 (1 << 10)
155 #define DSI_CIO_IRQ_ERRCONTROL2 (1 << 11)
156 #define DSI_CIO_IRQ_ERRCONTROL3 (1 << 12)
157 #define DSI_CIO_IRQ_STATEULPS1 (1 << 15)
158 #define DSI_CIO_IRQ_STATEULPS2 (1 << 16)
159 #define DSI_CIO_IRQ_STATEULPS3 (1 << 17)
160 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_1 (1 << 20)
161 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_1 (1 << 21)
162 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_2 (1 << 22)
163 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_2 (1 << 23)
164 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_3 (1 << 24)
165 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_3 (1 << 25)
166 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL0 (1 << 30)
167 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL1 (1 << 31)
168 #define DSI_CIO_IRQ_ERROR_MASK \
169 (DSI_CIO_IRQ_ERRSYNCESC1 | DSI_CIO_IRQ_ERRSYNCESC2 | \
170 DSI_CIO_IRQ_ERRSYNCESC3 | DSI_CIO_IRQ_ERRESC1 | DSI_CIO_IRQ_ERRESC2 | \
171 DSI_CIO_IRQ_ERRESC3 | DSI_CIO_IRQ_ERRCONTROL1 | \
172 DSI_CIO_IRQ_ERRCONTROL2 | DSI_CIO_IRQ_ERRCONTROL3 | \
173 DSI_CIO_IRQ_ERRCONTENTIONLP0_1 | DSI_CIO_IRQ_ERRCONTENTIONLP1_1 | \
174 DSI_CIO_IRQ_ERRCONTENTIONLP0_2 | DSI_CIO_IRQ_ERRCONTENTIONLP1_2 | \
175 DSI_CIO_IRQ_ERRCONTENTIONLP0_3 | DSI_CIO_IRQ_ERRCONTENTIONLP1_3)
177 #define DSI_DT_DCS_SHORT_WRITE_0 0x05
178 #define DSI_DT_DCS_SHORT_WRITE_1 0x15
179 #define DSI_DT_DCS_READ 0x06
180 #define DSI_DT_SET_MAX_RET_PKG_SIZE 0x37
181 #define DSI_DT_NULL_PACKET 0x09
182 #define DSI_DT_DCS_LONG_WRITE 0x39
184 #define DSI_DT_RX_ACK_WITH_ERR 0x02
185 #define DSI_DT_RX_DCS_LONG_READ 0x1c
186 #define DSI_DT_RX_SHORT_READ_1 0x21
187 #define DSI_DT_RX_SHORT_READ_2 0x22
189 #define FINT_MAX 2100000
190 #define FINT_MIN 750000
191 #define REGN_MAX (1 << 7)
192 #define REGM_MAX ((1 << 11) - 1)
193 #define REGM3_MAX (1 << 4)
194 #define REGM4_MAX (1 << 4)
195 #define LP_DIV_MAX ((1 << 13) - 1)
199 DSI_FIFO_SIZE_32
= 1,
200 DSI_FIFO_SIZE_64
= 2,
201 DSI_FIFO_SIZE_96
= 3,
202 DSI_FIFO_SIZE_128
= 4,
210 struct dsi_update_region
{
212 struct omap_dss_device
*device
;
215 struct dsi_irq_stats
{
216 unsigned long last_reset
;
218 unsigned dsi_irqs
[32];
219 unsigned vc_irqs
[4][32];
220 unsigned cio_irqs
[32];
227 struct dsi_clock_info current_cinfo
;
229 struct regulator
*vdds_dsi_reg
;
232 enum dsi_vc_mode mode
;
233 struct omap_dss_device
*dssdev
;
234 enum fifo_size fifo_size
;
238 struct semaphore bus_lock
;
242 struct completion bta_completion
;
243 void (*bta_callback
)(void);
246 struct dsi_update_region update_region
;
250 struct workqueue_struct
*workqueue
;
252 void (*framedone_callback
)(int, void *);
253 void *framedone_data
;
255 struct delayed_work framedone_timeout_work
;
257 #ifdef DSI_CATCH_MISSING_TE
258 struct timer_list te_timer
;
261 unsigned long cache_req_pck
;
262 unsigned long cache_clk_freq
;
263 struct dsi_clock_info cache_cinfo
;
266 spinlock_t errors_lock
;
268 ktime_t perf_setup_time
;
269 ktime_t perf_start_time
;
274 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
275 spinlock_t irq_stats_lock
;
276 struct dsi_irq_stats irq_stats
;
281 static unsigned int dsi_perf
;
282 module_param_named(dsi_perf
, dsi_perf
, bool, 0644);
285 static inline void dsi_write_reg(const struct dsi_reg idx
, u32 val
)
287 __raw_writel(val
, dsi
.base
+ idx
.idx
);
290 static inline u32
dsi_read_reg(const struct dsi_reg idx
)
292 return __raw_readl(dsi
.base
+ idx
.idx
);
296 void dsi_save_context(void)
300 void dsi_restore_context(void)
304 void dsi_bus_lock(void)
308 EXPORT_SYMBOL(dsi_bus_lock
);
310 void dsi_bus_unlock(void)
314 EXPORT_SYMBOL(dsi_bus_unlock
);
316 static bool dsi_bus_is_locked(void)
318 return dsi
.bus_lock
.count
== 0;
321 static inline int wait_for_bit_change(const struct dsi_reg idx
, int bitnum
,
326 while (REG_GET(idx
, bitnum
, bitnum
) != value
) {
335 static void dsi_perf_mark_setup(void)
337 dsi
.perf_setup_time
= ktime_get();
340 static void dsi_perf_mark_start(void)
342 dsi
.perf_start_time
= ktime_get();
345 static void dsi_perf_show(const char *name
)
347 ktime_t t
, setup_time
, trans_time
;
349 u32 setup_us
, trans_us
, total_us
;
356 setup_time
= ktime_sub(dsi
.perf_start_time
, dsi
.perf_setup_time
);
357 setup_us
= (u32
)ktime_to_us(setup_time
);
361 trans_time
= ktime_sub(t
, dsi
.perf_start_time
);
362 trans_us
= (u32
)ktime_to_us(trans_time
);
366 total_us
= setup_us
+ trans_us
;
368 total_bytes
= dsi
.update_region
.w
*
369 dsi
.update_region
.h
*
370 dsi
.update_region
.device
->ctrl
.pixel_size
/ 8;
372 printk(KERN_INFO
"DSI(%s): %u us + %u us = %u us (%uHz), "
373 "%u bytes, %u kbytes/sec\n",
378 1000*1000 / total_us
,
380 total_bytes
* 1000 / total_us
);
383 #define dsi_perf_mark_setup()
384 #define dsi_perf_mark_start()
385 #define dsi_perf_show(x)
388 static void print_irq_status(u32 status
)
391 if ((status
& ~DSI_IRQ_CHANNEL_MASK
) == 0)
394 printk(KERN_DEBUG
"DSI IRQ: 0x%x: ", status
);
397 if (status & DSI_IRQ_##x) \
423 static void print_irq_status_vc(int channel
, u32 status
)
426 if ((status
& ~DSI_VC_IRQ_PACKET_SENT
) == 0)
429 printk(KERN_DEBUG
"DSI VC(%d) IRQ 0x%x: ", channel
, status
);
432 if (status & DSI_VC_IRQ_##x) \
449 static void print_irq_status_cio(u32 status
)
451 printk(KERN_DEBUG
"DSI CIO IRQ 0x%x: ", status
);
454 if (status & DSI_CIO_IRQ_##x) \
468 PIS(ERRCONTENTIONLP0_1
);
469 PIS(ERRCONTENTIONLP1_1
);
470 PIS(ERRCONTENTIONLP0_2
);
471 PIS(ERRCONTENTIONLP1_2
);
472 PIS(ERRCONTENTIONLP0_3
);
473 PIS(ERRCONTENTIONLP1_3
);
474 PIS(ULPSACTIVENOT_ALL0
);
475 PIS(ULPSACTIVENOT_ALL1
);
481 static int debug_irq
;
483 /* called from dss */
484 void dsi_irq_handler(void)
486 u32 irqstatus
, vcstatus
, ciostatus
;
489 irqstatus
= dsi_read_reg(DSI_IRQSTATUS
);
491 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
492 spin_lock(&dsi
.irq_stats_lock
);
493 dsi
.irq_stats
.irq_count
++;
494 dss_collect_irq_stats(irqstatus
, dsi
.irq_stats
.dsi_irqs
);
497 if (irqstatus
& DSI_IRQ_ERROR_MASK
) {
498 DSSERR("DSI error, irqstatus %x\n", irqstatus
);
499 print_irq_status(irqstatus
);
500 spin_lock(&dsi
.errors_lock
);
501 dsi
.errors
|= irqstatus
& DSI_IRQ_ERROR_MASK
;
502 spin_unlock(&dsi
.errors_lock
);
503 } else if (debug_irq
) {
504 print_irq_status(irqstatus
);
507 #ifdef DSI_CATCH_MISSING_TE
508 if (irqstatus
& DSI_IRQ_TE_TRIGGER
)
509 del_timer(&dsi
.te_timer
);
512 for (i
= 0; i
< 4; ++i
) {
513 if ((irqstatus
& (1<<i
)) == 0)
516 vcstatus
= dsi_read_reg(DSI_VC_IRQSTATUS(i
));
518 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
519 dss_collect_irq_stats(vcstatus
, dsi
.irq_stats
.vc_irqs
[i
]);
522 if (vcstatus
& DSI_VC_IRQ_BTA
) {
523 complete(&dsi
.bta_completion
);
525 if (dsi
.bta_callback
)
529 if (vcstatus
& DSI_VC_IRQ_ERROR_MASK
) {
530 DSSERR("DSI VC(%d) error, vc irqstatus %x\n",
532 print_irq_status_vc(i
, vcstatus
);
533 } else if (debug_irq
) {
534 print_irq_status_vc(i
, vcstatus
);
537 dsi_write_reg(DSI_VC_IRQSTATUS(i
), vcstatus
);
538 /* flush posted write */
539 dsi_read_reg(DSI_VC_IRQSTATUS(i
));
542 if (irqstatus
& DSI_IRQ_COMPLEXIO_ERR
) {
543 ciostatus
= dsi_read_reg(DSI_COMPLEXIO_IRQ_STATUS
);
545 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
546 dss_collect_irq_stats(ciostatus
, dsi
.irq_stats
.cio_irqs
);
549 dsi_write_reg(DSI_COMPLEXIO_IRQ_STATUS
, ciostatus
);
550 /* flush posted write */
551 dsi_read_reg(DSI_COMPLEXIO_IRQ_STATUS
);
553 if (ciostatus
& DSI_CIO_IRQ_ERROR_MASK
) {
554 DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus
);
555 print_irq_status_cio(ciostatus
);
556 } else if (debug_irq
) {
557 print_irq_status_cio(ciostatus
);
561 dsi_write_reg(DSI_IRQSTATUS
, irqstatus
& ~DSI_IRQ_CHANNEL_MASK
);
562 /* flush posted write */
563 dsi_read_reg(DSI_IRQSTATUS
);
565 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
566 spin_unlock(&dsi
.irq_stats_lock
);
571 static void _dsi_initialize_irq(void)
576 /* disable all interrupts */
577 dsi_write_reg(DSI_IRQENABLE
, 0);
578 for (i
= 0; i
< 4; ++i
)
579 dsi_write_reg(DSI_VC_IRQENABLE(i
), 0);
580 dsi_write_reg(DSI_COMPLEXIO_IRQ_ENABLE
, 0);
582 /* clear interrupt status */
583 l
= dsi_read_reg(DSI_IRQSTATUS
);
584 dsi_write_reg(DSI_IRQSTATUS
, l
& ~DSI_IRQ_CHANNEL_MASK
);
586 for (i
= 0; i
< 4; ++i
) {
587 l
= dsi_read_reg(DSI_VC_IRQSTATUS(i
));
588 dsi_write_reg(DSI_VC_IRQSTATUS(i
), l
);
591 l
= dsi_read_reg(DSI_COMPLEXIO_IRQ_STATUS
);
592 dsi_write_reg(DSI_COMPLEXIO_IRQ_STATUS
, l
);
594 /* enable error irqs */
595 l
= DSI_IRQ_ERROR_MASK
;
596 #ifdef DSI_CATCH_MISSING_TE
597 l
|= DSI_IRQ_TE_TRIGGER
;
599 dsi_write_reg(DSI_IRQENABLE
, l
);
601 l
= DSI_VC_IRQ_ERROR_MASK
;
602 for (i
= 0; i
< 4; ++i
)
603 dsi_write_reg(DSI_VC_IRQENABLE(i
), l
);
605 l
= DSI_CIO_IRQ_ERROR_MASK
;
606 dsi_write_reg(DSI_COMPLEXIO_IRQ_ENABLE
, l
);
609 static u32
dsi_get_errors(void)
613 spin_lock_irqsave(&dsi
.errors_lock
, flags
);
616 spin_unlock_irqrestore(&dsi
.errors_lock
, flags
);
620 static void dsi_vc_enable_bta_irq(int channel
)
624 dsi_write_reg(DSI_VC_IRQSTATUS(channel
), DSI_VC_IRQ_BTA
);
626 l
= dsi_read_reg(DSI_VC_IRQENABLE(channel
));
628 dsi_write_reg(DSI_VC_IRQENABLE(channel
), l
);
631 static void dsi_vc_disable_bta_irq(int channel
)
635 l
= dsi_read_reg(DSI_VC_IRQENABLE(channel
));
636 l
&= ~DSI_VC_IRQ_BTA
;
637 dsi_write_reg(DSI_VC_IRQENABLE(channel
), l
);
640 /* DSI func clock. this could also be DSI2_PLL_FCLK */
641 static inline void enable_clocks(bool enable
)
644 dss_clk_enable(DSS_CLK_ICK
| DSS_CLK_FCK1
);
646 dss_clk_disable(DSS_CLK_ICK
| DSS_CLK_FCK1
);
649 /* source clock for DSI PLL. this could also be PCLKFREE */
650 static inline void dsi_enable_pll_clock(bool enable
)
653 dss_clk_enable(DSS_CLK_FCK2
);
655 dss_clk_disable(DSS_CLK_FCK2
);
657 if (enable
&& dsi
.pll_locked
) {
658 if (wait_for_bit_change(DSI_PLL_STATUS
, 1, 1) != 1)
659 DSSERR("cannot lock PLL when enabling clocks\n");
664 static void _dsi_print_reset_status(void)
671 /* A dummy read using the SCP interface to any DSIPHY register is
672 * required after DSIPHY reset to complete the reset of the DSI complex
674 l
= dsi_read_reg(DSI_DSIPHY_CFG5
);
676 printk(KERN_DEBUG
"DSI resets: ");
678 l
= dsi_read_reg(DSI_PLL_STATUS
);
679 printk("PLL (%d) ", FLD_GET(l
, 0, 0));
681 l
= dsi_read_reg(DSI_COMPLEXIO_CFG1
);
682 printk("CIO (%d) ", FLD_GET(l
, 29, 29));
684 l
= dsi_read_reg(DSI_DSIPHY_CFG5
);
685 printk("PHY (%x, %d, %d, %d)\n",
692 #define _dsi_print_reset_status()
695 static inline int dsi_if_enable(bool enable
)
697 DSSDBG("dsi_if_enable(%d)\n", enable
);
699 enable
= enable
? 1 : 0;
700 REG_FLD_MOD(DSI_CTRL
, enable
, 0, 0); /* IF_EN */
702 if (wait_for_bit_change(DSI_CTRL
, 0, enable
) != enable
) {
703 DSSERR("Failed to set dsi_if_enable to %d\n", enable
);
710 unsigned long dsi_get_dsi1_pll_rate(void)
712 return dsi
.current_cinfo
.dsi1_pll_fclk
;
715 static unsigned long dsi_get_dsi2_pll_rate(void)
717 return dsi
.current_cinfo
.dsi2_pll_fclk
;
720 static unsigned long dsi_get_txbyteclkhs(void)
722 return dsi
.current_cinfo
.clkin4ddr
/ 16;
725 static unsigned long dsi_fclk_rate(void)
729 if (dss_get_dsi_clk_source() == DSS_SRC_DSS1_ALWON_FCLK
) {
730 /* DSI FCLK source is DSS1_ALWON_FCK, which is dss1_fck */
731 r
= dss_clk_get_rate(DSS_CLK_FCK1
);
733 /* DSI FCLK source is DSI2_PLL_FCLK */
734 r
= dsi_get_dsi2_pll_rate();
740 static int dsi_set_lp_clk_divisor(struct omap_dss_device
*dssdev
)
742 unsigned long dsi_fclk
;
744 unsigned long lp_clk
;
746 lp_clk_div
= dssdev
->phy
.dsi
.div
.lp_clk_div
;
748 if (lp_clk_div
== 0 || lp_clk_div
> LP_DIV_MAX
)
751 dsi_fclk
= dsi_fclk_rate();
753 lp_clk
= dsi_fclk
/ 2 / lp_clk_div
;
755 DSSDBG("LP_CLK_DIV %u, LP_CLK %lu\n", lp_clk_div
, lp_clk
);
756 dsi
.current_cinfo
.lp_clk
= lp_clk
;
757 dsi
.current_cinfo
.lp_clk_div
= lp_clk_div
;
759 REG_FLD_MOD(DSI_CLK_CTRL
, lp_clk_div
, 12, 0); /* LP_CLK_DIVISOR */
761 REG_FLD_MOD(DSI_CLK_CTRL
, dsi_fclk
> 30000000 ? 1 : 0,
762 21, 21); /* LP_RX_SYNCHRO_ENABLE */
768 enum dsi_pll_power_state
{
769 DSI_PLL_POWER_OFF
= 0x0,
770 DSI_PLL_POWER_ON_HSCLK
= 0x1,
771 DSI_PLL_POWER_ON_ALL
= 0x2,
772 DSI_PLL_POWER_ON_DIV
= 0x3,
775 static int dsi_pll_power(enum dsi_pll_power_state state
)
779 REG_FLD_MOD(DSI_CLK_CTRL
, state
, 31, 30); /* PLL_PWR_CMD */
782 while (FLD_GET(dsi_read_reg(DSI_CLK_CTRL
), 29, 28) != state
) {
784 DSSERR("Failed to set DSI PLL power mode to %d\n",
794 /* calculate clock rates using dividers in cinfo */
795 static int dsi_calc_clock_rates(struct dsi_clock_info
*cinfo
)
797 if (cinfo
->regn
== 0 || cinfo
->regn
> REGN_MAX
)
800 if (cinfo
->regm
== 0 || cinfo
->regm
> REGM_MAX
)
803 if (cinfo
->regm3
> REGM3_MAX
)
806 if (cinfo
->regm4
> REGM4_MAX
)
809 if (cinfo
->use_dss2_fck
) {
810 cinfo
->clkin
= dss_clk_get_rate(DSS_CLK_FCK2
);
813 cinfo
->clkin
= dispc_pclk_rate();
815 if (cinfo
->clkin
< 32000000)
821 cinfo
->fint
= cinfo
->clkin
/ (cinfo
->regn
* (cinfo
->highfreq
? 2 : 1));
823 if (cinfo
->fint
> FINT_MAX
|| cinfo
->fint
< FINT_MIN
)
826 cinfo
->clkin4ddr
= 2 * cinfo
->regm
* cinfo
->fint
;
828 if (cinfo
->clkin4ddr
> 1800 * 1000 * 1000)
831 if (cinfo
->regm3
> 0)
832 cinfo
->dsi1_pll_fclk
= cinfo
->clkin4ddr
/ cinfo
->regm3
;
834 cinfo
->dsi1_pll_fclk
= 0;
836 if (cinfo
->regm4
> 0)
837 cinfo
->dsi2_pll_fclk
= cinfo
->clkin4ddr
/ cinfo
->regm4
;
839 cinfo
->dsi2_pll_fclk
= 0;
844 int dsi_pll_calc_clock_div_pck(bool is_tft
, unsigned long req_pck
,
845 struct dsi_clock_info
*dsi_cinfo
,
846 struct dispc_clock_info
*dispc_cinfo
)
848 struct dsi_clock_info cur
, best
;
849 struct dispc_clock_info best_dispc
;
852 unsigned long dss_clk_fck2
;
854 dss_clk_fck2
= dss_clk_get_rate(DSS_CLK_FCK2
);
856 if (req_pck
== dsi
.cache_req_pck
&&
857 dsi
.cache_cinfo
.clkin
== dss_clk_fck2
) {
858 DSSDBG("DSI clock info found from cache\n");
859 *dsi_cinfo
= dsi
.cache_cinfo
;
860 dispc_find_clk_divs(is_tft
, req_pck
, dsi_cinfo
->dsi1_pll_fclk
,
865 min_fck_per_pck
= CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK
;
867 if (min_fck_per_pck
&&
868 req_pck
* min_fck_per_pck
> DISPC_MAX_FCK
) {
869 DSSERR("Requested pixel clock not possible with the current "
870 "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
871 "the constraint off.\n");
875 DSSDBG("dsi_pll_calc\n");
878 memset(&best
, 0, sizeof(best
));
879 memset(&best_dispc
, 0, sizeof(best_dispc
));
881 memset(&cur
, 0, sizeof(cur
));
882 cur
.clkin
= dss_clk_fck2
;
883 cur
.use_dss2_fck
= 1;
886 /* no highfreq: 0.75MHz < Fint = clkin / regn < 2.1MHz */
887 /* highfreq: 0.75MHz < Fint = clkin / (2*regn) < 2.1MHz */
888 /* To reduce PLL lock time, keep Fint high (around 2 MHz) */
889 for (cur
.regn
= 1; cur
.regn
< REGN_MAX
; ++cur
.regn
) {
890 if (cur
.highfreq
== 0)
891 cur
.fint
= cur
.clkin
/ cur
.regn
;
893 cur
.fint
= cur
.clkin
/ (2 * cur
.regn
);
895 if (cur
.fint
> FINT_MAX
|| cur
.fint
< FINT_MIN
)
898 /* DSIPHY(MHz) = (2 * regm / regn) * (clkin / (highfreq + 1)) */
899 for (cur
.regm
= 1; cur
.regm
< REGM_MAX
; ++cur
.regm
) {
902 a
= 2 * cur
.regm
* (cur
.clkin
/1000);
903 b
= cur
.regn
* (cur
.highfreq
+ 1);
904 cur
.clkin4ddr
= a
/ b
* 1000;
906 if (cur
.clkin4ddr
> 1800 * 1000 * 1000)
909 /* DSI1_PLL_FCLK(MHz) = DSIPHY(MHz) / regm3 < 173MHz */
910 for (cur
.regm3
= 1; cur
.regm3
< REGM3_MAX
;
912 struct dispc_clock_info cur_dispc
;
913 cur
.dsi1_pll_fclk
= cur
.clkin4ddr
/ cur
.regm3
;
915 /* this will narrow down the search a bit,
916 * but still give pixclocks below what was
918 if (cur
.dsi1_pll_fclk
< req_pck
)
921 if (cur
.dsi1_pll_fclk
> DISPC_MAX_FCK
)
924 if (min_fck_per_pck
&&
926 req_pck
* min_fck_per_pck
)
931 dispc_find_clk_divs(is_tft
, req_pck
,
935 if (abs(cur_dispc
.pck
- req_pck
) <
936 abs(best_dispc
.pck
- req_pck
)) {
938 best_dispc
= cur_dispc
;
940 if (cur_dispc
.pck
== req_pck
)
948 if (min_fck_per_pck
) {
949 DSSERR("Could not find suitable clock settings.\n"
950 "Turning FCK/PCK constraint off and"
956 DSSERR("Could not find suitable clock settings.\n");
961 /* DSI2_PLL_FCLK (regm4) is not used */
963 best
.dsi2_pll_fclk
= 0;
968 *dispc_cinfo
= best_dispc
;
970 dsi
.cache_req_pck
= req_pck
;
971 dsi
.cache_clk_freq
= 0;
972 dsi
.cache_cinfo
= best
;
977 int dsi_pll_set_clock_div(struct dsi_clock_info
*cinfo
)
985 dsi
.current_cinfo
.fint
= cinfo
->fint
;
986 dsi
.current_cinfo
.clkin4ddr
= cinfo
->clkin4ddr
;
987 dsi
.current_cinfo
.dsi1_pll_fclk
= cinfo
->dsi1_pll_fclk
;
988 dsi
.current_cinfo
.dsi2_pll_fclk
= cinfo
->dsi2_pll_fclk
;
990 dsi
.current_cinfo
.regn
= cinfo
->regn
;
991 dsi
.current_cinfo
.regm
= cinfo
->regm
;
992 dsi
.current_cinfo
.regm3
= cinfo
->regm3
;
993 dsi
.current_cinfo
.regm4
= cinfo
->regm4
;
995 DSSDBG("DSI Fint %ld\n", cinfo
->fint
);
997 DSSDBG("clkin (%s) rate %ld, highfreq %d\n",
998 cinfo
->use_dss2_fck
? "dss2_fck" : "pclkfree",
1002 /* DSIPHY == CLKIN4DDR */
1003 DSSDBG("CLKIN4DDR = 2 * %d / %d * %lu / %d = %lu\n",
1007 cinfo
->highfreq
+ 1,
1010 DSSDBG("Data rate on 1 DSI lane %ld Mbps\n",
1011 cinfo
->clkin4ddr
/ 1000 / 1000 / 2);
1013 DSSDBG("Clock lane freq %ld Hz\n", cinfo
->clkin4ddr
/ 4);
1015 DSSDBG("regm3 = %d, dsi1_pll_fclk = %lu\n",
1016 cinfo
->regm3
, cinfo
->dsi1_pll_fclk
);
1017 DSSDBG("regm4 = %d, dsi2_pll_fclk = %lu\n",
1018 cinfo
->regm4
, cinfo
->dsi2_pll_fclk
);
1020 REG_FLD_MOD(DSI_PLL_CONTROL
, 0, 0, 0); /* DSI_PLL_AUTOMODE = manual */
1022 l
= dsi_read_reg(DSI_PLL_CONFIGURATION1
);
1023 l
= FLD_MOD(l
, 1, 0, 0); /* DSI_PLL_STOPMODE */
1024 l
= FLD_MOD(l
, cinfo
->regn
- 1, 7, 1); /* DSI_PLL_REGN */
1025 l
= FLD_MOD(l
, cinfo
->regm
, 18, 8); /* DSI_PLL_REGM */
1026 l
= FLD_MOD(l
, cinfo
->regm3
> 0 ? cinfo
->regm3
- 1 : 0,
1027 22, 19); /* DSI_CLOCK_DIV */
1028 l
= FLD_MOD(l
, cinfo
->regm4
> 0 ? cinfo
->regm4
- 1 : 0,
1029 26, 23); /* DSIPROTO_CLOCK_DIV */
1030 dsi_write_reg(DSI_PLL_CONFIGURATION1
, l
);
1032 BUG_ON(cinfo
->fint
< 750000 || cinfo
->fint
> 2100000);
1033 if (cinfo
->fint
< 1000000)
1035 else if (cinfo
->fint
< 1250000)
1037 else if (cinfo
->fint
< 1500000)
1039 else if (cinfo
->fint
< 1750000)
1044 l
= dsi_read_reg(DSI_PLL_CONFIGURATION2
);
1045 l
= FLD_MOD(l
, f
, 4, 1); /* DSI_PLL_FREQSEL */
1046 l
= FLD_MOD(l
, cinfo
->use_dss2_fck
? 0 : 1,
1047 11, 11); /* DSI_PLL_CLKSEL */
1048 l
= FLD_MOD(l
, cinfo
->highfreq
,
1049 12, 12); /* DSI_PLL_HIGHFREQ */
1050 l
= FLD_MOD(l
, 1, 13, 13); /* DSI_PLL_REFEN */
1051 l
= FLD_MOD(l
, 0, 14, 14); /* DSIPHY_CLKINEN */
1052 l
= FLD_MOD(l
, 1, 20, 20); /* DSI_HSDIVBYPASS */
1053 dsi_write_reg(DSI_PLL_CONFIGURATION2
, l
);
1055 REG_FLD_MOD(DSI_PLL_GO
, 1, 0, 0); /* DSI_PLL_GO */
1057 if (wait_for_bit_change(DSI_PLL_GO
, 0, 0) != 0) {
1058 DSSERR("dsi pll go bit not going down.\n");
1063 if (wait_for_bit_change(DSI_PLL_STATUS
, 1, 1) != 1) {
1064 DSSERR("cannot lock PLL\n");
1071 l
= dsi_read_reg(DSI_PLL_CONFIGURATION2
);
1072 l
= FLD_MOD(l
, 0, 0, 0); /* DSI_PLL_IDLE */
1073 l
= FLD_MOD(l
, 0, 5, 5); /* DSI_PLL_PLLLPMODE */
1074 l
= FLD_MOD(l
, 0, 6, 6); /* DSI_PLL_LOWCURRSTBY */
1075 l
= FLD_MOD(l
, 0, 7, 7); /* DSI_PLL_TIGHTPHASELOCK */
1076 l
= FLD_MOD(l
, 0, 8, 8); /* DSI_PLL_DRIFTGUARDEN */
1077 l
= FLD_MOD(l
, 0, 10, 9); /* DSI_PLL_LOCKSEL */
1078 l
= FLD_MOD(l
, 1, 13, 13); /* DSI_PLL_REFEN */
1079 l
= FLD_MOD(l
, 1, 14, 14); /* DSIPHY_CLKINEN */
1080 l
= FLD_MOD(l
, 0, 15, 15); /* DSI_BYPASSEN */
1081 l
= FLD_MOD(l
, 1, 16, 16); /* DSS_CLOCK_EN */
1082 l
= FLD_MOD(l
, 0, 17, 17); /* DSS_CLOCK_PWDN */
1083 l
= FLD_MOD(l
, 1, 18, 18); /* DSI_PROTO_CLOCK_EN */
1084 l
= FLD_MOD(l
, 0, 19, 19); /* DSI_PROTO_CLOCK_PWDN */
1085 l
= FLD_MOD(l
, 0, 20, 20); /* DSI_HSDIVBYPASS */
1086 dsi_write_reg(DSI_PLL_CONFIGURATION2
, l
);
1088 DSSDBG("PLL config done\n");
1093 int dsi_pll_init(struct omap_dss_device
*dssdev
, bool enable_hsclk
,
1097 enum dsi_pll_power_state pwstate
;
1099 DSSDBG("PLL init\n");
1102 dsi_enable_pll_clock(1);
1104 r
= regulator_enable(dsi
.vdds_dsi_reg
);
1108 dispc_pck_free_enable(1);
1110 if (wait_for_bit_change(DSI_PLL_STATUS
, 0, 1) != 1) {
1111 DSSERR("PLL not coming out of reset.\n");
1113 dispc_pck_free_enable(0);
1117 dispc_pck_free_enable(0);
1119 if (enable_hsclk
&& enable_hsdiv
)
1120 pwstate
= DSI_PLL_POWER_ON_ALL
;
1121 else if (enable_hsclk
)
1122 pwstate
= DSI_PLL_POWER_ON_HSCLK
;
1123 else if (enable_hsdiv
)
1124 pwstate
= DSI_PLL_POWER_ON_DIV
;
1126 pwstate
= DSI_PLL_POWER_OFF
;
1128 r
= dsi_pll_power(pwstate
);
1133 DSSDBG("PLL init done\n");
1137 regulator_disable(dsi
.vdds_dsi_reg
);
1140 dsi_enable_pll_clock(0);
1144 void dsi_pll_uninit(void)
1147 dsi_enable_pll_clock(0);
1150 dsi_pll_power(DSI_PLL_POWER_OFF
);
1151 regulator_disable(dsi
.vdds_dsi_reg
);
1152 DSSDBG("PLL uninit done\n");
1155 void dsi_dump_clocks(struct seq_file
*s
)
1158 struct dsi_clock_info
*cinfo
= &dsi
.current_cinfo
;
1162 clksel
= REG_GET(DSI_PLL_CONFIGURATION2
, 11, 11);
1164 seq_printf(s
, "- DSI PLL -\n");
1166 seq_printf(s
, "dsi pll source = %s\n",
1168 "dss2_alwon_fclk" : "pclkfree");
1170 seq_printf(s
, "Fint\t\t%-16luregn %u\n", cinfo
->fint
, cinfo
->regn
);
1172 seq_printf(s
, "CLKIN4DDR\t%-16luregm %u\n",
1173 cinfo
->clkin4ddr
, cinfo
->regm
);
1175 seq_printf(s
, "dsi1_pll_fck\t%-16luregm3 %u\t(%s)\n",
1176 cinfo
->dsi1_pll_fclk
,
1178 dss_get_dispc_clk_source() == DSS_SRC_DSS1_ALWON_FCLK
?
1181 seq_printf(s
, "dsi2_pll_fck\t%-16luregm4 %u\t(%s)\n",
1182 cinfo
->dsi2_pll_fclk
,
1184 dss_get_dsi_clk_source() == DSS_SRC_DSS1_ALWON_FCLK
?
1187 seq_printf(s
, "- DSI -\n");
1189 seq_printf(s
, "dsi fclk source = %s\n",
1190 dss_get_dsi_clk_source() == DSS_SRC_DSS1_ALWON_FCLK
?
1191 "dss1_alwon_fclk" : "dsi2_pll_fclk");
1193 seq_printf(s
, "DSI_FCLK\t%lu\n", dsi_fclk_rate());
1195 seq_printf(s
, "DDR_CLK\t\t%lu\n",
1196 cinfo
->clkin4ddr
/ 4);
1198 seq_printf(s
, "TxByteClkHS\t%lu\n", dsi_get_txbyteclkhs());
1200 seq_printf(s
, "LP_CLK\t\t%lu\n", cinfo
->lp_clk
);
1202 seq_printf(s
, "VP_CLK\t\t%lu\n"
1210 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
1211 void dsi_dump_irqs(struct seq_file
*s
)
1213 unsigned long flags
;
1214 struct dsi_irq_stats stats
;
1216 spin_lock_irqsave(&dsi
.irq_stats_lock
, flags
);
1218 stats
= dsi
.irq_stats
;
1219 memset(&dsi
.irq_stats
, 0, sizeof(dsi
.irq_stats
));
1220 dsi
.irq_stats
.last_reset
= jiffies
;
1222 spin_unlock_irqrestore(&dsi
.irq_stats_lock
, flags
);
1224 seq_printf(s
, "period %u ms\n",
1225 jiffies_to_msecs(jiffies
- stats
.last_reset
));
1227 seq_printf(s
, "irqs %d\n", stats
.irq_count
);
1229 seq_printf(s, "%-20s %10d\n", #x, stats.dsi_irqs[ffs(DSI_IRQ_##x)-1]);
1231 seq_printf(s
, "-- DSI interrupts --\n");
1247 PIS(LDO_POWER_GOOD
);
1252 seq_printf(s, "%-20s %10d %10d %10d %10d\n", #x, \
1253 stats.vc_irqs[0][ffs(DSI_VC_IRQ_##x)-1], \
1254 stats.vc_irqs[1][ffs(DSI_VC_IRQ_##x)-1], \
1255 stats.vc_irqs[2][ffs(DSI_VC_IRQ_##x)-1], \
1256 stats.vc_irqs[3][ffs(DSI_VC_IRQ_##x)-1]);
1258 seq_printf(s
, "-- VC interrupts --\n");
1267 PIS(PP_BUSY_CHANGE
);
1271 seq_printf(s, "%-20s %10d\n", #x, \
1272 stats.cio_irqs[ffs(DSI_CIO_IRQ_##x)-1]);
1274 seq_printf(s
, "-- CIO interrupts --\n");
1287 PIS(ERRCONTENTIONLP0_1
);
1288 PIS(ERRCONTENTIONLP1_1
);
1289 PIS(ERRCONTENTIONLP0_2
);
1290 PIS(ERRCONTENTIONLP1_2
);
1291 PIS(ERRCONTENTIONLP0_3
);
1292 PIS(ERRCONTENTIONLP1_3
);
1293 PIS(ULPSACTIVENOT_ALL0
);
1294 PIS(ULPSACTIVENOT_ALL1
);
1299 void dsi_dump_regs(struct seq_file
*s
)
1301 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(r))
1303 dss_clk_enable(DSS_CLK_ICK
| DSS_CLK_FCK1
);
1305 DUMPREG(DSI_REVISION
);
1306 DUMPREG(DSI_SYSCONFIG
);
1307 DUMPREG(DSI_SYSSTATUS
);
1308 DUMPREG(DSI_IRQSTATUS
);
1309 DUMPREG(DSI_IRQENABLE
);
1311 DUMPREG(DSI_COMPLEXIO_CFG1
);
1312 DUMPREG(DSI_COMPLEXIO_IRQ_STATUS
);
1313 DUMPREG(DSI_COMPLEXIO_IRQ_ENABLE
);
1314 DUMPREG(DSI_CLK_CTRL
);
1315 DUMPREG(DSI_TIMING1
);
1316 DUMPREG(DSI_TIMING2
);
1317 DUMPREG(DSI_VM_TIMING1
);
1318 DUMPREG(DSI_VM_TIMING2
);
1319 DUMPREG(DSI_VM_TIMING3
);
1320 DUMPREG(DSI_CLK_TIMING
);
1321 DUMPREG(DSI_TX_FIFO_VC_SIZE
);
1322 DUMPREG(DSI_RX_FIFO_VC_SIZE
);
1323 DUMPREG(DSI_COMPLEXIO_CFG2
);
1324 DUMPREG(DSI_RX_FIFO_VC_FULLNESS
);
1325 DUMPREG(DSI_VM_TIMING4
);
1326 DUMPREG(DSI_TX_FIFO_VC_EMPTINESS
);
1327 DUMPREG(DSI_VM_TIMING5
);
1328 DUMPREG(DSI_VM_TIMING6
);
1329 DUMPREG(DSI_VM_TIMING7
);
1330 DUMPREG(DSI_STOPCLK_TIMING
);
1332 DUMPREG(DSI_VC_CTRL(0));
1333 DUMPREG(DSI_VC_TE(0));
1334 DUMPREG(DSI_VC_LONG_PACKET_HEADER(0));
1335 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(0));
1336 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(0));
1337 DUMPREG(DSI_VC_IRQSTATUS(0));
1338 DUMPREG(DSI_VC_IRQENABLE(0));
1340 DUMPREG(DSI_VC_CTRL(1));
1341 DUMPREG(DSI_VC_TE(1));
1342 DUMPREG(DSI_VC_LONG_PACKET_HEADER(1));
1343 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(1));
1344 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(1));
1345 DUMPREG(DSI_VC_IRQSTATUS(1));
1346 DUMPREG(DSI_VC_IRQENABLE(1));
1348 DUMPREG(DSI_VC_CTRL(2));
1349 DUMPREG(DSI_VC_TE(2));
1350 DUMPREG(DSI_VC_LONG_PACKET_HEADER(2));
1351 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(2));
1352 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(2));
1353 DUMPREG(DSI_VC_IRQSTATUS(2));
1354 DUMPREG(DSI_VC_IRQENABLE(2));
1356 DUMPREG(DSI_VC_CTRL(3));
1357 DUMPREG(DSI_VC_TE(3));
1358 DUMPREG(DSI_VC_LONG_PACKET_HEADER(3));
1359 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(3));
1360 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(3));
1361 DUMPREG(DSI_VC_IRQSTATUS(3));
1362 DUMPREG(DSI_VC_IRQENABLE(3));
1364 DUMPREG(DSI_DSIPHY_CFG0
);
1365 DUMPREG(DSI_DSIPHY_CFG1
);
1366 DUMPREG(DSI_DSIPHY_CFG2
);
1367 DUMPREG(DSI_DSIPHY_CFG5
);
1369 DUMPREG(DSI_PLL_CONTROL
);
1370 DUMPREG(DSI_PLL_STATUS
);
1371 DUMPREG(DSI_PLL_GO
);
1372 DUMPREG(DSI_PLL_CONFIGURATION1
);
1373 DUMPREG(DSI_PLL_CONFIGURATION2
);
1375 dss_clk_disable(DSS_CLK_ICK
| DSS_CLK_FCK1
);
1379 enum dsi_complexio_power_state
{
1380 DSI_COMPLEXIO_POWER_OFF
= 0x0,
1381 DSI_COMPLEXIO_POWER_ON
= 0x1,
1382 DSI_COMPLEXIO_POWER_ULPS
= 0x2,
1385 static int dsi_complexio_power(enum dsi_complexio_power_state state
)
1390 REG_FLD_MOD(DSI_COMPLEXIO_CFG1
, state
, 28, 27);
1393 while (FLD_GET(dsi_read_reg(DSI_COMPLEXIO_CFG1
), 26, 25) != state
) {
1395 DSSERR("failed to set complexio power state to "
1405 static void dsi_complexio_config(struct omap_dss_device
*dssdev
)
1409 int clk_lane
= dssdev
->phy
.dsi
.clk_lane
;
1410 int data1_lane
= dssdev
->phy
.dsi
.data1_lane
;
1411 int data2_lane
= dssdev
->phy
.dsi
.data2_lane
;
1412 int clk_pol
= dssdev
->phy
.dsi
.clk_pol
;
1413 int data1_pol
= dssdev
->phy
.dsi
.data1_pol
;
1414 int data2_pol
= dssdev
->phy
.dsi
.data2_pol
;
1416 r
= dsi_read_reg(DSI_COMPLEXIO_CFG1
);
1417 r
= FLD_MOD(r
, clk_lane
, 2, 0);
1418 r
= FLD_MOD(r
, clk_pol
, 3, 3);
1419 r
= FLD_MOD(r
, data1_lane
, 6, 4);
1420 r
= FLD_MOD(r
, data1_pol
, 7, 7);
1421 r
= FLD_MOD(r
, data2_lane
, 10, 8);
1422 r
= FLD_MOD(r
, data2_pol
, 11, 11);
1423 dsi_write_reg(DSI_COMPLEXIO_CFG1
, r
);
1425 /* The configuration of the DSI complex I/O (number of data lanes,
1426 position, differential order) should not be changed while
1427 DSS.DSI_CLK_CRTRL[20] LP_CLK_ENABLE bit is set to 1. In order for
1428 the hardware to take into account a new configuration of the complex
1429 I/O (done in DSS.DSI_COMPLEXIO_CFG1 register), it is recommended to
1430 follow this sequence: First set the DSS.DSI_CTRL[0] IF_EN bit to 1,
1431 then reset the DSS.DSI_CTRL[0] IF_EN to 0, then set
1432 DSS.DSI_CLK_CTRL[20] LP_CLK_ENABLE to 1 and finally set again the
1433 DSS.DSI_CTRL[0] IF_EN bit to 1. If the sequence is not followed, the
1434 DSI complex I/O configuration is unknown. */
1437 REG_FLD_MOD(DSI_CTRL, 1, 0, 0);
1438 REG_FLD_MOD(DSI_CTRL, 0, 0, 0);
1439 REG_FLD_MOD(DSI_CLK_CTRL, 1, 20, 20);
1440 REG_FLD_MOD(DSI_CTRL, 1, 0, 0);
1444 static inline unsigned ns2ddr(unsigned ns
)
1446 /* convert time in ns to ddr ticks, rounding up */
1447 unsigned long ddr_clk
= dsi
.current_cinfo
.clkin4ddr
/ 4;
1448 return (ns
* (ddr_clk
/ 1000 / 1000) + 999) / 1000;
1451 static inline unsigned ddr2ns(unsigned ddr
)
1453 unsigned long ddr_clk
= dsi
.current_cinfo
.clkin4ddr
/ 4;
1454 return ddr
* 1000 * 1000 / (ddr_clk
/ 1000);
1457 static void dsi_complexio_timings(void)
1460 u32 ths_prepare
, ths_prepare_ths_zero
, ths_trail
, ths_exit
;
1461 u32 tlpx_half
, tclk_trail
, tclk_zero
;
1464 /* calculate timings */
1466 /* 1 * DDR_CLK = 2 * UI */
1468 /* min 40ns + 4*UI max 85ns + 6*UI */
1469 ths_prepare
= ns2ddr(70) + 2;
1471 /* min 145ns + 10*UI */
1472 ths_prepare_ths_zero
= ns2ddr(175) + 2;
1474 /* min max(8*UI, 60ns+4*UI) */
1475 ths_trail
= ns2ddr(60) + 5;
1478 ths_exit
= ns2ddr(145);
1481 tlpx_half
= ns2ddr(25);
1484 tclk_trail
= ns2ddr(60) + 2;
1486 /* min 38ns, max 95ns */
1487 tclk_prepare
= ns2ddr(65);
1489 /* min tclk-prepare + tclk-zero = 300ns */
1490 tclk_zero
= ns2ddr(260);
1492 DSSDBG("ths_prepare %u (%uns), ths_prepare_ths_zero %u (%uns)\n",
1493 ths_prepare
, ddr2ns(ths_prepare
),
1494 ths_prepare_ths_zero
, ddr2ns(ths_prepare_ths_zero
));
1495 DSSDBG("ths_trail %u (%uns), ths_exit %u (%uns)\n",
1496 ths_trail
, ddr2ns(ths_trail
),
1497 ths_exit
, ddr2ns(ths_exit
));
1499 DSSDBG("tlpx_half %u (%uns), tclk_trail %u (%uns), "
1500 "tclk_zero %u (%uns)\n",
1501 tlpx_half
, ddr2ns(tlpx_half
),
1502 tclk_trail
, ddr2ns(tclk_trail
),
1503 tclk_zero
, ddr2ns(tclk_zero
));
1504 DSSDBG("tclk_prepare %u (%uns)\n",
1505 tclk_prepare
, ddr2ns(tclk_prepare
));
1507 /* program timings */
1509 r
= dsi_read_reg(DSI_DSIPHY_CFG0
);
1510 r
= FLD_MOD(r
, ths_prepare
, 31, 24);
1511 r
= FLD_MOD(r
, ths_prepare_ths_zero
, 23, 16);
1512 r
= FLD_MOD(r
, ths_trail
, 15, 8);
1513 r
= FLD_MOD(r
, ths_exit
, 7, 0);
1514 dsi_write_reg(DSI_DSIPHY_CFG0
, r
);
1516 r
= dsi_read_reg(DSI_DSIPHY_CFG1
);
1517 r
= FLD_MOD(r
, tlpx_half
, 22, 16);
1518 r
= FLD_MOD(r
, tclk_trail
, 15, 8);
1519 r
= FLD_MOD(r
, tclk_zero
, 7, 0);
1520 dsi_write_reg(DSI_DSIPHY_CFG1
, r
);
1522 r
= dsi_read_reg(DSI_DSIPHY_CFG2
);
1523 r
= FLD_MOD(r
, tclk_prepare
, 7, 0);
1524 dsi_write_reg(DSI_DSIPHY_CFG2
, r
);
1528 static int dsi_complexio_init(struct omap_dss_device
*dssdev
)
1532 DSSDBG("dsi_complexio_init\n");
1534 /* CIO_CLK_ICG, enable L3 clk to CIO */
1535 REG_FLD_MOD(DSI_CLK_CTRL
, 1, 14, 14);
1537 /* A dummy read using the SCP interface to any DSIPHY register is
1538 * required after DSIPHY reset to complete the reset of the DSI complex
1540 dsi_read_reg(DSI_DSIPHY_CFG5
);
1542 if (wait_for_bit_change(DSI_DSIPHY_CFG5
, 30, 1) != 1) {
1543 DSSERR("ComplexIO PHY not coming out of reset.\n");
1548 dsi_complexio_config(dssdev
);
1550 r
= dsi_complexio_power(DSI_COMPLEXIO_POWER_ON
);
1555 if (wait_for_bit_change(DSI_COMPLEXIO_CFG1
, 29, 1) != 1) {
1556 DSSERR("ComplexIO not coming out of reset.\n");
1561 if (wait_for_bit_change(DSI_COMPLEXIO_CFG1
, 21, 1) != 1) {
1562 DSSERR("ComplexIO LDO power down.\n");
1567 dsi_complexio_timings();
1570 The configuration of the DSI complex I/O (number of data lanes,
1571 position, differential order) should not be changed while
1572 DSS.DSI_CLK_CRTRL[20] LP_CLK_ENABLE bit is set to 1. For the
1573 hardware to recognize a new configuration of the complex I/O (done
1574 in DSS.DSI_COMPLEXIO_CFG1 register), it is recommended to follow
1575 this sequence: First set the DSS.DSI_CTRL[0] IF_EN bit to 1, next
1576 reset the DSS.DSI_CTRL[0] IF_EN to 0, then set DSS.DSI_CLK_CTRL[20]
1577 LP_CLK_ENABLE to 1, and finally, set again the DSS.DSI_CTRL[0] IF_EN
1578 bit to 1. If the sequence is not followed, the DSi complex I/O
1579 configuration is undetermined.
1583 REG_FLD_MOD(DSI_CLK_CTRL
, 1, 20, 20); /* LP_CLK_ENABLE */
1587 DSSDBG("CIO init done\n");
1592 static void dsi_complexio_uninit(void)
1594 dsi_complexio_power(DSI_COMPLEXIO_POWER_OFF
);
1597 static int _dsi_wait_reset(void)
1601 while (REG_GET(DSI_SYSSTATUS
, 0, 0) == 0) {
1603 DSSERR("soft reset failed\n");
1612 static int _dsi_reset(void)
1615 REG_FLD_MOD(DSI_SYSCONFIG
, 1, 1, 1);
1616 return _dsi_wait_reset();
1619 static void dsi_reset_tx_fifo(int channel
)
1624 /* set fifosize of the channel to 0, then return the old size */
1625 l
= dsi_read_reg(DSI_TX_FIFO_VC_SIZE
);
1627 mask
= FLD_MASK((8 * channel
) + 7, (8 * channel
) + 4);
1628 dsi_write_reg(DSI_TX_FIFO_VC_SIZE
, l
& ~mask
);
1630 dsi_write_reg(DSI_TX_FIFO_VC_SIZE
, l
);
1633 static void dsi_config_tx_fifo(enum fifo_size size1
, enum fifo_size size2
,
1634 enum fifo_size size3
, enum fifo_size size4
)
1640 dsi
.vc
[0].fifo_size
= size1
;
1641 dsi
.vc
[1].fifo_size
= size2
;
1642 dsi
.vc
[2].fifo_size
= size3
;
1643 dsi
.vc
[3].fifo_size
= size4
;
1645 for (i
= 0; i
< 4; i
++) {
1647 int size
= dsi
.vc
[i
].fifo_size
;
1649 if (add
+ size
> 4) {
1650 DSSERR("Illegal FIFO configuration\n");
1654 v
= FLD_VAL(add
, 2, 0) | FLD_VAL(size
, 7, 4);
1656 /*DSSDBG("TX FIFO vc %d: size %d, add %d\n", i, size, add); */
1660 dsi_write_reg(DSI_TX_FIFO_VC_SIZE
, r
);
1663 static void dsi_config_rx_fifo(enum fifo_size size1
, enum fifo_size size2
,
1664 enum fifo_size size3
, enum fifo_size size4
)
1670 dsi
.vc
[0].fifo_size
= size1
;
1671 dsi
.vc
[1].fifo_size
= size2
;
1672 dsi
.vc
[2].fifo_size
= size3
;
1673 dsi
.vc
[3].fifo_size
= size4
;
1675 for (i
= 0; i
< 4; i
++) {
1677 int size
= dsi
.vc
[i
].fifo_size
;
1679 if (add
+ size
> 4) {
1680 DSSERR("Illegal FIFO configuration\n");
1684 v
= FLD_VAL(add
, 2, 0) | FLD_VAL(size
, 7, 4);
1686 /*DSSDBG("RX FIFO vc %d: size %d, add %d\n", i, size, add); */
1690 dsi_write_reg(DSI_RX_FIFO_VC_SIZE
, r
);
1693 static int dsi_force_tx_stop_mode_io(void)
1697 r
= dsi_read_reg(DSI_TIMING1
);
1698 r
= FLD_MOD(r
, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
1699 dsi_write_reg(DSI_TIMING1
, r
);
1701 if (wait_for_bit_change(DSI_TIMING1
, 15, 0) != 0) {
1702 DSSERR("TX_STOP bit not going down\n");
1709 static int dsi_vc_enable(int channel
, bool enable
)
1711 DSSDBG("dsi_vc_enable channel %d, enable %d\n",
1714 enable
= enable
? 1 : 0;
1716 REG_FLD_MOD(DSI_VC_CTRL(channel
), enable
, 0, 0);
1718 if (wait_for_bit_change(DSI_VC_CTRL(channel
), 0, enable
) != enable
) {
1719 DSSERR("Failed to set dsi_vc_enable to %d\n", enable
);
1726 static void dsi_vc_initial_config(int channel
)
1730 DSSDBGF("%d", channel
);
1732 r
= dsi_read_reg(DSI_VC_CTRL(channel
));
1734 if (FLD_GET(r
, 15, 15)) /* VC_BUSY */
1735 DSSERR("VC(%d) busy when trying to configure it!\n",
1738 r
= FLD_MOD(r
, 0, 1, 1); /* SOURCE, 0 = L4 */
1739 r
= FLD_MOD(r
, 0, 2, 2); /* BTA_SHORT_EN */
1740 r
= FLD_MOD(r
, 0, 3, 3); /* BTA_LONG_EN */
1741 r
= FLD_MOD(r
, 0, 4, 4); /* MODE, 0 = command */
1742 r
= FLD_MOD(r
, 1, 7, 7); /* CS_TX_EN */
1743 r
= FLD_MOD(r
, 1, 8, 8); /* ECC_TX_EN */
1744 r
= FLD_MOD(r
, 0, 9, 9); /* MODE_SPEED, high speed on/off */
1746 r
= FLD_MOD(r
, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */
1747 r
= FLD_MOD(r
, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */
1749 dsi_write_reg(DSI_VC_CTRL(channel
), r
);
1751 dsi
.vc
[channel
].mode
= DSI_VC_MODE_L4
;
1754 static int dsi_vc_config_l4(int channel
)
1756 if (dsi
.vc
[channel
].mode
== DSI_VC_MODE_L4
)
1759 DSSDBGF("%d", channel
);
1761 dsi_vc_enable(channel
, 0);
1764 if (wait_for_bit_change(DSI_VC_CTRL(channel
), 15, 0) != 0) {
1765 DSSERR("vc(%d) busy when trying to config for L4\n", channel
);
1769 REG_FLD_MOD(DSI_VC_CTRL(channel
), 0, 1, 1); /* SOURCE, 0 = L4 */
1771 dsi_vc_enable(channel
, 1);
1773 dsi
.vc
[channel
].mode
= DSI_VC_MODE_L4
;
1778 static int dsi_vc_config_vp(int channel
)
1780 if (dsi
.vc
[channel
].mode
== DSI_VC_MODE_VP
)
1783 DSSDBGF("%d", channel
);
1785 dsi_vc_enable(channel
, 0);
1788 if (wait_for_bit_change(DSI_VC_CTRL(channel
), 15, 0) != 0) {
1789 DSSERR("vc(%d) busy when trying to config for VP\n", channel
);
1793 REG_FLD_MOD(DSI_VC_CTRL(channel
), 1, 1, 1); /* SOURCE, 1 = video port */
1795 dsi_vc_enable(channel
, 1);
1797 dsi
.vc
[channel
].mode
= DSI_VC_MODE_VP
;
1803 void omapdss_dsi_vc_enable_hs(int channel
, bool enable
)
1805 DSSDBG("dsi_vc_enable_hs(%d, %d)\n", channel
, enable
);
1807 WARN_ON(!dsi_bus_is_locked());
1809 dsi_vc_enable(channel
, 0);
1812 REG_FLD_MOD(DSI_VC_CTRL(channel
), enable
, 9, 9);
1814 dsi_vc_enable(channel
, 1);
1817 dsi_force_tx_stop_mode_io();
1819 EXPORT_SYMBOL(omapdss_dsi_vc_enable_hs
);
1821 static void dsi_vc_flush_long_data(int channel
)
1823 while (REG_GET(DSI_VC_CTRL(channel
), 20, 20)) {
1825 val
= dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel
));
1826 DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n",
1830 (val
>> 24) & 0xff);
1834 static void dsi_show_rx_ack_with_err(u16 err
)
1836 DSSERR("\tACK with ERROR (%#x):\n", err
);
1838 DSSERR("\t\tSoT Error\n");
1840 DSSERR("\t\tSoT Sync Error\n");
1842 DSSERR("\t\tEoT Sync Error\n");
1844 DSSERR("\t\tEscape Mode Entry Command Error\n");
1846 DSSERR("\t\tLP Transmit Sync Error\n");
1848 DSSERR("\t\tHS Receive Timeout Error\n");
1850 DSSERR("\t\tFalse Control Error\n");
1852 DSSERR("\t\t(reserved7)\n");
1854 DSSERR("\t\tECC Error, single-bit (corrected)\n");
1856 DSSERR("\t\tECC Error, multi-bit (not corrected)\n");
1857 if (err
& (1 << 10))
1858 DSSERR("\t\tChecksum Error\n");
1859 if (err
& (1 << 11))
1860 DSSERR("\t\tData type not recognized\n");
1861 if (err
& (1 << 12))
1862 DSSERR("\t\tInvalid VC ID\n");
1863 if (err
& (1 << 13))
1864 DSSERR("\t\tInvalid Transmission Length\n");
1865 if (err
& (1 << 14))
1866 DSSERR("\t\t(reserved14)\n");
1867 if (err
& (1 << 15))
1868 DSSERR("\t\tDSI Protocol Violation\n");
1871 static u16
dsi_vc_flush_receive_data(int channel
)
1873 /* RX_FIFO_NOT_EMPTY */
1874 while (REG_GET(DSI_VC_CTRL(channel
), 20, 20)) {
1877 val
= dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel
));
1878 DSSERR("\trawval %#08x\n", val
);
1879 dt
= FLD_GET(val
, 5, 0);
1880 if (dt
== DSI_DT_RX_ACK_WITH_ERR
) {
1881 u16 err
= FLD_GET(val
, 23, 8);
1882 dsi_show_rx_ack_with_err(err
);
1883 } else if (dt
== DSI_DT_RX_SHORT_READ_1
) {
1884 DSSERR("\tDCS short response, 1 byte: %#x\n",
1885 FLD_GET(val
, 23, 8));
1886 } else if (dt
== DSI_DT_RX_SHORT_READ_2
) {
1887 DSSERR("\tDCS short response, 2 byte: %#x\n",
1888 FLD_GET(val
, 23, 8));
1889 } else if (dt
== DSI_DT_RX_DCS_LONG_READ
) {
1890 DSSERR("\tDCS long response, len %d\n",
1891 FLD_GET(val
, 23, 8));
1892 dsi_vc_flush_long_data(channel
);
1894 DSSERR("\tunknown datatype 0x%02x\n", dt
);
1900 static int dsi_vc_send_bta(int channel
)
1902 if (dsi
.debug_write
|| dsi
.debug_read
)
1903 DSSDBG("dsi_vc_send_bta %d\n", channel
);
1905 WARN_ON(!dsi_bus_is_locked());
1907 if (REG_GET(DSI_VC_CTRL(channel
), 20, 20)) { /* RX_FIFO_NOT_EMPTY */
1908 DSSERR("rx fifo not empty when sending BTA, dumping data:\n");
1909 dsi_vc_flush_receive_data(channel
);
1912 REG_FLD_MOD(DSI_VC_CTRL(channel
), 1, 6, 6); /* BTA_EN */
1917 int dsi_vc_send_bta_sync(int channel
)
1922 INIT_COMPLETION(dsi
.bta_completion
);
1924 dsi_vc_enable_bta_irq(channel
);
1926 r
= dsi_vc_send_bta(channel
);
1930 if (wait_for_completion_timeout(&dsi
.bta_completion
,
1931 msecs_to_jiffies(500)) == 0) {
1932 DSSERR("Failed to receive BTA\n");
1937 err
= dsi_get_errors();
1939 DSSERR("Error while sending BTA: %x\n", err
);
1944 dsi_vc_disable_bta_irq(channel
);
1948 EXPORT_SYMBOL(dsi_vc_send_bta_sync
);
1950 static inline void dsi_vc_write_long_header(int channel
, u8 data_type
,
1956 WARN_ON(!dsi_bus_is_locked());
1958 data_id
= data_type
| channel
<< 6;
1960 val
= FLD_VAL(data_id
, 7, 0) | FLD_VAL(len
, 23, 8) |
1961 FLD_VAL(ecc
, 31, 24);
1963 dsi_write_reg(DSI_VC_LONG_PACKET_HEADER(channel
), val
);
1966 static inline void dsi_vc_write_long_payload(int channel
,
1967 u8 b1
, u8 b2
, u8 b3
, u8 b4
)
1971 val
= b4
<< 24 | b3
<< 16 | b2
<< 8 | b1
<< 0;
1973 /* DSSDBG("\twriting %02x, %02x, %02x, %02x (%#010x)\n",
1974 b1, b2, b3, b4, val); */
1976 dsi_write_reg(DSI_VC_LONG_PACKET_PAYLOAD(channel
), val
);
1979 static int dsi_vc_send_long(int channel
, u8 data_type
, u8
*data
, u16 len
,
1988 if (dsi
.debug_write
)
1989 DSSDBG("dsi_vc_send_long, %d bytes\n", len
);
1992 if (dsi
.vc
[channel
].fifo_size
* 32 * 4 < len
+ 4) {
1993 DSSERR("unable to send long packet: packet too long.\n");
1997 dsi_vc_config_l4(channel
);
1999 dsi_vc_write_long_header(channel
, data_type
, len
, ecc
);
2002 for (i
= 0; i
< len
>> 2; i
++) {
2003 if (dsi
.debug_write
)
2004 DSSDBG("\tsending full packet %d\n", i
);
2011 dsi_vc_write_long_payload(channel
, b1
, b2
, b3
, b4
);
2016 b1
= 0; b2
= 0; b3
= 0;
2018 if (dsi
.debug_write
)
2019 DSSDBG("\tsending remainder bytes %d\n", i
);
2036 dsi_vc_write_long_payload(channel
, b1
, b2
, b3
, 0);
2042 static int dsi_vc_send_short(int channel
, u8 data_type
, u16 data
, u8 ecc
)
2047 WARN_ON(!dsi_bus_is_locked());
2049 if (dsi
.debug_write
)
2050 DSSDBG("dsi_vc_send_short(ch%d, dt %#x, b1 %#x, b2 %#x)\n",
2052 data_type
, data
& 0xff, (data
>> 8) & 0xff);
2054 dsi_vc_config_l4(channel
);
2056 if (FLD_GET(dsi_read_reg(DSI_VC_CTRL(channel
)), 16, 16)) {
2057 DSSERR("ERROR FIFO FULL, aborting transfer\n");
2061 data_id
= data_type
| channel
<< 6;
2063 r
= (data_id
<< 0) | (data
<< 8) | (ecc
<< 24);
2065 dsi_write_reg(DSI_VC_SHORT_PACKET_HEADER(channel
), r
);
2070 int dsi_vc_send_null(int channel
)
2072 u8 nullpkg
[] = {0, 0, 0, 0};
2073 return dsi_vc_send_long(channel
, DSI_DT_NULL_PACKET
, nullpkg
, 4, 0);
2075 EXPORT_SYMBOL(dsi_vc_send_null
);
2077 int dsi_vc_dcs_write_nosync(int channel
, u8
*data
, int len
)
2084 r
= dsi_vc_send_short(channel
, DSI_DT_DCS_SHORT_WRITE_0
,
2086 } else if (len
== 2) {
2087 r
= dsi_vc_send_short(channel
, DSI_DT_DCS_SHORT_WRITE_1
,
2088 data
[0] | (data
[1] << 8), 0);
2090 /* 0x39 = DCS Long Write */
2091 r
= dsi_vc_send_long(channel
, DSI_DT_DCS_LONG_WRITE
,
2097 EXPORT_SYMBOL(dsi_vc_dcs_write_nosync
);
2099 int dsi_vc_dcs_write(int channel
, u8
*data
, int len
)
2103 r
= dsi_vc_dcs_write_nosync(channel
, data
, len
);
2107 r
= dsi_vc_send_bta_sync(channel
);
2111 if (REG_GET(DSI_VC_CTRL(channel
), 20, 20)) { /* RX_FIFO_NOT_EMPTY */
2112 DSSERR("rx fifo not empty after write, dumping data:\n");
2113 dsi_vc_flush_receive_data(channel
);
2120 DSSERR("dsi_vc_dcs_write(ch %d, cmd 0x%02x, len %d) failed\n",
2121 channel
, data
[0], len
);
2124 EXPORT_SYMBOL(dsi_vc_dcs_write
);
2126 int dsi_vc_dcs_write_0(int channel
, u8 dcs_cmd
)
2128 return dsi_vc_dcs_write(channel
, &dcs_cmd
, 1);
2130 EXPORT_SYMBOL(dsi_vc_dcs_write_0
);
2132 int dsi_vc_dcs_write_1(int channel
, u8 dcs_cmd
, u8 param
)
2137 return dsi_vc_dcs_write(channel
, buf
, 2);
2139 EXPORT_SYMBOL(dsi_vc_dcs_write_1
);
2141 int dsi_vc_dcs_read(int channel
, u8 dcs_cmd
, u8
*buf
, int buflen
)
2148 DSSDBG("dsi_vc_dcs_read(ch%d, dcs_cmd %x)\n", channel
, dcs_cmd
);
2150 r
= dsi_vc_send_short(channel
, DSI_DT_DCS_READ
, dcs_cmd
, 0);
2154 r
= dsi_vc_send_bta_sync(channel
);
2158 /* RX_FIFO_NOT_EMPTY */
2159 if (REG_GET(DSI_VC_CTRL(channel
), 20, 20) == 0) {
2160 DSSERR("RX fifo empty when trying to read.\n");
2165 val
= dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel
));
2167 DSSDBG("\theader: %08x\n", val
);
2168 dt
= FLD_GET(val
, 5, 0);
2169 if (dt
== DSI_DT_RX_ACK_WITH_ERR
) {
2170 u16 err
= FLD_GET(val
, 23, 8);
2171 dsi_show_rx_ack_with_err(err
);
2175 } else if (dt
== DSI_DT_RX_SHORT_READ_1
) {
2176 u8 data
= FLD_GET(val
, 15, 8);
2178 DSSDBG("\tDCS short response, 1 byte: %02x\n", data
);
2188 } else if (dt
== DSI_DT_RX_SHORT_READ_2
) {
2189 u16 data
= FLD_GET(val
, 23, 8);
2191 DSSDBG("\tDCS short response, 2 byte: %04x\n", data
);
2198 buf
[0] = data
& 0xff;
2199 buf
[1] = (data
>> 8) & 0xff;
2202 } else if (dt
== DSI_DT_RX_DCS_LONG_READ
) {
2204 int len
= FLD_GET(val
, 23, 8);
2206 DSSDBG("\tDCS long response, len %d\n", len
);
2213 /* two byte checksum ends the packet, not included in len */
2214 for (w
= 0; w
< len
+ 2;) {
2216 val
= dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel
));
2218 DSSDBG("\t\t%02x %02x %02x %02x\n",
2222 (val
>> 24) & 0xff);
2224 for (b
= 0; b
< 4; ++b
) {
2226 buf
[w
] = (val
>> (b
* 8)) & 0xff;
2227 /* we discard the 2 byte checksum */
2234 DSSERR("\tunknown datatype 0x%02x\n", dt
);
2241 DSSERR("dsi_vc_dcs_read(ch %d, cmd 0x%02x) failed\n",
2246 EXPORT_SYMBOL(dsi_vc_dcs_read
);
2248 int dsi_vc_dcs_read_1(int channel
, u8 dcs_cmd
, u8
*data
)
2252 r
= dsi_vc_dcs_read(channel
, dcs_cmd
, data
, 1);
2262 EXPORT_SYMBOL(dsi_vc_dcs_read_1
);
2264 int dsi_vc_dcs_read_2(int channel
, u8 dcs_cmd
, u8
*data1
, u8
*data2
)
2269 r
= dsi_vc_dcs_read(channel
, dcs_cmd
, buf
, 2);
2282 EXPORT_SYMBOL(dsi_vc_dcs_read_2
);
2284 int dsi_vc_set_max_rx_packet_size(int channel
, u16 len
)
2286 return dsi_vc_send_short(channel
, DSI_DT_SET_MAX_RET_PKG_SIZE
,
2289 EXPORT_SYMBOL(dsi_vc_set_max_rx_packet_size
);
2291 static void dsi_set_lp_rx_timeout(unsigned ticks
, bool x4
, bool x16
)
2294 unsigned long total_ticks
;
2297 BUG_ON(ticks
> 0x1fff);
2299 /* ticks in DSI_FCK */
2300 fck
= dsi_fclk_rate();
2302 r
= dsi_read_reg(DSI_TIMING2
);
2303 r
= FLD_MOD(r
, 1, 15, 15); /* LP_RX_TO */
2304 r
= FLD_MOD(r
, x16
? 1 : 0, 14, 14); /* LP_RX_TO_X16 */
2305 r
= FLD_MOD(r
, x4
? 1 : 0, 13, 13); /* LP_RX_TO_X4 */
2306 r
= FLD_MOD(r
, ticks
, 12, 0); /* LP_RX_COUNTER */
2307 dsi_write_reg(DSI_TIMING2
, r
);
2309 total_ticks
= ticks
* (x16
? 16 : 1) * (x4
? 4 : 1);
2311 DSSDBG("LP_RX_TO %lu ticks (%#x%s%s) = %lu ns\n",
2313 ticks
, x4
? " x4" : "", x16
? " x16" : "",
2314 (total_ticks
* 1000) / (fck
/ 1000 / 1000));
2317 static void dsi_set_ta_timeout(unsigned ticks
, bool x8
, bool x16
)
2320 unsigned long total_ticks
;
2323 BUG_ON(ticks
> 0x1fff);
2325 /* ticks in DSI_FCK */
2326 fck
= dsi_fclk_rate();
2328 r
= dsi_read_reg(DSI_TIMING1
);
2329 r
= FLD_MOD(r
, 1, 31, 31); /* TA_TO */
2330 r
= FLD_MOD(r
, x16
? 1 : 0, 30, 30); /* TA_TO_X16 */
2331 r
= FLD_MOD(r
, x8
? 1 : 0, 29, 29); /* TA_TO_X8 */
2332 r
= FLD_MOD(r
, ticks
, 28, 16); /* TA_TO_COUNTER */
2333 dsi_write_reg(DSI_TIMING1
, r
);
2335 total_ticks
= ticks
* (x16
? 16 : 1) * (x8
? 8 : 1);
2337 DSSDBG("TA_TO %lu ticks (%#x%s%s) = %lu ns\n",
2339 ticks
, x8
? " x8" : "", x16
? " x16" : "",
2340 (total_ticks
* 1000) / (fck
/ 1000 / 1000));
2343 static void dsi_set_stop_state_counter(unsigned ticks
, bool x4
, bool x16
)
2346 unsigned long total_ticks
;
2349 BUG_ON(ticks
> 0x1fff);
2351 /* ticks in DSI_FCK */
2352 fck
= dsi_fclk_rate();
2354 r
= dsi_read_reg(DSI_TIMING1
);
2355 r
= FLD_MOD(r
, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
2356 r
= FLD_MOD(r
, x16
? 1 : 0, 14, 14); /* STOP_STATE_X16_IO */
2357 r
= FLD_MOD(r
, x4
? 1 : 0, 13, 13); /* STOP_STATE_X4_IO */
2358 r
= FLD_MOD(r
, ticks
, 12, 0); /* STOP_STATE_COUNTER_IO */
2359 dsi_write_reg(DSI_TIMING1
, r
);
2361 total_ticks
= ticks
* (x16
? 16 : 1) * (x4
? 4 : 1);
2363 DSSDBG("STOP_STATE_COUNTER %lu ticks (%#x%s%s) = %lu ns\n",
2365 ticks
, x4
? " x4" : "", x16
? " x16" : "",
2366 (total_ticks
* 1000) / (fck
/ 1000 / 1000));
2369 static void dsi_set_hs_tx_timeout(unsigned ticks
, bool x4
, bool x16
)
2372 unsigned long total_ticks
;
2375 BUG_ON(ticks
> 0x1fff);
2377 /* ticks in TxByteClkHS */
2378 fck
= dsi_get_txbyteclkhs();
2380 r
= dsi_read_reg(DSI_TIMING2
);
2381 r
= FLD_MOD(r
, 1, 31, 31); /* HS_TX_TO */
2382 r
= FLD_MOD(r
, x16
? 1 : 0, 30, 30); /* HS_TX_TO_X16 */
2383 r
= FLD_MOD(r
, x4
? 1 : 0, 29, 29); /* HS_TX_TO_X8 (4 really) */
2384 r
= FLD_MOD(r
, ticks
, 28, 16); /* HS_TX_TO_COUNTER */
2385 dsi_write_reg(DSI_TIMING2
, r
);
2387 total_ticks
= ticks
* (x16
? 16 : 1) * (x4
? 4 : 1);
2389 DSSDBG("HS_TX_TO %lu ticks (%#x%s%s) = %lu ns\n",
2391 ticks
, x4
? " x4" : "", x16
? " x16" : "",
2392 (total_ticks
* 1000) / (fck
/ 1000 / 1000));
2394 static int dsi_proto_config(struct omap_dss_device
*dssdev
)
2399 dsi_config_tx_fifo(DSI_FIFO_SIZE_32
,
2404 dsi_config_rx_fifo(DSI_FIFO_SIZE_32
,
2409 dsi_set_stop_state_counter(0x1000, false, false);
2410 dsi_set_ta_timeout(0x1fff, true, true);
2411 dsi_set_lp_rx_timeout(0x1fff, true, true);
2412 dsi_set_hs_tx_timeout(0x1fff, true, true);
2414 switch (dssdev
->ctrl
.pixel_size
) {
2428 r
= dsi_read_reg(DSI_CTRL
);
2429 r
= FLD_MOD(r
, 1, 1, 1); /* CS_RX_EN */
2430 r
= FLD_MOD(r
, 1, 2, 2); /* ECC_RX_EN */
2431 r
= FLD_MOD(r
, 1, 3, 3); /* TX_FIFO_ARBITRATION */
2432 r
= FLD_MOD(r
, 1, 4, 4); /* VP_CLK_RATIO, always 1, see errata*/
2433 r
= FLD_MOD(r
, buswidth
, 7, 6); /* VP_DATA_BUS_WIDTH */
2434 r
= FLD_MOD(r
, 0, 8, 8); /* VP_CLK_POL */
2435 r
= FLD_MOD(r
, 2, 13, 12); /* LINE_BUFFER, 2 lines */
2436 r
= FLD_MOD(r
, 1, 14, 14); /* TRIGGER_RESET_MODE */
2437 r
= FLD_MOD(r
, 1, 19, 19); /* EOT_ENABLE */
2438 r
= FLD_MOD(r
, 1, 24, 24); /* DCS_CMD_ENABLE */
2439 r
= FLD_MOD(r
, 0, 25, 25); /* DCS_CMD_CODE, 1=start, 0=continue */
2441 dsi_write_reg(DSI_CTRL
, r
);
2443 dsi_vc_initial_config(0);
2444 dsi_vc_initial_config(1);
2445 dsi_vc_initial_config(2);
2446 dsi_vc_initial_config(3);
2451 static void dsi_proto_timings(struct omap_dss_device
*dssdev
)
2453 unsigned tlpx
, tclk_zero
, tclk_prepare
, tclk_trail
;
2454 unsigned tclk_pre
, tclk_post
;
2455 unsigned ths_prepare
, ths_prepare_ths_zero
, ths_zero
;
2456 unsigned ths_trail
, ths_exit
;
2457 unsigned ddr_clk_pre
, ddr_clk_post
;
2458 unsigned enter_hs_mode_lat
, exit_hs_mode_lat
;
2462 r
= dsi_read_reg(DSI_DSIPHY_CFG0
);
2463 ths_prepare
= FLD_GET(r
, 31, 24);
2464 ths_prepare_ths_zero
= FLD_GET(r
, 23, 16);
2465 ths_zero
= ths_prepare_ths_zero
- ths_prepare
;
2466 ths_trail
= FLD_GET(r
, 15, 8);
2467 ths_exit
= FLD_GET(r
, 7, 0);
2469 r
= dsi_read_reg(DSI_DSIPHY_CFG1
);
2470 tlpx
= FLD_GET(r
, 22, 16) * 2;
2471 tclk_trail
= FLD_GET(r
, 15, 8);
2472 tclk_zero
= FLD_GET(r
, 7, 0);
2474 r
= dsi_read_reg(DSI_DSIPHY_CFG2
);
2475 tclk_prepare
= FLD_GET(r
, 7, 0);
2479 /* min 60ns + 52*UI */
2480 tclk_post
= ns2ddr(60) + 26;
2482 /* ths_eot is 2 for 2 datalanes and 4 for 1 datalane */
2483 if (dssdev
->phy
.dsi
.data1_lane
!= 0 &&
2484 dssdev
->phy
.dsi
.data2_lane
!= 0)
2489 ddr_clk_pre
= DIV_ROUND_UP(tclk_pre
+ tlpx
+ tclk_zero
+ tclk_prepare
,
2491 ddr_clk_post
= DIV_ROUND_UP(tclk_post
+ ths_trail
, 4) + ths_eot
;
2493 BUG_ON(ddr_clk_pre
== 0 || ddr_clk_pre
> 255);
2494 BUG_ON(ddr_clk_post
== 0 || ddr_clk_post
> 255);
2496 r
= dsi_read_reg(DSI_CLK_TIMING
);
2497 r
= FLD_MOD(r
, ddr_clk_pre
, 15, 8);
2498 r
= FLD_MOD(r
, ddr_clk_post
, 7, 0);
2499 dsi_write_reg(DSI_CLK_TIMING
, r
);
2501 DSSDBG("ddr_clk_pre %u, ddr_clk_post %u\n",
2505 enter_hs_mode_lat
= 1 + DIV_ROUND_UP(tlpx
, 4) +
2506 DIV_ROUND_UP(ths_prepare
, 4) +
2507 DIV_ROUND_UP(ths_zero
+ 3, 4);
2509 exit_hs_mode_lat
= DIV_ROUND_UP(ths_trail
+ ths_exit
, 4) + 1 + ths_eot
;
2511 r
= FLD_VAL(enter_hs_mode_lat
, 31, 16) |
2512 FLD_VAL(exit_hs_mode_lat
, 15, 0);
2513 dsi_write_reg(DSI_VM_TIMING7
, r
);
2515 DSSDBG("enter_hs_mode_lat %u, exit_hs_mode_lat %u\n",
2516 enter_hs_mode_lat
, exit_hs_mode_lat
);
2520 #define DSI_DECL_VARS \
2521 int __dsi_cb = 0; u32 __dsi_cv = 0;
2523 #define DSI_FLUSH(ch) \
2524 if (__dsi_cb > 0) { \
2525 /*DSSDBG("sending long packet %#010x\n", __dsi_cv);*/ \
2526 dsi_write_reg(DSI_VC_LONG_PACKET_PAYLOAD(ch), __dsi_cv); \
2527 __dsi_cb = __dsi_cv = 0; \
2530 #define DSI_PUSH(ch, data) \
2532 __dsi_cv |= (data) << (__dsi_cb * 8); \
2533 /*DSSDBG("cv = %#010x, cb = %d\n", __dsi_cv, __dsi_cb);*/ \
2534 if (++__dsi_cb > 3) \
2538 static int dsi_update_screen_l4(struct omap_dss_device
*dssdev
,
2539 int x
, int y
, int w
, int h
)
2541 /* Note: supports only 24bit colors in 32bit container */
2543 int fifo_stalls
= 0;
2544 int max_dsi_packet_size
;
2545 int max_data_per_packet
;
2546 int max_pixels_per_packet
;
2548 int bytespp
= dssdev
->ctrl
.pixel_size
/ 8;
2554 struct omap_overlay
*ovl
;
2558 DSSDBG("dsi_update_screen_l4 (%d,%d %dx%d)\n",
2561 ovl
= dssdev
->manager
->overlays
[0];
2563 if (ovl
->info
.color_mode
!= OMAP_DSS_COLOR_RGB24U
)
2566 if (dssdev
->ctrl
.pixel_size
!= 24)
2569 scr_width
= ovl
->info
.screen_width
;
2570 data
= ovl
->info
.vaddr
;
2572 start_offset
= scr_width
* y
+ x
;
2573 horiz_inc
= scr_width
- w
;
2576 /* We need header(4) + DCSCMD(1) + pixels(numpix*bytespp) bytes
2579 /* When using CPU, max long packet size is TX buffer size */
2580 max_dsi_packet_size
= dsi
.vc
[0].fifo_size
* 32 * 4;
2582 /* we seem to get better perf if we divide the tx fifo to half,
2583 and while the other half is being sent, we fill the other half
2584 max_dsi_packet_size /= 2; */
2586 max_data_per_packet
= max_dsi_packet_size
- 4 - 1;
2588 max_pixels_per_packet
= max_data_per_packet
/ bytespp
;
2590 DSSDBG("max_pixels_per_packet %d\n", max_pixels_per_packet
);
2592 pixels_left
= w
* h
;
2594 DSSDBG("total pixels %d\n", pixels_left
);
2596 data
+= start_offset
;
2598 while (pixels_left
> 0) {
2599 /* 0x2c = write_memory_start */
2600 /* 0x3c = write_memory_continue */
2601 u8 dcs_cmd
= first
? 0x2c : 0x3c;
2606 /* using fifo not empty */
2607 /* TX_FIFO_NOT_EMPTY */
2608 while (FLD_GET(dsi_read_reg(DSI_VC_CTRL(0)), 5, 5)) {
2610 if (fifo_stalls
> 0xfffff) {
2611 DSSERR("fifo stalls overflow, pixels left %d\n",
2618 pixels
= min(max_pixels_per_packet
, pixels_left
);
2620 pixels_left
-= pixels
;
2622 dsi_vc_write_long_header(0, DSI_DT_DCS_LONG_WRITE
,
2623 1 + pixels
* bytespp
, 0);
2625 DSI_PUSH(0, dcs_cmd
);
2627 while (pixels
-- > 0) {
2628 u32 pix
= __raw_readl(data
++);
2630 DSI_PUSH(0, (pix
>> 16) & 0xff);
2631 DSI_PUSH(0, (pix
>> 8) & 0xff);
2632 DSI_PUSH(0, (pix
>> 0) & 0xff);
2635 if (current_x
== x
+w
) {
2647 static void dsi_update_screen_dispc(struct omap_dss_device
*dssdev
,
2648 u16 x
, u16 y
, u16 w
, u16 h
)
2654 unsigned packet_payload
;
2655 unsigned packet_len
;
2658 const unsigned channel
= dsi
.update_channel
;
2659 /* line buffer is 1024 x 24bits */
2660 const unsigned line_buf_size
= 1023 * 3;
2662 DSSDBG("dsi_update_screen_dispc(%d,%d %dx%d)\n",
2665 dsi_vc_config_vp(channel
);
2667 bytespp
= dssdev
->ctrl
.pixel_size
/ 8;
2668 bytespl
= w
* bytespp
;
2669 bytespf
= bytespl
* h
;
2671 /* NOTE: packet_payload has to be equal to N * bytespl, where N is
2672 * number of lines in a packet. See errata about VP_CLK_RATIO */
2674 if (bytespf
< line_buf_size
)
2675 packet_payload
= bytespf
;
2677 packet_payload
= (line_buf_size
) / bytespl
* bytespl
;
2679 packet_len
= packet_payload
+ 1; /* 1 byte for DCS cmd */
2680 total_len
= (bytespf
/ packet_payload
) * packet_len
;
2682 if (bytespf
% packet_payload
)
2683 total_len
+= (bytespf
% packet_payload
) + 1;
2685 l
= FLD_VAL(total_len
, 23, 0); /* TE_SIZE */
2686 dsi_write_reg(DSI_VC_TE(channel
), l
);
2688 dsi_vc_write_long_header(channel
, DSI_DT_DCS_LONG_WRITE
, packet_len
, 0);
2691 l
= FLD_MOD(l
, 1, 30, 30); /* TE_EN */
2693 l
= FLD_MOD(l
, 1, 31, 31); /* TE_START */
2694 dsi_write_reg(DSI_VC_TE(channel
), l
);
2696 /* We put SIDLEMODE to no-idle for the duration of the transfer,
2697 * because DSS interrupts are not capable of waking up the CPU and the
2698 * framedone interrupt could be delayed for quite a long time. I think
2699 * the same goes for any DSS interrupts, but for some reason I have not
2700 * seen the problem anywhere else than here.
2702 dispc_disable_sidle();
2704 dsi_perf_mark_start();
2706 r
= queue_delayed_work(dsi
.workqueue
, &dsi
.framedone_timeout_work
,
2707 msecs_to_jiffies(250));
2710 dss_start_update(dssdev
);
2712 if (dsi
.te_enabled
) {
2713 /* disable LP_RX_TO, so that we can receive TE. Time to wait
2714 * for TE is longer than the timer allows */
2715 REG_FLD_MOD(DSI_TIMING2
, 0, 15, 15); /* LP_RX_TO */
2717 dsi_vc_send_bta(channel
);
2719 #ifdef DSI_CATCH_MISSING_TE
2720 mod_timer(&dsi
.te_timer
, jiffies
+ msecs_to_jiffies(250));
2725 #ifdef DSI_CATCH_MISSING_TE
2726 static void dsi_te_timeout(unsigned long arg
)
2728 DSSERR("TE not received for 250ms!\n");
2732 static void dsi_handle_framedone(int error
)
2734 const int channel
= dsi
.update_channel
;
2736 cancel_delayed_work(&dsi
.framedone_timeout_work
);
2738 dsi_vc_disable_bta_irq(channel
);
2740 /* SIDLEMODE back to smart-idle */
2741 dispc_enable_sidle();
2743 dsi
.bta_callback
= NULL
;
2745 if (dsi
.te_enabled
) {
2746 /* enable LP_RX_TO again after the TE */
2747 REG_FLD_MOD(DSI_TIMING2
, 1, 15, 15); /* LP_RX_TO */
2750 /* RX_FIFO_NOT_EMPTY */
2751 if (REG_GET(DSI_VC_CTRL(channel
), 20, 20)) {
2752 DSSERR("Received error during frame transfer:\n");
2753 dsi_vc_flush_receive_data(channel
);
2758 dsi
.framedone_callback(error
, dsi
.framedone_data
);
2761 dsi_perf_show("DISPC");
2764 static void dsi_framedone_timeout_work_callback(struct work_struct
*work
)
2767 DSSERR("Framedone not received for 250ms!\n");
2769 dsi_handle_framedone(-ETIMEDOUT
);
2772 static void dsi_framedone_bta_callback(void)
2774 dsi_handle_framedone(0);
2776 #ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
2777 dispc_fake_vsync_irq();
2781 static void dsi_framedone_irq_callback(void *data
, u32 mask
)
2783 const int channel
= dsi
.update_channel
;
2786 /* Note: We get FRAMEDONE when DISPC has finished sending pixels and
2787 * turns itself off. However, DSI still has the pixels in its buffers,
2788 * and is sending the data.
2791 if (dsi
.te_enabled
) {
2792 /* enable LP_RX_TO again after the TE */
2793 REG_FLD_MOD(DSI_TIMING2
, 1, 15, 15); /* LP_RX_TO */
2796 /* Send BTA after the frame. We need this for the TE to work, as TE
2797 * trigger is only sent for BTAs without preceding packet. Thus we need
2798 * to BTA after the pixel packets so that next BTA will cause TE
2801 * This is not needed when TE is not in use, but we do it anyway to
2802 * make sure that the transfer has been completed. It would be more
2803 * optimal, but more complex, to wait only just before starting next
2806 * Also, as there's no interrupt telling when the transfer has been
2807 * done and the channel could be reconfigured, the only way is to
2808 * busyloop until TE_SIZE is zero. With BTA we can do this
2812 dsi
.bta_callback
= dsi_framedone_bta_callback
;
2816 dsi_vc_enable_bta_irq(channel
);
2818 r
= dsi_vc_send_bta(channel
);
2820 DSSERR("BTA after framedone failed\n");
2821 dsi_handle_framedone(-EIO
);
2825 int omap_dsi_prepare_update(struct omap_dss_device
*dssdev
,
2826 u16
*x
, u16
*y
, u16
*w
, u16
*h
,
2827 bool enlarge_update_area
)
2831 dssdev
->driver
->get_resolution(dssdev
, &dw
, &dh
);
2833 if (*x
> dw
|| *y
> dh
)
2845 if (*w
== 0 || *h
== 0)
2848 dsi_perf_mark_setup();
2850 if (dssdev
->manager
->caps
& OMAP_DSS_OVL_MGR_CAP_DISPC
) {
2851 dss_setup_partial_planes(dssdev
, x
, y
, w
, h
,
2852 enlarge_update_area
);
2853 dispc_set_lcd_size(*w
, *h
);
2858 EXPORT_SYMBOL(omap_dsi_prepare_update
);
2860 int omap_dsi_update(struct omap_dss_device
*dssdev
,
2862 u16 x
, u16 y
, u16 w
, u16 h
,
2863 void (*callback
)(int, void *), void *data
)
2865 dsi
.update_channel
= channel
;
2867 /* OMAP DSS cannot send updates of odd widths.
2868 * omap_dsi_prepare_update() makes the widths even, but add a BUG_ON
2869 * here to make sure we catch erroneous updates. Otherwise we'll only
2870 * see rather obscure HW error happening, as DSS halts. */
2873 if (dssdev
->manager
->caps
& OMAP_DSS_OVL_MGR_CAP_DISPC
) {
2874 dsi
.framedone_callback
= callback
;
2875 dsi
.framedone_data
= data
;
2877 dsi
.update_region
.x
= x
;
2878 dsi
.update_region
.y
= y
;
2879 dsi
.update_region
.w
= w
;
2880 dsi
.update_region
.h
= h
;
2881 dsi
.update_region
.device
= dssdev
;
2883 dsi_update_screen_dispc(dssdev
, x
, y
, w
, h
);
2887 r
= dsi_update_screen_l4(dssdev
, x
, y
, w
, h
);
2891 dsi_perf_show("L4");
2897 EXPORT_SYMBOL(omap_dsi_update
);
2901 static int dsi_display_init_dispc(struct omap_dss_device
*dssdev
)
2905 r
= omap_dispc_register_isr(dsi_framedone_irq_callback
, NULL
,
2906 DISPC_IRQ_FRAMEDONE
);
2908 DSSERR("can't get FRAMEDONE irq\n");
2912 dispc_set_lcd_display_type(OMAP_DSS_LCD_DISPLAY_TFT
);
2914 dispc_set_parallel_interface_mode(OMAP_DSS_PARALLELMODE_DSI
);
2915 dispc_enable_fifohandcheck(1);
2917 dispc_set_tft_data_lines(dssdev
->ctrl
.pixel_size
);
2920 struct omap_video_timings timings
= {
2929 dispc_set_lcd_timings(&timings
);
2935 static void dsi_display_uninit_dispc(struct omap_dss_device
*dssdev
)
2937 omap_dispc_unregister_isr(dsi_framedone_irq_callback
, NULL
,
2938 DISPC_IRQ_FRAMEDONE
);
2941 static int dsi_configure_dsi_clocks(struct omap_dss_device
*dssdev
)
2943 struct dsi_clock_info cinfo
;
2946 /* we always use DSS2_FCK as input clock */
2947 cinfo
.use_dss2_fck
= true;
2948 cinfo
.regn
= dssdev
->phy
.dsi
.div
.regn
;
2949 cinfo
.regm
= dssdev
->phy
.dsi
.div
.regm
;
2950 cinfo
.regm3
= dssdev
->phy
.dsi
.div
.regm3
;
2951 cinfo
.regm4
= dssdev
->phy
.dsi
.div
.regm4
;
2952 r
= dsi_calc_clock_rates(&cinfo
);
2954 DSSERR("Failed to calc dsi clocks\n");
2958 r
= dsi_pll_set_clock_div(&cinfo
);
2960 DSSERR("Failed to set dsi clocks\n");
2967 static int dsi_configure_dispc_clocks(struct omap_dss_device
*dssdev
)
2969 struct dispc_clock_info dispc_cinfo
;
2971 unsigned long long fck
;
2973 fck
= dsi_get_dsi1_pll_rate();
2975 dispc_cinfo
.lck_div
= dssdev
->phy
.dsi
.div
.lck_div
;
2976 dispc_cinfo
.pck_div
= dssdev
->phy
.dsi
.div
.pck_div
;
2978 r
= dispc_calc_clock_rates(fck
, &dispc_cinfo
);
2980 DSSERR("Failed to calc dispc clocks\n");
2984 r
= dispc_set_clock_div(&dispc_cinfo
);
2986 DSSERR("Failed to set dispc clocks\n");
2993 static int dsi_display_init_dsi(struct omap_dss_device
*dssdev
)
2997 _dsi_print_reset_status();
2999 r
= dsi_pll_init(dssdev
, true, true);
3003 r
= dsi_configure_dsi_clocks(dssdev
);
3007 dss_select_dispc_clk_source(DSS_SRC_DSI1_PLL_FCLK
);
3008 dss_select_dsi_clk_source(DSS_SRC_DSI2_PLL_FCLK
);
3012 r
= dsi_configure_dispc_clocks(dssdev
);
3016 r
= dsi_complexio_init(dssdev
);
3020 _dsi_print_reset_status();
3022 dsi_proto_timings(dssdev
);
3023 dsi_set_lp_clk_divisor(dssdev
);
3026 _dsi_print_reset_status();
3028 r
= dsi_proto_config(dssdev
);
3032 /* enable interface */
3033 dsi_vc_enable(0, 1);
3034 dsi_vc_enable(1, 1);
3035 dsi_vc_enable(2, 1);
3036 dsi_vc_enable(3, 1);
3038 dsi_force_tx_stop_mode_io();
3042 dsi_complexio_uninit();
3044 dss_select_dispc_clk_source(DSS_SRC_DSS1_ALWON_FCLK
);
3045 dss_select_dsi_clk_source(DSS_SRC_DSS1_ALWON_FCLK
);
3052 static void dsi_display_uninit_dsi(struct omap_dss_device
*dssdev
)
3054 /* disable interface */
3056 dsi_vc_enable(0, 0);
3057 dsi_vc_enable(1, 0);
3058 dsi_vc_enable(2, 0);
3059 dsi_vc_enable(3, 0);
3061 dss_select_dispc_clk_source(DSS_SRC_DSS1_ALWON_FCLK
);
3062 dss_select_dsi_clk_source(DSS_SRC_DSS1_ALWON_FCLK
);
3063 dsi_complexio_uninit();
3067 static int dsi_core_init(void)
3070 REG_FLD_MOD(DSI_SYSCONFIG
, 1, 0, 0);
3073 REG_FLD_MOD(DSI_SYSCONFIG
, 1, 2, 2);
3075 /* SIDLEMODE smart-idle */
3076 REG_FLD_MOD(DSI_SYSCONFIG
, 2, 4, 3);
3078 _dsi_initialize_irq();
3083 int omapdss_dsi_display_enable(struct omap_dss_device
*dssdev
)
3087 DSSDBG("dsi_display_enable\n");
3089 WARN_ON(!dsi_bus_is_locked());
3091 mutex_lock(&dsi
.lock
);
3093 r
= omap_dss_start_device(dssdev
);
3095 DSSERR("failed to start device\n");
3100 dsi_enable_pll_clock(1);
3108 r
= dsi_display_init_dispc(dssdev
);
3112 r
= dsi_display_init_dsi(dssdev
);
3116 mutex_unlock(&dsi
.lock
);
3121 dsi_display_uninit_dispc(dssdev
);
3124 dsi_enable_pll_clock(0);
3125 omap_dss_stop_device(dssdev
);
3127 mutex_unlock(&dsi
.lock
);
3128 DSSDBG("dsi_display_enable FAILED\n");
3131 EXPORT_SYMBOL(omapdss_dsi_display_enable
);
3133 void omapdss_dsi_display_disable(struct omap_dss_device
*dssdev
)
3135 DSSDBG("dsi_display_disable\n");
3137 WARN_ON(!dsi_bus_is_locked());
3139 mutex_lock(&dsi
.lock
);
3141 dsi_display_uninit_dispc(dssdev
);
3143 dsi_display_uninit_dsi(dssdev
);
3146 dsi_enable_pll_clock(0);
3148 omap_dss_stop_device(dssdev
);
3150 mutex_unlock(&dsi
.lock
);
3152 EXPORT_SYMBOL(omapdss_dsi_display_disable
);
3154 int omapdss_dsi_enable_te(struct omap_dss_device
*dssdev
, bool enable
)
3156 dsi
.te_enabled
= enable
;
3159 EXPORT_SYMBOL(omapdss_dsi_enable_te
);
3161 void dsi_get_overlay_fifo_thresholds(enum omap_plane plane
,
3162 u32 fifo_size
, enum omap_burst_size
*burst_size
,
3163 u32
*fifo_low
, u32
*fifo_high
)
3165 unsigned burst_size_bytes
;
3167 *burst_size
= OMAP_DSS_BURST_16x32
;
3168 burst_size_bytes
= 16 * 32 / 8;
3170 *fifo_high
= fifo_size
- burst_size_bytes
;
3171 *fifo_low
= fifo_size
- burst_size_bytes
* 2;
3174 int dsi_init_display(struct omap_dss_device
*dssdev
)
3176 DSSDBG("DSI init\n");
3178 dssdev
->caps
= OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE
|
3179 OMAP_DSS_DISPLAY_CAP_TEAR_ELIM
;
3181 dsi
.vc
[0].dssdev
= dssdev
;
3182 dsi
.vc
[1].dssdev
= dssdev
;
3187 void dsi_wait_dsi1_pll_active(void)
3189 if (wait_for_bit_change(DSI_PLL_STATUS
, 7, 1) != 1)
3190 DSSERR("DSI1 PLL clock not active\n");
3193 void dsi_wait_dsi2_pll_active(void)
3195 if (wait_for_bit_change(DSI_PLL_STATUS
, 8, 1) != 1)
3196 DSSERR("DSI2 PLL clock not active\n");
3199 int dsi_init(struct platform_device
*pdev
)
3204 spin_lock_init(&dsi
.errors_lock
);
3207 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3208 spin_lock_init(&dsi
.irq_stats_lock
);
3209 dsi
.irq_stats
.last_reset
= jiffies
;
3212 init_completion(&dsi
.bta_completion
);
3214 mutex_init(&dsi
.lock
);
3215 sema_init(&dsi
.bus_lock
, 1);
3217 dsi
.workqueue
= create_singlethread_workqueue("dsi");
3218 if (dsi
.workqueue
== NULL
)
3221 INIT_DELAYED_WORK_DEFERRABLE(&dsi
.framedone_timeout_work
,
3222 dsi_framedone_timeout_work_callback
);
3224 #ifdef DSI_CATCH_MISSING_TE
3225 init_timer(&dsi
.te_timer
);
3226 dsi
.te_timer
.function
= dsi_te_timeout
;
3227 dsi
.te_timer
.data
= 0;
3229 dsi
.base
= ioremap(DSI_BASE
, DSI_SZ_REGS
);
3231 DSSERR("can't ioremap DSI\n");
3236 dsi
.vdds_dsi_reg
= dss_get_vdds_dsi();
3237 if (IS_ERR(dsi
.vdds_dsi_reg
)) {
3239 DSSERR("can't get VDDS_DSI regulator\n");
3240 r
= PTR_ERR(dsi
.vdds_dsi_reg
);
3246 rev
= dsi_read_reg(DSI_REVISION
);
3247 printk(KERN_INFO
"OMAP DSI rev %d.%d\n",
3248 FLD_GET(rev
, 7, 4), FLD_GET(rev
, 3, 0));
3256 destroy_workqueue(dsi
.workqueue
);
3264 destroy_workqueue(dsi
.workqueue
);
3266 DSSDBG("omap_dsi_exit\n");