4 * Linux framebuffer driver for Intel(R) 865G integrated graphics chips.
6 * Copyright © 2002, 2003 David Dawes <dawes@xfree86.org>
9 * This driver consists of two parts. The first part (intelfbdrv.c) provides
10 * the basic fbdev interfaces, is derived in part from the radeonfb and
11 * vesafb drivers, and is covered by the GPL. The second part (intelfbhw.c)
12 * provides the code to program the hardware. Most of it is derived from
13 * the i810/i830 XFree86 driver. The HW-specific code is covered here
14 * under a dual license (GPL and MIT/XFree86 license).
20 /* $DHD: intelfb/intelfbhw.c,v 1.9 2003/06/27 15:06:25 dawes Exp $ */
22 #include <linux/module.h>
23 #include <linux/kernel.h>
24 #include <linux/errno.h>
25 #include <linux/string.h>
27 #include <linux/delay.h>
29 #include <linux/ioport.h>
30 #include <linux/init.h>
31 #include <linux/pci.h>
32 #include <linux/vmalloc.h>
33 #include <linux/pagemap.h>
34 #include <linux/interrupt.h>
39 #include "intelfbhw.h"
42 int min_m
, max_m
, min_m1
, max_m1
;
43 int min_m2
, max_m2
, min_n
, max_n
;
44 int min_p
, max_p
, min_p1
, max_p1
;
45 int min_vco
, max_vco
, p_transition_clk
, ref_clk
;
46 int p_inc_lo
, p_inc_hi
;
53 static struct pll_min_max plls
[PLLS_MAX
] = {
57 930000, 1400000, 165000, 48000,
63 1400000, 2800000, 200000, 96000,
67 int intelfbhw_get_chipset(struct pci_dev
*pdev
, struct intelfb_info
*dinfo
)
73 switch (pdev
->device
) {
74 case PCI_DEVICE_ID_INTEL_830M
:
75 dinfo
->name
= "Intel(R) 830M";
76 dinfo
->chipset
= INTEL_830M
;
78 dinfo
->pll_index
= PLLS_I8xx
;
80 case PCI_DEVICE_ID_INTEL_845G
:
81 dinfo
->name
= "Intel(R) 845G";
82 dinfo
->chipset
= INTEL_845G
;
84 dinfo
->pll_index
= PLLS_I8xx
;
86 case PCI_DEVICE_ID_INTEL_854
:
88 dinfo
->name
= "Intel(R) 854";
89 dinfo
->chipset
= INTEL_854
;
91 case PCI_DEVICE_ID_INTEL_85XGM
:
94 dinfo
->pll_index
= PLLS_I8xx
;
95 pci_read_config_dword(pdev
, INTEL_85X_CAPID
, &tmp
);
96 switch ((tmp
>> INTEL_85X_VARIANT_SHIFT
) &
97 INTEL_85X_VARIANT_MASK
) {
98 case INTEL_VAR_855GME
:
99 dinfo
->name
= "Intel(R) 855GME";
100 dinfo
->chipset
= INTEL_855GME
;
102 case INTEL_VAR_855GM
:
103 dinfo
->name
= "Intel(R) 855GM";
104 dinfo
->chipset
= INTEL_855GM
;
106 case INTEL_VAR_852GME
:
107 dinfo
->name
= "Intel(R) 852GME";
108 dinfo
->chipset
= INTEL_852GME
;
110 case INTEL_VAR_852GM
:
111 dinfo
->name
= "Intel(R) 852GM";
112 dinfo
->chipset
= INTEL_852GM
;
115 dinfo
->name
= "Intel(R) 852GM/855GM";
116 dinfo
->chipset
= INTEL_85XGM
;
120 case PCI_DEVICE_ID_INTEL_865G
:
121 dinfo
->name
= "Intel(R) 865G";
122 dinfo
->chipset
= INTEL_865G
;
124 dinfo
->pll_index
= PLLS_I8xx
;
126 case PCI_DEVICE_ID_INTEL_915G
:
127 dinfo
->name
= "Intel(R) 915G";
128 dinfo
->chipset
= INTEL_915G
;
130 dinfo
->pll_index
= PLLS_I9xx
;
132 case PCI_DEVICE_ID_INTEL_915GM
:
133 dinfo
->name
= "Intel(R) 915GM";
134 dinfo
->chipset
= INTEL_915GM
;
136 dinfo
->pll_index
= PLLS_I9xx
;
138 case PCI_DEVICE_ID_INTEL_945G
:
139 dinfo
->name
= "Intel(R) 945G";
140 dinfo
->chipset
= INTEL_945G
;
142 dinfo
->pll_index
= PLLS_I9xx
;
144 case PCI_DEVICE_ID_INTEL_945GM
:
145 dinfo
->name
= "Intel(R) 945GM";
146 dinfo
->chipset
= INTEL_945GM
;
148 dinfo
->pll_index
= PLLS_I9xx
;
150 case PCI_DEVICE_ID_INTEL_945GME
:
151 dinfo
->name
= "Intel(R) 945GME";
152 dinfo
->chipset
= INTEL_945GME
;
154 dinfo
->pll_index
= PLLS_I9xx
;
156 case PCI_DEVICE_ID_INTEL_965G
:
157 dinfo
->name
= "Intel(R) 965G";
158 dinfo
->chipset
= INTEL_965G
;
160 dinfo
->pll_index
= PLLS_I9xx
;
162 case PCI_DEVICE_ID_INTEL_965GM
:
163 dinfo
->name
= "Intel(R) 965GM";
164 dinfo
->chipset
= INTEL_965GM
;
166 dinfo
->pll_index
= PLLS_I9xx
;
173 int intelfbhw_get_memory(struct pci_dev
*pdev
, int *aperture_size
,
176 struct pci_dev
*bridge_dev
;
180 if (!pdev
|| !aperture_size
|| !stolen_size
)
183 /* Find the bridge device. It is always 0:0.0 */
184 if (!(bridge_dev
= pci_get_bus_and_slot(0, PCI_DEVFN(0, 0)))) {
185 ERR_MSG("cannot find bridge device\n");
189 /* Get the fb aperture size and "stolen" memory amount. */
191 pci_read_config_word(bridge_dev
, INTEL_GMCH_CTRL
, &tmp
);
192 pci_dev_put(bridge_dev
);
194 switch (pdev
->device
) {
195 case PCI_DEVICE_ID_INTEL_915G
:
196 case PCI_DEVICE_ID_INTEL_915GM
:
197 case PCI_DEVICE_ID_INTEL_945G
:
198 case PCI_DEVICE_ID_INTEL_945GM
:
199 case PCI_DEVICE_ID_INTEL_945GME
:
200 case PCI_DEVICE_ID_INTEL_965G
:
201 case PCI_DEVICE_ID_INTEL_965GM
:
202 /* 915, 945 and 965 chipsets support a 256MB aperture.
203 Aperture size is determined by inspected the
204 base address of the aperture. */
205 if (pci_resource_start(pdev
, 2) & 0x08000000)
206 *aperture_size
= MB(128);
208 *aperture_size
= MB(256);
211 if ((tmp
& INTEL_GMCH_MEM_MASK
) == INTEL_GMCH_MEM_64M
)
212 *aperture_size
= MB(64);
214 *aperture_size
= MB(128);
218 /* Stolen memory size is reduced by the GTT and the popup.
219 GTT is 1K per MB of aperture size, and popup is 4K. */
220 stolen_overhead
= (*aperture_size
/ MB(1)) + 4;
221 switch(pdev
->device
) {
222 case PCI_DEVICE_ID_INTEL_830M
:
223 case PCI_DEVICE_ID_INTEL_845G
:
224 switch (tmp
& INTEL_830_GMCH_GMS_MASK
) {
225 case INTEL_830_GMCH_GMS_STOLEN_512
:
226 *stolen_size
= KB(512) - KB(stolen_overhead
);
228 case INTEL_830_GMCH_GMS_STOLEN_1024
:
229 *stolen_size
= MB(1) - KB(stolen_overhead
);
231 case INTEL_830_GMCH_GMS_STOLEN_8192
:
232 *stolen_size
= MB(8) - KB(stolen_overhead
);
234 case INTEL_830_GMCH_GMS_LOCAL
:
235 ERR_MSG("only local memory found\n");
237 case INTEL_830_GMCH_GMS_DISABLED
:
238 ERR_MSG("video memory is disabled\n");
241 ERR_MSG("unexpected GMCH_GMS value: 0x%02x\n",
242 tmp
& INTEL_830_GMCH_GMS_MASK
);
247 switch (tmp
& INTEL_855_GMCH_GMS_MASK
) {
248 case INTEL_855_GMCH_GMS_STOLEN_1M
:
249 *stolen_size
= MB(1) - KB(stolen_overhead
);
251 case INTEL_855_GMCH_GMS_STOLEN_4M
:
252 *stolen_size
= MB(4) - KB(stolen_overhead
);
254 case INTEL_855_GMCH_GMS_STOLEN_8M
:
255 *stolen_size
= MB(8) - KB(stolen_overhead
);
257 case INTEL_855_GMCH_GMS_STOLEN_16M
:
258 *stolen_size
= MB(16) - KB(stolen_overhead
);
260 case INTEL_855_GMCH_GMS_STOLEN_32M
:
261 *stolen_size
= MB(32) - KB(stolen_overhead
);
263 case INTEL_915G_GMCH_GMS_STOLEN_48M
:
264 *stolen_size
= MB(48) - KB(stolen_overhead
);
266 case INTEL_915G_GMCH_GMS_STOLEN_64M
:
267 *stolen_size
= MB(64) - KB(stolen_overhead
);
269 case INTEL_855_GMCH_GMS_DISABLED
:
270 ERR_MSG("video memory is disabled\n");
273 ERR_MSG("unexpected GMCH_GMS value: 0x%02x\n",
274 tmp
& INTEL_855_GMCH_GMS_MASK
);
280 int intelfbhw_check_non_crt(struct intelfb_info
*dinfo
)
284 if (INREG(LVDS
) & PORT_ENABLE
)
286 if (INREG(DVOA
) & PORT_ENABLE
)
288 if (INREG(DVOB
) & PORT_ENABLE
)
290 if (INREG(DVOC
) & PORT_ENABLE
)
296 const char * intelfbhw_dvo_to_string(int dvo
)
300 else if (dvo
& DVOB_PORT
)
302 else if (dvo
& DVOC_PORT
)
304 else if (dvo
& LVDS_PORT
)
311 int intelfbhw_validate_mode(struct intelfb_info
*dinfo
,
312 struct fb_var_screeninfo
*var
)
318 DBG_MSG("intelfbhw_validate_mode\n");
321 bytes_per_pixel
= var
->bits_per_pixel
/ 8;
322 if (bytes_per_pixel
== 3)
325 /* Check if enough video memory. */
326 tmp
= var
->yres_virtual
* var
->xres_virtual
* bytes_per_pixel
;
327 if (tmp
> dinfo
->fb
.size
) {
328 WRN_MSG("Not enough video ram for mode "
329 "(%d KByte vs %d KByte).\n",
330 BtoKB(tmp
), BtoKB(dinfo
->fb
.size
));
334 /* Check if x/y limits are OK. */
335 if (var
->xres
- 1 > HACTIVE_MASK
) {
336 WRN_MSG("X resolution too large (%d vs %d).\n",
337 var
->xres
, HACTIVE_MASK
+ 1);
340 if (var
->yres
- 1 > VACTIVE_MASK
) {
341 WRN_MSG("Y resolution too large (%d vs %d).\n",
342 var
->yres
, VACTIVE_MASK
+ 1);
346 WRN_MSG("X resolution too small (%d vs 4).\n", var
->xres
);
350 WRN_MSG("Y resolution too small (%d vs 4).\n", var
->yres
);
354 /* Check for doublescan modes. */
355 if (var
->vmode
& FB_VMODE_DOUBLE
) {
356 WRN_MSG("Mode is double-scan.\n");
360 if ((var
->vmode
& FB_VMODE_INTERLACED
) && (var
->yres
& 1)) {
361 WRN_MSG("Odd number of lines in interlaced mode\n");
365 /* Check if clock is OK. */
366 tmp
= 1000000000 / var
->pixclock
;
367 if (tmp
< MIN_CLOCK
) {
368 WRN_MSG("Pixel clock is too low (%d MHz vs %d MHz).\n",
369 (tmp
+ 500) / 1000, MIN_CLOCK
/ 1000);
372 if (tmp
> MAX_CLOCK
) {
373 WRN_MSG("Pixel clock is too high (%d MHz vs %d MHz).\n",
374 (tmp
+ 500) / 1000, MAX_CLOCK
/ 1000);
381 int intelfbhw_pan_display(struct fb_var_screeninfo
*var
, struct fb_info
*info
)
383 struct intelfb_info
*dinfo
= GET_DINFO(info
);
384 u32 offset
, xoffset
, yoffset
;
387 DBG_MSG("intelfbhw_pan_display\n");
390 xoffset
= ROUND_DOWN_TO(var
->xoffset
, 8);
391 yoffset
= var
->yoffset
;
393 if ((xoffset
+ var
->xres
> var
->xres_virtual
) ||
394 (yoffset
+ var
->yres
> var
->yres_virtual
))
397 offset
= (yoffset
* dinfo
->pitch
) +
398 (xoffset
* var
->bits_per_pixel
) / 8;
400 offset
+= dinfo
->fb
.offset
<< 12;
402 dinfo
->vsync
.pan_offset
= offset
;
403 if ((var
->activate
& FB_ACTIVATE_VBL
) &&
404 !intelfbhw_enable_irq(dinfo
))
405 dinfo
->vsync
.pan_display
= 1;
407 dinfo
->vsync
.pan_display
= 0;
408 OUTREG(DSPABASE
, offset
);
414 /* Blank the screen. */
415 void intelfbhw_do_blank(int blank
, struct fb_info
*info
)
417 struct intelfb_info
*dinfo
= GET_DINFO(info
);
421 DBG_MSG("intelfbhw_do_blank: blank is %d\n", blank
);
424 /* Turn plane A on or off */
425 tmp
= INREG(DSPACNTR
);
427 tmp
&= ~DISPPLANE_PLANE_ENABLE
;
429 tmp
|= DISPPLANE_PLANE_ENABLE
;
430 OUTREG(DSPACNTR
, tmp
);
432 tmp
= INREG(DSPABASE
);
433 OUTREG(DSPABASE
, tmp
);
435 /* Turn off/on the HW cursor */
437 DBG_MSG("cursor_on is %d\n", dinfo
->cursor_on
);
439 if (dinfo
->cursor_on
) {
441 intelfbhw_cursor_hide(dinfo
);
443 intelfbhw_cursor_show(dinfo
);
444 dinfo
->cursor_on
= 1;
446 dinfo
->cursor_blanked
= blank
;
449 tmp
= INREG(ADPA
) & ~ADPA_DPMS_CONTROL_MASK
;
451 case FB_BLANK_UNBLANK
:
452 case FB_BLANK_NORMAL
:
455 case FB_BLANK_VSYNC_SUSPEND
:
458 case FB_BLANK_HSYNC_SUSPEND
:
461 case FB_BLANK_POWERDOWN
:
471 /* Check which pipe is connected to an active display plane. */
472 int intelfbhw_active_pipe(const struct intelfb_hwstate
*hw
)
476 /* keep old default behaviour - prefer PIPE_A */
477 if (hw
->disp_b_ctrl
& DISPPLANE_PLANE_ENABLE
) {
478 pipe
= (hw
->disp_b_ctrl
>> DISPPLANE_SEL_PIPE_SHIFT
);
480 if (unlikely(pipe
== PIPE_A
))
483 if (hw
->disp_a_ctrl
& DISPPLANE_PLANE_ENABLE
) {
484 pipe
= (hw
->disp_a_ctrl
>> DISPPLANE_SEL_PIPE_SHIFT
);
486 if (likely(pipe
== PIPE_A
))
489 /* Impossible that no pipe is selected - return PIPE_A */
491 if (unlikely(pipe
== -1))
497 void intelfbhw_setcolreg(struct intelfb_info
*dinfo
, unsigned regno
,
498 unsigned red
, unsigned green
, unsigned blue
,
501 u32 palette_reg
= (dinfo
->pipe
== PIPE_A
) ?
502 PALETTE_A
: PALETTE_B
;
505 DBG_MSG("intelfbhw_setcolreg: %d: (%d, %d, %d)\n",
506 regno
, red
, green
, blue
);
509 OUTREG(palette_reg
+ (regno
<< 2),
510 (red
<< PALETTE_8_RED_SHIFT
) |
511 (green
<< PALETTE_8_GREEN_SHIFT
) |
512 (blue
<< PALETTE_8_BLUE_SHIFT
));
516 int intelfbhw_read_hw_state(struct intelfb_info
*dinfo
,
517 struct intelfb_hwstate
*hw
, int flag
)
522 DBG_MSG("intelfbhw_read_hw_state\n");
528 /* Read in as much of the HW state as possible. */
529 hw
->vga0_divisor
= INREG(VGA0_DIVISOR
);
530 hw
->vga1_divisor
= INREG(VGA1_DIVISOR
);
531 hw
->vga_pd
= INREG(VGAPD
);
532 hw
->dpll_a
= INREG(DPLL_A
);
533 hw
->dpll_b
= INREG(DPLL_B
);
534 hw
->fpa0
= INREG(FPA0
);
535 hw
->fpa1
= INREG(FPA1
);
536 hw
->fpb0
= INREG(FPB0
);
537 hw
->fpb1
= INREG(FPB1
);
546 hw
->htotal_a
= INREG(HTOTAL_A
);
547 hw
->hblank_a
= INREG(HBLANK_A
);
548 hw
->hsync_a
= INREG(HSYNC_A
);
549 hw
->vtotal_a
= INREG(VTOTAL_A
);
550 hw
->vblank_a
= INREG(VBLANK_A
);
551 hw
->vsync_a
= INREG(VSYNC_A
);
552 hw
->src_size_a
= INREG(SRC_SIZE_A
);
553 hw
->bclrpat_a
= INREG(BCLRPAT_A
);
554 hw
->htotal_b
= INREG(HTOTAL_B
);
555 hw
->hblank_b
= INREG(HBLANK_B
);
556 hw
->hsync_b
= INREG(HSYNC_B
);
557 hw
->vtotal_b
= INREG(VTOTAL_B
);
558 hw
->vblank_b
= INREG(VBLANK_B
);
559 hw
->vsync_b
= INREG(VSYNC_B
);
560 hw
->src_size_b
= INREG(SRC_SIZE_B
);
561 hw
->bclrpat_b
= INREG(BCLRPAT_B
);
566 hw
->adpa
= INREG(ADPA
);
567 hw
->dvoa
= INREG(DVOA
);
568 hw
->dvob
= INREG(DVOB
);
569 hw
->dvoc
= INREG(DVOC
);
570 hw
->dvoa_srcdim
= INREG(DVOA_SRCDIM
);
571 hw
->dvob_srcdim
= INREG(DVOB_SRCDIM
);
572 hw
->dvoc_srcdim
= INREG(DVOC_SRCDIM
);
573 hw
->lvds
= INREG(LVDS
);
578 hw
->pipe_a_conf
= INREG(PIPEACONF
);
579 hw
->pipe_b_conf
= INREG(PIPEBCONF
);
580 hw
->disp_arb
= INREG(DISPARB
);
585 hw
->cursor_a_control
= INREG(CURSOR_A_CONTROL
);
586 hw
->cursor_b_control
= INREG(CURSOR_B_CONTROL
);
587 hw
->cursor_a_base
= INREG(CURSOR_A_BASEADDR
);
588 hw
->cursor_b_base
= INREG(CURSOR_B_BASEADDR
);
593 for (i
= 0; i
< 4; i
++) {
594 hw
->cursor_a_palette
[i
] = INREG(CURSOR_A_PALETTE0
+ (i
<< 2));
595 hw
->cursor_b_palette
[i
] = INREG(CURSOR_B_PALETTE0
+ (i
<< 2));
601 hw
->cursor_size
= INREG(CURSOR_SIZE
);
606 hw
->disp_a_ctrl
= INREG(DSPACNTR
);
607 hw
->disp_b_ctrl
= INREG(DSPBCNTR
);
608 hw
->disp_a_base
= INREG(DSPABASE
);
609 hw
->disp_b_base
= INREG(DSPBBASE
);
610 hw
->disp_a_stride
= INREG(DSPASTRIDE
);
611 hw
->disp_b_stride
= INREG(DSPBSTRIDE
);
616 hw
->vgacntrl
= INREG(VGACNTRL
);
621 hw
->add_id
= INREG(ADD_ID
);
626 for (i
= 0; i
< 7; i
++) {
627 hw
->swf0x
[i
] = INREG(SWF00
+ (i
<< 2));
628 hw
->swf1x
[i
] = INREG(SWF10
+ (i
<< 2));
630 hw
->swf3x
[i
] = INREG(SWF30
+ (i
<< 2));
633 for (i
= 0; i
< 8; i
++)
634 hw
->fence
[i
] = INREG(FENCE
+ (i
<< 2));
636 hw
->instpm
= INREG(INSTPM
);
637 hw
->mem_mode
= INREG(MEM_MODE
);
638 hw
->fw_blc_0
= INREG(FW_BLC_0
);
639 hw
->fw_blc_1
= INREG(FW_BLC_1
);
641 hw
->hwstam
= INREG16(HWSTAM
);
642 hw
->ier
= INREG16(IER
);
643 hw
->iir
= INREG16(IIR
);
644 hw
->imr
= INREG16(IMR
);
650 static int calc_vclock3(int index
, int m
, int n
, int p
)
652 if (p
== 0 || n
== 0)
654 return plls
[index
].ref_clk
* m
/ n
/ p
;
657 static int calc_vclock(int index
, int m1
, int m2
, int n
, int p1
, int p2
,
660 struct pll_min_max
*pll
= &plls
[index
];
663 m
= (5 * (m1
+ 2)) + (m2
+ 2);
665 vco
= pll
->ref_clk
* m
/ n
;
667 if (index
== PLLS_I8xx
)
668 p
= ((p1
+ 2) * (1 << (p2
+ 1)));
670 p
= ((p1
) * (p2
? 5 : 10));
675 static void intelfbhw_get_p1p2(struct intelfb_info
*dinfo
, int dpll
,
676 int *o_p1
, int *o_p2
)
680 if (IS_I9XX(dinfo
)) {
681 if (dpll
& DPLL_P1_FORCE_DIV2
)
684 p1
= (dpll
>> DPLL_P1_SHIFT
) & 0xff;
688 p2
= (dpll
>> DPLL_I9XX_P2_SHIFT
) & DPLL_P2_MASK
;
690 if (dpll
& DPLL_P1_FORCE_DIV2
)
693 p1
= (dpll
>> DPLL_P1_SHIFT
) & DPLL_P1_MASK
;
694 p2
= (dpll
>> DPLL_P2_SHIFT
) & DPLL_P2_MASK
;
703 void intelfbhw_print_hw_state(struct intelfb_info
*dinfo
,
704 struct intelfb_hwstate
*hw
)
707 int i
, m1
, m2
, n
, p1
, p2
;
708 int index
= dinfo
->pll_index
;
709 DBG_MSG("intelfbhw_print_hw_state\n");
713 /* Read in as much of the HW state as possible. */
714 printk("hw state dump start\n");
715 printk(" VGA0_DIVISOR: 0x%08x\n", hw
->vga0_divisor
);
716 printk(" VGA1_DIVISOR: 0x%08x\n", hw
->vga1_divisor
);
717 printk(" VGAPD: 0x%08x\n", hw
->vga_pd
);
718 n
= (hw
->vga0_divisor
>> FP_N_DIVISOR_SHIFT
) & FP_DIVISOR_MASK
;
719 m1
= (hw
->vga0_divisor
>> FP_M1_DIVISOR_SHIFT
) & FP_DIVISOR_MASK
;
720 m2
= (hw
->vga0_divisor
>> FP_M2_DIVISOR_SHIFT
) & FP_DIVISOR_MASK
;
722 intelfbhw_get_p1p2(dinfo
, hw
->vga_pd
, &p1
, &p2
);
724 printk(" VGA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
726 printk(" VGA0: clock is %d\n",
727 calc_vclock(index
, m1
, m2
, n
, p1
, p2
, 0));
729 n
= (hw
->vga1_divisor
>> FP_N_DIVISOR_SHIFT
) & FP_DIVISOR_MASK
;
730 m1
= (hw
->vga1_divisor
>> FP_M1_DIVISOR_SHIFT
) & FP_DIVISOR_MASK
;
731 m2
= (hw
->vga1_divisor
>> FP_M2_DIVISOR_SHIFT
) & FP_DIVISOR_MASK
;
733 intelfbhw_get_p1p2(dinfo
, hw
->vga_pd
, &p1
, &p2
);
734 printk(" VGA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
736 printk(" VGA1: clock is %d\n",
737 calc_vclock(index
, m1
, m2
, n
, p1
, p2
, 0));
739 printk(" DPLL_A: 0x%08x\n", hw
->dpll_a
);
740 printk(" DPLL_B: 0x%08x\n", hw
->dpll_b
);
741 printk(" FPA0: 0x%08x\n", hw
->fpa0
);
742 printk(" FPA1: 0x%08x\n", hw
->fpa1
);
743 printk(" FPB0: 0x%08x\n", hw
->fpb0
);
744 printk(" FPB1: 0x%08x\n", hw
->fpb1
);
746 n
= (hw
->fpa0
>> FP_N_DIVISOR_SHIFT
) & FP_DIVISOR_MASK
;
747 m1
= (hw
->fpa0
>> FP_M1_DIVISOR_SHIFT
) & FP_DIVISOR_MASK
;
748 m2
= (hw
->fpa0
>> FP_M2_DIVISOR_SHIFT
) & FP_DIVISOR_MASK
;
750 intelfbhw_get_p1p2(dinfo
, hw
->dpll_a
, &p1
, &p2
);
752 printk(" PLLA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
754 printk(" PLLA0: clock is %d\n",
755 calc_vclock(index
, m1
, m2
, n
, p1
, p2
, 0));
757 n
= (hw
->fpa1
>> FP_N_DIVISOR_SHIFT
) & FP_DIVISOR_MASK
;
758 m1
= (hw
->fpa1
>> FP_M1_DIVISOR_SHIFT
) & FP_DIVISOR_MASK
;
759 m2
= (hw
->fpa1
>> FP_M2_DIVISOR_SHIFT
) & FP_DIVISOR_MASK
;
761 intelfbhw_get_p1p2(dinfo
, hw
->dpll_a
, &p1
, &p2
);
763 printk(" PLLA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
765 printk(" PLLA1: clock is %d\n",
766 calc_vclock(index
, m1
, m2
, n
, p1
, p2
, 0));
769 printk(" HTOTAL_A: 0x%08x\n", hw
->htotal_a
);
770 printk(" HBLANK_A: 0x%08x\n", hw
->hblank_a
);
771 printk(" HSYNC_A: 0x%08x\n", hw
->hsync_a
);
772 printk(" VTOTAL_A: 0x%08x\n", hw
->vtotal_a
);
773 printk(" VBLANK_A: 0x%08x\n", hw
->vblank_a
);
774 printk(" VSYNC_A: 0x%08x\n", hw
->vsync_a
);
775 printk(" SRC_SIZE_A: 0x%08x\n", hw
->src_size_a
);
776 printk(" BCLRPAT_A: 0x%08x\n", hw
->bclrpat_a
);
777 printk(" HTOTAL_B: 0x%08x\n", hw
->htotal_b
);
778 printk(" HBLANK_B: 0x%08x\n", hw
->hblank_b
);
779 printk(" HSYNC_B: 0x%08x\n", hw
->hsync_b
);
780 printk(" VTOTAL_B: 0x%08x\n", hw
->vtotal_b
);
781 printk(" VBLANK_B: 0x%08x\n", hw
->vblank_b
);
782 printk(" VSYNC_B: 0x%08x\n", hw
->vsync_b
);
783 printk(" SRC_SIZE_B: 0x%08x\n", hw
->src_size_b
);
784 printk(" BCLRPAT_B: 0x%08x\n", hw
->bclrpat_b
);
786 printk(" ADPA: 0x%08x\n", hw
->adpa
);
787 printk(" DVOA: 0x%08x\n", hw
->dvoa
);
788 printk(" DVOB: 0x%08x\n", hw
->dvob
);
789 printk(" DVOC: 0x%08x\n", hw
->dvoc
);
790 printk(" DVOA_SRCDIM: 0x%08x\n", hw
->dvoa_srcdim
);
791 printk(" DVOB_SRCDIM: 0x%08x\n", hw
->dvob_srcdim
);
792 printk(" DVOC_SRCDIM: 0x%08x\n", hw
->dvoc_srcdim
);
793 printk(" LVDS: 0x%08x\n", hw
->lvds
);
795 printk(" PIPEACONF: 0x%08x\n", hw
->pipe_a_conf
);
796 printk(" PIPEBCONF: 0x%08x\n", hw
->pipe_b_conf
);
797 printk(" DISPARB: 0x%08x\n", hw
->disp_arb
);
799 printk(" CURSOR_A_CONTROL: 0x%08x\n", hw
->cursor_a_control
);
800 printk(" CURSOR_B_CONTROL: 0x%08x\n", hw
->cursor_b_control
);
801 printk(" CURSOR_A_BASEADDR: 0x%08x\n", hw
->cursor_a_base
);
802 printk(" CURSOR_B_BASEADDR: 0x%08x\n", hw
->cursor_b_base
);
804 printk(" CURSOR_A_PALETTE: ");
805 for (i
= 0; i
< 4; i
++) {
806 printk("0x%08x", hw
->cursor_a_palette
[i
]);
811 printk(" CURSOR_B_PALETTE: ");
812 for (i
= 0; i
< 4; i
++) {
813 printk("0x%08x", hw
->cursor_b_palette
[i
]);
819 printk(" CURSOR_SIZE: 0x%08x\n", hw
->cursor_size
);
821 printk(" DSPACNTR: 0x%08x\n", hw
->disp_a_ctrl
);
822 printk(" DSPBCNTR: 0x%08x\n", hw
->disp_b_ctrl
);
823 printk(" DSPABASE: 0x%08x\n", hw
->disp_a_base
);
824 printk(" DSPBBASE: 0x%08x\n", hw
->disp_b_base
);
825 printk(" DSPASTRIDE: 0x%08x\n", hw
->disp_a_stride
);
826 printk(" DSPBSTRIDE: 0x%08x\n", hw
->disp_b_stride
);
828 printk(" VGACNTRL: 0x%08x\n", hw
->vgacntrl
);
829 printk(" ADD_ID: 0x%08x\n", hw
->add_id
);
831 for (i
= 0; i
< 7; i
++) {
832 printk(" SWF0%d 0x%08x\n", i
,
835 for (i
= 0; i
< 7; i
++) {
836 printk(" SWF1%d 0x%08x\n", i
,
839 for (i
= 0; i
< 3; i
++) {
840 printk(" SWF3%d 0x%08x\n", i
,
843 for (i
= 0; i
< 8; i
++)
844 printk(" FENCE%d 0x%08x\n", i
,
847 printk(" INSTPM 0x%08x\n", hw
->instpm
);
848 printk(" MEM_MODE 0x%08x\n", hw
->mem_mode
);
849 printk(" FW_BLC_0 0x%08x\n", hw
->fw_blc_0
);
850 printk(" FW_BLC_1 0x%08x\n", hw
->fw_blc_1
);
852 printk(" HWSTAM 0x%04x\n", hw
->hwstam
);
853 printk(" IER 0x%04x\n", hw
->ier
);
854 printk(" IIR 0x%04x\n", hw
->iir
);
855 printk(" IMR 0x%04x\n", hw
->imr
);
856 printk("hw state dump end\n");
862 /* Split the M parameter into M1 and M2. */
863 static int splitm(int index
, unsigned int m
, unsigned int *retm1
,
868 struct pll_min_max
*pll
= &plls
[index
];
870 /* no point optimising too much - brute force m */
871 for (m1
= pll
->min_m1
; m1
< pll
->max_m1
+ 1; m1
++) {
872 for (m2
= pll
->min_m2
; m2
< pll
->max_m2
+ 1; m2
++) {
873 testm
= (5 * (m1
+ 2)) + (m2
+ 2);
875 *retm1
= (unsigned int)m1
;
876 *retm2
= (unsigned int)m2
;
884 /* Split the P parameter into P1 and P2. */
885 static int splitp(int index
, unsigned int p
, unsigned int *retp1
,
889 struct pll_min_max
*pll
= &plls
[index
];
891 if (index
== PLLS_I9xx
) {
892 p2
= (p
% 10) ? 1 : 0;
894 p1
= p
/ (p2
? 5 : 10);
896 *retp1
= (unsigned int)p1
;
897 *retp2
= (unsigned int)p2
;
905 p1
= (p
/ (1 << (p2
+ 1))) - 2;
906 if (p
% 4 == 0 && p1
< pll
->min_p1
) {
908 p1
= (p
/ (1 << (p2
+ 1))) - 2;
910 if (p1
< pll
->min_p1
|| p1
> pll
->max_p1
||
911 (p1
+ 2) * (1 << (p2
+ 1)) != p
) {
914 *retp1
= (unsigned int)p1
;
915 *retp2
= (unsigned int)p2
;
920 static int calc_pll_params(int index
, int clock
, u32
*retm1
, u32
*retm2
,
921 u32
*retn
, u32
*retp1
, u32
*retp2
, u32
*retclock
)
923 u32 m1
, m2
, n
, p1
, p2
, n1
, testm
;
924 u32 f_vco
, p
, p_best
= 0, m
, f_out
= 0;
925 u32 err_max
, err_target
, err_best
= 10000000;
926 u32 n_best
= 0, m_best
= 0, f_best
, f_err
;
927 u32 p_min
, p_max
, p_inc
, div_max
;
928 struct pll_min_max
*pll
= &plls
[index
];
930 /* Accept 0.5% difference, but aim for 0.1% */
931 err_max
= 5 * clock
/ 1000;
932 err_target
= clock
/ 1000;
934 DBG_MSG("Clock is %d\n", clock
);
936 div_max
= pll
->max_vco
/ clock
;
938 p_inc
= (clock
<= pll
->p_transition_clk
) ? pll
->p_inc_lo
: pll
->p_inc_hi
;
940 p_max
= ROUND_DOWN_TO(div_max
, p_inc
);
941 if (p_min
< pll
->min_p
)
943 if (p_max
> pll
->max_p
)
946 DBG_MSG("p range is %d-%d (%d)\n", p_min
, p_max
, p_inc
);
950 if (splitp(index
, p
, &p1
, &p2
)) {
951 WRN_MSG("cannot split p = %d\n", p
);
959 m
= ROUND_UP_TO(f_vco
* n
, pll
->ref_clk
) / pll
->ref_clk
;
964 for (testm
= m
- 1; testm
<= m
; testm
++) {
965 f_out
= calc_vclock3(index
, testm
, n
, p
);
966 if (splitm(index
, testm
, &m1
, &m2
)) {
967 WRN_MSG("cannot split m = %d\n",
972 f_err
= clock
- f_out
;
973 else/* slightly bias the error for bigger clocks */
974 f_err
= f_out
- clock
+ 1;
976 if (f_err
< err_best
) {
985 } while ((n
<= pll
->max_n
) && (f_out
>= clock
));
987 } while ((p
<= p_max
));
990 WRN_MSG("cannot find parameters for clock %d\n", clock
);
996 splitm(index
, m
, &m1
, &m2
);
997 splitp(index
, p
, &p1
, &p2
);
1000 DBG_MSG("m, n, p: %d (%d,%d), %d (%d), %d (%d,%d), "
1001 "f: %d (%d), VCO: %d\n",
1002 m
, m1
, m2
, n
, n1
, p
, p1
, p2
,
1003 calc_vclock3(index
, m
, n
, p
),
1004 calc_vclock(index
, m1
, m2
, n1
, p1
, p2
, 0),
1005 calc_vclock3(index
, m
, n
, p
) * p
);
1011 *retclock
= calc_vclock(index
, m1
, m2
, n1
, p1
, p2
, 0);
1016 static __inline__
int check_overflow(u32 value
, u32 limit
,
1017 const char *description
)
1019 if (value
> limit
) {
1020 WRN_MSG("%s value %d exceeds limit %d\n",
1021 description
, value
, limit
);
1027 /* It is assumed that hw is filled in with the initial state information. */
1028 int intelfbhw_mode_to_hw(struct intelfb_info
*dinfo
,
1029 struct intelfb_hwstate
*hw
,
1030 struct fb_var_screeninfo
*var
)
1032 int pipe
= intelfbhw_active_pipe(hw
);
1033 u32
*dpll
, *fp0
, *fp1
;
1034 u32 m1
, m2
, n
, p1
, p2
, clock_target
, clock
;
1035 u32 hsync_start
, hsync_end
, hblank_start
, hblank_end
, htotal
, hactive
;
1036 u32 vsync_start
, vsync_end
, vblank_start
, vblank_end
, vtotal
, vactive
;
1037 u32 vsync_pol
, hsync_pol
;
1038 u32
*vs
, *vb
, *vt
, *hs
, *hb
, *ht
, *ss
, *pipe_conf
;
1039 u32 stride_alignment
;
1041 DBG_MSG("intelfbhw_mode_to_hw\n");
1044 hw
->vgacntrl
|= VGA_DISABLE
;
1046 /* Set which pipe's registers will be set. */
1047 if (pipe
== PIPE_B
) {
1057 ss
= &hw
->src_size_b
;
1058 pipe_conf
= &hw
->pipe_b_conf
;
1069 ss
= &hw
->src_size_a
;
1070 pipe_conf
= &hw
->pipe_a_conf
;
1073 /* Use ADPA register for sync control. */
1074 hw
->adpa
&= ~ADPA_USE_VGA_HVPOLARITY
;
1077 hsync_pol
= (var
->sync
& FB_SYNC_HOR_HIGH_ACT
) ?
1078 ADPA_SYNC_ACTIVE_HIGH
: ADPA_SYNC_ACTIVE_LOW
;
1079 vsync_pol
= (var
->sync
& FB_SYNC_VERT_HIGH_ACT
) ?
1080 ADPA_SYNC_ACTIVE_HIGH
: ADPA_SYNC_ACTIVE_LOW
;
1081 hw
->adpa
&= ~((ADPA_SYNC_ACTIVE_MASK
<< ADPA_VSYNC_ACTIVE_SHIFT
) |
1082 (ADPA_SYNC_ACTIVE_MASK
<< ADPA_HSYNC_ACTIVE_SHIFT
));
1083 hw
->adpa
|= (hsync_pol
<< ADPA_HSYNC_ACTIVE_SHIFT
) |
1084 (vsync_pol
<< ADPA_VSYNC_ACTIVE_SHIFT
);
1086 /* Connect correct pipe to the analog port DAC */
1087 hw
->adpa
&= ~(PIPE_MASK
<< ADPA_PIPE_SELECT_SHIFT
);
1088 hw
->adpa
|= (pipe
<< ADPA_PIPE_SELECT_SHIFT
);
1090 /* Set DPMS state to D0 (on) */
1091 hw
->adpa
&= ~ADPA_DPMS_CONTROL_MASK
;
1092 hw
->adpa
|= ADPA_DPMS_D0
;
1094 hw
->adpa
|= ADPA_DAC_ENABLE
;
1096 *dpll
|= (DPLL_VCO_ENABLE
| DPLL_VGA_MODE_DISABLE
);
1097 *dpll
&= ~(DPLL_RATE_SELECT_MASK
| DPLL_REFERENCE_SELECT_MASK
);
1098 *dpll
|= (DPLL_REFERENCE_DEFAULT
| DPLL_RATE_SELECT_FP0
);
1100 /* Desired clock in kHz */
1101 clock_target
= 1000000000 / var
->pixclock
;
1103 if (calc_pll_params(dinfo
->pll_index
, clock_target
, &m1
, &m2
,
1104 &n
, &p1
, &p2
, &clock
)) {
1105 WRN_MSG("calc_pll_params failed\n");
1109 /* Check for overflow. */
1110 if (check_overflow(p1
, DPLL_P1_MASK
, "PLL P1 parameter"))
1112 if (check_overflow(p2
, DPLL_P2_MASK
, "PLL P2 parameter"))
1114 if (check_overflow(m1
, FP_DIVISOR_MASK
, "PLL M1 parameter"))
1116 if (check_overflow(m2
, FP_DIVISOR_MASK
, "PLL M2 parameter"))
1118 if (check_overflow(n
, FP_DIVISOR_MASK
, "PLL N parameter"))
1121 *dpll
&= ~DPLL_P1_FORCE_DIV2
;
1122 *dpll
&= ~((DPLL_P2_MASK
<< DPLL_P2_SHIFT
) |
1123 (DPLL_P1_MASK
<< DPLL_P1_SHIFT
));
1125 if (IS_I9XX(dinfo
)) {
1126 *dpll
|= (p2
<< DPLL_I9XX_P2_SHIFT
);
1127 *dpll
|= (1 << (p1
- 1)) << DPLL_P1_SHIFT
;
1129 *dpll
|= (p2
<< DPLL_P2_SHIFT
) | (p1
<< DPLL_P1_SHIFT
);
1131 *fp0
= (n
<< FP_N_DIVISOR_SHIFT
) |
1132 (m1
<< FP_M1_DIVISOR_SHIFT
) |
1133 (m2
<< FP_M2_DIVISOR_SHIFT
);
1136 hw
->dvob
&= ~PORT_ENABLE
;
1137 hw
->dvoc
&= ~PORT_ENABLE
;
1139 /* Use display plane A. */
1140 hw
->disp_a_ctrl
|= DISPPLANE_PLANE_ENABLE
;
1141 hw
->disp_a_ctrl
&= ~DISPPLANE_GAMMA_ENABLE
;
1142 hw
->disp_a_ctrl
&= ~DISPPLANE_PIXFORMAT_MASK
;
1143 switch (intelfb_var_to_depth(var
)) {
1145 hw
->disp_a_ctrl
|= DISPPLANE_8BPP
| DISPPLANE_GAMMA_ENABLE
;
1148 hw
->disp_a_ctrl
|= DISPPLANE_15_16BPP
;
1151 hw
->disp_a_ctrl
|= DISPPLANE_16BPP
;
1154 hw
->disp_a_ctrl
|= DISPPLANE_32BPP_NO_ALPHA
;
1157 hw
->disp_a_ctrl
&= ~(PIPE_MASK
<< DISPPLANE_SEL_PIPE_SHIFT
);
1158 hw
->disp_a_ctrl
|= (pipe
<< DISPPLANE_SEL_PIPE_SHIFT
);
1160 /* Set CRTC registers. */
1161 hactive
= var
->xres
;
1162 hsync_start
= hactive
+ var
->right_margin
;
1163 hsync_end
= hsync_start
+ var
->hsync_len
;
1164 htotal
= hsync_end
+ var
->left_margin
;
1165 hblank_start
= hactive
;
1166 hblank_end
= htotal
;
1168 DBG_MSG("H: act %d, ss %d, se %d, tot %d bs %d, be %d\n",
1169 hactive
, hsync_start
, hsync_end
, htotal
, hblank_start
,
1172 vactive
= var
->yres
;
1173 if (var
->vmode
& FB_VMODE_INTERLACED
)
1174 vactive
--; /* the chip adds 2 halflines automatically */
1175 vsync_start
= vactive
+ var
->lower_margin
;
1176 vsync_end
= vsync_start
+ var
->vsync_len
;
1177 vtotal
= vsync_end
+ var
->upper_margin
;
1178 vblank_start
= vactive
;
1179 vblank_end
= vtotal
;
1180 vblank_end
= vsync_end
+ 1;
1182 DBG_MSG("V: act %d, ss %d, se %d, tot %d bs %d, be %d\n",
1183 vactive
, vsync_start
, vsync_end
, vtotal
, vblank_start
,
1186 /* Adjust for register values, and check for overflow. */
1188 if (check_overflow(hactive
, HACTIVE_MASK
, "CRTC hactive"))
1191 if (check_overflow(hsync_start
, HSYNCSTART_MASK
, "CRTC hsync_start"))
1194 if (check_overflow(hsync_end
, HSYNCEND_MASK
, "CRTC hsync_end"))
1197 if (check_overflow(htotal
, HTOTAL_MASK
, "CRTC htotal"))
1200 if (check_overflow(hblank_start
, HBLANKSTART_MASK
, "CRTC hblank_start"))
1203 if (check_overflow(hblank_end
, HBLANKEND_MASK
, "CRTC hblank_end"))
1207 if (check_overflow(vactive
, VACTIVE_MASK
, "CRTC vactive"))
1210 if (check_overflow(vsync_start
, VSYNCSTART_MASK
, "CRTC vsync_start"))
1213 if (check_overflow(vsync_end
, VSYNCEND_MASK
, "CRTC vsync_end"))
1216 if (check_overflow(vtotal
, VTOTAL_MASK
, "CRTC vtotal"))
1219 if (check_overflow(vblank_start
, VBLANKSTART_MASK
, "CRTC vblank_start"))
1222 if (check_overflow(vblank_end
, VBLANKEND_MASK
, "CRTC vblank_end"))
1225 *ht
= (htotal
<< HTOTAL_SHIFT
) | (hactive
<< HACTIVE_SHIFT
);
1226 *hb
= (hblank_start
<< HBLANKSTART_SHIFT
) |
1227 (hblank_end
<< HSYNCEND_SHIFT
);
1228 *hs
= (hsync_start
<< HSYNCSTART_SHIFT
) | (hsync_end
<< HSYNCEND_SHIFT
);
1230 *vt
= (vtotal
<< VTOTAL_SHIFT
) | (vactive
<< VACTIVE_SHIFT
);
1231 *vb
= (vblank_start
<< VBLANKSTART_SHIFT
) |
1232 (vblank_end
<< VSYNCEND_SHIFT
);
1233 *vs
= (vsync_start
<< VSYNCSTART_SHIFT
) | (vsync_end
<< VSYNCEND_SHIFT
);
1234 *ss
= (hactive
<< SRC_SIZE_HORIZ_SHIFT
) |
1235 (vactive
<< SRC_SIZE_VERT_SHIFT
);
1237 hw
->disp_a_stride
= dinfo
->pitch
;
1238 DBG_MSG("pitch is %d\n", hw
->disp_a_stride
);
1240 hw
->disp_a_base
= hw
->disp_a_stride
* var
->yoffset
+
1241 var
->xoffset
* var
->bits_per_pixel
/ 8;
1243 hw
->disp_a_base
+= dinfo
->fb
.offset
<< 12;
1245 /* Check stride alignment. */
1246 stride_alignment
= IS_I9XX(dinfo
) ? STRIDE_ALIGNMENT_I9XX
:
1248 if (hw
->disp_a_stride
% stride_alignment
!= 0) {
1249 WRN_MSG("display stride %d has bad alignment %d\n",
1250 hw
->disp_a_stride
, stride_alignment
);
1254 /* Set the palette to 8-bit mode. */
1255 *pipe_conf
&= ~PIPECONF_GAMMA
;
1257 if (var
->vmode
& FB_VMODE_INTERLACED
)
1258 *pipe_conf
|= PIPECONF_INTERLACE_W_FIELD_INDICATION
;
1260 *pipe_conf
&= ~PIPECONF_INTERLACE_MASK
;
1265 /* Program a (non-VGA) video mode. */
1266 int intelfbhw_program_mode(struct intelfb_info
*dinfo
,
1267 const struct intelfb_hwstate
*hw
, int blank
)
1270 const u32
*dpll
, *fp0
, *fp1
, *pipe_conf
;
1271 const u32
*hs
, *ht
, *hb
, *vs
, *vt
, *vb
, *ss
;
1272 u32 dpll_reg
, fp0_reg
, fp1_reg
, pipe_conf_reg
, pipe_stat_reg
;
1273 u32 hsync_reg
, htotal_reg
, hblank_reg
;
1274 u32 vsync_reg
, vtotal_reg
, vblank_reg
;
1276 u32 count
, tmp_val
[3];
1278 /* Assume single pipe */
1281 DBG_MSG("intelfbhw_program_mode\n");
1285 tmp
= INREG(VGACNTRL
);
1287 OUTREG(VGACNTRL
, tmp
);
1289 dinfo
->pipe
= intelfbhw_active_pipe(hw
);
1291 if (dinfo
->pipe
== PIPE_B
) {
1295 pipe_conf
= &hw
->pipe_b_conf
;
1302 ss
= &hw
->src_size_b
;
1306 pipe_conf_reg
= PIPEBCONF
;
1307 pipe_stat_reg
= PIPEBSTAT
;
1308 hsync_reg
= HSYNC_B
;
1309 htotal_reg
= HTOTAL_B
;
1310 hblank_reg
= HBLANK_B
;
1311 vsync_reg
= VSYNC_B
;
1312 vtotal_reg
= VTOTAL_B
;
1313 vblank_reg
= VBLANK_B
;
1314 src_size_reg
= SRC_SIZE_B
;
1319 pipe_conf
= &hw
->pipe_a_conf
;
1326 ss
= &hw
->src_size_a
;
1330 pipe_conf_reg
= PIPEACONF
;
1331 pipe_stat_reg
= PIPEASTAT
;
1332 hsync_reg
= HSYNC_A
;
1333 htotal_reg
= HTOTAL_A
;
1334 hblank_reg
= HBLANK_A
;
1335 vsync_reg
= VSYNC_A
;
1336 vtotal_reg
= VTOTAL_A
;
1337 vblank_reg
= VBLANK_A
;
1338 src_size_reg
= SRC_SIZE_A
;
1342 tmp
= INREG(pipe_conf_reg
);
1343 tmp
&= ~PIPECONF_ENABLE
;
1344 OUTREG(pipe_conf_reg
, tmp
);
1348 tmp_val
[count
% 3] = INREG(PIPEA_DSL
);
1349 if ((tmp_val
[0] == tmp_val
[1]) && (tmp_val
[1] == tmp_val
[2]))
1353 if (count
% 200 == 0) {
1354 tmp
= INREG(pipe_conf_reg
);
1355 tmp
&= ~PIPECONF_ENABLE
;
1356 OUTREG(pipe_conf_reg
, tmp
);
1358 } while (count
< 2000);
1360 OUTREG(ADPA
, INREG(ADPA
) & ~ADPA_DAC_ENABLE
);
1362 /* Disable planes A and B. */
1363 tmp
= INREG(DSPACNTR
);
1364 tmp
&= ~DISPPLANE_PLANE_ENABLE
;
1365 OUTREG(DSPACNTR
, tmp
);
1366 tmp
= INREG(DSPBCNTR
);
1367 tmp
&= ~DISPPLANE_PLANE_ENABLE
;
1368 OUTREG(DSPBCNTR
, tmp
);
1370 /* Wait for vblank. For now, just wait for a 50Hz cycle (20ms)) */
1373 OUTREG(DVOB
, INREG(DVOB
) & ~PORT_ENABLE
);
1374 OUTREG(DVOC
, INREG(DVOC
) & ~PORT_ENABLE
);
1375 OUTREG(ADPA
, INREG(ADPA
) & ~ADPA_DAC_ENABLE
);
1379 tmp
&= ~ADPA_DPMS_CONTROL_MASK
;
1380 tmp
|= ADPA_DPMS_D3
;
1383 /* do some funky magic - xyzzy */
1384 OUTREG(0x61204, 0xabcd0000);
1387 tmp
= INREG(dpll_reg
);
1388 tmp
&= ~DPLL_VCO_ENABLE
;
1389 OUTREG(dpll_reg
, tmp
);
1391 /* Set PLL parameters */
1392 OUTREG(fp0_reg
, *fp0
);
1393 OUTREG(fp1_reg
, *fp1
);
1396 OUTREG(dpll_reg
, *dpll
);
1399 OUTREG(DVOB
, hw
->dvob
);
1400 OUTREG(DVOC
, hw
->dvoc
);
1402 /* undo funky magic */
1403 OUTREG(0x61204, 0x00000000);
1406 OUTREG(ADPA
, INREG(ADPA
) | ADPA_DAC_ENABLE
);
1407 OUTREG(ADPA
, (hw
->adpa
& ~(ADPA_DPMS_CONTROL_MASK
)) | ADPA_DPMS_D3
);
1409 /* Set pipe parameters */
1410 OUTREG(hsync_reg
, *hs
);
1411 OUTREG(hblank_reg
, *hb
);
1412 OUTREG(htotal_reg
, *ht
);
1413 OUTREG(vsync_reg
, *vs
);
1414 OUTREG(vblank_reg
, *vb
);
1415 OUTREG(vtotal_reg
, *vt
);
1416 OUTREG(src_size_reg
, *ss
);
1418 switch (dinfo
->info
->var
.vmode
& (FB_VMODE_INTERLACED
|
1419 FB_VMODE_ODD_FLD_FIRST
)) {
1420 case FB_VMODE_INTERLACED
| FB_VMODE_ODD_FLD_FIRST
:
1421 OUTREG(pipe_stat_reg
, 0xFFFF | PIPESTAT_FLD_EVT_ODD_EN
);
1423 case FB_VMODE_INTERLACED
: /* even lines first */
1424 OUTREG(pipe_stat_reg
, 0xFFFF | PIPESTAT_FLD_EVT_EVEN_EN
);
1426 default: /* non-interlaced */
1427 OUTREG(pipe_stat_reg
, 0xFFFF); /* clear all status bits only */
1430 OUTREG(pipe_conf_reg
, *pipe_conf
| PIPECONF_ENABLE
);
1434 tmp
&= ~ADPA_DPMS_CONTROL_MASK
;
1435 tmp
|= ADPA_DPMS_D0
;
1438 /* setup display plane */
1439 if (dinfo
->pdev
->device
== PCI_DEVICE_ID_INTEL_830M
) {
1441 * i830M errata: the display plane must be enabled
1442 * to allow writes to the other bits in the plane
1445 tmp
= INREG(DSPACNTR
);
1446 if ((tmp
& DISPPLANE_PLANE_ENABLE
) != DISPPLANE_PLANE_ENABLE
) {
1447 tmp
|= DISPPLANE_PLANE_ENABLE
;
1448 OUTREG(DSPACNTR
, tmp
);
1450 hw
->disp_a_ctrl
|DISPPLANE_PLANE_ENABLE
);
1455 OUTREG(DSPACNTR
, hw
->disp_a_ctrl
& ~DISPPLANE_PLANE_ENABLE
);
1456 OUTREG(DSPASTRIDE
, hw
->disp_a_stride
);
1457 OUTREG(DSPABASE
, hw
->disp_a_base
);
1461 tmp
= INREG(DSPACNTR
);
1462 tmp
|= DISPPLANE_PLANE_ENABLE
;
1463 OUTREG(DSPACNTR
, tmp
);
1464 OUTREG(DSPABASE
, hw
->disp_a_base
);
1470 /* forward declarations */
1471 static void refresh_ring(struct intelfb_info
*dinfo
);
1472 static void reset_state(struct intelfb_info
*dinfo
);
1473 static void do_flush(struct intelfb_info
*dinfo
);
1475 static u32
get_ring_space(struct intelfb_info
*dinfo
)
1479 if (dinfo
->ring_tail
>= dinfo
->ring_head
)
1480 ring_space
= dinfo
->ring
.size
-
1481 (dinfo
->ring_tail
- dinfo
->ring_head
);
1483 ring_space
= dinfo
->ring_head
- dinfo
->ring_tail
;
1485 if (ring_space
> RING_MIN_FREE
)
1486 ring_space
-= RING_MIN_FREE
;
1493 static int wait_ring(struct intelfb_info
*dinfo
, int n
)
1497 u32 last_head
= INREG(PRI_RING_HEAD
) & RING_HEAD_MASK
;
1500 DBG_MSG("wait_ring: %d\n", n
);
1503 end
= jiffies
+ (HZ
* 3);
1504 while (dinfo
->ring_space
< n
) {
1505 dinfo
->ring_head
= INREG(PRI_RING_HEAD
) & RING_HEAD_MASK
;
1506 dinfo
->ring_space
= get_ring_space(dinfo
);
1508 if (dinfo
->ring_head
!= last_head
) {
1509 end
= jiffies
+ (HZ
* 3);
1510 last_head
= dinfo
->ring_head
;
1513 if (time_before(end
, jiffies
)) {
1517 refresh_ring(dinfo
);
1519 end
= jiffies
+ (HZ
* 3);
1522 WRN_MSG("ring buffer : space: %d wanted %d\n",
1523 dinfo
->ring_space
, n
);
1524 WRN_MSG("lockup - turning off hardware "
1526 dinfo
->ring_lockup
= 1;
1535 static void do_flush(struct intelfb_info
*dinfo
)
1538 OUT_RING(MI_FLUSH
| MI_WRITE_DIRTY_STATE
| MI_INVALIDATE_MAP_CACHE
);
1543 void intelfbhw_do_sync(struct intelfb_info
*dinfo
)
1546 DBG_MSG("intelfbhw_do_sync\n");
1553 * Send a flush, then wait until the ring is empty. This is what
1554 * the XFree86 driver does, and actually it doesn't seem a lot worse
1555 * than the recommended method (both have problems).
1558 wait_ring(dinfo
, dinfo
->ring
.size
- RING_MIN_FREE
);
1559 dinfo
->ring_space
= dinfo
->ring
.size
- RING_MIN_FREE
;
1562 static void refresh_ring(struct intelfb_info
*dinfo
)
1565 DBG_MSG("refresh_ring\n");
1568 dinfo
->ring_head
= INREG(PRI_RING_HEAD
) & RING_HEAD_MASK
;
1569 dinfo
->ring_tail
= INREG(PRI_RING_TAIL
) & RING_TAIL_MASK
;
1570 dinfo
->ring_space
= get_ring_space(dinfo
);
1573 static void reset_state(struct intelfb_info
*dinfo
)
1579 DBG_MSG("reset_state\n");
1582 for (i
= 0; i
< FENCE_NUM
; i
++)
1583 OUTREG(FENCE
+ (i
<< 2), 0);
1585 /* Flush the ring buffer if it's enabled. */
1586 tmp
= INREG(PRI_RING_LENGTH
);
1587 if (tmp
& RING_ENABLE
) {
1589 DBG_MSG("reset_state: ring was enabled\n");
1591 refresh_ring(dinfo
);
1592 intelfbhw_do_sync(dinfo
);
1596 OUTREG(PRI_RING_LENGTH
, 0);
1597 OUTREG(PRI_RING_HEAD
, 0);
1598 OUTREG(PRI_RING_TAIL
, 0);
1599 OUTREG(PRI_RING_START
, 0);
1602 /* Stop the 2D engine, and turn off the ring buffer. */
1603 void intelfbhw_2d_stop(struct intelfb_info
*dinfo
)
1606 DBG_MSG("intelfbhw_2d_stop: accel: %d, ring_active: %d\n",
1607 dinfo
->accel
, dinfo
->ring_active
);
1613 dinfo
->ring_active
= 0;
1618 * Enable the ring buffer, and initialise the 2D engine.
1619 * It is assumed that the graphics engine has been stopped by previously
1620 * calling intelfb_2d_stop().
1622 void intelfbhw_2d_start(struct intelfb_info
*dinfo
)
1625 DBG_MSG("intelfbhw_2d_start: accel: %d, ring_active: %d\n",
1626 dinfo
->accel
, dinfo
->ring_active
);
1632 /* Initialise the primary ring buffer. */
1633 OUTREG(PRI_RING_LENGTH
, 0);
1634 OUTREG(PRI_RING_TAIL
, 0);
1635 OUTREG(PRI_RING_HEAD
, 0);
1637 OUTREG(PRI_RING_START
, dinfo
->ring
.physical
& RING_START_MASK
);
1638 OUTREG(PRI_RING_LENGTH
,
1639 ((dinfo
->ring
.size
- GTT_PAGE_SIZE
) & RING_LENGTH_MASK
) |
1640 RING_NO_REPORT
| RING_ENABLE
);
1641 refresh_ring(dinfo
);
1642 dinfo
->ring_active
= 1;
1645 /* 2D fillrect (solid fill or invert) */
1646 void intelfbhw_do_fillrect(struct intelfb_info
*dinfo
, u32 x
, u32 y
, u32 w
,
1647 u32 h
, u32 color
, u32 pitch
, u32 bpp
, u32 rop
)
1649 u32 br00
, br09
, br13
, br14
, br16
;
1652 DBG_MSG("intelfbhw_do_fillrect: (%d,%d) %dx%d, c 0x%06x, p %d bpp %d, "
1653 "rop 0x%02x\n", x
, y
, w
, h
, color
, pitch
, bpp
, rop
);
1656 br00
= COLOR_BLT_CMD
;
1657 br09
= dinfo
->fb_start
+ (y
* pitch
+ x
* (bpp
/ 8));
1658 br13
= (rop
<< ROP_SHIFT
) | pitch
;
1659 br14
= (h
<< HEIGHT_SHIFT
) | ((w
* (bpp
/ 8)) << WIDTH_SHIFT
);
1664 br13
|= COLOR_DEPTH_8
;
1667 br13
|= COLOR_DEPTH_16
;
1670 br13
|= COLOR_DEPTH_32
;
1671 br00
|= WRITE_ALPHA
| WRITE_RGB
;
1685 DBG_MSG("ring = 0x%08x, 0x%08x (%d)\n", dinfo
->ring_head
,
1686 dinfo
->ring_tail
, dinfo
->ring_space
);
1691 intelfbhw_do_bitblt(struct intelfb_info
*dinfo
, u32 curx
, u32 cury
,
1692 u32 dstx
, u32 dsty
, u32 w
, u32 h
, u32 pitch
, u32 bpp
)
1694 u32 br00
, br09
, br11
, br12
, br13
, br22
, br23
, br26
;
1697 DBG_MSG("intelfbhw_do_bitblt: (%d,%d)->(%d,%d) %dx%d, p %d bpp %d\n",
1698 curx
, cury
, dstx
, dsty
, w
, h
, pitch
, bpp
);
1701 br00
= XY_SRC_COPY_BLT_CMD
;
1702 br09
= dinfo
->fb_start
;
1703 br11
= (pitch
<< PITCH_SHIFT
);
1704 br12
= dinfo
->fb_start
;
1705 br13
= (SRC_ROP_GXCOPY
<< ROP_SHIFT
) | (pitch
<< PITCH_SHIFT
);
1706 br22
= (dstx
<< WIDTH_SHIFT
) | (dsty
<< HEIGHT_SHIFT
);
1707 br23
= ((dstx
+ w
) << WIDTH_SHIFT
) |
1708 ((dsty
+ h
) << HEIGHT_SHIFT
);
1709 br26
= (curx
<< WIDTH_SHIFT
) | (cury
<< HEIGHT_SHIFT
);
1713 br13
|= COLOR_DEPTH_8
;
1716 br13
|= COLOR_DEPTH_16
;
1719 br13
|= COLOR_DEPTH_32
;
1720 br00
|= WRITE_ALPHA
| WRITE_RGB
;
1736 int intelfbhw_do_drawglyph(struct intelfb_info
*dinfo
, u32 fg
, u32 bg
, u32 w
,
1737 u32 h
, const u8
* cdat
, u32 x
, u32 y
, u32 pitch
,
1740 int nbytes
, ndwords
, pad
, tmp
;
1741 u32 br00
, br09
, br13
, br18
, br19
, br22
, br23
;
1742 int dat
, ix
, iy
, iw
;
1746 DBG_MSG("intelfbhw_do_drawglyph: (%d,%d) %dx%d\n", x
, y
, w
, h
);
1749 /* size in bytes of a padded scanline */
1750 nbytes
= ROUND_UP_TO(w
, 16) / 8;
1752 /* Total bytes of padded scanline data to write out. */
1753 nbytes
= nbytes
* h
;
1756 * Check if the glyph data exceeds the immediate mode limit.
1757 * It would take a large font (1K pixels) to hit this limit.
1759 if (nbytes
> MAX_MONO_IMM_SIZE
)
1762 /* Src data is packaged a dword (32-bit) at a time. */
1763 ndwords
= ROUND_UP_TO(nbytes
, 4) / 4;
1766 * Ring has to be padded to a quad word. But because the command starts
1767 with 7 bytes, pad only if there is an even number of ndwords
1769 pad
= !(ndwords
% 2);
1771 tmp
= (XY_MONO_SRC_IMM_BLT_CMD
& DW_LENGTH_MASK
) + ndwords
;
1772 br00
= (XY_MONO_SRC_IMM_BLT_CMD
& ~DW_LENGTH_MASK
) | tmp
;
1773 br09
= dinfo
->fb_start
;
1774 br13
= (SRC_ROP_GXCOPY
<< ROP_SHIFT
) | (pitch
<< PITCH_SHIFT
);
1777 br22
= (x
<< WIDTH_SHIFT
) | (y
<< HEIGHT_SHIFT
);
1778 br23
= ((x
+ w
) << WIDTH_SHIFT
) | ((y
+ h
) << HEIGHT_SHIFT
);
1782 br13
|= COLOR_DEPTH_8
;
1785 br13
|= COLOR_DEPTH_16
;
1788 br13
|= COLOR_DEPTH_32
;
1789 br00
|= WRITE_ALPHA
| WRITE_RGB
;
1793 START_RING(8 + ndwords
);
1802 iw
= ROUND_UP_TO(w
, 8) / 8;
1805 for (j
= 0; j
< 2; ++j
) {
1806 for (i
= 0; i
< 2; ++i
) {
1807 if (ix
!= iw
|| i
== 0)
1808 dat
|= cdat
[iy
*iw
+ ix
++] << (i
+j
*2)*8;
1810 if (ix
== iw
&& iy
!= (h
-1)) {
1824 /* HW cursor functions. */
1825 void intelfbhw_cursor_init(struct intelfb_info
*dinfo
)
1830 DBG_MSG("intelfbhw_cursor_init\n");
1833 if (dinfo
->mobile
|| IS_I9XX(dinfo
)) {
1834 if (!dinfo
->cursor
.physical
)
1836 tmp
= INREG(CURSOR_A_CONTROL
);
1837 tmp
&= ~(CURSOR_MODE_MASK
| CURSOR_MOBILE_GAMMA_ENABLE
|
1838 CURSOR_MEM_TYPE_LOCAL
|
1839 (1 << CURSOR_PIPE_SELECT_SHIFT
));
1840 tmp
|= CURSOR_MODE_DISABLE
;
1841 OUTREG(CURSOR_A_CONTROL
, tmp
);
1842 OUTREG(CURSOR_A_BASEADDR
, dinfo
->cursor
.physical
);
1844 tmp
= INREG(CURSOR_CONTROL
);
1845 tmp
&= ~(CURSOR_FORMAT_MASK
| CURSOR_GAMMA_ENABLE
|
1846 CURSOR_ENABLE
| CURSOR_STRIDE_MASK
);
1847 tmp
= CURSOR_FORMAT_3C
;
1848 OUTREG(CURSOR_CONTROL
, tmp
);
1849 OUTREG(CURSOR_A_BASEADDR
, dinfo
->cursor
.offset
<< 12);
1850 tmp
= (64 << CURSOR_SIZE_H_SHIFT
) |
1851 (64 << CURSOR_SIZE_V_SHIFT
);
1852 OUTREG(CURSOR_SIZE
, tmp
);
1856 void intelfbhw_cursor_hide(struct intelfb_info
*dinfo
)
1861 DBG_MSG("intelfbhw_cursor_hide\n");
1864 dinfo
->cursor_on
= 0;
1865 if (dinfo
->mobile
|| IS_I9XX(dinfo
)) {
1866 if (!dinfo
->cursor
.physical
)
1868 tmp
= INREG(CURSOR_A_CONTROL
);
1869 tmp
&= ~CURSOR_MODE_MASK
;
1870 tmp
|= CURSOR_MODE_DISABLE
;
1871 OUTREG(CURSOR_A_CONTROL
, tmp
);
1873 OUTREG(CURSOR_A_BASEADDR
, dinfo
->cursor
.physical
);
1875 tmp
= INREG(CURSOR_CONTROL
);
1876 tmp
&= ~CURSOR_ENABLE
;
1877 OUTREG(CURSOR_CONTROL
, tmp
);
1881 void intelfbhw_cursor_show(struct intelfb_info
*dinfo
)
1886 DBG_MSG("intelfbhw_cursor_show\n");
1889 dinfo
->cursor_on
= 1;
1891 if (dinfo
->cursor_blanked
)
1894 if (dinfo
->mobile
|| IS_I9XX(dinfo
)) {
1895 if (!dinfo
->cursor
.physical
)
1897 tmp
= INREG(CURSOR_A_CONTROL
);
1898 tmp
&= ~CURSOR_MODE_MASK
;
1899 tmp
|= CURSOR_MODE_64_4C_AX
;
1900 OUTREG(CURSOR_A_CONTROL
, tmp
);
1902 OUTREG(CURSOR_A_BASEADDR
, dinfo
->cursor
.physical
);
1904 tmp
= INREG(CURSOR_CONTROL
);
1905 tmp
|= CURSOR_ENABLE
;
1906 OUTREG(CURSOR_CONTROL
, tmp
);
1910 void intelfbhw_cursor_setpos(struct intelfb_info
*dinfo
, int x
, int y
)
1915 DBG_MSG("intelfbhw_cursor_setpos: (%d, %d)\n", x
, y
);
1919 * Sets the position. The coordinates are assumed to already
1920 * have any offset adjusted. Assume that the cursor is never
1921 * completely off-screen, and that x, y are always >= 0.
1924 tmp
= ((x
& CURSOR_POS_MASK
) << CURSOR_X_SHIFT
) |
1925 ((y
& CURSOR_POS_MASK
) << CURSOR_Y_SHIFT
);
1926 OUTREG(CURSOR_A_POSITION
, tmp
);
1929 OUTREG(CURSOR_A_BASEADDR
, dinfo
->cursor
.physical
);
1932 void intelfbhw_cursor_setcolor(struct intelfb_info
*dinfo
, u32 bg
, u32 fg
)
1935 DBG_MSG("intelfbhw_cursor_setcolor\n");
1938 OUTREG(CURSOR_A_PALETTE0
, bg
& CURSOR_PALETTE_MASK
);
1939 OUTREG(CURSOR_A_PALETTE1
, fg
& CURSOR_PALETTE_MASK
);
1940 OUTREG(CURSOR_A_PALETTE2
, fg
& CURSOR_PALETTE_MASK
);
1941 OUTREG(CURSOR_A_PALETTE3
, bg
& CURSOR_PALETTE_MASK
);
1944 void intelfbhw_cursor_load(struct intelfb_info
*dinfo
, int width
, int height
,
1947 u8 __iomem
*addr
= (u8 __iomem
*)dinfo
->cursor
.virtual;
1948 int i
, j
, w
= width
/ 8;
1949 int mod
= width
% 8, t_mask
, d_mask
;
1952 DBG_MSG("intelfbhw_cursor_load\n");
1955 if (!dinfo
->cursor
.virtual)
1958 t_mask
= 0xff >> mod
;
1959 d_mask
= ~(0xff >> mod
);
1960 for (i
= height
; i
--; ) {
1961 for (j
= 0; j
< w
; j
++) {
1962 writeb(0x00, addr
+ j
);
1963 writeb(*(data
++), addr
+ j
+8);
1966 writeb(t_mask
, addr
+ j
);
1967 writeb(*(data
++) & d_mask
, addr
+ j
+8);
1973 void intelfbhw_cursor_reset(struct intelfb_info
*dinfo
)
1975 u8 __iomem
*addr
= (u8 __iomem
*)dinfo
->cursor
.virtual;
1979 DBG_MSG("intelfbhw_cursor_reset\n");
1982 if (!dinfo
->cursor
.virtual)
1985 for (i
= 64; i
--; ) {
1986 for (j
= 0; j
< 8; j
++) {
1987 writeb(0xff, addr
+ j
+0);
1988 writeb(0x00, addr
+ j
+8);
1994 static irqreturn_t
intelfbhw_irq(int irq
, void *dev_id
)
1997 struct intelfb_info
*dinfo
= dev_id
;
1999 spin_lock(&dinfo
->int_lock
);
2002 if (dinfo
->info
->var
.vmode
& FB_VMODE_INTERLACED
)
2003 tmp
&= PIPE_A_EVENT_INTERRUPT
;
2005 tmp
&= VSYNC_PIPE_A_INTERRUPT
; /* non-interlaced */
2008 spin_unlock(&dinfo
->int_lock
);
2009 return IRQ_RETVAL(0); /* not us */
2012 /* clear status bits 0-15 ASAP and don't touch bits 16-31 */
2013 OUTREG(PIPEASTAT
, INREG(PIPEASTAT
));
2016 if (dinfo
->vsync
.pan_display
) {
2017 dinfo
->vsync
.pan_display
= 0;
2018 OUTREG(DSPABASE
, dinfo
->vsync
.pan_offset
);
2021 dinfo
->vsync
.count
++;
2022 wake_up_interruptible(&dinfo
->vsync
.wait
);
2024 spin_unlock(&dinfo
->int_lock
);
2026 return IRQ_RETVAL(1);
2029 int intelfbhw_enable_irq(struct intelfb_info
*dinfo
)
2032 if (!test_and_set_bit(0, &dinfo
->irq_flags
)) {
2033 if (request_irq(dinfo
->pdev
->irq
, intelfbhw_irq
, IRQF_SHARED
,
2034 "intelfb", dinfo
)) {
2035 clear_bit(0, &dinfo
->irq_flags
);
2039 spin_lock_irq(&dinfo
->int_lock
);
2040 OUTREG16(HWSTAM
, 0xfffe); /* i830 DRM uses ffff */
2043 spin_lock_irq(&dinfo
->int_lock
);
2045 if (dinfo
->info
->var
.vmode
& FB_VMODE_INTERLACED
)
2046 tmp
= PIPE_A_EVENT_INTERRUPT
;
2048 tmp
= VSYNC_PIPE_A_INTERRUPT
; /* non-interlaced */
2049 if (tmp
!= INREG16(IER
)) {
2050 DBG_MSG("changing IER to 0x%X\n", tmp
);
2054 spin_unlock_irq(&dinfo
->int_lock
);
2058 void intelfbhw_disable_irq(struct intelfb_info
*dinfo
)
2060 if (test_and_clear_bit(0, &dinfo
->irq_flags
)) {
2061 if (dinfo
->vsync
.pan_display
) {
2062 dinfo
->vsync
.pan_display
= 0;
2063 OUTREG(DSPABASE
, dinfo
->vsync
.pan_offset
);
2065 spin_lock_irq(&dinfo
->int_lock
);
2066 OUTREG16(HWSTAM
, 0xffff);
2067 OUTREG16(IMR
, 0xffff);
2070 OUTREG16(IIR
, INREG16(IIR
)); /* clear IRQ requests */
2071 spin_unlock_irq(&dinfo
->int_lock
);
2073 free_irq(dinfo
->pdev
->irq
, dinfo
);
2077 int intelfbhw_wait_for_vsync(struct intelfb_info
*dinfo
, u32 pipe
)
2079 struct intelfb_vsync
*vsync
;
2085 vsync
= &dinfo
->vsync
;
2091 ret
= intelfbhw_enable_irq(dinfo
);
2095 count
= vsync
->count
;
2096 ret
= wait_event_interruptible_timeout(vsync
->wait
,
2097 count
!= vsync
->count
, HZ
/ 10);
2101 DBG_MSG("wait_for_vsync timed out!\n");