2 * Geode GX display controller.
4 * Copyright (C) 2005 Arcom Control Systems Ltd.
6 * Portions from AMD's original 2.4 driver:
7 * Copyright (C) 2004 Advanced Micro Devices, Inc.
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by * the
11 * Free Software Foundation; either version 2 of the License, or * (at your
12 * option) any later version.
14 #include <linux/spinlock.h>
16 #include <linux/delay.h>
18 #include <asm/div64.h>
19 #include <asm/delay.h>
20 #include <linux/cs5535.h>
24 unsigned int gx_frame_buffer_size(void)
28 if (!cs5535_has_vsa2()) {
31 /* The number of pages is (PMAX - PMIN)+1 */
32 rdmsr(MSR_GLIU_P2D_RO0
, lo
, hi
);
35 val
= ((hi
& 0xff) << 12) | ((lo
& 0xfff00000) >> 20);
37 val
-= (lo
& 0x000fffff);
40 /* The page size is 4k */
44 /* FB size can be obtained from the VSA II */
45 /* Virtual register class = 0x02 */
46 /* VG_MEM_SIZE(512Kb units) = 0x00 */
48 outw(VSA_VR_UNLOCK
, VSA_VRC_INDEX
);
49 outw(VSA_VR_MEM_SIZE
, VSA_VRC_INDEX
);
51 val
= (unsigned int)(inw(VSA_VRC_DATA
)) & 0xFFl
;
55 int gx_line_delta(int xres
, int bpp
)
57 /* Must be a multiple of 8 bytes. */
58 return (xres
* (bpp
>> 3) + 7) & ~0x7;
61 void gx_set_mode(struct fb_info
*info
)
63 struct gxfb_par
*par
= info
->par
;
65 int hactive
, hblankstart
, hsyncstart
, hsyncend
, hblankend
, htotal
;
66 int vactive
, vblankstart
, vsyncstart
, vsyncend
, vblankend
, vtotal
;
68 /* Unlock the display controller registers. */
69 write_dc(par
, DC_UNLOCK
, DC_UNLOCK_UNLOCK
);
71 gcfg
= read_dc(par
, DC_GENERAL_CFG
);
72 dcfg
= read_dc(par
, DC_DISPLAY_CFG
);
74 /* Disable the timing generator. */
75 dcfg
&= ~DC_DISPLAY_CFG_TGEN
;
76 write_dc(par
, DC_DISPLAY_CFG
, dcfg
);
78 /* Wait for pending memory requests before disabling the FIFO load. */
81 /* Disable FIFO load and compression. */
82 gcfg
&= ~(DC_GENERAL_CFG_DFLE
| DC_GENERAL_CFG_CMPE
|
84 write_dc(par
, DC_GENERAL_CFG
, gcfg
);
86 /* Setup DCLK and its divisor. */
87 gx_set_dclk_frequency(info
);
93 /* Clear all unused feature bits. */
94 gcfg
&= DC_GENERAL_CFG_YUVM
| DC_GENERAL_CFG_VDSE
;
97 /* Set FIFO priority (default 6/5) and enable. */
98 gcfg
|= (6 << DC_GENERAL_CFG_DFHPEL_SHIFT
) |
99 (5 << DC_GENERAL_CFG_DFHPSL_SHIFT
) | DC_GENERAL_CFG_DFLE
;
101 /* Framebuffer start offset. */
102 write_dc(par
, DC_FB_ST_OFFSET
, 0);
104 /* Line delta and line buffer length. */
105 write_dc(par
, DC_GFX_PITCH
, info
->fix
.line_length
>> 3);
106 write_dc(par
, DC_LINE_SIZE
,
107 ((info
->var
.xres
* info
->var
.bits_per_pixel
/8) >> 3) + 2);
110 /* Enable graphics and video data and unmask address lines. */
111 dcfg
|= DC_DISPLAY_CFG_GDEN
| DC_DISPLAY_CFG_VDEN
|
112 DC_DISPLAY_CFG_A20M
| DC_DISPLAY_CFG_A18M
;
114 /* Set pixel format. */
115 switch (info
->var
.bits_per_pixel
) {
117 dcfg
|= DC_DISPLAY_CFG_DISP_MODE_8BPP
;
120 dcfg
|= DC_DISPLAY_CFG_DISP_MODE_16BPP
;
123 dcfg
|= DC_DISPLAY_CFG_DISP_MODE_24BPP
;
124 dcfg
|= DC_DISPLAY_CFG_PALB
;
128 /* Enable timing generator. */
129 dcfg
|= DC_DISPLAY_CFG_TGEN
;
131 /* Horizontal and vertical timings. */
132 hactive
= info
->var
.xres
;
133 hblankstart
= hactive
;
134 hsyncstart
= hblankstart
+ info
->var
.right_margin
;
135 hsyncend
= hsyncstart
+ info
->var
.hsync_len
;
136 hblankend
= hsyncend
+ info
->var
.left_margin
;
139 vactive
= info
->var
.yres
;
140 vblankstart
= vactive
;
141 vsyncstart
= vblankstart
+ info
->var
.lower_margin
;
142 vsyncend
= vsyncstart
+ info
->var
.vsync_len
;
143 vblankend
= vsyncend
+ info
->var
.upper_margin
;
146 write_dc(par
, DC_H_ACTIVE_TIMING
, (hactive
- 1) |
147 ((htotal
- 1) << 16));
148 write_dc(par
, DC_H_BLANK_TIMING
, (hblankstart
- 1) |
149 ((hblankend
- 1) << 16));
150 write_dc(par
, DC_H_SYNC_TIMING
, (hsyncstart
- 1) |
151 ((hsyncend
- 1) << 16));
153 write_dc(par
, DC_V_ACTIVE_TIMING
, (vactive
- 1) |
154 ((vtotal
- 1) << 16));
155 write_dc(par
, DC_V_BLANK_TIMING
, (vblankstart
- 1) |
156 ((vblankend
- 1) << 16));
157 write_dc(par
, DC_V_SYNC_TIMING
, (vsyncstart
- 1) |
158 ((vsyncend
- 1) << 16));
160 /* Write final register values. */
161 write_dc(par
, DC_DISPLAY_CFG
, dcfg
);
162 write_dc(par
, DC_GENERAL_CFG
, gcfg
);
164 gx_configure_display(info
);
166 /* Relock display controller registers */
167 write_dc(par
, DC_UNLOCK
, DC_UNLOCK_LOCK
);
170 void gx_set_hw_palette_reg(struct fb_info
*info
, unsigned regno
,
171 unsigned red
, unsigned green
, unsigned blue
)
173 struct gxfb_par
*par
= info
->par
;
176 /* Hardware palette is in RGB 8-8-8 format. */
177 val
= (red
<< 8) & 0xff0000;
178 val
|= (green
) & 0x00ff00;
179 val
|= (blue
>> 8) & 0x0000ff;
181 write_dc(par
, DC_PAL_ADDRESS
, regno
);
182 write_dc(par
, DC_PAL_DATA
, val
);