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GUI: Fix Tomato RAF theme for all builds. Compilation typo.
[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / drivers / usb / musb / tusb6010.c
blobaf458b97592bc8b42d4774648167c91c7ccb7d6e
1 /*
2 * TUSB6010 USB 2.0 OTG Dual Role controller
3 *
4 * Copyright (C) 2006 Nokia Corporation
5 * Tony Lindgren <tony@atomide.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * Notes:
12 * - Driver assumes that interface to external host (main CPU) is
13 * configured for NOR FLASH interface instead of VLYNQ serial
14 * interface.
15 */
16
17 #include <linux/module.h>
18 #include <linux/kernel.h>
19 #include <linux/errno.h>
20 #include <linux/init.h>
21 #include <linux/usb.h>
22 #include <linux/irq.h>
23 #include <linux/platform_device.h>
24
25 #include "musb_core.h"
26
27 static void tusb_source_power(struct musb *musb, int is_on);
28
29 #define TUSB_REV_MAJOR(reg_val) ((reg_val >> 4) & 0xf)
30 #define TUSB_REV_MINOR(reg_val) (reg_val & 0xf)
31
32 /*
33 * Checks the revision. We need to use the DMA register as 3.0 does not
34 * have correct versions for TUSB_PRCM_REV or TUSB_INT_CTRL_REV.
35 */
36 u8 tusb_get_revision(struct musb *musb)
37 {
38 void __iomem *tbase = musb->ctrl_base;
39 u32 die_id;
40 u8 rev;
41
42 rev = musb_readl(tbase, TUSB_DMA_CTRL_REV) & 0xff;
43 if (TUSB_REV_MAJOR(rev) == 3) {
44 die_id = TUSB_DIDR1_HI_CHIP_REV(musb_readl(tbase,
45 TUSB_DIDR1_HI));
46 if (die_id >= TUSB_DIDR1_HI_REV_31)
47 rev |= 1;
48 }
49
50 return rev;
51 }
52
53 static int __init tusb_print_revision(struct musb *musb)
54 {
55 void __iomem *tbase = musb->ctrl_base;
56 u8 rev;
57
58 rev = tusb_get_revision(musb);
59
60 pr_info("tusb: %s%i.%i %s%i.%i %s%i.%i %s%i.%i %s%i %s%i.%i\n",
61 "prcm",
62 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_PRCM_REV)),
63 TUSB_REV_MINOR(musb_readl(tbase, TUSB_PRCM_REV)),
64 "int",
65 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_INT_CTRL_REV)),
66 TUSB_REV_MINOR(musb_readl(tbase, TUSB_INT_CTRL_REV)),
67 "gpio",
68 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_GPIO_REV)),
69 TUSB_REV_MINOR(musb_readl(tbase, TUSB_GPIO_REV)),
70 "dma",
71 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_DMA_CTRL_REV)),
72 TUSB_REV_MINOR(musb_readl(tbase, TUSB_DMA_CTRL_REV)),
73 "dieid",
74 TUSB_DIDR1_HI_CHIP_REV(musb_readl(tbase, TUSB_DIDR1_HI)),
75 "rev",
76 TUSB_REV_MAJOR(rev), TUSB_REV_MINOR(rev));
77
78 return tusb_get_revision(musb);
79 }
80
81 #define WBUS_QUIRK_MASK (TUSB_PHY_OTG_CTRL_TESTM2 | TUSB_PHY_OTG_CTRL_TESTM1 \
82 | TUSB_PHY_OTG_CTRL_TESTM0)
83
84 static void tusb_wbus_quirk(struct musb *musb, int enabled)
85 {
86 void __iomem *tbase = musb->ctrl_base;
87 static u32 phy_otg_ctrl, phy_otg_ena;
88 u32 tmp;
89
90 if (enabled) {
91 phy_otg_ctrl = musb_readl(tbase, TUSB_PHY_OTG_CTRL);
92 phy_otg_ena = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);
93 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT
94 | phy_otg_ena | WBUS_QUIRK_MASK;
95 musb_writel(tbase, TUSB_PHY_OTG_CTRL, tmp);
96 tmp = phy_otg_ena & ~WBUS_QUIRK_MASK;
97 tmp |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_TESTM2;
98 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp);
99 DBG(2, "Enabled tusb wbus quirk ctrl %08x ena %08x\n",
100 musb_readl(tbase, TUSB_PHY_OTG_CTRL),
101 musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE));
102 } else if (musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE)
103 & TUSB_PHY_OTG_CTRL_TESTM2) {
104 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ctrl;
105 musb_writel(tbase, TUSB_PHY_OTG_CTRL, tmp);
106 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ena;
107 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp);
108 DBG(2, "Disabled tusb wbus quirk ctrl %08x ena %08x\n",
109 musb_readl(tbase, TUSB_PHY_OTG_CTRL),
110 musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE));
111 phy_otg_ctrl = 0;
112 phy_otg_ena = 0;
113 }
114 }
115
116 /*
117 * TUSB 6010 may use a parallel bus that doesn't support byte ops;
118 * so both loading and unloading FIFOs need explicit byte counts.
119 */
120
121 static inline void
122 tusb_fifo_write_unaligned(void __iomem *fifo, const u8 *buf, u16 len)
123 {
124 u32 val;
125 int i;
126
127 if (len > 4) {
128 for (i = 0; i < (len >> 2); i++) {
129 memcpy(&val, buf, 4);
130 musb_writel(fifo, 0, val);
131 buf += 4;
132 }
133 len %= 4;
134 }
135 if (len > 0) {
136 /* Write the rest 1 - 3 bytes to FIFO */
137 memcpy(&val, buf, len);
138 musb_writel(fifo, 0, val);
139 }
140 }
141
142 static inline void tusb_fifo_read_unaligned(void __iomem *fifo,
143 void __iomem *buf, u16 len)
144 {
145 u32 val;
146 int i;
147
148 if (len > 4) {
149 for (i = 0; i < (len >> 2); i++) {
150 val = musb_readl(fifo, 0);
151 memcpy(buf, &val, 4);
152 buf += 4;
153 }
154 len %= 4;
155 }
156 if (len > 0) {
157 /* Read the rest 1 - 3 bytes from FIFO */
158 val = musb_readl(fifo, 0);
159 memcpy(buf, &val, len);
160 }
161 }
162
163 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *buf)
164 {
165 void __iomem *ep_conf = hw_ep->conf;
166 void __iomem *fifo = hw_ep->fifo;
167 u8 epnum = hw_ep->epnum;
168
169 prefetch(buf);
170
171 DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
172 'T', epnum, fifo, len, buf);
173
174 if (epnum)
175 musb_writel(ep_conf, TUSB_EP_TX_OFFSET,
176 TUSB_EP_CONFIG_XFR_SIZE(len));
177 else
178 musb_writel(ep_conf, 0, TUSB_EP0_CONFIG_DIR_TX |
179 TUSB_EP0_CONFIG_XFR_SIZE(len));
180
181 if (likely((0x01 & (unsigned long) buf) == 0)) {
182
183 /* Best case is 32bit-aligned destination address */
184 if ((0x02 & (unsigned long) buf) == 0) {
185 if (len >= 4) {
186 writesl(fifo, buf, len >> 2);
187 buf += (len & ~0x03);
188 len &= 0x03;
189 }
190 } else {
191 if (len >= 2) {
192 u32 val;
193 int i;
194
195 /* Cannot use writesw, fifo is 32-bit */
196 for (i = 0; i < (len >> 2); i++) {
197 val = (u32)(*(u16 *)buf);
198 buf += 2;
199 val |= (*(u16 *)buf) << 16;
200 buf += 2;
201 musb_writel(fifo, 0, val);
202 }
203 len &= 0x03;
204 }
205 }
206 }
207
208 if (len > 0)
209 tusb_fifo_write_unaligned(fifo, buf, len);
210 }
211
212 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *buf)
213 {
214 void __iomem *ep_conf = hw_ep->conf;
215 void __iomem *fifo = hw_ep->fifo;
216 u8 epnum = hw_ep->epnum;
217
218 DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
219 'R', epnum, fifo, len, buf);
220
221 if (epnum)
222 musb_writel(ep_conf, TUSB_EP_RX_OFFSET,
223 TUSB_EP_CONFIG_XFR_SIZE(len));
224 else
225 musb_writel(ep_conf, 0, TUSB_EP0_CONFIG_XFR_SIZE(len));
226
227 if (likely((0x01 & (unsigned long) buf) == 0)) {
228
229 /* Best case is 32bit-aligned destination address */
230 if ((0x02 & (unsigned long) buf) == 0) {
231 if (len >= 4) {
232 readsl(fifo, buf, len >> 2);
233 buf += (len & ~0x03);
234 len &= 0x03;
235 }
236 } else {
237 if (len >= 2) {
238 u32 val;
239 int i;
240
241 /* Cannot use readsw, fifo is 32-bit */
242 for (i = 0; i < (len >> 2); i++) {
243 val = musb_readl(fifo, 0);
244 *(u16 *)buf = (u16)(val & 0xffff);
245 buf += 2;
246 *(u16 *)buf = (u16)(val >> 16);
247 buf += 2;
248 }
249 len &= 0x03;
250 }
251 }
252 }
253
254 if (len > 0)
255 tusb_fifo_read_unaligned(fifo, buf, len);
256 }
257
258 static struct musb *the_musb;
259
260 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
261
262 /* This is used by gadget drivers, and OTG transceiver logic, allowing
263 * at most mA current to be drawn from VBUS during a Default-B session
264 * (that is, while VBUS exceeds 4.4V). In Default-A (including pure host
265 * mode), or low power Default-B sessions, something else supplies power.
266 * Caller must take care of locking.
267 */
268 static int tusb_draw_power(struct otg_transceiver *x, unsigned mA)
269 {
270 struct musb *musb = the_musb;
271 void __iomem *tbase = musb->ctrl_base;
272 u32 reg;
273
274 /*
275 * Keep clock active when enabled. Note that this is not tied to
276 * drawing VBUS, as with OTG mA can be less than musb->min_power.
277 */
278 if (musb->set_clock) {
279 if (mA)
280 musb->set_clock(musb->clock, 1);
281 else
282 musb->set_clock(musb->clock, 0);
283 }
284
285 /* tps65030 seems to consume max 100mA, with maybe 60mA available
286 * (measured on one board) for things other than tps and tusb.
287 *
288 * Boards sharing the CPU clock with CLKIN will need to prevent
289 * certain idle sleep states while the USB link is active.
290 *
291 * REVISIT we could use VBUS to supply only _one_ of { 1.5V, 3.3V }.
292 * The actual current usage would be very board-specific. For now,
293 * it's simpler to just use an aggregate (also board-specific).
294 */
295 if (x->default_a || mA < (musb->min_power << 1))
296 mA = 0;
297
298 reg = musb_readl(tbase, TUSB_PRCM_MNGMT);
299 if (mA) {
300 musb->is_bus_powered = 1;
301 reg |= TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN;
302 } else {
303 musb->is_bus_powered = 0;
304 reg &= ~(TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN);
305 }
306 musb_writel(tbase, TUSB_PRCM_MNGMT, reg);
307
308 DBG(2, "draw max %d mA VBUS\n", mA);
309 return 0;
310 }
311
312 #else
313 #define tusb_draw_power NULL
314 #endif
315
316 static void tusb_set_clock_source(struct musb *musb, unsigned mode)
317 {
318 void __iomem *tbase = musb->ctrl_base;
319 u32 reg;
320
321 reg = musb_readl(tbase, TUSB_PRCM_CONF);
322 reg &= ~TUSB_PRCM_CONF_SYS_CLKSEL(0x3);
323
324 /* 0 = refclk (clkin, XI)
325 * 1 = PHY 60 MHz (internal PLL)
326 * 2 = not supported
327 * 3 = what?
328 */
329 if (mode > 0)
330 reg |= TUSB_PRCM_CONF_SYS_CLKSEL(mode & 0x3);
331
332 musb_writel(tbase, TUSB_PRCM_CONF, reg);
333
334 }
335
336 /*
337 * Idle TUSB6010 until next wake-up event; NOR access always wakes.
338 * Other code ensures that we idle unless we're connected _and_ the
339 * USB link is not suspended ... and tells us the relevant wakeup
340 * events. SW_EN for voltage is handled separately.
341 */
342 void tusb_allow_idle(struct musb *musb, u32 wakeup_enables)
343 {
344 void __iomem *tbase = musb->ctrl_base;
345 u32 reg;
346
347 if ((wakeup_enables & TUSB_PRCM_WBUS)
348 && (tusb_get_revision(musb) == TUSB_REV_30))
349 tusb_wbus_quirk(musb, 1);
350
351 tusb_set_clock_source(musb, 0);
352
353 wakeup_enables |= TUSB_PRCM_WNORCS;
354 musb_writel(tbase, TUSB_PRCM_WAKEUP_MASK, ~wakeup_enables);
355
356 /* REVISIT writeup of WID implies that if WID set and ID is grounded,
357 * TUSB_PHY_OTG_CTRL.TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP must be cleared.
358 * Presumably that's mostly to save power, hence WID is immaterial ...
359 */
360
361 reg = musb_readl(tbase, TUSB_PRCM_MNGMT);
362 /* issue 4: when driving vbus, use hipower (vbus_det) comparator */
363 if (is_host_active(musb)) {
364 reg |= TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN;
365 reg &= ~TUSB_PRCM_MNGMT_OTG_SESS_END_EN;
366 } else {
367 reg |= TUSB_PRCM_MNGMT_OTG_SESS_END_EN;
368 reg &= ~TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN;
369 }
370 reg |= TUSB_PRCM_MNGMT_PM_IDLE | TUSB_PRCM_MNGMT_DEV_IDLE;
371 musb_writel(tbase, TUSB_PRCM_MNGMT, reg);
372
373 DBG(6, "idle, wake on %02x\n", wakeup_enables);
374 }
375
376 /*
377 * Updates cable VBUS status. Caller must take care of locking.
378 */
379 int musb_platform_get_vbus_status(struct musb *musb)
380 {
381 void __iomem *tbase = musb->ctrl_base;
382 u32 otg_stat, prcm_mngmt;
383 int ret = 0;
384
385 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
386 prcm_mngmt = musb_readl(tbase, TUSB_PRCM_MNGMT);
387
388 /* Temporarily enable VBUS detection if it was disabled for
389 * suspend mode. Unless it's enabled otg_stat and devctl will
390 * not show correct VBUS state.
391 */
392 if (!(prcm_mngmt & TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN)) {
393 u32 tmp = prcm_mngmt;
394 tmp |= TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN;
395 musb_writel(tbase, TUSB_PRCM_MNGMT, tmp);
396 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
397 musb_writel(tbase, TUSB_PRCM_MNGMT, prcm_mngmt);
398 }
399
400 if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID)
401 ret = 1;
402
403 return ret;
404 }
405
406 static struct timer_list musb_idle_timer;
407
408 static void musb_do_idle(unsigned long _musb)
409 {
410 struct musb *musb = (void *)_musb;
411 unsigned long flags;
412
413 spin_lock_irqsave(&musb->lock, flags);
414
415 switch (musb->xceiv->state) {
416 case OTG_STATE_A_WAIT_BCON:
417 if ((musb->a_wait_bcon != 0)
418 && (musb->idle_timeout == 0
419 || time_after(jiffies, musb->idle_timeout))) {
420 DBG(4, "Nothing connected %s, turning off VBUS\n",
421 otg_state_string(musb));
422 }
423 /* FALLTHROUGH */
424 case OTG_STATE_A_IDLE:
425 tusb_source_power(musb, 0);
426 default:
427 break;
428 }
429
430 if (!musb->is_active) {
431 u32 wakeups;
432
433 /* wait until khubd handles port change status */
434 if (is_host_active(musb) && (musb->port1_status >> 16))
435 goto done;
436
437 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
438 if (is_peripheral_enabled(musb) && !musb->gadget_driver)
439 wakeups = 0;
440 else {
441 wakeups = TUSB_PRCM_WHOSTDISCON
442 | TUSB_PRCM_WBUS
443 | TUSB_PRCM_WVBUS;
444 if (is_otg_enabled(musb))
445 wakeups |= TUSB_PRCM_WID;
446 }
447 #else
448 wakeups = TUSB_PRCM_WHOSTDISCON | TUSB_PRCM_WBUS;
449 #endif
450 tusb_allow_idle(musb, wakeups);
451 }
452 done:
453 spin_unlock_irqrestore(&musb->lock, flags);
454 }
455
456 /*
457 * Maybe put TUSB6010 into idle mode mode depending on USB link status,
458 * like "disconnected" or "suspended". We'll be woken out of it by
459 * connect, resume, or disconnect.
460 *
461 * Needs to be called as the last function everywhere where there is
462 * register access to TUSB6010 because of NOR flash wake-up.
463 * Caller should own controller spinlock.
464 *
465 * Delay because peripheral enables D+ pullup 3msec after SE0, and
466 * we don't want to treat that full speed J as a wakeup event.
467 * ... peripherals must draw only suspend current after 10 msec.
468 */
469 void musb_platform_try_idle(struct musb *musb, unsigned long timeout)
470 {
471 unsigned long default_timeout = jiffies + msecs_to_jiffies(3);
472 static unsigned long last_timer;
473
474 if (timeout == 0)
475 timeout = default_timeout;
476
477 /* Never idle if active, or when VBUS timeout is not set as host */
478 if (musb->is_active || ((musb->a_wait_bcon == 0)
479 && (musb->xceiv->state == OTG_STATE_A_WAIT_BCON))) {
480 DBG(4, "%s active, deleting timer\n", otg_state_string(musb));
481 del_timer(&musb_idle_timer);
482 last_timer = jiffies;
483 return;
484 }
485
486 if (time_after(last_timer, timeout)) {
487 if (!timer_pending(&musb_idle_timer))
488 last_timer = timeout;
489 else {
490 DBG(4, "Longer idle timer already pending, ignoring\n");
491 return;
492 }
493 }
494 last_timer = timeout;
495
496 DBG(4, "%s inactive, for idle timer for %lu ms\n",
497 otg_state_string(musb),
498 (unsigned long)jiffies_to_msecs(timeout - jiffies));
499 mod_timer(&musb_idle_timer, timeout);
500 }
501
502 /* ticks of 60 MHz clock */
503 #define DEVCLOCK 60000000
504 #define OTG_TIMER_MS(msecs) ((msecs) \
505 ? (TUSB_DEV_OTG_TIMER_VAL((DEVCLOCK/1000)*(msecs)) \
506 | TUSB_DEV_OTG_TIMER_ENABLE) \
507 : 0)
508
509 static void tusb_source_power(struct musb *musb, int is_on)
510 {
511 void __iomem *tbase = musb->ctrl_base;
512 u32 conf, prcm, timer;
513 u8 devctl;
514
515 /* HDRC controls CPEN, but beware current surges during device
516 * connect. They can trigger transient overcurrent conditions
517 * that must be ignored.
518 */
519
520 prcm = musb_readl(tbase, TUSB_PRCM_MNGMT);
521 conf = musb_readl(tbase, TUSB_DEV_CONF);
522 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
523
524 if (is_on) {
525 if (musb->set_clock)
526 musb->set_clock(musb->clock, 1);
527 timer = OTG_TIMER_MS(OTG_TIME_A_WAIT_VRISE);
528 musb->xceiv->default_a = 1;
529 musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
530 devctl |= MUSB_DEVCTL_SESSION;
531
532 conf |= TUSB_DEV_CONF_USB_HOST_MODE;
533 MUSB_HST_MODE(musb);
534 } else {
535 u32 otg_stat;
536
537 timer = 0;
538
539 /* If ID pin is grounded, we want to be a_idle */
540 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
541 if (!(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS)) {
542 switch (musb->xceiv->state) {
543 case OTG_STATE_A_WAIT_VRISE:
544 case OTG_STATE_A_WAIT_BCON:
545 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
546 break;
547 case OTG_STATE_A_WAIT_VFALL:
548 musb->xceiv->state = OTG_STATE_A_IDLE;
549 break;
550 default:
551 musb->xceiv->state = OTG_STATE_A_IDLE;
552 }
553 musb->is_active = 0;
554 musb->xceiv->default_a = 1;
555 MUSB_HST_MODE(musb);
556 } else {
557 musb->is_active = 0;
558 musb->xceiv->default_a = 0;
559 musb->xceiv->state = OTG_STATE_B_IDLE;
560 MUSB_DEV_MODE(musb);
561 }
562
563 devctl &= ~MUSB_DEVCTL_SESSION;
564 conf &= ~TUSB_DEV_CONF_USB_HOST_MODE;
565 if (musb->set_clock)
566 musb->set_clock(musb->clock, 0);
567 }
568 prcm &= ~(TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN);
569
570 musb_writel(tbase, TUSB_PRCM_MNGMT, prcm);
571 musb_writel(tbase, TUSB_DEV_OTG_TIMER, timer);
572 musb_writel(tbase, TUSB_DEV_CONF, conf);
573 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
574
575 DBG(1, "VBUS %s, devctl %02x otg %3x conf %08x prcm %08x\n",
576 otg_state_string(musb),
577 musb_readb(musb->mregs, MUSB_DEVCTL),
578 musb_readl(tbase, TUSB_DEV_OTG_STAT),
579 conf, prcm);
580 }
581
582 /*
583 * Sets the mode to OTG, peripheral or host by changing the ID detection.
584 * Caller must take care of locking.
585 *
586 * Note that if a mini-A cable is plugged in the ID line will stay down as
587 * the weak ID pull-up is not able to pull the ID up.
588 *
589 * REVISIT: It would be possible to add support for changing between host
590 * and peripheral modes in non-OTG configurations by reconfiguring hardware
591 * and then setting musb->board_mode. For now, only support OTG mode.
592 */
593 int musb_platform_set_mode(struct musb *musb, u8 musb_mode)
594 {
595 void __iomem *tbase = musb->ctrl_base;
596 u32 otg_stat, phy_otg_ctrl, phy_otg_ena, dev_conf;
597
598 if (musb->board_mode != MUSB_OTG) {
599 ERR("Changing mode currently only supported in OTG mode\n");
600 return -EINVAL;
601 }
602
603 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
604 phy_otg_ctrl = musb_readl(tbase, TUSB_PHY_OTG_CTRL);
605 phy_otg_ena = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);
606 dev_conf = musb_readl(tbase, TUSB_DEV_CONF);
607
608 switch (musb_mode) {
609
610 #ifdef CONFIG_USB_MUSB_HDRC_HCD
611 case MUSB_HOST: /* Disable PHY ID detect, ground ID */
612 phy_otg_ctrl &= ~TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
613 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
614 dev_conf |= TUSB_DEV_CONF_ID_SEL;
615 dev_conf &= ~TUSB_DEV_CONF_SOFT_ID;
616 break;
617 #endif
618
619 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
620 case MUSB_PERIPHERAL: /* Disable PHY ID detect, keep ID pull-up on */
621 phy_otg_ctrl |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
622 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
623 dev_conf |= (TUSB_DEV_CONF_ID_SEL | TUSB_DEV_CONF_SOFT_ID);
624 break;
625 #endif
626
627 #ifdef CONFIG_USB_MUSB_OTG
628 case MUSB_OTG: /* Use PHY ID detection */
629 phy_otg_ctrl |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
630 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
631 dev_conf &= ~(TUSB_DEV_CONF_ID_SEL | TUSB_DEV_CONF_SOFT_ID);
632 break;
633 #endif
634
635 default:
636 DBG(2, "Trying to set mode %i\n", musb_mode);
637 return -EINVAL;
638 }
639
640 musb_writel(tbase, TUSB_PHY_OTG_CTRL,
641 TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ctrl);
642 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE,
643 TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ena);
644 musb_writel(tbase, TUSB_DEV_CONF, dev_conf);
645
646 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
647 if ((musb_mode == MUSB_PERIPHERAL) &&
648 !(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS))
649 INFO("Cannot be peripheral with mini-A cable "
650 "otg_stat: %08x\n", otg_stat);
651
652 return 0;
653 }
654
655 static inline unsigned long
656 tusb_otg_ints(struct musb *musb, u32 int_src, void __iomem *tbase)
657 {
658 u32 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
659 unsigned long idle_timeout = 0;
660
661 /* ID pin */
662 if ((int_src & TUSB_INT_SRC_ID_STATUS_CHNG)) {
663 int default_a;
664
665 if (is_otg_enabled(musb))
666 default_a = !(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS);
667 else
668 default_a = is_host_enabled(musb);
669 DBG(2, "Default-%c\n", default_a ? 'A' : 'B');
670 musb->xceiv->default_a = default_a;
671 tusb_source_power(musb, default_a);
672
673 /* Don't allow idling immediately */
674 if (default_a)
675 idle_timeout = jiffies + (HZ * 3);
676 }
677
678 /* VBUS state change */
679 if (int_src & TUSB_INT_SRC_VBUS_SENSE_CHNG) {
680
681 /* B-dev state machine: no vbus ~= disconnect */
682 if ((is_otg_enabled(musb) && !musb->xceiv->default_a)
683 || !is_host_enabled(musb)) {
684 #ifdef CONFIG_USB_MUSB_HDRC_HCD
685 /* ? musb_root_disconnect(musb); */
686 musb->port1_status &=
687 ~(USB_PORT_STAT_CONNECTION
688 | USB_PORT_STAT_ENABLE
689 | USB_PORT_STAT_LOW_SPEED
690 | USB_PORT_STAT_HIGH_SPEED
691 | USB_PORT_STAT_TEST
692 );
693 #endif
694
695 if (otg_stat & TUSB_DEV_OTG_STAT_SESS_END) {
696 DBG(1, "Forcing disconnect (no interrupt)\n");
697 if (musb->xceiv->state != OTG_STATE_B_IDLE) {
698 /* INTR_DISCONNECT can hide... */
699 musb->xceiv->state = OTG_STATE_B_IDLE;
700 musb->int_usb |= MUSB_INTR_DISCONNECT;
701 }
702 musb->is_active = 0;
703 }
704 DBG(2, "vbus change, %s, otg %03x\n",
705 otg_state_string(musb), otg_stat);
706 idle_timeout = jiffies + (1 * HZ);
707 schedule_work(&musb->irq_work);
708
709 } else /* A-dev state machine */ {
710 DBG(2, "vbus change, %s, otg %03x\n",
711 otg_state_string(musb), otg_stat);
712
713 switch (musb->xceiv->state) {
714 case OTG_STATE_A_IDLE:
715 DBG(2, "Got SRP, turning on VBUS\n");
716 musb_set_vbus(musb, 1);
717
718 /* CONNECT can wake if a_wait_bcon is set */
719 if (musb->a_wait_bcon != 0)
720 musb->is_active = 0;
721 else
722 musb->is_active = 1;
723
724 /*
725 * OPT FS A TD.4.6 needs few seconds for
726 * A_WAIT_VRISE
727 */
728 idle_timeout = jiffies + (2 * HZ);
729
730 break;
731 case OTG_STATE_A_WAIT_VRISE:
732 /* ignore; A-session-valid < VBUS_VALID/2,
733 * we monitor this with the timer
734 */
735 break;
736 case OTG_STATE_A_WAIT_VFALL:
737 /* REVISIT this irq triggers during short
738 * spikes caused by enumeration ...
739 */
740 if (musb->vbuserr_retry) {
741 musb->vbuserr_retry--;
742 tusb_source_power(musb, 1);
743 } else {
744 musb->vbuserr_retry
745 = VBUSERR_RETRY_COUNT;
746 tusb_source_power(musb, 0);
747 }
748 break;
749 default:
750 break;
751 }
752 }
753 }
754
755 /* OTG timer expiration */
756 if (int_src & TUSB_INT_SRC_OTG_TIMEOUT) {
757 u8 devctl;
758
759 DBG(4, "%s timer, %03x\n", otg_state_string(musb), otg_stat);
760
761 switch (musb->xceiv->state) {
762 case OTG_STATE_A_WAIT_VRISE:
763 /* VBUS has probably been valid for a while now,
764 * but may well have bounced out of range a bit
765 */
766 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
767 if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID) {
768 if ((devctl & MUSB_DEVCTL_VBUS)
769 != MUSB_DEVCTL_VBUS) {
770 DBG(2, "devctl %02x\n", devctl);
771 break;
772 }
773 musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
774 musb->is_active = 0;
775 idle_timeout = jiffies
776 + msecs_to_jiffies(musb->a_wait_bcon);
777 } else {
778 /* REVISIT report overcurrent to hub? */
779 ERR("vbus too slow, devctl %02x\n", devctl);
780 tusb_source_power(musb, 0);
781 }
782 break;
783 case OTG_STATE_A_WAIT_BCON:
784 if (musb->a_wait_bcon != 0)
785 idle_timeout = jiffies
786 + msecs_to_jiffies(musb->a_wait_bcon);
787 break;
788 case OTG_STATE_A_SUSPEND:
789 break;
790 case OTG_STATE_B_WAIT_ACON:
791 break;
792 default:
793 break;
794 }
795 }
796 schedule_work(&musb->irq_work);
797
798 return idle_timeout;
799 }
800
801 static irqreturn_t tusb_interrupt(int irq, void *__hci)
802 {
803 struct musb *musb = __hci;
804 void __iomem *tbase = musb->ctrl_base;
805 unsigned long flags, idle_timeout = 0;
806 u32 int_mask, int_src;
807
808 spin_lock_irqsave(&musb->lock, flags);
809
810 /* Mask all interrupts to allow using both edge and level GPIO irq */
811 int_mask = musb_readl(tbase, TUSB_INT_MASK);
812 musb_writel(tbase, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS);
813
814 int_src = musb_readl(tbase, TUSB_INT_SRC) & ~TUSB_INT_SRC_RESERVED_BITS;
815 DBG(3, "TUSB IRQ %08x\n", int_src);
816
817 musb->int_usb = (u8) int_src;
818
819 /* Acknowledge wake-up source interrupts */
820 if (int_src & TUSB_INT_SRC_DEV_WAKEUP) {
821 u32 reg;
822 u32 i;
823
824 if (tusb_get_revision(musb) == TUSB_REV_30)
825 tusb_wbus_quirk(musb, 0);
826
827 /* there are issues re-locking the PLL on wakeup ... */
828
829 for (i = 0xf7f7f7; i > 0xf7f7f7 - 1000; i--) {
830 musb_writel(tbase, TUSB_SCRATCH_PAD, 0);
831 musb_writel(tbase, TUSB_SCRATCH_PAD, i);
832 reg = musb_readl(tbase, TUSB_SCRATCH_PAD);
833 if (reg == i)
834 break;
835 DBG(6, "TUSB NOR not ready\n");
836 }
837
838 tusb_set_clock_source(musb, 1);
839
840 reg = musb_readl(tbase, TUSB_PRCM_WAKEUP_SOURCE);
841 musb_writel(tbase, TUSB_PRCM_WAKEUP_CLEAR, reg);
842 if (reg & ~TUSB_PRCM_WNORCS) {
843 musb->is_active = 1;
844 schedule_work(&musb->irq_work);
845 }
846 DBG(3, "wake %sactive %02x\n",
847 musb->is_active ? "" : "in", reg);
848
849 /* REVISIT host side TUSB_PRCM_WHOSTDISCON, TUSB_PRCM_WBUS */
850 }
851
852 if (int_src & TUSB_INT_SRC_USB_IP_CONN)
853 del_timer(&musb_idle_timer);
854
855 /* OTG state change reports (annoyingly) not issued by Mentor core */
856 if (int_src & (TUSB_INT_SRC_VBUS_SENSE_CHNG
857 | TUSB_INT_SRC_OTG_TIMEOUT
858 | TUSB_INT_SRC_ID_STATUS_CHNG))
859 idle_timeout = tusb_otg_ints(musb, int_src, tbase);
860
861 /* TX dma callback must be handled here, RX dma callback is
862 * handled in tusb_omap_dma_cb.
863 */
864 if ((int_src & TUSB_INT_SRC_TXRX_DMA_DONE)) {
865 u32 dma_src = musb_readl(tbase, TUSB_DMA_INT_SRC);
866 u32 real_dma_src = musb_readl(tbase, TUSB_DMA_INT_MASK);
867
868 DBG(3, "DMA IRQ %08x\n", dma_src);
869 real_dma_src = ~real_dma_src & dma_src;
870 if (tusb_dma_omap() && real_dma_src) {
871 int tx_source = (real_dma_src & 0xffff);
872 int i;
873
874 for (i = 1; i <= 15; i++) {
875 if (tx_source & (1 << i)) {
876 DBG(3, "completing ep%i %s\n", i, "tx");
877 musb_dma_completion(musb, i, 1);
878 }
879 }
880 }
881 musb_writel(tbase, TUSB_DMA_INT_CLEAR, dma_src);
882 }
883
884 /* EP interrupts. In OCP mode tusb6010 mirrors the MUSB interrupts */
885 if (int_src & (TUSB_INT_SRC_USB_IP_TX | TUSB_INT_SRC_USB_IP_RX)) {
886 u32 musb_src = musb_readl(tbase, TUSB_USBIP_INT_SRC);
887
888 musb_writel(tbase, TUSB_USBIP_INT_CLEAR, musb_src);
889 musb->int_rx = (((musb_src >> 16) & 0xffff) << 1);
890 musb->int_tx = (musb_src & 0xffff);
891 } else {
892 musb->int_rx = 0;
893 musb->int_tx = 0;
894 }
895
896 if (int_src & (TUSB_INT_SRC_USB_IP_TX | TUSB_INT_SRC_USB_IP_RX | 0xff))
897 musb_interrupt(musb);
898
899 /* Acknowledge TUSB interrupts. Clear only non-reserved bits */
900 musb_writel(tbase, TUSB_INT_SRC_CLEAR,
901 int_src & ~TUSB_INT_MASK_RESERVED_BITS);
902
903 musb_platform_try_idle(musb, idle_timeout);
904
905 musb_writel(tbase, TUSB_INT_MASK, int_mask);
906 spin_unlock_irqrestore(&musb->lock, flags);
907
908 return IRQ_HANDLED;
909 }
910
911 static int dma_off;
912
913 /*
914 * Enables TUSB6010. Caller must take care of locking.
915 * REVISIT:
916 * - Check what is unnecessary in MGC_HdrcStart()
917 */
918 void musb_platform_enable(struct musb *musb)
919 {
920 void __iomem *tbase = musb->ctrl_base;
921
922 /* Setup TUSB6010 main interrupt mask. Enable all interrupts except SOF.
923 * REVISIT: Enable and deal with TUSB_INT_SRC_USB_IP_SOF */
924 musb_writel(tbase, TUSB_INT_MASK, TUSB_INT_SRC_USB_IP_SOF);
925
926 /* Setup TUSB interrupt, disable DMA and GPIO interrupts */
927 musb_writel(tbase, TUSB_USBIP_INT_MASK, 0);
928 musb_writel(tbase, TUSB_DMA_INT_MASK, 0x7fffffff);
929 musb_writel(tbase, TUSB_GPIO_INT_MASK, 0x1ff);
930
931 /* Clear all subsystem interrups */
932 musb_writel(tbase, TUSB_USBIP_INT_CLEAR, 0x7fffffff);
933 musb_writel(tbase, TUSB_DMA_INT_CLEAR, 0x7fffffff);
934 musb_writel(tbase, TUSB_GPIO_INT_CLEAR, 0x1ff);
935
936 /* Acknowledge pending interrupt(s) */
937 musb_writel(tbase, TUSB_INT_SRC_CLEAR, ~TUSB_INT_MASK_RESERVED_BITS);
938
939 /* Only 0 clock cycles for minimum interrupt de-assertion time and
940 * interrupt polarity active low seems to work reliably here */
941 musb_writel(tbase, TUSB_INT_CTRL_CONF,
942 TUSB_INT_CTRL_CONF_INT_RELCYC(0));
943
944 set_irq_type(musb->nIrq, IRQ_TYPE_LEVEL_LOW);
945
946 /* maybe force into the Default-A OTG state machine */
947 if (!(musb_readl(tbase, TUSB_DEV_OTG_STAT)
948 & TUSB_DEV_OTG_STAT_ID_STATUS))
949 musb_writel(tbase, TUSB_INT_SRC_SET,
950 TUSB_INT_SRC_ID_STATUS_CHNG);
951
952 if (is_dma_capable() && dma_off)
953 printk(KERN_WARNING "%s %s: dma not reactivated\n",
954 __FILE__, __func__);
955 else
956 dma_off = 1;
957 }
958
959 /*
960 * Disables TUSB6010. Caller must take care of locking.
961 */
962 void musb_platform_disable(struct musb *musb)
963 {
964 void __iomem *tbase = musb->ctrl_base;
965
966
967 /* disable all IRQs */
968 musb_writel(tbase, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS);
969 musb_writel(tbase, TUSB_USBIP_INT_MASK, 0x7fffffff);
970 musb_writel(tbase, TUSB_DMA_INT_MASK, 0x7fffffff);
971 musb_writel(tbase, TUSB_GPIO_INT_MASK, 0x1ff);
972
973 del_timer(&musb_idle_timer);
974
975 if (is_dma_capable() && !dma_off) {
976 printk(KERN_WARNING "%s %s: dma still active\n",
977 __FILE__, __func__);
978 dma_off = 1;
979 }
980 }
981
982 /*
983 * Sets up TUSB6010 CPU interface specific signals and registers
984 * Note: Settings optimized for OMAP24xx
985 */
986 static void __init tusb_setup_cpu_interface(struct musb *musb)
987 {
988 void __iomem *tbase = musb->ctrl_base;
989
990 /*
991 * Disable GPIO[5:0] pullups (used as output DMA requests)
992 * Don't disable GPIO[7:6] as they are needed for wake-up.
993 */
994 musb_writel(tbase, TUSB_PULLUP_1_CTRL, 0x0000003F);
995
996 /* Disable all pullups on NOR IF, DMAREQ0 and DMAREQ1 */
997 musb_writel(tbase, TUSB_PULLUP_2_CTRL, 0x01FFFFFF);
998
999 /* Turn GPIO[5:0] to DMAREQ[5:0] signals */
1000 musb_writel(tbase, TUSB_GPIO_CONF, TUSB_GPIO_CONF_DMAREQ(0x3f));
1001
1002 /* Burst size 16x16 bits, all six DMA requests enabled, DMA request
1003 * de-assertion time 2 system clocks p 62 */
1004 musb_writel(tbase, TUSB_DMA_REQ_CONF,
1005 TUSB_DMA_REQ_CONF_BURST_SIZE(2) |
1006 TUSB_DMA_REQ_CONF_DMA_REQ_EN(0x3f) |
1007 TUSB_DMA_REQ_CONF_DMA_REQ_ASSER(2));
1008
1009 /* Set 0 wait count for synchronous burst access */
1010 musb_writel(tbase, TUSB_WAIT_COUNT, 1);
1011 }
1012
1013 static int __init tusb_start(struct musb *musb)
1014 {
1015 void __iomem *tbase = musb->ctrl_base;
1016 int ret = 0;
1017 unsigned long flags;
1018 u32 reg;
1019
1020 if (musb->board_set_power)
1021 ret = musb->board_set_power(1);
1022 if (ret != 0) {
1023 printk(KERN_ERR "tusb: Cannot enable TUSB6010\n");
1024 return ret;
1025 }
1026
1027 spin_lock_irqsave(&musb->lock, flags);
1028
1029 if (musb_readl(tbase, TUSB_PROD_TEST_RESET) !=
1030 TUSB_PROD_TEST_RESET_VAL) {
1031 printk(KERN_ERR "tusb: Unable to detect TUSB6010\n");
1032 goto err;
1033 }
1034
1035 ret = tusb_print_revision(musb);
1036 if (ret < 2) {
1037 printk(KERN_ERR "tusb: Unsupported TUSB6010 revision %i\n",
1038 ret);
1039 goto err;
1040 }
1041
1042 /* The uint bit for "USB non-PDR interrupt enable" has to be 1 when
1043 * NOR FLASH interface is used */
1044 musb_writel(tbase, TUSB_VLYNQ_CTRL, 8);
1045
1046 /* Select PHY free running 60MHz as a system clock */
1047 tusb_set_clock_source(musb, 1);
1048
1049 /* VBus valid timer 1us, disable DFT/Debug and VLYNQ clocks for
1050 * power saving, enable VBus detect and session end comparators,
1051 * enable IDpullup, enable VBus charging */
1052 musb_writel(tbase, TUSB_PRCM_MNGMT,
1053 TUSB_PRCM_MNGMT_VBUS_VALID_TIMER(0xa) |
1054 TUSB_PRCM_MNGMT_VBUS_VALID_FLT_EN |
1055 TUSB_PRCM_MNGMT_OTG_SESS_END_EN |
1056 TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN |
1057 TUSB_PRCM_MNGMT_OTG_ID_PULLUP);
1058 tusb_setup_cpu_interface(musb);
1059
1060 /* simplify: always sense/pullup ID pins, as if in OTG mode */
1061 reg = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);
1062 reg |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
1063 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, reg);
1064
1065 reg = musb_readl(tbase, TUSB_PHY_OTG_CTRL);
1066 reg |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
1067 musb_writel(tbase, TUSB_PHY_OTG_CTRL, reg);
1068
1069 spin_unlock_irqrestore(&musb->lock, flags);
1070
1071 return 0;
1072
1073 err:
1074 spin_unlock_irqrestore(&musb->lock, flags);
1075
1076 if (musb->board_set_power)
1077 musb->board_set_power(0);
1078
1079 return -ENODEV;
1080 }
1081
1082 int __init musb_platform_init(struct musb *musb, void *board_data)
1083 {
1084 struct platform_device *pdev;
1085 struct resource *mem;
1086 void __iomem *sync = NULL;
1087 int ret;
1088
1089 usb_nop_xceiv_register();
1090 musb->xceiv = otg_get_transceiver();
1091 if (!musb->xceiv)
1092 return -ENODEV;
1093
1094 pdev = to_platform_device(musb->controller);
1095
1096 /* dma address for async dma */
1097 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1098 musb->async = mem->start;
1099
1100 /* dma address for sync dma */
1101 mem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1102 if (!mem) {
1103 pr_debug("no sync dma resource?\n");
1104 ret = -ENODEV;
1105 goto done;
1106 }
1107 musb->sync = mem->start;
1108
1109 sync = ioremap(mem->start, resource_size(mem));
1110 if (!sync) {
1111 pr_debug("ioremap for sync failed\n");
1112 ret = -ENOMEM;
1113 goto done;
1114 }
1115 musb->sync_va = sync;
1116
1117 /* Offsets from base: VLYNQ at 0x000, MUSB regs at 0x400,
1118 * FIFOs at 0x600, TUSB at 0x800
1119 */
1120 musb->mregs += TUSB_BASE_OFFSET;
1121
1122 ret = tusb_start(musb);
1123 if (ret) {
1124 printk(KERN_ERR "Could not start tusb6010 (%d)\n",
1125 ret);
1126 goto done;
1127 }
1128 musb->isr = tusb_interrupt;
1129
1130 if (is_host_enabled(musb))
1131 musb->board_set_vbus = tusb_source_power;
1132 if (is_peripheral_enabled(musb)) {
1133 musb->xceiv->set_power = tusb_draw_power;
1134 the_musb = musb;
1135 }
1136
1137 setup_timer(&musb_idle_timer, musb_do_idle, (unsigned long) musb);
1138
1139 done:
1140 if (ret < 0) {
1141 if (sync)
1142 iounmap(sync);
1143
1144 otg_put_transceiver(musb->xceiv);
1145 usb_nop_xceiv_unregister();
1146 }
1147 return ret;
1148 }
1149
1150 int musb_platform_exit(struct musb *musb)
1151 {
1152 del_timer_sync(&musb_idle_timer);
1153 the_musb = NULL;
1154
1155 if (musb->board_set_power)
1156 musb->board_set_power(0);
1157
1158 iounmap(musb->sync_va);
1159
1160 otg_put_transceiver(musb->xceiv);
1161 usb_nop_xceiv_unregister();
1162 return 0;
1163 }
Tomato firmware and modifications.