release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/usb/musb/omap2430.c

   1 /*
   2  * Copyright (C) 2005-2007 by Texas Instruments
   3  * Some code has been taken from tusb6010.c
   4  * Copyrights for that are attributable to:
   5  * Copyright (C) 2006 Nokia Corporation
   6  * Tony Lindgren <tony@atomide.com>
   7  *
   8  * This file is part of the Inventra Controller Driver for Linux.
   9  *
  10  * The Inventra Controller Driver for Linux is free software; you
  11  * can redistribute it and/or modify it under the terms of the GNU
  12  * General Public License version 2 as published by the Free Software
  13  * Foundation.
  14  *
  15  * The Inventra Controller Driver for Linux is distributed in
  16  * the hope that it will be useful, but WITHOUT ANY WARRANTY;
  17  * without even the implied warranty of MERCHANTABILITY or
  18  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  19  * License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with The Inventra Controller Driver for Linux ; if not,
  23  * write to the Free Software Foundation, Inc., 59 Temple Place,
  24  * Suite 330, Boston, MA  02111-1307  USA
  25  *
  26  */
  27 #include <linux/module.h>
  28 #include <linux/kernel.h>
  29 #include <linux/sched.h>
  30 #include <linux/init.h>
  31 #include <linux/list.h>
  32 #include <linux/clk.h>
  33 #include <linux/io.h>
  34
  35 #include "musb_core.h"
  36 #include "omap2430.h"
  37
  38
  39 static struct timer_list musb_idle_timer;
  40
  41 static void musb_do_idle(unsigned long _musb)
  42 {
  43         struct musb     *musb = (void *)_musb;
  44         unsigned long   flags;
  45 #ifdef CONFIG_USB_MUSB_HDRC_HCD
  46         u8      power;
  47 #endif
  48         u8      devctl;
  49
  50         spin_lock_irqsave(&musb->lock, flags);
  51
  52         devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
  53
  54         switch (musb->xceiv->state) {
  55         case OTG_STATE_A_WAIT_BCON:
  56                 devctl &= ~MUSB_DEVCTL_SESSION;
  57                 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
  58
  59                 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
  60                 if (devctl & MUSB_DEVCTL_BDEVICE) {
  61                         musb->xceiv->state = OTG_STATE_B_IDLE;
  62                         MUSB_DEV_MODE(musb);
  63                 } else {
  64                         musb->xceiv->state = OTG_STATE_A_IDLE;
  65                         MUSB_HST_MODE(musb);
  66                 }
  67                 break;
  68 #ifdef CONFIG_USB_MUSB_HDRC_HCD
  69         case OTG_STATE_A_SUSPEND:
  70                 /* finish RESUME signaling? */
  71                 if (musb->port1_status & MUSB_PORT_STAT_RESUME) {
  72                         power = musb_readb(musb->mregs, MUSB_POWER);
  73                         power &= ~MUSB_POWER_RESUME;
  74                         DBG(1, "root port resume stopped, power %02x\n", power);
  75                         musb_writeb(musb->mregs, MUSB_POWER, power);
  76                         musb->is_active = 1;
  77                         musb->port1_status &= ~(USB_PORT_STAT_SUSPEND
  78                                                 | MUSB_PORT_STAT_RESUME);
  79                         musb->port1_status |= USB_PORT_STAT_C_SUSPEND << 16;
  80                         usb_hcd_poll_rh_status(musb_to_hcd(musb));
  81                         /* NOTE: it might really be A_WAIT_BCON ... */
  82                         musb->xceiv->state = OTG_STATE_A_HOST;
  83                 }
  84                 break;
  85 #endif
  86 #ifdef CONFIG_USB_MUSB_HDRC_HCD
  87         case OTG_STATE_A_HOST:
  88                 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
  89                 if (devctl &  MUSB_DEVCTL_BDEVICE)
  90                         musb->xceiv->state = OTG_STATE_B_IDLE;
  91                 else
  92                         musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
  93 #endif
  94         default:
  95                 break;
  96         }
  97         spin_unlock_irqrestore(&musb->lock, flags);
  98 }
  99
 100
 101 void musb_platform_try_idle(struct musb *musb, unsigned long timeout)
 102 {
 103         unsigned long           default_timeout = jiffies + msecs_to_jiffies(3);
 104         static unsigned long    last_timer;
 105
 106         if (timeout == 0)
 107                 timeout = default_timeout;
 108
 109         /* Never idle if active, or when VBUS timeout is not set as host */
 110         if (musb->is_active || ((musb->a_wait_bcon == 0)
 111                         && (musb->xceiv->state == OTG_STATE_A_WAIT_BCON))) {
 112                 DBG(4, "%s active, deleting timer\n", otg_state_string(musb));
 113                 del_timer(&musb_idle_timer);
 114                 last_timer = jiffies;
 115                 return;
 116         }
 117
 118         if (time_after(last_timer, timeout)) {
 119                 if (!timer_pending(&musb_idle_timer))
 120                         last_timer = timeout;
 121                 else {
 122                         DBG(4, "Longer idle timer already pending, ignoring\n");
 123                         return;
 124                 }
 125         }
 126         last_timer = timeout;
 127
 128         DBG(4, "%s inactive, for idle timer for %lu ms\n",
 129                 otg_state_string(musb),
 130                 (unsigned long)jiffies_to_msecs(timeout - jiffies));
 131         mod_timer(&musb_idle_timer, timeout);
 132 }
 133
 134 void musb_platform_enable(struct musb *musb)
 135 {
 136 }
 137 void musb_platform_disable(struct musb *musb)
 138 {
 139 }
 140 static void omap_set_vbus(struct musb *musb, int is_on)
 141 {
 142         u8              devctl;
 143         /* HDRC controls CPEN, but beware current surges during device
 144          * connect.  They can trigger transient overcurrent conditions
 145          * that must be ignored.
 146          */
 147
 148         devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
 149
 150         if (is_on) {
 151                 musb->is_active = 1;
 152                 musb->xceiv->default_a = 1;
 153                 musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
 154                 devctl |= MUSB_DEVCTL_SESSION;
 155
 156                 MUSB_HST_MODE(musb);
 157         } else {
 158                 musb->is_active = 0;
 159
 160                 /* NOTE:  we're skipping A_WAIT_VFALL -> A_IDLE and
 161                  * jumping right to B_IDLE...
 162                  */
 163
 164                 musb->xceiv->default_a = 0;
 165                 musb->xceiv->state = OTG_STATE_B_IDLE;
 166                 devctl &= ~MUSB_DEVCTL_SESSION;
 167
 168                 MUSB_DEV_MODE(musb);
 169         }
 170         musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
 171
 172         DBG(1, "VBUS %s, devctl %02x "
 173                 /* otg %3x conf %08x prcm %08x */ "\n",
 174                 otg_state_string(musb),
 175                 musb_readb(musb->mregs, MUSB_DEVCTL));
 176 }
 177
 178 static int musb_platform_resume(struct musb *musb);
 179
 180 int musb_platform_set_mode(struct musb *musb, u8 musb_mode)
 181 {
 182         u8      devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
 183
 184         devctl |= MUSB_DEVCTL_SESSION;
 185         musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
 186
 187         return 0;
 188 }
 189
 190 int __init musb_platform_init(struct musb *musb, void *board_data)
 191 {
 192         u32 l;
 193         struct omap_musb_board_data *data = board_data;
 194
 195         /* We require some kind of external transceiver, hooked
 196          * up through ULPI.  TWL4030-family PMICs include one,
 197          * which needs a driver, drivers aren't always needed.
 198          */
 199         musb->xceiv = otg_get_transceiver();
 200         if (!musb->xceiv) {
 201                 pr_err("HS USB OTG: no transceiver configured\n");
 202                 return -ENODEV;
 203         }
 204
 205         musb_platform_resume(musb);
 206
 207         l = musb_readl(musb->mregs, OTG_SYSCONFIG);
 208         l &= ~ENABLEWAKEUP;     /* disable wakeup */
 209         l &= ~NOSTDBY;          /* remove possible nostdby */
 210         l |= SMARTSTDBY;        /* enable smart standby */
 211         l &= ~AUTOIDLE;         /* disable auto idle */
 212         l &= ~NOIDLE;           /* remove possible noidle */
 213         l |= SMARTIDLE;         /* enable smart idle */
 214         if (!cpu_is_omap3430())
 215                 l |= AUTOIDLE;          /* enable auto idle */
 216         musb_writel(musb->mregs, OTG_SYSCONFIG, l);
 217
 218         l = musb_readl(musb->mregs, OTG_INTERFSEL);
 219
 220         if (data->interface_type == MUSB_INTERFACE_UTMI) {
 221                 /* OMAP4 uses Internal PHY GS70 which uses UTMI interface */
 222                 l &= ~ULPI_12PIN;       /* Disable ULPI */
 223                 l |= UTMI_8BIT;         /* Enable UTMI  */
 224         } else {
 225                 l |= ULPI_12PIN;
 226         }
 227
 228         musb_writel(musb->mregs, OTG_INTERFSEL, l);
 229
 230         pr_debug("HS USB OTG: revision 0x%x, sysconfig 0x%02x, "
 231                         "sysstatus 0x%x, intrfsel 0x%x, simenable  0x%x\n",
 232                         musb_readl(musb->mregs, OTG_REVISION),
 233                         musb_readl(musb->mregs, OTG_SYSCONFIG),
 234                         musb_readl(musb->mregs, OTG_SYSSTATUS),
 235                         musb_readl(musb->mregs, OTG_INTERFSEL),
 236                         musb_readl(musb->mregs, OTG_SIMENABLE));
 237
 238         if (is_host_enabled(musb))
 239                 musb->board_set_vbus = omap_set_vbus;
 240
 241         setup_timer(&musb_idle_timer, musb_do_idle, (unsigned long) musb);
 242
 243         return 0;
 244 }
 245
 246 #ifdef CONFIG_PM
 247 void musb_platform_save_context(struct musb *musb,
 248                 struct musb_context_registers *musb_context)
 249 {
 250         musb_context->otg_sysconfig = musb_readl(musb->mregs, OTG_SYSCONFIG);
 251         musb_context->otg_forcestandby = musb_readl(musb->mregs, OTG_FORCESTDBY);
 252 }
 253
 254 void musb_platform_restore_context(struct musb *musb,
 255                 struct musb_context_registers *musb_context)
 256 {
 257         musb_writel(musb->mregs, OTG_SYSCONFIG, musb_context->otg_sysconfig);
 258         musb_writel(musb->mregs, OTG_FORCESTDBY, musb_context->otg_forcestandby);
 259 }
 260 #endif
 261
 262 static int musb_platform_suspend(struct musb *musb)
 263 {
 264         u32 l;
 265
 266         if (!musb->clock)
 267                 return 0;
 268
 269         /* in any role */
 270         l = musb_readl(musb->mregs, OTG_FORCESTDBY);
 271         l |= ENABLEFORCE;       /* enable MSTANDBY */
 272         musb_writel(musb->mregs, OTG_FORCESTDBY, l);
 273
 274         l = musb_readl(musb->mregs, OTG_SYSCONFIG);
 275         l |= ENABLEWAKEUP;      /* enable wakeup */
 276         musb_writel(musb->mregs, OTG_SYSCONFIG, l);
 277
 278         otg_set_suspend(musb->xceiv, 1);
 279
 280         if (musb->set_clock)
 281                 musb->set_clock(musb->clock, 0);
 282         else
 283                 clk_disable(musb->clock);
 284
 285         return 0;
 286 }
 287
 288 static int musb_platform_resume(struct musb *musb)
 289 {
 290         u32 l;
 291
 292         if (!musb->clock)
 293                 return 0;
 294
 295         otg_set_suspend(musb->xceiv, 0);
 296
 297         if (musb->set_clock)
 298                 musb->set_clock(musb->clock, 1);
 299         else
 300                 clk_enable(musb->clock);
 301
 302         l = musb_readl(musb->mregs, OTG_SYSCONFIG);
 303         l &= ~ENABLEWAKEUP;     /* disable wakeup */
 304         musb_writel(musb->mregs, OTG_SYSCONFIG, l);
 305
 306         l = musb_readl(musb->mregs, OTG_FORCESTDBY);
 307         l &= ~ENABLEFORCE;      /* disable MSTANDBY */
 308         musb_writel(musb->mregs, OTG_FORCESTDBY, l);
 309
 310         return 0;
 311 }
 312
 313
 314 int musb_platform_exit(struct musb *musb)
 315 {
 316
 317         musb_platform_suspend(musb);
 318
 319         otg_put_transceiver(musb->xceiv);
 320         return 0;
 321 }