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GUI: Fix Tomato RAF theme for all builds. Compilation typo.
[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / drivers / usb / musb / musb_core.c
bloba450542efbf28b492c878cc1138ac0d7459af8c6
1 /*
2 * MUSB OTG driver core code
3 *
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20 * 02110-1301 USA
21 *
22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 */
34
35 /*
36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
37 *
38 * This consists of a Host Controller Driver (HCD) and a peripheral
39 * controller driver implementing the "Gadget" API; OTG support is
40 * in the works. These are normal Linux-USB controller drivers which
41 * use IRQs and have no dedicated thread.
42 *
43 * This version of the driver has only been used with products from
44 * Texas Instruments. Those products integrate the Inventra logic
45 * with other DMA, IRQ, and bus modules, as well as other logic that
46 * needs to be reflected in this driver.
47 *
48 *
49 * NOTE: the original Mentor code here was pretty much a collection
50 * of mechanisms that don't seem to have been fully integrated/working
51 * for *any* Linux kernel version. This version aims at Linux 2.6.now,
52 * Key open issues include:
53 *
54 * - Lack of host-side transaction scheduling, for all transfer types.
55 * The hardware doesn't do it; instead, software must.
56 *
57 * This is not an issue for OTG devices that don't support external
58 * hubs, but for more "normal" USB hosts it's a user issue that the
59 * "multipoint" support doesn't scale in the expected ways. That
60 * includes DaVinci EVM in a common non-OTG mode.
61 *
62 * * Control and bulk use dedicated endpoints, and there's as
63 * yet no mechanism to either (a) reclaim the hardware when
64 * peripherals are NAKing, which gets complicated with bulk
65 * endpoints, or (b) use more than a single bulk endpoint in
66 * each direction.
67 *
68 * RESULT: one device may be perceived as blocking another one.
69 *
70 * * Interrupt and isochronous will dynamically allocate endpoint
71 * hardware, but (a) there's no record keeping for bandwidth;
72 * (b) in the common case that few endpoints are available, there
73 * is no mechanism to reuse endpoints to talk to multiple devices.
74 *
75 * RESULT: At one extreme, bandwidth can be overcommitted in
76 * some hardware configurations, no faults will be reported.
77 * At the other extreme, the bandwidth capabilities which do
78 * exist tend to be severely undercommitted. You can't yet hook
79 * up both a keyboard and a mouse to an external USB hub.
80 */
81
82 /*
83 * This gets many kinds of configuration information:
84 * - Kconfig for everything user-configurable
85 * - platform_device for addressing, irq, and platform_data
86 * - platform_data is mostly for board-specific informarion
87 * (plus recentrly, SOC or family details)
88 *
89 * Most of the conditional compilation will (someday) vanish.
90 */
91
92 #include <linux/module.h>
93 #include <linux/kernel.h>
94 #include <linux/sched.h>
95 #include <linux/slab.h>
96 #include <linux/init.h>
97 #include <linux/list.h>
98 #include <linux/kobject.h>
99 #include <linux/platform_device.h>
100 #include <linux/io.h>
101
102 #ifdef CONFIG_ARM
103 #include <mach/hardware.h>
104 #include <mach/memory.h>
105 #include <asm/mach-types.h>
106 #endif
107
108 #include "musb_core.h"
109
110
111 #ifdef CONFIG_ARCH_DAVINCI
112 #include "davinci.h"
113 #endif
114
115 #define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON)
116
117
118 unsigned musb_debug;
119 module_param_named(debug, musb_debug, uint, S_IRUGO | S_IWUSR);
120 MODULE_PARM_DESC(debug, "Debug message level. Default = 0");
121
122 #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
123 #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
124
125 #define MUSB_VERSION "6.0"
126
127 #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
128
129 #define MUSB_DRIVER_NAME "musb_hdrc"
130 const char musb_driver_name[] = MUSB_DRIVER_NAME;
131
132 MODULE_DESCRIPTION(DRIVER_INFO);
133 MODULE_AUTHOR(DRIVER_AUTHOR);
134 MODULE_LICENSE("GPL");
135 MODULE_ALIAS("platform:" MUSB_DRIVER_NAME);
136
137
138 /*-------------------------------------------------------------------------*/
139
140 static inline struct musb *dev_to_musb(struct device *dev)
141 {
142 #ifdef CONFIG_USB_MUSB_HDRC_HCD
143 /* usbcore insists dev->driver_data is a "struct hcd *" */
144 return hcd_to_musb(dev_get_drvdata(dev));
145 #else
146 return dev_get_drvdata(dev);
147 #endif
148 }
149
150 /*-------------------------------------------------------------------------*/
151
152 #ifndef CONFIG_BLACKFIN
153 static int musb_ulpi_read(struct otg_transceiver *otg, u32 offset)
154 {
155 void __iomem *addr = otg->io_priv;
156 int i = 0;
157 u8 r;
158 u8 power;
159
160 /* Make sure the transceiver is not in low power mode */
161 power = musb_readb(addr, MUSB_POWER);
162 power &= ~MUSB_POWER_SUSPENDM;
163 musb_writeb(addr, MUSB_POWER, power);
164
165 /* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the
166 * ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM.
167 */
168
169 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset);
170 musb_writeb(addr, MUSB_ULPI_REG_CONTROL,
171 MUSB_ULPI_REG_REQ | MUSB_ULPI_RDN_WR);
172
173 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
174 & MUSB_ULPI_REG_CMPLT)) {
175 i++;
176 if (i == 10000) {
177 DBG(3, "ULPI read timed out\n");
178 return -ETIMEDOUT;
179 }
180
181 }
182 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
183 r &= ~MUSB_ULPI_REG_CMPLT;
184 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
185
186 return musb_readb(addr, MUSB_ULPI_REG_DATA);
187 }
188
189 static int musb_ulpi_write(struct otg_transceiver *otg,
190 u32 offset, u32 data)
191 {
192 void __iomem *addr = otg->io_priv;
193 int i = 0;
194 u8 r = 0;
195 u8 power;
196
197 /* Make sure the transceiver is not in low power mode */
198 power = musb_readb(addr, MUSB_POWER);
199 power &= ~MUSB_POWER_SUSPENDM;
200 musb_writeb(addr, MUSB_POWER, power);
201
202 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset);
203 musb_writeb(addr, MUSB_ULPI_REG_DATA, (u8)data);
204 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, MUSB_ULPI_REG_REQ);
205
206 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
207 & MUSB_ULPI_REG_CMPLT)) {
208 i++;
209 if (i == 10000) {
210 DBG(3, "ULPI write timed out\n");
211 return -ETIMEDOUT;
212 }
213 }
214
215 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
216 r &= ~MUSB_ULPI_REG_CMPLT;
217 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
218
219 return 0;
220 }
221 #else
222 #define musb_ulpi_read NULL
223 #define musb_ulpi_write NULL
224 #endif
225
226 static struct otg_io_access_ops musb_ulpi_access = {
227 .read = musb_ulpi_read,
228 .write = musb_ulpi_write,
229 };
230
231 /*-------------------------------------------------------------------------*/
232
233 #if !defined(CONFIG_USB_TUSB6010) && !defined(CONFIG_BLACKFIN)
234
235 /*
236 * Load an endpoint's FIFO
237 */
238 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
239 {
240 void __iomem *fifo = hw_ep->fifo;
241
242 prefetch((u8 *)src);
243
244 DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
245 'T', hw_ep->epnum, fifo, len, src);
246
247 /* we can't assume unaligned reads work */
248 if (likely((0x01 & (unsigned long) src) == 0)) {
249 u16 index = 0;
250
251 /* best case is 32bit-aligned source address */
252 if ((0x02 & (unsigned long) src) == 0) {
253 if (len >= 4) {
254 writesl(fifo, src + index, len >> 2);
255 index += len & ~0x03;
256 }
257 if (len & 0x02) {
258 musb_writew(fifo, 0, *(u16 *)&src[index]);
259 index += 2;
260 }
261 } else {
262 if (len >= 2) {
263 writesw(fifo, src + index, len >> 1);
264 index += len & ~0x01;
265 }
266 }
267 if (len & 0x01)
268 musb_writeb(fifo, 0, src[index]);
269 } else {
270 /* byte aligned */
271 writesb(fifo, src, len);
272 }
273 }
274
275 /*
276 * Unload an endpoint's FIFO
277 */
278 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
279 {
280 void __iomem *fifo = hw_ep->fifo;
281
282 DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
283 'R', hw_ep->epnum, fifo, len, dst);
284
285 /* we can't assume unaligned writes work */
286 if (likely((0x01 & (unsigned long) dst) == 0)) {
287 u16 index = 0;
288
289 /* best case is 32bit-aligned destination address */
290 if ((0x02 & (unsigned long) dst) == 0) {
291 if (len >= 4) {
292 readsl(fifo, dst, len >> 2);
293 index = len & ~0x03;
294 }
295 if (len & 0x02) {
296 *(u16 *)&dst[index] = musb_readw(fifo, 0);
297 index += 2;
298 }
299 } else {
300 if (len >= 2) {
301 readsw(fifo, dst, len >> 1);
302 index = len & ~0x01;
303 }
304 }
305 if (len & 0x01)
306 dst[index] = musb_readb(fifo, 0);
307 } else {
308 /* byte aligned */
309 readsb(fifo, dst, len);
310 }
311 }
312
313 #endif /* normal PIO */
314
315
316 /*-------------------------------------------------------------------------*/
317
318 /* for high speed test mode; see USB 2.0 spec 7.1.20 */
319 static const u8 musb_test_packet[53] = {
320 /* implicit SYNC then DATA0 to start */
321
322 /* JKJKJKJK x9 */
323 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
324 /* JJKKJJKK x8 */
325 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
326 /* JJJJKKKK x8 */
327 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
328 /* JJJJJJJKKKKKKK x8 */
329 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
330 /* JJJJJJJK x8 */
331 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
332 /* JKKKKKKK x10, JK */
333 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
334
335 /* implicit CRC16 then EOP to end */
336 };
337
338 void musb_load_testpacket(struct musb *musb)
339 {
340 void __iomem *regs = musb->endpoints[0].regs;
341
342 musb_ep_select(musb->mregs, 0);
343 musb_write_fifo(musb->control_ep,
344 sizeof(musb_test_packet), musb_test_packet);
345 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
346 }
347
348 /*-------------------------------------------------------------------------*/
349
350 const char *otg_state_string(struct musb *musb)
351 {
352 switch (musb->xceiv->state) {
353 case OTG_STATE_A_IDLE: return "a_idle";
354 case OTG_STATE_A_WAIT_VRISE: return "a_wait_vrise";
355 case OTG_STATE_A_WAIT_BCON: return "a_wait_bcon";
356 case OTG_STATE_A_HOST: return "a_host";
357 case OTG_STATE_A_SUSPEND: return "a_suspend";
358 case OTG_STATE_A_PERIPHERAL: return "a_peripheral";
359 case OTG_STATE_A_WAIT_VFALL: return "a_wait_vfall";
360 case OTG_STATE_A_VBUS_ERR: return "a_vbus_err";
361 case OTG_STATE_B_IDLE: return "b_idle";
362 case OTG_STATE_B_SRP_INIT: return "b_srp_init";
363 case OTG_STATE_B_PERIPHERAL: return "b_peripheral";
364 case OTG_STATE_B_WAIT_ACON: return "b_wait_acon";
365 case OTG_STATE_B_HOST: return "b_host";
366 default: return "UNDEFINED";
367 }
368 }
369
370 #ifdef CONFIG_USB_MUSB_OTG
371
372 /*
373 * Handles OTG hnp timeouts, such as b_ase0_brst
374 */
375 void musb_otg_timer_func(unsigned long data)
376 {
377 struct musb *musb = (struct musb *)data;
378 unsigned long flags;
379
380 spin_lock_irqsave(&musb->lock, flags);
381 switch (musb->xceiv->state) {
382 case OTG_STATE_B_WAIT_ACON:
383 DBG(1, "HNP: b_wait_acon timeout; back to b_peripheral\n");
384 musb_g_disconnect(musb);
385 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
386 musb->is_active = 0;
387 break;
388 case OTG_STATE_A_SUSPEND:
389 case OTG_STATE_A_WAIT_BCON:
390 DBG(1, "HNP: %s timeout\n", otg_state_string(musb));
391 musb_set_vbus(musb, 0);
392 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
393 break;
394 default:
395 DBG(1, "HNP: Unhandled mode %s\n", otg_state_string(musb));
396 }
397 musb->ignore_disconnect = 0;
398 spin_unlock_irqrestore(&musb->lock, flags);
399 }
400
401 /*
402 * Stops the HNP transition. Caller must take care of locking.
403 */
404 void musb_hnp_stop(struct musb *musb)
405 {
406 struct usb_hcd *hcd = musb_to_hcd(musb);
407 void __iomem *mbase = musb->mregs;
408 u8 reg;
409
410 DBG(1, "HNP: stop from %s\n", otg_state_string(musb));
411
412 switch (musb->xceiv->state) {
413 case OTG_STATE_A_PERIPHERAL:
414 musb_g_disconnect(musb);
415 DBG(1, "HNP: back to %s\n", otg_state_string(musb));
416 break;
417 case OTG_STATE_B_HOST:
418 DBG(1, "HNP: Disabling HR\n");
419 hcd->self.is_b_host = 0;
420 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
421 MUSB_DEV_MODE(musb);
422 reg = musb_readb(mbase, MUSB_POWER);
423 reg |= MUSB_POWER_SUSPENDM;
424 musb_writeb(mbase, MUSB_POWER, reg);
425 /* REVISIT: Start SESSION_REQUEST here? */
426 break;
427 default:
428 DBG(1, "HNP: Stopping in unknown state %s\n",
429 otg_state_string(musb));
430 }
431
432 /*
433 * When returning to A state after HNP, avoid hub_port_rebounce(),
434 * which cause occasional OPT A "Did not receive reset after connect"
435 * errors.
436 */
437 musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16);
438 }
439
440 #endif
441
442 /*
443 * Interrupt Service Routine to record USB "global" interrupts.
444 * Since these do not happen often and signify things of
445 * paramount importance, it seems OK to check them individually;
446 * the order of the tests is specified in the manual
447 *
448 * @param musb instance pointer
449 * @param int_usb register contents
450 * @param devctl
451 * @param power
452 */
453
454 static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
455 u8 devctl, u8 power)
456 {
457 irqreturn_t handled = IRQ_NONE;
458
459 DBG(3, "<== Power=%02x, DevCtl=%02x, int_usb=0x%x\n", power, devctl,
460 int_usb);
461
462 /* in host mode, the peripheral may issue remote wakeup.
463 * in peripheral mode, the host may resume the link.
464 * spurious RESUME irqs happen too, paired with SUSPEND.
465 */
466 if (int_usb & MUSB_INTR_RESUME) {
467 handled = IRQ_HANDLED;
468 DBG(3, "RESUME (%s)\n", otg_state_string(musb));
469
470 if (devctl & MUSB_DEVCTL_HM) {
471 #ifdef CONFIG_USB_MUSB_HDRC_HCD
472 void __iomem *mbase = musb->mregs;
473
474 switch (musb->xceiv->state) {
475 case OTG_STATE_A_SUSPEND:
476 /* remote wakeup? later, GetPortStatus
477 * will stop RESUME signaling
478 */
479
480 if (power & MUSB_POWER_SUSPENDM) {
481 /* spurious */
482 musb->int_usb &= ~MUSB_INTR_SUSPEND;
483 DBG(2, "Spurious SUSPENDM\n");
484 break;
485 }
486
487 power &= ~MUSB_POWER_SUSPENDM;
488 musb_writeb(mbase, MUSB_POWER,
489 power | MUSB_POWER_RESUME);
490
491 musb->port1_status |=
492 (USB_PORT_STAT_C_SUSPEND << 16)
493 | MUSB_PORT_STAT_RESUME;
494 musb->rh_timer = jiffies
495 + msecs_to_jiffies(20);
496
497 musb->xceiv->state = OTG_STATE_A_HOST;
498 musb->is_active = 1;
499 usb_hcd_resume_root_hub(musb_to_hcd(musb));
500 break;
501 case OTG_STATE_B_WAIT_ACON:
502 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
503 musb->is_active = 1;
504 MUSB_DEV_MODE(musb);
505 break;
506 default:
507 WARNING("bogus %s RESUME (%s)\n",
508 "host",
509 otg_state_string(musb));
510 }
511 #endif
512 } else {
513 switch (musb->xceiv->state) {
514 #ifdef CONFIG_USB_MUSB_HDRC_HCD
515 case OTG_STATE_A_SUSPEND:
516 /* possibly DISCONNECT is upcoming */
517 musb->xceiv->state = OTG_STATE_A_HOST;
518 usb_hcd_resume_root_hub(musb_to_hcd(musb));
519 break;
520 #endif
521 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
522 case OTG_STATE_B_WAIT_ACON:
523 case OTG_STATE_B_PERIPHERAL:
524 /* disconnect while suspended? we may
525 * not get a disconnect irq...
526 */
527 if ((devctl & MUSB_DEVCTL_VBUS)
528 != (3 << MUSB_DEVCTL_VBUS_SHIFT)
529 ) {
530 musb->int_usb |= MUSB_INTR_DISCONNECT;
531 musb->int_usb &= ~MUSB_INTR_SUSPEND;
532 break;
533 }
534 musb_g_resume(musb);
535 break;
536 case OTG_STATE_B_IDLE:
537 musb->int_usb &= ~MUSB_INTR_SUSPEND;
538 break;
539 #endif
540 default:
541 WARNING("bogus %s RESUME (%s)\n",
542 "peripheral",
543 otg_state_string(musb));
544 }
545 }
546 }
547
548 #ifdef CONFIG_USB_MUSB_HDRC_HCD
549 /* see manual for the order of the tests */
550 if (int_usb & MUSB_INTR_SESSREQ) {
551 void __iomem *mbase = musb->mregs;
552
553 DBG(1, "SESSION_REQUEST (%s)\n", otg_state_string(musb));
554
555 /* IRQ arrives from ID pin sense or (later, if VBUS power
556 * is removed) SRP. responses are time critical:
557 * - turn on VBUS (with silicon-specific mechanism)
558 * - go through A_WAIT_VRISE
559 * - ... to A_WAIT_BCON.
560 * a_wait_vrise_tmout triggers VBUS_ERROR transitions
561 */
562 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
563 musb->ep0_stage = MUSB_EP0_START;
564 musb->xceiv->state = OTG_STATE_A_IDLE;
565 MUSB_HST_MODE(musb);
566 musb_set_vbus(musb, 1);
567
568 handled = IRQ_HANDLED;
569 }
570
571 if (int_usb & MUSB_INTR_VBUSERROR) {
572 int ignore = 0;
573
574 /* During connection as an A-Device, we may see a short
575 * current spikes causing voltage drop, because of cable
576 * and peripheral capacitance combined with vbus draw.
577 * (So: less common with truly self-powered devices, where
578 * vbus doesn't act like a power supply.)
579 *
580 * Such spikes are short; usually less than ~500 usec, max
581 * of ~2 msec. That is, they're not sustained overcurrent
582 * errors, though they're reported using VBUSERROR irqs.
583 *
584 * Workarounds: (a) hardware: use self powered devices.
585 * (b) software: ignore non-repeated VBUS errors.
586 *
587 * REVISIT: do delays from lots of DEBUG_KERNEL checks
588 * make trouble here, keeping VBUS < 4.4V ?
589 */
590 switch (musb->xceiv->state) {
591 case OTG_STATE_A_HOST:
592 /* recovery is dicey once we've gotten past the
593 * initial stages of enumeration, but if VBUS
594 * stayed ok at the other end of the link, and
595 * another reset is due (at least for high speed,
596 * to redo the chirp etc), it might work OK...
597 */
598 case OTG_STATE_A_WAIT_BCON:
599 case OTG_STATE_A_WAIT_VRISE:
600 if (musb->vbuserr_retry) {
601 void __iomem *mbase = musb->mregs;
602
603 musb->vbuserr_retry--;
604 ignore = 1;
605 devctl |= MUSB_DEVCTL_SESSION;
606 musb_writeb(mbase, MUSB_DEVCTL, devctl);
607 } else {
608 musb->port1_status |=
609 USB_PORT_STAT_OVERCURRENT
610 | (USB_PORT_STAT_C_OVERCURRENT << 16);
611 }
612 break;
613 default:
614 break;
615 }
616
617 DBG(1, "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
618 otg_state_string(musb),
619 devctl,
620 ({ char *s;
621 switch (devctl & MUSB_DEVCTL_VBUS) {
622 case 0 << MUSB_DEVCTL_VBUS_SHIFT:
623 s = "<SessEnd"; break;
624 case 1 << MUSB_DEVCTL_VBUS_SHIFT:
625 s = "<AValid"; break;
626 case 2 << MUSB_DEVCTL_VBUS_SHIFT:
627 s = "<VBusValid"; break;
628 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */
629 default:
630 s = "VALID"; break;
631 }; s; }),
632 VBUSERR_RETRY_COUNT - musb->vbuserr_retry,
633 musb->port1_status);
634
635 /* go through A_WAIT_VFALL then start a new session */
636 if (!ignore)
637 musb_set_vbus(musb, 0);
638 handled = IRQ_HANDLED;
639 }
640
641 #endif
642 if (int_usb & MUSB_INTR_SUSPEND) {
643 DBG(1, "SUSPEND (%s) devctl %02x power %02x\n",
644 otg_state_string(musb), devctl, power);
645 handled = IRQ_HANDLED;
646
647 switch (musb->xceiv->state) {
648 #ifdef CONFIG_USB_MUSB_OTG
649 case OTG_STATE_A_PERIPHERAL:
650 /* We also come here if the cable is removed, since
651 * this silicon doesn't report ID-no-longer-grounded.
652 *
653 * We depend on T(a_wait_bcon) to shut us down, and
654 * hope users don't do anything dicey during this
655 * undesired detour through A_WAIT_BCON.
656 */
657 musb_hnp_stop(musb);
658 usb_hcd_resume_root_hub(musb_to_hcd(musb));
659 musb_root_disconnect(musb);
660 musb_platform_try_idle(musb, jiffies
661 + msecs_to_jiffies(musb->a_wait_bcon
662 ? : OTG_TIME_A_WAIT_BCON));
663
664 break;
665 #endif
666 case OTG_STATE_B_IDLE:
667 if (!musb->is_active)
668 break;
669 case OTG_STATE_B_PERIPHERAL:
670 musb_g_suspend(musb);
671 musb->is_active = is_otg_enabled(musb)
672 && musb->xceiv->gadget->b_hnp_enable;
673 if (musb->is_active) {
674 #ifdef CONFIG_USB_MUSB_OTG
675 musb->xceiv->state = OTG_STATE_B_WAIT_ACON;
676 DBG(1, "HNP: Setting timer for b_ase0_brst\n");
677 mod_timer(&musb->otg_timer, jiffies
678 + msecs_to_jiffies(
679 OTG_TIME_B_ASE0_BRST));
680 #endif
681 }
682 break;
683 case OTG_STATE_A_WAIT_BCON:
684 if (musb->a_wait_bcon != 0)
685 musb_platform_try_idle(musb, jiffies
686 + msecs_to_jiffies(musb->a_wait_bcon));
687 break;
688 case OTG_STATE_A_HOST:
689 musb->xceiv->state = OTG_STATE_A_SUSPEND;
690 musb->is_active = is_otg_enabled(musb)
691 && musb->xceiv->host->b_hnp_enable;
692 break;
693 case OTG_STATE_B_HOST:
694 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
695 DBG(1, "REVISIT: SUSPEND as B_HOST\n");
696 break;
697 default:
698 /* "should not happen" */
699 musb->is_active = 0;
700 break;
701 }
702 }
703
704 #ifdef CONFIG_USB_MUSB_HDRC_HCD
705 if (int_usb & MUSB_INTR_CONNECT) {
706 struct usb_hcd *hcd = musb_to_hcd(musb);
707
708 handled = IRQ_HANDLED;
709 musb->is_active = 1;
710 set_bit(HCD_FLAG_SAW_IRQ, &hcd->flags);
711
712 musb->ep0_stage = MUSB_EP0_START;
713
714 #ifdef CONFIG_USB_MUSB_OTG
715 /* flush endpoints when transitioning from Device Mode */
716 if (is_peripheral_active(musb)) {
717 /* REVISIT HNP; just force disconnect */
718 }
719 musb_writew(musb->mregs, MUSB_INTRTXE, musb->epmask);
720 musb_writew(musb->mregs, MUSB_INTRRXE, musb->epmask & 0xfffe);
721 musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7);
722 #endif
723 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
724 |USB_PORT_STAT_HIGH_SPEED
725 |USB_PORT_STAT_ENABLE
726 );
727 musb->port1_status |= USB_PORT_STAT_CONNECTION
728 |(USB_PORT_STAT_C_CONNECTION << 16);
729
730 /* high vs full speed is just a guess until after reset */
731 if (devctl & MUSB_DEVCTL_LSDEV)
732 musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
733
734 /* indicate new connection to OTG machine */
735 switch (musb->xceiv->state) {
736 case OTG_STATE_B_PERIPHERAL:
737 if (int_usb & MUSB_INTR_SUSPEND) {
738 DBG(1, "HNP: SUSPEND+CONNECT, now b_host\n");
739 int_usb &= ~MUSB_INTR_SUSPEND;
740 goto b_host;
741 } else
742 DBG(1, "CONNECT as b_peripheral???\n");
743 break;
744 case OTG_STATE_B_WAIT_ACON:
745 DBG(1, "HNP: CONNECT, now b_host\n");
746 b_host:
747 musb->xceiv->state = OTG_STATE_B_HOST;
748 hcd->self.is_b_host = 1;
749 musb->ignore_disconnect = 0;
750 del_timer(&musb->otg_timer);
751 break;
752 default:
753 if ((devctl & MUSB_DEVCTL_VBUS)
754 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
755 musb->xceiv->state = OTG_STATE_A_HOST;
756 hcd->self.is_b_host = 0;
757 }
758 break;
759 }
760
761 /* poke the root hub */
762 MUSB_HST_MODE(musb);
763 if (hcd->status_urb)
764 usb_hcd_poll_rh_status(hcd);
765 else
766 usb_hcd_resume_root_hub(hcd);
767
768 DBG(1, "CONNECT (%s) devctl %02x\n",
769 otg_state_string(musb), devctl);
770 }
771 #endif /* CONFIG_USB_MUSB_HDRC_HCD */
772
773 if ((int_usb & MUSB_INTR_DISCONNECT) && !musb->ignore_disconnect) {
774 DBG(1, "DISCONNECT (%s) as %s, devctl %02x\n",
775 otg_state_string(musb),
776 MUSB_MODE(musb), devctl);
777 handled = IRQ_HANDLED;
778
779 switch (musb->xceiv->state) {
780 #ifdef CONFIG_USB_MUSB_HDRC_HCD
781 case OTG_STATE_A_HOST:
782 case OTG_STATE_A_SUSPEND:
783 usb_hcd_resume_root_hub(musb_to_hcd(musb));
784 musb_root_disconnect(musb);
785 if (musb->a_wait_bcon != 0 && is_otg_enabled(musb))
786 musb_platform_try_idle(musb, jiffies
787 + msecs_to_jiffies(musb->a_wait_bcon));
788 break;
789 #endif /* HOST */
790 #ifdef CONFIG_USB_MUSB_OTG
791 case OTG_STATE_B_HOST:
792 /* REVISIT this behaves for "real disconnect"
793 * cases; make sure the other transitions from
794 * from B_HOST act right too. The B_HOST code
795 * in hnp_stop() is currently not used...
796 */
797 musb_root_disconnect(musb);
798 musb_to_hcd(musb)->self.is_b_host = 0;
799 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
800 MUSB_DEV_MODE(musb);
801 musb_g_disconnect(musb);
802 break;
803 case OTG_STATE_A_PERIPHERAL:
804 musb_hnp_stop(musb);
805 musb_root_disconnect(musb);
806 /* FALLTHROUGH */
807 case OTG_STATE_B_WAIT_ACON:
808 /* FALLTHROUGH */
809 #endif /* OTG */
810 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
811 case OTG_STATE_B_PERIPHERAL:
812 case OTG_STATE_B_IDLE:
813 musb_g_disconnect(musb);
814 break;
815 #endif /* GADGET */
816 default:
817 WARNING("unhandled DISCONNECT transition (%s)\n",
818 otg_state_string(musb));
819 break;
820 }
821 }
822
823 /* mentor saves a bit: bus reset and babble share the same irq.
824 * only host sees babble; only peripheral sees bus reset.
825 */
826 if (int_usb & MUSB_INTR_RESET) {
827 handled = IRQ_HANDLED;
828 if (is_host_capable() && (devctl & MUSB_DEVCTL_HM) != 0) {
829 /*
830 * Looks like non-HS BABBLE can be ignored, but
831 * HS BABBLE is an error condition. For HS the solution
832 * is to avoid babble in the first place and fix what
833 * caused BABBLE. When HS BABBLE happens we can only
834 * stop the session.
835 */
836 if (devctl & (MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV))
837 DBG(1, "BABBLE devctl: %02x\n", devctl);
838 else {
839 ERR("Stopping host session -- babble\n");
840 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
841 }
842 } else if (is_peripheral_capable()) {
843 DBG(1, "BUS RESET as %s\n", otg_state_string(musb));
844 switch (musb->xceiv->state) {
845 #ifdef CONFIG_USB_OTG
846 case OTG_STATE_A_SUSPEND:
847 /* We need to ignore disconnect on suspend
848 * otherwise tusb 2.0 won't reconnect after a
849 * power cycle, which breaks otg compliance.
850 */
851 musb->ignore_disconnect = 1;
852 musb_g_reset(musb);
853 /* FALLTHROUGH */
854 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */
855 /* never use invalid T(a_wait_bcon) */
856 DBG(1, "HNP: in %s, %d msec timeout\n",
857 otg_state_string(musb),
858 TA_WAIT_BCON(musb));
859 mod_timer(&musb->otg_timer, jiffies
860 + msecs_to_jiffies(TA_WAIT_BCON(musb)));
861 break;
862 case OTG_STATE_A_PERIPHERAL:
863 musb->ignore_disconnect = 0;
864 del_timer(&musb->otg_timer);
865 musb_g_reset(musb);
866 break;
867 case OTG_STATE_B_WAIT_ACON:
868 DBG(1, "HNP: RESET (%s), to b_peripheral\n",
869 otg_state_string(musb));
870 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
871 musb_g_reset(musb);
872 break;
873 #endif
874 case OTG_STATE_B_IDLE:
875 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
876 /* FALLTHROUGH */
877 case OTG_STATE_B_PERIPHERAL:
878 musb_g_reset(musb);
879 break;
880 default:
881 DBG(1, "Unhandled BUS RESET as %s\n",
882 otg_state_string(musb));
883 }
884 }
885 }
886
887
888 schedule_work(&musb->irq_work);
889
890 return handled;
891 }
892
893 /*-------------------------------------------------------------------------*/
894
895 /*
896 * Program the HDRC to start (enable interrupts, dma, etc.).
897 */
898 void musb_start(struct musb *musb)
899 {
900 void __iomem *regs = musb->mregs;
901 u8 devctl = musb_readb(regs, MUSB_DEVCTL);
902
903 DBG(2, "<== devctl %02x\n", devctl);
904
905 /* Set INT enable registers, enable interrupts */
906 musb_writew(regs, MUSB_INTRTXE, musb->epmask);
907 musb_writew(regs, MUSB_INTRRXE, musb->epmask & 0xfffe);
908 musb_writeb(regs, MUSB_INTRUSBE, 0xf7);
909
910 musb_writeb(regs, MUSB_TESTMODE, 0);
911
912 /* put into basic highspeed mode and start session */
913 musb_writeb(regs, MUSB_POWER, MUSB_POWER_ISOUPDATE
914 | MUSB_POWER_SOFTCONN
915 | MUSB_POWER_HSENAB
916 /* ENSUSPEND wedges tusb */
917 /* | MUSB_POWER_ENSUSPEND */
918 );
919
920 musb->is_active = 0;
921 devctl = musb_readb(regs, MUSB_DEVCTL);
922 devctl &= ~MUSB_DEVCTL_SESSION;
923
924 if (is_otg_enabled(musb)) {
925 /* session started after:
926 * (a) ID-grounded irq, host mode;
927 * (b) vbus present/connect IRQ, peripheral mode;
928 * (c) peripheral initiates, using SRP
929 */
930 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
931 musb->is_active = 1;
932 else
933 devctl |= MUSB_DEVCTL_SESSION;
934
935 } else if (is_host_enabled(musb)) {
936 /* assume ID pin is hard-wired to ground */
937 devctl |= MUSB_DEVCTL_SESSION;
938
939 } else /* peripheral is enabled */ {
940 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
941 musb->is_active = 1;
942 }
943 musb_platform_enable(musb);
944 musb_writeb(regs, MUSB_DEVCTL, devctl);
945 }
946
947
948 static void musb_generic_disable(struct musb *musb)
949 {
950 void __iomem *mbase = musb->mregs;
951 u16 temp;
952
953 /* disable interrupts */
954 musb_writeb(mbase, MUSB_INTRUSBE, 0);
955 musb_writew(mbase, MUSB_INTRTXE, 0);
956 musb_writew(mbase, MUSB_INTRRXE, 0);
957
958 /* off */
959 musb_writeb(mbase, MUSB_DEVCTL, 0);
960
961 /* flush pending interrupts */
962 temp = musb_readb(mbase, MUSB_INTRUSB);
963 temp = musb_readw(mbase, MUSB_INTRTX);
964 temp = musb_readw(mbase, MUSB_INTRRX);
965
966 }
967
968 /*
969 * Make the HDRC stop (disable interrupts, etc.);
970 * reversible by musb_start
971 * called on gadget driver unregister
972 * with controller locked, irqs blocked
973 * acts as a NOP unless some role activated the hardware
974 */
975 void musb_stop(struct musb *musb)
976 {
977 /* stop IRQs, timers, ... */
978 musb_platform_disable(musb);
979 musb_generic_disable(musb);
980 DBG(3, "HDRC disabled\n");
981
982 musb_platform_try_idle(musb, 0);
983 }
984
985 static void musb_shutdown(struct platform_device *pdev)
986 {
987 struct musb *musb = dev_to_musb(&pdev->dev);
988 unsigned long flags;
989
990 spin_lock_irqsave(&musb->lock, flags);
991 musb_platform_disable(musb);
992 musb_generic_disable(musb);
993 if (musb->clock)
994 clk_put(musb->clock);
995 spin_unlock_irqrestore(&musb->lock, flags);
996
997 }
998
999
1000 /*-------------------------------------------------------------------------*/
1001
1002 /*
1003 * The silicon either has hard-wired endpoint configurations, or else
1004 * "dynamic fifo" sizing. The driver has support for both, though at this
1005 * writing only the dynamic sizing is very well tested. Since we switched
1006 * away from compile-time hardware parameters, we can no longer rely on
1007 * dead code elimination to leave only the relevant one in the object file.
1008 *
1009 * We don't currently use dynamic fifo setup capability to do anything
1010 * more than selecting one of a bunch of predefined configurations.
1011 */
1012 #if defined(CONFIG_USB_TUSB6010) || defined(CONFIG_ARCH_OMAP2430) || \
1013 defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
1014 static ushort __initdata fifo_mode = 4;
1015 #else
1016 static ushort __initdata fifo_mode = 2;
1017 #endif
1018
1019 /* "modprobe ... fifo_mode=1" etc */
1020 module_param(fifo_mode, ushort, 0);
1021 MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
1022
1023 /*
1024 * tables defining fifo_mode values. define more if you like.
1025 * for host side, make sure both halves of ep1 are set up.
1026 */
1027
1028 /* mode 0 - fits in 2KB */
1029 static struct musb_fifo_cfg __initdata mode_0_cfg[] = {
1030 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1031 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1032 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
1033 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1034 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1035 };
1036
1037 /* mode 1 - fits in 4KB */
1038 static struct musb_fifo_cfg __initdata mode_1_cfg[] = {
1039 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1040 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1041 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1042 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1043 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1044 };
1045
1046 /* mode 2 - fits in 4KB */
1047 static struct musb_fifo_cfg __initdata mode_2_cfg[] = {
1048 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1049 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1050 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1051 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1052 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1053 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1054 };
1055
1056 /* mode 3 - fits in 4KB */
1057 static struct musb_fifo_cfg __initdata mode_3_cfg[] = {
1058 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1059 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1060 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1061 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1062 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1063 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1064 };
1065
1066 /* mode 4 - fits in 16KB */
1067 static struct musb_fifo_cfg __initdata mode_4_cfg[] = {
1068 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1069 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1070 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1071 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1072 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1073 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1074 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1075 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1076 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1077 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1078 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
1079 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
1080 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
1081 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
1082 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, },
1083 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, },
1084 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },
1085 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, },
1086 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, },
1087 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, },
1088 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, },
1089 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, },
1090 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, },
1091 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, },
1092 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, },
1093 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1094 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1095 };
1096
1097 /* mode 5 - fits in 8KB */
1098 static struct musb_fifo_cfg __initdata mode_5_cfg[] = {
1099 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1100 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1101 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1102 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1103 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1104 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1105 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1106 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1107 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1108 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1109 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, },
1110 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, },
1111 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, },
1112 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, },
1113 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, },
1114 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, },
1115 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, },
1116 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, },
1117 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, },
1118 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, },
1119 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, },
1120 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, },
1121 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, },
1122 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, },
1123 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, },
1124 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1125 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1126 };
1127
1128 /*
1129 * configure a fifo; for non-shared endpoints, this may be called
1130 * once for a tx fifo and once for an rx fifo.
1131 *
1132 * returns negative errno or offset for next fifo.
1133 */
1134 static int __init
1135 fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep,
1136 const struct musb_fifo_cfg *cfg, u16 offset)
1137 {
1138 void __iomem *mbase = musb->mregs;
1139 int size = 0;
1140 u16 maxpacket = cfg->maxpacket;
1141 u16 c_off = offset >> 3;
1142 u8 c_size;
1143
1144 /* expect hw_ep has already been zero-initialized */
1145
1146 size = ffs(max(maxpacket, (u16) 8)) - 1;
1147 maxpacket = 1 << size;
1148
1149 c_size = size - 3;
1150 if (cfg->mode == BUF_DOUBLE) {
1151 if ((offset + (maxpacket << 1)) >
1152 (1 << (musb->config->ram_bits + 2)))
1153 return -EMSGSIZE;
1154 c_size |= MUSB_FIFOSZ_DPB;
1155 } else {
1156 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2)))
1157 return -EMSGSIZE;
1158 }
1159
1160 /* configure the FIFO */
1161 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum);
1162
1163 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1164 /* EP0 reserved endpoint for control, bidirectional;
1165 * EP1 reserved for bulk, two unidirection halves.
1166 */
1167 if (hw_ep->epnum == 1)
1168 musb->bulk_ep = hw_ep;
1169 /* REVISIT error check: be sure ep0 can both rx and tx ... */
1170 #endif
1171 switch (cfg->style) {
1172 case FIFO_TX:
1173 musb_write_txfifosz(mbase, c_size);
1174 musb_write_txfifoadd(mbase, c_off);
1175 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1176 hw_ep->max_packet_sz_tx = maxpacket;
1177 break;
1178 case FIFO_RX:
1179 musb_write_rxfifosz(mbase, c_size);
1180 musb_write_rxfifoadd(mbase, c_off);
1181 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1182 hw_ep->max_packet_sz_rx = maxpacket;
1183 break;
1184 case FIFO_RXTX:
1185 musb_write_txfifosz(mbase, c_size);
1186 musb_write_txfifoadd(mbase, c_off);
1187 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1188 hw_ep->max_packet_sz_rx = maxpacket;
1189
1190 musb_write_rxfifosz(mbase, c_size);
1191 musb_write_rxfifoadd(mbase, c_off);
1192 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
1193 hw_ep->max_packet_sz_tx = maxpacket;
1194
1195 hw_ep->is_shared_fifo = true;
1196 break;
1197 }
1198
1199 /* NOTE rx and tx endpoint irqs aren't managed separately,
1200 * which happens to be ok
1201 */
1202 musb->epmask |= (1 << hw_ep->epnum);
1203
1204 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
1205 }
1206
1207 static struct musb_fifo_cfg __initdata ep0_cfg = {
1208 .style = FIFO_RXTX, .maxpacket = 64,
1209 };
1210
1211 static int __init ep_config_from_table(struct musb *musb)
1212 {
1213 const struct musb_fifo_cfg *cfg;
1214 unsigned i, n;
1215 int offset;
1216 struct musb_hw_ep *hw_ep = musb->endpoints;
1217
1218 if (musb->config->fifo_cfg) {
1219 cfg = musb->config->fifo_cfg;
1220 n = musb->config->fifo_cfg_size;
1221 goto done;
1222 }
1223
1224 switch (fifo_mode) {
1225 default:
1226 fifo_mode = 0;
1227 /* FALLTHROUGH */
1228 case 0:
1229 cfg = mode_0_cfg;
1230 n = ARRAY_SIZE(mode_0_cfg);
1231 break;
1232 case 1:
1233 cfg = mode_1_cfg;
1234 n = ARRAY_SIZE(mode_1_cfg);
1235 break;
1236 case 2:
1237 cfg = mode_2_cfg;
1238 n = ARRAY_SIZE(mode_2_cfg);
1239 break;
1240 case 3:
1241 cfg = mode_3_cfg;
1242 n = ARRAY_SIZE(mode_3_cfg);
1243 break;
1244 case 4:
1245 cfg = mode_4_cfg;
1246 n = ARRAY_SIZE(mode_4_cfg);
1247 break;
1248 case 5:
1249 cfg = mode_5_cfg;
1250 n = ARRAY_SIZE(mode_5_cfg);
1251 break;
1252 }
1253
1254 printk(KERN_DEBUG "%s: setup fifo_mode %d\n",
1255 musb_driver_name, fifo_mode);
1256
1257
1258 done:
1259 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
1260 /* assert(offset > 0) */
1261
1262 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would
1263 * be better than static musb->config->num_eps and DYN_FIFO_SIZE...
1264 */
1265
1266 for (i = 0; i < n; i++) {
1267 u8 epn = cfg->hw_ep_num;
1268
1269 if (epn >= musb->config->num_eps) {
1270 pr_debug("%s: invalid ep %d\n",
1271 musb_driver_name, epn);
1272 return -EINVAL;
1273 }
1274 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
1275 if (offset < 0) {
1276 pr_debug("%s: mem overrun, ep %d\n",
1277 musb_driver_name, epn);
1278 return -EINVAL;
1279 }
1280 epn++;
1281 musb->nr_endpoints = max(epn, musb->nr_endpoints);
1282 }
1283
1284 printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n",
1285 musb_driver_name,
1286 n + 1, musb->config->num_eps * 2 - 1,
1287 offset, (1 << (musb->config->ram_bits + 2)));
1288
1289 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1290 if (!musb->bulk_ep) {
1291 pr_debug("%s: missing bulk\n", musb_driver_name);
1292 return -EINVAL;
1293 }
1294 #endif
1295
1296 return 0;
1297 }
1298
1299
1300 /*
1301 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1302 * @param musb the controller
1303 */
1304 static int __init ep_config_from_hw(struct musb *musb)
1305 {
1306 u8 epnum = 0;
1307 struct musb_hw_ep *hw_ep;
1308 void *mbase = musb->mregs;
1309 int ret = 0;
1310
1311 DBG(2, "<== static silicon ep config\n");
1312
1313
1314 for (epnum = 1; epnum < musb->config->num_eps; epnum++) {
1315 musb_ep_select(mbase, epnum);
1316 hw_ep = musb->endpoints + epnum;
1317
1318 ret = musb_read_fifosize(musb, hw_ep, epnum);
1319 if (ret < 0)
1320 break;
1321
1322
1323 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1324 /* pick an RX/TX endpoint for bulk */
1325 if (hw_ep->max_packet_sz_tx < 512
1326 || hw_ep->max_packet_sz_rx < 512)
1327 continue;
1328
1329 /* REVISIT: this algorithm is lazy, we should at least
1330 * try to pick a double buffered endpoint.
1331 */
1332 if (musb->bulk_ep)
1333 continue;
1334 musb->bulk_ep = hw_ep;
1335 #endif
1336 }
1337
1338 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1339 if (!musb->bulk_ep) {
1340 pr_debug("%s: missing bulk\n", musb_driver_name);
1341 return -EINVAL;
1342 }
1343 #endif
1344
1345 return 0;
1346 }
1347
1348 enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
1349
1350 /* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1351 * configure endpoints, or take their config from silicon
1352 */
1353 static int __init musb_core_init(u16 musb_type, struct musb *musb)
1354 {
1355 u8 reg;
1356 char *type;
1357 char aInfo[90], aRevision[32], aDate[12];
1358 void __iomem *mbase = musb->mregs;
1359 int status = 0;
1360 int i;
1361
1362 /* log core options (read using indexed model) */
1363 reg = musb_read_configdata(mbase);
1364
1365 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
1366 if (reg & MUSB_CONFIGDATA_DYNFIFO) {
1367 strcat(aInfo, ", dyn FIFOs");
1368 musb->dyn_fifo = true;
1369 }
1370 if (reg & MUSB_CONFIGDATA_MPRXE) {
1371 strcat(aInfo, ", bulk combine");
1372 musb->bulk_combine = true;
1373 }
1374 if (reg & MUSB_CONFIGDATA_MPTXE) {
1375 strcat(aInfo, ", bulk split");
1376 musb->bulk_split = true;
1377 }
1378 if (reg & MUSB_CONFIGDATA_HBRXE) {
1379 strcat(aInfo, ", HB-ISO Rx");
1380 musb->hb_iso_rx = true;
1381 }
1382 if (reg & MUSB_CONFIGDATA_HBTXE) {
1383 strcat(aInfo, ", HB-ISO Tx");
1384 musb->hb_iso_tx = true;
1385 }
1386 if (reg & MUSB_CONFIGDATA_SOFTCONE)
1387 strcat(aInfo, ", SoftConn");
1388
1389 printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n",
1390 musb_driver_name, reg, aInfo);
1391
1392 aDate[0] = 0;
1393 if (MUSB_CONTROLLER_MHDRC == musb_type) {
1394 musb->is_multipoint = 1;
1395 type = "M";
1396 } else {
1397 musb->is_multipoint = 0;
1398 type = "";
1399 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1400 #ifndef CONFIG_USB_OTG_BLACKLIST_HUB
1401 printk(KERN_ERR
1402 "%s: kernel must blacklist external hubs\n",
1403 musb_driver_name);
1404 #endif
1405 #endif
1406 }
1407
1408 /* log release info */
1409 musb->hwvers = musb_read_hwvers(mbase);
1410 snprintf(aRevision, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb->hwvers),
1411 MUSB_HWVERS_MINOR(musb->hwvers),
1412 (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : "");
1413 printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n",
1414 musb_driver_name, type, aRevision, aDate);
1415
1416 /* configure ep0 */
1417 musb_configure_ep0(musb);
1418
1419 /* discover endpoint configuration */
1420 musb->nr_endpoints = 1;
1421 musb->epmask = 1;
1422
1423 if (musb->dyn_fifo)
1424 status = ep_config_from_table(musb);
1425 else
1426 status = ep_config_from_hw(musb);
1427
1428 if (status < 0)
1429 return status;
1430
1431 /* finish init, and print endpoint config */
1432 for (i = 0; i < musb->nr_endpoints; i++) {
1433 struct musb_hw_ep *hw_ep = musb->endpoints + i;
1434
1435 hw_ep->fifo = MUSB_FIFO_OFFSET(i) + mbase;
1436 #ifdef CONFIG_USB_TUSB6010
1437 hw_ep->fifo_async = musb->async + 0x400 + MUSB_FIFO_OFFSET(i);
1438 hw_ep->fifo_sync = musb->sync + 0x400 + MUSB_FIFO_OFFSET(i);
1439 hw_ep->fifo_sync_va =
1440 musb->sync_va + 0x400 + MUSB_FIFO_OFFSET(i);
1441
1442 if (i == 0)
1443 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
1444 else
1445 hw_ep->conf = mbase + 0x400 + (((i - 1) & 0xf) << 2);
1446 #endif
1447
1448 hw_ep->regs = MUSB_EP_OFFSET(i, 0) + mbase;
1449 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1450 hw_ep->target_regs = musb_read_target_reg_base(i, mbase);
1451 hw_ep->rx_reinit = 1;
1452 hw_ep->tx_reinit = 1;
1453 #endif
1454
1455 if (hw_ep->max_packet_sz_tx) {
1456 DBG(1,
1457 "%s: hw_ep %d%s, %smax %d\n",
1458 musb_driver_name, i,
1459 hw_ep->is_shared_fifo ? "shared" : "tx",
1460 hw_ep->tx_double_buffered
1461 ? "doublebuffer, " : "",
1462 hw_ep->max_packet_sz_tx);
1463 }
1464 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
1465 DBG(1,
1466 "%s: hw_ep %d%s, %smax %d\n",
1467 musb_driver_name, i,
1468 "rx",
1469 hw_ep->rx_double_buffered
1470 ? "doublebuffer, " : "",
1471 hw_ep->max_packet_sz_rx);
1472 }
1473 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx))
1474 DBG(1, "hw_ep %d not configured\n", i);
1475 }
1476
1477 return 0;
1478 }
1479
1480 /*-------------------------------------------------------------------------*/
1481
1482 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430) || \
1483 defined(CONFIG_ARCH_OMAP4)
1484
1485 static irqreturn_t generic_interrupt(int irq, void *__hci)
1486 {
1487 unsigned long flags;
1488 irqreturn_t retval = IRQ_NONE;
1489 struct musb *musb = __hci;
1490
1491 spin_lock_irqsave(&musb->lock, flags);
1492
1493 musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
1494 musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
1495 musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
1496
1497 if (musb->int_usb || musb->int_tx || musb->int_rx)
1498 retval = musb_interrupt(musb);
1499
1500 spin_unlock_irqrestore(&musb->lock, flags);
1501
1502 return retval;
1503 }
1504
1505 #else
1506 #define generic_interrupt NULL
1507 #endif
1508
1509 /*
1510 * handle all the irqs defined by the HDRC core. for now we expect: other
1511 * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1512 * will be assigned, and the irq will already have been acked.
1513 *
1514 * called in irq context with spinlock held, irqs blocked
1515 */
1516 irqreturn_t musb_interrupt(struct musb *musb)
1517 {
1518 irqreturn_t retval = IRQ_NONE;
1519 u8 devctl, power;
1520 int ep_num;
1521 u32 reg;
1522
1523 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1524 power = musb_readb(musb->mregs, MUSB_POWER);
1525
1526 DBG(4, "** IRQ %s usb%04x tx%04x rx%04x\n",
1527 (devctl & MUSB_DEVCTL_HM) ? "host" : "peripheral",
1528 musb->int_usb, musb->int_tx, musb->int_rx);
1529
1530 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1531 if (is_otg_enabled(musb) || is_peripheral_enabled(musb))
1532 if (!musb->gadget_driver) {
1533 DBG(5, "No gadget driver loaded\n");
1534 return IRQ_HANDLED;
1535 }
1536 #endif
1537
1538 /* the core can interrupt us for multiple reasons; docs have
1539 * a generic interrupt flowchart to follow
1540 */
1541 if (musb->int_usb)
1542 retval |= musb_stage0_irq(musb, musb->int_usb,
1543 devctl, power);
1544
1545 /* "stage 1" is handling endpoint irqs */
1546
1547 /* handle endpoint 0 first */
1548 if (musb->int_tx & 1) {
1549 if (devctl & MUSB_DEVCTL_HM)
1550 retval |= musb_h_ep0_irq(musb);
1551 else
1552 retval |= musb_g_ep0_irq(musb);
1553 }
1554
1555 /* RX on endpoints 1-15 */
1556 reg = musb->int_rx >> 1;
1557 ep_num = 1;
1558 while (reg) {
1559 if (reg & 1) {
1560 /* musb_ep_select(musb->mregs, ep_num); */
1561 /* REVISIT just retval = ep->rx_irq(...) */
1562 retval = IRQ_HANDLED;
1563 if (devctl & MUSB_DEVCTL_HM) {
1564 if (is_host_capable())
1565 musb_host_rx(musb, ep_num);
1566 } else {
1567 if (is_peripheral_capable())
1568 musb_g_rx(musb, ep_num);
1569 }
1570 }
1571
1572 reg >>= 1;
1573 ep_num++;
1574 }
1575
1576 /* TX on endpoints 1-15 */
1577 reg = musb->int_tx >> 1;
1578 ep_num = 1;
1579 while (reg) {
1580 if (reg & 1) {
1581 /* musb_ep_select(musb->mregs, ep_num); */
1582 /* REVISIT just retval |= ep->tx_irq(...) */
1583 retval = IRQ_HANDLED;
1584 if (devctl & MUSB_DEVCTL_HM) {
1585 if (is_host_capable())
1586 musb_host_tx(musb, ep_num);
1587 } else {
1588 if (is_peripheral_capable())
1589 musb_g_tx(musb, ep_num);
1590 }
1591 }
1592 reg >>= 1;
1593 ep_num++;
1594 }
1595
1596 return retval;
1597 }
1598
1599
1600 #ifndef CONFIG_MUSB_PIO_ONLY
1601 static int __initdata use_dma = 1;
1602
1603 /* "modprobe ... use_dma=0" etc */
1604 module_param(use_dma, bool, 0);
1605 MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
1606
1607 void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit)
1608 {
1609 u8 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1610
1611 /* called with controller lock already held */
1612
1613 if (!epnum) {
1614 #ifndef CONFIG_USB_TUSB_OMAP_DMA
1615 if (!is_cppi_enabled()) {
1616 /* endpoint 0 */
1617 if (devctl & MUSB_DEVCTL_HM)
1618 musb_h_ep0_irq(musb);
1619 else
1620 musb_g_ep0_irq(musb);
1621 }
1622 #endif
1623 } else {
1624 /* endpoints 1..15 */
1625 if (transmit) {
1626 if (devctl & MUSB_DEVCTL_HM) {
1627 if (is_host_capable())
1628 musb_host_tx(musb, epnum);
1629 } else {
1630 if (is_peripheral_capable())
1631 musb_g_tx(musb, epnum);
1632 }
1633 } else {
1634 /* receive */
1635 if (devctl & MUSB_DEVCTL_HM) {
1636 if (is_host_capable())
1637 musb_host_rx(musb, epnum);
1638 } else {
1639 if (is_peripheral_capable())
1640 musb_g_rx(musb, epnum);
1641 }
1642 }
1643 }
1644 }
1645
1646 #else
1647 #define use_dma 0
1648 #endif
1649
1650 /*-------------------------------------------------------------------------*/
1651
1652 #ifdef CONFIG_SYSFS
1653
1654 static ssize_t
1655 musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1656 {
1657 struct musb *musb = dev_to_musb(dev);
1658 unsigned long flags;
1659 int ret = -EINVAL;
1660
1661 spin_lock_irqsave(&musb->lock, flags);
1662 ret = sprintf(buf, "%s\n", otg_state_string(musb));
1663 spin_unlock_irqrestore(&musb->lock, flags);
1664
1665 return ret;
1666 }
1667
1668 static ssize_t
1669 musb_mode_store(struct device *dev, struct device_attribute *attr,
1670 const char *buf, size_t n)
1671 {
1672 struct musb *musb = dev_to_musb(dev);
1673 unsigned long flags;
1674 int status;
1675
1676 spin_lock_irqsave(&musb->lock, flags);
1677 if (sysfs_streq(buf, "host"))
1678 status = musb_platform_set_mode(musb, MUSB_HOST);
1679 else if (sysfs_streq(buf, "peripheral"))
1680 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
1681 else if (sysfs_streq(buf, "otg"))
1682 status = musb_platform_set_mode(musb, MUSB_OTG);
1683 else
1684 status = -EINVAL;
1685 spin_unlock_irqrestore(&musb->lock, flags);
1686
1687 return (status == 0) ? n : status;
1688 }
1689 static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store);
1690
1691 static ssize_t
1692 musb_vbus_store(struct device *dev, struct device_attribute *attr,
1693 const char *buf, size_t n)
1694 {
1695 struct musb *musb = dev_to_musb(dev);
1696 unsigned long flags;
1697 unsigned long val;
1698
1699 if (sscanf(buf, "%lu", &val) < 1) {
1700 dev_err(dev, "Invalid VBUS timeout ms value\n");
1701 return -EINVAL;
1702 }
1703
1704 spin_lock_irqsave(&musb->lock, flags);
1705 /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */
1706 musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ;
1707 if (musb->xceiv->state == OTG_STATE_A_WAIT_BCON)
1708 musb->is_active = 0;
1709 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
1710 spin_unlock_irqrestore(&musb->lock, flags);
1711
1712 return n;
1713 }
1714
1715 static ssize_t
1716 musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf)
1717 {
1718 struct musb *musb = dev_to_musb(dev);
1719 unsigned long flags;
1720 unsigned long val;
1721 int vbus;
1722
1723 spin_lock_irqsave(&musb->lock, flags);
1724 val = musb->a_wait_bcon;
1725 vbus = musb_platform_get_vbus_status(musb);
1726 spin_unlock_irqrestore(&musb->lock, flags);
1727
1728 return sprintf(buf, "Vbus %s, timeout %lu msec\n",
1729 vbus ? "on" : "off", val);
1730 }
1731 static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store);
1732
1733 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1734
1735 /* Gadget drivers can't know that a host is connected so they might want
1736 * to start SRP, but users can. This allows userspace to trigger SRP.
1737 */
1738 static ssize_t
1739 musb_srp_store(struct device *dev, struct device_attribute *attr,
1740 const char *buf, size_t n)
1741 {
1742 struct musb *musb = dev_to_musb(dev);
1743 unsigned short srp;
1744
1745 if (sscanf(buf, "%hu", &srp) != 1
1746 || (srp != 1)) {
1747 dev_err(dev, "SRP: Value must be 1\n");
1748 return -EINVAL;
1749 }
1750
1751 if (srp == 1)
1752 musb_g_wakeup(musb);
1753
1754 return n;
1755 }
1756 static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store);
1757
1758 #endif /* CONFIG_USB_GADGET_MUSB_HDRC */
1759
1760 static struct attribute *musb_attributes[] = {
1761 &dev_attr_mode.attr,
1762 &dev_attr_vbus.attr,
1763 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1764 &dev_attr_srp.attr,
1765 #endif
1766 NULL
1767 };
1768
1769 static const struct attribute_group musb_attr_group = {
1770 .attrs = musb_attributes,
1771 };
1772
1773 #endif /* sysfs */
1774
1775 /* Only used to provide driver mode change events */
1776 static void musb_irq_work(struct work_struct *data)
1777 {
1778 struct musb *musb = container_of(data, struct musb, irq_work);
1779 static int old_state;
1780
1781 if (musb->xceiv->state != old_state) {
1782 old_state = musb->xceiv->state;
1783 sysfs_notify(&musb->controller->kobj, NULL, "mode");
1784 }
1785 }
1786
1787 /* --------------------------------------------------------------------------
1788 * Init support
1789 */
1790
1791 static struct musb *__init
1792 allocate_instance(struct device *dev,
1793 struct musb_hdrc_config *config, void __iomem *mbase)
1794 {
1795 struct musb *musb;
1796 struct musb_hw_ep *ep;
1797 int epnum;
1798 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1799 struct usb_hcd *hcd;
1800
1801 hcd = usb_create_hcd(&musb_hc_driver, dev, dev_name(dev));
1802 if (!hcd)
1803 return NULL;
1804 /* usbcore sets dev->driver_data to hcd, and sometimes uses that... */
1805
1806 musb = hcd_to_musb(hcd);
1807 INIT_LIST_HEAD(&musb->control);
1808 INIT_LIST_HEAD(&musb->in_bulk);
1809 INIT_LIST_HEAD(&musb->out_bulk);
1810
1811 hcd->uses_new_polling = 1;
1812
1813 musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
1814 musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON;
1815 #else
1816 musb = kzalloc(sizeof *musb, GFP_KERNEL);
1817 if (!musb)
1818 return NULL;
1819 dev_set_drvdata(dev, musb);
1820
1821 #endif
1822
1823 musb->mregs = mbase;
1824 musb->ctrl_base = mbase;
1825 musb->nIrq = -ENODEV;
1826 musb->config = config;
1827 BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS);
1828 for (epnum = 0, ep = musb->endpoints;
1829 epnum < musb->config->num_eps;
1830 epnum++, ep++) {
1831 ep->musb = musb;
1832 ep->epnum = epnum;
1833 }
1834
1835 musb->controller = dev;
1836 return musb;
1837 }
1838
1839 static void musb_free(struct musb *musb)
1840 {
1841 /* this has multiple entry modes. it handles fault cleanup after
1842 * probe(), where things may be partially set up, as well as rmmod
1843 * cleanup after everything's been de-activated.
1844 */
1845
1846 #ifdef CONFIG_SYSFS
1847 sysfs_remove_group(&musb->controller->kobj, &musb_attr_group);
1848 #endif
1849
1850 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1851 musb_gadget_cleanup(musb);
1852 #endif
1853
1854 if (musb->nIrq >= 0) {
1855 if (musb->irq_wake)
1856 disable_irq_wake(musb->nIrq);
1857 free_irq(musb->nIrq, musb);
1858 }
1859 if (is_dma_capable() && musb->dma_controller) {
1860 struct dma_controller *c = musb->dma_controller;
1861
1862 (void) c->stop(c);
1863 dma_controller_destroy(c);
1864 }
1865
1866 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1867 usb_put_hcd(musb_to_hcd(musb));
1868 #else
1869 kfree(musb);
1870 #endif
1871 }
1872
1873 /*
1874 * Perform generic per-controller initialization.
1875 *
1876 * @pDevice: the controller (already clocked, etc)
1877 * @nIrq: irq
1878 * @mregs: virtual address of controller registers,
1879 * not yet corrected for platform-specific offsets
1880 */
1881 static int __init
1882 musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
1883 {
1884 int status;
1885 struct musb *musb;
1886 struct musb_hdrc_platform_data *plat = dev->platform_data;
1887
1888 /* The driver might handle more features than the board; OK.
1889 * Fail when the board needs a feature that's not enabled.
1890 */
1891 if (!plat) {
1892 dev_dbg(dev, "no platform_data?\n");
1893 status = -ENODEV;
1894 goto fail0;
1895 }
1896
1897 switch (plat->mode) {
1898 case MUSB_HOST:
1899 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1900 break;
1901 #else
1902 goto bad_config;
1903 #endif
1904 case MUSB_PERIPHERAL:
1905 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1906 break;
1907 #else
1908 goto bad_config;
1909 #endif
1910 case MUSB_OTG:
1911 #ifdef CONFIG_USB_MUSB_OTG
1912 break;
1913 #else
1914 bad_config:
1915 #endif
1916 default:
1917 dev_err(dev, "incompatible Kconfig role setting\n");
1918 status = -EINVAL;
1919 goto fail0;
1920 }
1921
1922 /* allocate */
1923 musb = allocate_instance(dev, plat->config, ctrl);
1924 if (!musb) {
1925 status = -ENOMEM;
1926 goto fail0;
1927 }
1928
1929 spin_lock_init(&musb->lock);
1930 musb->board_mode = plat->mode;
1931 musb->board_set_power = plat->set_power;
1932 musb->set_clock = plat->set_clock;
1933 musb->min_power = plat->min_power;
1934
1935 /* Clock usage is chip-specific ... functional clock (DaVinci,
1936 * OMAP2430), or PHY ref (some TUSB6010 boards). All this core
1937 * code does is make sure a clock handle is available; platform
1938 * code manages it during start/stop and suspend/resume.
1939 */
1940 if (plat->clock) {
1941 musb->clock = clk_get(dev, plat->clock);
1942 if (IS_ERR(musb->clock)) {
1943 status = PTR_ERR(musb->clock);
1944 musb->clock = NULL;
1945 goto fail1;
1946 }
1947 }
1948
1949 /* The musb_platform_init() call:
1950 * - adjusts musb->mregs and musb->isr if needed,
1951 * - may initialize an integrated tranceiver
1952 * - initializes musb->xceiv, usually by otg_get_transceiver()
1953 * - activates clocks.
1954 * - stops powering VBUS
1955 * - assigns musb->board_set_vbus if host mode is enabled
1956 *
1957 * There are various transciever configurations. Blackfin,
1958 * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses
1959 * external/discrete ones in various flavors (twl4030 family,
1960 * isp1504, non-OTG, etc) mostly hooking up through ULPI.
1961 */
1962 musb->isr = generic_interrupt;
1963 status = musb_platform_init(musb, plat->board_data);
1964 if (status < 0)
1965 goto fail2;
1966
1967 if (!musb->isr) {
1968 status = -ENODEV;
1969 goto fail3;
1970 }
1971
1972 if (!musb->xceiv->io_ops) {
1973 musb->xceiv->io_priv = musb->mregs;
1974 musb->xceiv->io_ops = &musb_ulpi_access;
1975 }
1976
1977 #ifndef CONFIG_MUSB_PIO_ONLY
1978 if (use_dma && dev->dma_mask) {
1979 struct dma_controller *c;
1980
1981 c = dma_controller_create(musb, musb->mregs);
1982 musb->dma_controller = c;
1983 if (c)
1984 (void) c->start(c);
1985 }
1986 #endif
1987 /* ideally this would be abstracted in platform setup */
1988 if (!is_dma_capable() || !musb->dma_controller)
1989 dev->dma_mask = NULL;
1990
1991 /* be sure interrupts are disabled before connecting ISR */
1992 musb_platform_disable(musb);
1993 musb_generic_disable(musb);
1994
1995 /* setup musb parts of the core (especially endpoints) */
1996 status = musb_core_init(plat->config->multipoint
1997 ? MUSB_CONTROLLER_MHDRC
1998 : MUSB_CONTROLLER_HDRC, musb);
1999 if (status < 0)
2000 goto fail3;
2001
2002 #ifdef CONFIG_USB_MUSB_OTG
2003 setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb);
2004 #endif
2005
2006 /* Init IRQ workqueue before request_irq */
2007 INIT_WORK(&musb->irq_work, musb_irq_work);
2008
2009 /* attach to the IRQ */
2010 if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) {
2011 dev_err(dev, "request_irq %d failed!\n", nIrq);
2012 status = -ENODEV;
2013 goto fail3;
2014 }
2015 musb->nIrq = nIrq;
2016 if (enable_irq_wake(nIrq) == 0) {
2017 musb->irq_wake = 1;
2018 device_init_wakeup(dev, 1);
2019 } else {
2020 musb->irq_wake = 0;
2021 }
2022
2023 /* host side needs more setup */
2024 if (is_host_enabled(musb)) {
2025 struct usb_hcd *hcd = musb_to_hcd(musb);
2026
2027 otg_set_host(musb->xceiv, &hcd->self);
2028
2029 if (is_otg_enabled(musb))
2030 hcd->self.otg_port = 1;
2031 musb->xceiv->host = &hcd->self;
2032 hcd->power_budget = 2 * (plat->power ? : 250);
2033
2034 /* program PHY to use external vBus if required */
2035 if (plat->extvbus) {
2036 u8 busctl = musb_read_ulpi_buscontrol(musb->mregs);
2037 busctl |= MUSB_ULPI_USE_EXTVBUS;
2038 musb_write_ulpi_buscontrol(musb->mregs, busctl);
2039 }
2040 }
2041
2042 /* For the host-only role, we can activate right away.
2043 * (We expect the ID pin to be forcibly grounded!!)
2044 * Otherwise, wait till the gadget driver hooks up.
2045 */
2046 if (!is_otg_enabled(musb) && is_host_enabled(musb)) {
2047 MUSB_HST_MODE(musb);
2048 musb->xceiv->default_a = 1;
2049 musb->xceiv->state = OTG_STATE_A_IDLE;
2050
2051 status = usb_add_hcd(musb_to_hcd(musb), -1, 0);
2052
2053 DBG(1, "%s mode, status %d, devctl %02x %c\n",
2054 "HOST", status,
2055 musb_readb(musb->mregs, MUSB_DEVCTL),
2056 (musb_readb(musb->mregs, MUSB_DEVCTL)
2057 & MUSB_DEVCTL_BDEVICE
2058 ? 'B' : 'A'));
2059
2060 } else /* peripheral is enabled */ {
2061 MUSB_DEV_MODE(musb);
2062 musb->xceiv->default_a = 0;
2063 musb->xceiv->state = OTG_STATE_B_IDLE;
2064
2065 status = musb_gadget_setup(musb);
2066
2067 DBG(1, "%s mode, status %d, dev%02x\n",
2068 is_otg_enabled(musb) ? "OTG" : "PERIPHERAL",
2069 status,
2070 musb_readb(musb->mregs, MUSB_DEVCTL));
2071
2072 }
2073 if (status < 0)
2074 goto fail3;
2075
2076 status = musb_init_debugfs(musb);
2077 if (status < 0)
2078 goto fail4;
2079
2080 #ifdef CONFIG_SYSFS
2081 status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group);
2082 if (status)
2083 goto fail5;
2084 #endif
2085
2086 dev_info(dev, "USB %s mode controller at %p using %s, IRQ %d\n",
2087 ({char *s;
2088 switch (musb->board_mode) {
2089 case MUSB_HOST: s = "Host"; break;
2090 case MUSB_PERIPHERAL: s = "Peripheral"; break;
2091 default: s = "OTG"; break;
2092 }; s; }),
2093 ctrl,
2094 (is_dma_capable() && musb->dma_controller)
2095 ? "DMA" : "PIO",
2096 musb->nIrq);
2097
2098 return 0;
2099
2100 fail5:
2101 musb_exit_debugfs(musb);
2102
2103 fail4:
2104 if (!is_otg_enabled(musb) && is_host_enabled(musb))
2105 usb_remove_hcd(musb_to_hcd(musb));
2106 else
2107 musb_gadget_cleanup(musb);
2108
2109 fail3:
2110 if (musb->irq_wake)
2111 device_init_wakeup(dev, 0);
2112 musb_platform_exit(musb);
2113
2114 fail2:
2115 if (musb->clock)
2116 clk_put(musb->clock);
2117
2118 fail1:
2119 dev_err(musb->controller,
2120 "musb_init_controller failed with status %d\n", status);
2121
2122 musb_free(musb);
2123
2124 fail0:
2125
2126 return status;
2127
2128 }
2129
2130 /*-------------------------------------------------------------------------*/
2131
2132 /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
2133 * bridge to a platform device; this driver then suffices.
2134 */
2135
2136 #ifndef CONFIG_MUSB_PIO_ONLY
2137 static u64 *orig_dma_mask;
2138 #endif
2139
2140 static int __init musb_probe(struct platform_device *pdev)
2141 {
2142 struct device *dev = &pdev->dev;
2143 int irq = platform_get_irq(pdev, 0);
2144 int status;
2145 struct resource *iomem;
2146 void __iomem *base;
2147
2148 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2149 if (!iomem || irq == 0)
2150 return -ENODEV;
2151
2152 base = ioremap(iomem->start, resource_size(iomem));
2153 if (!base) {
2154 dev_err(dev, "ioremap failed\n");
2155 return -ENOMEM;
2156 }
2157
2158 #ifndef CONFIG_MUSB_PIO_ONLY
2159 /* clobbered by use_dma=n */
2160 orig_dma_mask = dev->dma_mask;
2161 #endif
2162 status = musb_init_controller(dev, irq, base);
2163 if (status < 0)
2164 iounmap(base);
2165
2166 return status;
2167 }
2168
2169 static int __exit musb_remove(struct platform_device *pdev)
2170 {
2171 struct musb *musb = dev_to_musb(&pdev->dev);
2172 void __iomem *ctrl_base = musb->ctrl_base;
2173
2174 /* this gets called on rmmod.
2175 * - Host mode: host may still be active
2176 * - Peripheral mode: peripheral is deactivated (or never-activated)
2177 * - OTG mode: both roles are deactivated (or never-activated)
2178 */
2179 musb_exit_debugfs(musb);
2180 musb_shutdown(pdev);
2181 #ifdef CONFIG_USB_MUSB_HDRC_HCD
2182 if (musb->board_mode == MUSB_HOST)
2183 usb_remove_hcd(musb_to_hcd(musb));
2184 #endif
2185 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
2186 musb_platform_exit(musb);
2187
2188 musb_free(musb);
2189 iounmap(ctrl_base);
2190 device_init_wakeup(&pdev->dev, 0);
2191 #ifndef CONFIG_MUSB_PIO_ONLY
2192 pdev->dev.dma_mask = orig_dma_mask;
2193 #endif
2194 return 0;
2195 }
2196
2197 #ifdef CONFIG_PM
2198
2199 static struct musb_context_registers musb_context;
2200
2201 void musb_save_context(struct musb *musb)
2202 {
2203 int i;
2204 void __iomem *musb_base = musb->mregs;
2205
2206 if (is_host_enabled(musb)) {
2207 musb_context.frame = musb_readw(musb_base, MUSB_FRAME);
2208 musb_context.testmode = musb_readb(musb_base, MUSB_TESTMODE);
2209 musb_context.busctl = musb_read_ulpi_buscontrol(musb->mregs);
2210 }
2211 musb_context.power = musb_readb(musb_base, MUSB_POWER);
2212 musb_context.intrtxe = musb_readw(musb_base, MUSB_INTRTXE);
2213 musb_context.intrrxe = musb_readw(musb_base, MUSB_INTRRXE);
2214 musb_context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE);
2215 musb_context.index = musb_readb(musb_base, MUSB_INDEX);
2216 musb_context.devctl = musb_readb(musb_base, MUSB_DEVCTL);
2217
2218 for (i = 0; i < MUSB_C_NUM_EPS; ++i) {
2219 musb_writeb(musb_base, MUSB_INDEX, i);
2220 musb_context.index_regs[i].txmaxp =
2221 musb_readw(musb_base, 0x10 + MUSB_TXMAXP);
2222 musb_context.index_regs[i].txcsr =
2223 musb_readw(musb_base, 0x10 + MUSB_TXCSR);
2224 musb_context.index_regs[i].rxmaxp =
2225 musb_readw(musb_base, 0x10 + MUSB_RXMAXP);
2226 musb_context.index_regs[i].rxcsr =
2227 musb_readw(musb_base, 0x10 + MUSB_RXCSR);
2228
2229 if (musb->dyn_fifo) {
2230 musb_context.index_regs[i].txfifoadd =
2231 musb_read_txfifoadd(musb_base);
2232 musb_context.index_regs[i].rxfifoadd =
2233 musb_read_rxfifoadd(musb_base);
2234 musb_context.index_regs[i].txfifosz =
2235 musb_read_txfifosz(musb_base);
2236 musb_context.index_regs[i].rxfifosz =
2237 musb_read_rxfifosz(musb_base);
2238 }
2239 if (is_host_enabled(musb)) {
2240 musb_context.index_regs[i].txtype =
2241 musb_readb(musb_base, 0x10 + MUSB_TXTYPE);
2242 musb_context.index_regs[i].txinterval =
2243 musb_readb(musb_base, 0x10 + MUSB_TXINTERVAL);
2244 musb_context.index_regs[i].rxtype =
2245 musb_readb(musb_base, 0x10 + MUSB_RXTYPE);
2246 musb_context.index_regs[i].rxinterval =
2247 musb_readb(musb_base, 0x10 + MUSB_RXINTERVAL);
2248
2249 musb_context.index_regs[i].txfunaddr =
2250 musb_read_txfunaddr(musb_base, i);
2251 musb_context.index_regs[i].txhubaddr =
2252 musb_read_txhubaddr(musb_base, i);
2253 musb_context.index_regs[i].txhubport =
2254 musb_read_txhubport(musb_base, i);
2255
2256 musb_context.index_regs[i].rxfunaddr =
2257 musb_read_rxfunaddr(musb_base, i);
2258 musb_context.index_regs[i].rxhubaddr =
2259 musb_read_rxhubaddr(musb_base, i);
2260 musb_context.index_regs[i].rxhubport =
2261 musb_read_rxhubport(musb_base, i);
2262 }
2263 }
2264
2265 musb_writeb(musb_base, MUSB_INDEX, musb_context.index);
2266
2267 musb_platform_save_context(musb, &musb_context);
2268 }
2269
2270 void musb_restore_context(struct musb *musb)
2271 {
2272 int i;
2273 void __iomem *musb_base = musb->mregs;
2274 void __iomem *ep_target_regs;
2275
2276 musb_platform_restore_context(musb, &musb_context);
2277
2278 if (is_host_enabled(musb)) {
2279 musb_writew(musb_base, MUSB_FRAME, musb_context.frame);
2280 musb_writeb(musb_base, MUSB_TESTMODE, musb_context.testmode);
2281 musb_write_ulpi_buscontrol(musb->mregs, musb_context.busctl);
2282 }
2283 musb_writeb(musb_base, MUSB_POWER, musb_context.power);
2284 musb_writew(musb_base, MUSB_INTRTXE, musb_context.intrtxe);
2285 musb_writew(musb_base, MUSB_INTRRXE, musb_context.intrrxe);
2286 musb_writeb(musb_base, MUSB_INTRUSBE, musb_context.intrusbe);
2287 musb_writeb(musb_base, MUSB_DEVCTL, musb_context.devctl);
2288
2289 for (i = 0; i < MUSB_C_NUM_EPS; ++i) {
2290 musb_writeb(musb_base, MUSB_INDEX, i);
2291 musb_writew(musb_base, 0x10 + MUSB_TXMAXP,
2292 musb_context.index_regs[i].txmaxp);
2293 musb_writew(musb_base, 0x10 + MUSB_TXCSR,
2294 musb_context.index_regs[i].txcsr);
2295 musb_writew(musb_base, 0x10 + MUSB_RXMAXP,
2296 musb_context.index_regs[i].rxmaxp);
2297 musb_writew(musb_base, 0x10 + MUSB_RXCSR,
2298 musb_context.index_regs[i].rxcsr);
2299
2300 if (musb->dyn_fifo) {
2301 musb_write_txfifosz(musb_base,
2302 musb_context.index_regs[i].txfifosz);
2303 musb_write_rxfifosz(musb_base,
2304 musb_context.index_regs[i].rxfifosz);
2305 musb_write_txfifoadd(musb_base,
2306 musb_context.index_regs[i].txfifoadd);
2307 musb_write_rxfifoadd(musb_base,
2308 musb_context.index_regs[i].rxfifoadd);
2309 }
2310
2311 if (is_host_enabled(musb)) {
2312 musb_writeb(musb_base, 0x10 + MUSB_TXTYPE,
2313 musb_context.index_regs[i].txtype);
2314 musb_writeb(musb_base, 0x10 + MUSB_TXINTERVAL,
2315 musb_context.index_regs[i].txinterval);
2316 musb_writeb(musb_base, 0x10 + MUSB_RXTYPE,
2317 musb_context.index_regs[i].rxtype);
2318 musb_writeb(musb_base, 0x10 + MUSB_RXINTERVAL,
2319
2320 musb_context.index_regs[i].rxinterval);
2321 musb_write_txfunaddr(musb_base, i,
2322 musb_context.index_regs[i].txfunaddr);
2323 musb_write_txhubaddr(musb_base, i,
2324 musb_context.index_regs[i].txhubaddr);
2325 musb_write_txhubport(musb_base, i,
2326 musb_context.index_regs[i].txhubport);
2327
2328 ep_target_regs =
2329 musb_read_target_reg_base(i, musb_base);
2330
2331 musb_write_rxfunaddr(ep_target_regs,
2332 musb_context.index_regs[i].rxfunaddr);
2333 musb_write_rxhubaddr(ep_target_regs,
2334 musb_context.index_regs[i].rxhubaddr);
2335 musb_write_rxhubport(ep_target_regs,
2336 musb_context.index_regs[i].rxhubport);
2337 }
2338 }
2339
2340 musb_writeb(musb_base, MUSB_INDEX, musb_context.index);
2341 }
2342
2343 static int musb_suspend(struct device *dev)
2344 {
2345 struct platform_device *pdev = to_platform_device(dev);
2346 unsigned long flags;
2347 struct musb *musb = dev_to_musb(&pdev->dev);
2348
2349 if (!musb->clock)
2350 return 0;
2351
2352 spin_lock_irqsave(&musb->lock, flags);
2353
2354 if (is_peripheral_active(musb)) {
2355 } else if (is_host_active(musb)) {
2356 /* we know all the children are suspended; sometimes
2357 * they will even be wakeup-enabled.
2358 */
2359 }
2360
2361 musb_save_context(musb);
2362
2363 if (musb->set_clock)
2364 musb->set_clock(musb->clock, 0);
2365 else
2366 clk_disable(musb->clock);
2367 spin_unlock_irqrestore(&musb->lock, flags);
2368 return 0;
2369 }
2370
2371 static int musb_resume_noirq(struct device *dev)
2372 {
2373 struct platform_device *pdev = to_platform_device(dev);
2374 struct musb *musb = dev_to_musb(&pdev->dev);
2375
2376 if (!musb->clock)
2377 return 0;
2378
2379 if (musb->set_clock)
2380 musb->set_clock(musb->clock, 1);
2381 else
2382 clk_enable(musb->clock);
2383
2384 musb_restore_context(musb);
2385
2386 /* for static cmos like DaVinci, register values were preserved
2387 * unless for some reason the whole soc powered down or the USB
2388 * module got reset through the PSC (vs just being disabled).
2389 */
2390 return 0;
2391 }
2392
2393 static const struct dev_pm_ops musb_dev_pm_ops = {
2394 .suspend = musb_suspend,
2395 .resume_noirq = musb_resume_noirq,
2396 };
2397
2398 #define MUSB_DEV_PM_OPS (&musb_dev_pm_ops)
2399 #else
2400 #define MUSB_DEV_PM_OPS NULL
2401 #endif
2402
2403 static struct platform_driver musb_driver = {
2404 .driver = {
2405 .name = (char *)musb_driver_name,
2406 .bus = &platform_bus_type,
2407 .owner = THIS_MODULE,
2408 .pm = MUSB_DEV_PM_OPS,
2409 },
2410 .remove = __exit_p(musb_remove),
2411 .shutdown = musb_shutdown,
2412 };
2413
2414 /*-------------------------------------------------------------------------*/
2415
2416 static int __init musb_init(void)
2417 {
2418 #ifdef CONFIG_USB_MUSB_HDRC_HCD
2419 if (usb_disabled())
2420 return 0;
2421 #endif
2422
2423 pr_info("%s: version " MUSB_VERSION ", "
2424 #ifdef CONFIG_MUSB_PIO_ONLY
2425 "pio"
2426 #elif defined(CONFIG_USB_TI_CPPI_DMA)
2427 "cppi-dma"
2428 #elif defined(CONFIG_USB_INVENTRA_DMA)
2429 "musb-dma"
2430 #elif defined(CONFIG_USB_TUSB_OMAP_DMA)
2431 "tusb-omap-dma"
2432 #else
2433 "?dma?"
2434 #endif
2435 ", "
2436 #ifdef CONFIG_USB_MUSB_OTG
2437 "otg (peripheral+host)"
2438 #elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
2439 "peripheral"
2440 #elif defined(CONFIG_USB_MUSB_HDRC_HCD)
2441 "host"
2442 #endif
2443 ", debug=%d\n",
2444 musb_driver_name, musb_debug);
2445 return platform_driver_probe(&musb_driver, musb_probe);
2446 }
2447
2448 /* make us init after usbcore and i2c (transceivers, regulators, etc)
2449 * and before usb gadget and host-side drivers start to register
2450 */
2451 fs_initcall(musb_init);
2452
2453 static void __exit musb_cleanup(void)
2454 {
2455 platform_driver_unregister(&musb_driver);
2456 }
2457 module_exit(musb_cleanup);
Tomato firmware and modifications.