release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/usb/host/xhci-hub.c

   1 /*
   2  * xHCI host controller driver
   3  *
   4  * Copyright (C) 2008 Intel Corp.
   5  *
   6  * Author: Sarah Sharp
   7  * Some code borrowed from the Linux EHCI driver.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16  * for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software Foundation,
  20  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 #include <asm/unaligned.h>
  24
  25 #include "xhci.h"
  26
  27 extern int usb2mode;
  28
  29 static void xhci_hub_descriptor(struct xhci_hcd *xhci,
  30                 struct usb_hub_descriptor *desc)
  31 {
  32         int ports;
  33         u16 temp;
  34
  35         ports = HCS_MAX_PORTS(xhci->hcs_params1);
  36
  37         /* USB 3.0 hubs have a different descriptor, but we fake this for now */
  38         desc->bDescriptorType = 0x29;
  39         desc->bPwrOn2PwrGood = 10;      /* xhci section 5.4.9 says 20ms max */
  40         desc->bHubContrCurrent = 0;
  41
  42         desc->bNbrPorts = ports;
  43         temp = 1 + (ports / 8);
  44         desc->bDescLength = 7 + 2 * temp;
  45
  46         /* Why does core/hcd.h define bitmap?  It's just confusing. */
  47         memset(&desc->DeviceRemovable[0], 0, temp);
  48         memset(&desc->DeviceRemovable[temp], 0xff, temp);
  49
  50         /* Using table 11-13 in USB 2.0 spec. */
  51         temp = 0;
  52         /* Bits 1:0 - support port power switching, or power always on */
  53         if (HCC_PPC(xhci->hcc_params))
  54                 temp |= 0x0001;
  55         else
  56                 temp |= 0x0002;
  57         /* Bit  2 - root hubs are not part of a compound device */
  58         /* Bits 4:3 - individual port over current protection */
  59         temp |= 0x0008;
  60         /* Bits 6:5 - no TTs in root ports */
  61         /* Bit  7 - no port indicators */
  62         desc->wHubCharacteristics = (__force __u16) cpu_to_le16(temp);
  63 }
  64
  65 static unsigned int xhci_port_speed(unsigned int port_status)
  66 {
  67         if (DEV_LOWSPEED(port_status))
  68                 return USB_PORT_STAT_LOW_SPEED;
  69         if (DEV_HIGHSPEED(port_status))
  70                 return USB_PORT_STAT_HIGH_SPEED;
  71         if (DEV_SUPERSPEED(port_status))
  72                 return USB_PORT_STAT_SUPER_SPEED;
  73         return 0;
  74 }
  75
  76 /*
  77  * These bits are Read Only (RO) and should be saved and written to the
  78  * registers: 0, 3, 10:13, 30
  79  * connect status, over-current status, port speed, and device removable.
  80  * connect status and port speed are also sticky - meaning they're in
  81  * the AUX well and they aren't changed by a hot, warm, or cold reset.
  82  */
  83 #define XHCI_PORT_RO    ((1<<0) | (1<<3) | (0xf<<10) | (1<<30))
  84 /*
  85  * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit:
  86  * bits 5:8, 9, 14:15, 25:27
  87  * link state, port power, port indicator state, "wake on" enable state
  88  */
  89 #define XHCI_PORT_RWS   ((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25))
  90 /*
  91  * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect:
  92  * bit 4 (port reset)
  93  */
  94 #define XHCI_PORT_RW1S  ((1<<4))
  95 /*
  96  * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect:
  97  * bits 1, 17, 18, 19, 20, 21, 22, 23
  98  * port enable/disable, and
  99  * change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports),
 100  * over-current, reset, link state, and L1 change
 101  */
 102 #define XHCI_PORT_RW1CS ((1<<1) | (0x7f<<17))
 103 /*
 104  * Bit 16 is RW, and writing a '1' to it causes the link state control to be
 105  * latched in
 106  */
 107 #define XHCI_PORT_RW    ((1<<16))
 108 /*
 109  * These bits are Reserved Zero (RsvdZ) and zero should be written to them:
 110  * bits 2, 24, 28:31
 111  */
 112 #define XHCI_PORT_RZ    ((1<<2) | (1<<24) | (0xf<<28))
 113
 114 /*
 115  * Given a port state, this function returns a value that would result in the
 116  * port being in the same state, if the value was written to the port status
 117  * control register.
 118  * Save Read Only (RO) bits and save read/write bits where
 119  * writing a 0 clears the bit and writing a 1 sets the bit (RWS).
 120  * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect.
 121  */
 122 static u32 xhci_port_state_to_neutral(u32 state)
 123 {
 124         /* Save read-only status and port state */
 125         return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS);
 126 }
 127
 128 static void xhci_disable_port(struct xhci_hcd *xhci, u16 wIndex,
 129                 u32 __iomem *addr, u32 port_status)
 130 {
 131         /* Don't allow the USB core to disable SuperSpeed ports. */
 132         if (xhci->port_array[wIndex] == 0x03) {
 133                 xhci_dbg(xhci, "Ignoring request to disable "
 134                                 "SuperSpeed port.\n");
 135                 return;
 136         }
 137
 138         /* Write 1 to disable the port */
 139         xhci_writel(xhci, port_status | PORT_PE, addr);
 140         port_status = xhci_readl(xhci, addr);
 141         xhci_dbg(xhci, "disable port, actual port %d status  = 0x%x\n",
 142                         wIndex, port_status);
 143 }
 144
 145 static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue,
 146                 u16 wIndex, u32 __iomem *addr, u32 port_status)
 147 {
 148         char *port_change_bit;
 149         u32 status;
 150
 151         switch (wValue) {
 152         case USB_PORT_FEAT_C_RESET:
 153                 status = PORT_RC;
 154                 port_change_bit = "reset";
 155                 break;
 156         case USB_PORT_FEAT_C_CONNECTION:
 157                 status = PORT_CSC;
 158                 port_change_bit = "connect";
 159                 break;
 160         case USB_PORT_FEAT_C_OVER_CURRENT:
 161                 status = PORT_OCC;
 162                 port_change_bit = "over-current";
 163                 break;
 164         case USB_PORT_FEAT_C_ENABLE:
 165                 status = PORT_PEC;
 166                 port_change_bit = "enable/disable";
 167                 break;
 168         default:
 169                 /* Should never happen */
 170                 return;
 171         }
 172         /* Change bits are all write 1 to clear */
 173         xhci_writel(xhci, port_status | status, addr);
 174         port_status = xhci_readl(xhci, addr);
 175         xhci_dbg(xhci, "clear port %s change, actual port %d status  = 0x%x\n",
 176                         port_change_bit, wIndex, port_status);
 177 }
 178
 179 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
 180                 u16 wIndex, char *buf, u16 wLength)
 181 {
 182         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 183         int ports;
 184         unsigned long flags;
 185         u32 temp, status;
 186         int retval = 0;
 187         u32 __iomem *addr;
 188
 189         ports = HCS_MAX_PORTS(xhci->hcs_params1);
 190
 191         spin_lock_irqsave(&xhci->lock, flags);
 192         switch (typeReq) {
 193         case GetHubStatus:
 194                 /* No power source, over-current reported per port */
 195                 memset(buf, 0, 4);
 196                 break;
 197         case GetHubDescriptor:
 198                 xhci_hub_descriptor(xhci, (struct usb_hub_descriptor *) buf);
 199                 break;
 200         case GetPortStatus:
 201                 if (!wIndex || wIndex > ports)
 202                         goto error;
 203                 wIndex--;
 204                 status = 0;
 205                 addr = &xhci->op_regs->port_status_base + NUM_PORT_REGS*(wIndex & 0xff);
 206                 temp = xhci_readl(xhci, addr);
 207                 xhci_dbg(xhci, "get port status, actual port %d status  = 0x%x\n", wIndex, temp);
 208
 209                 /* wPortChange bits */
 210                 if (temp & PORT_CSC)
 211                         status |= USB_PORT_STAT_C_CONNECTION << 16;
 212                 if (temp & PORT_PEC)
 213                         status |= USB_PORT_STAT_C_ENABLE << 16;
 214                 if ((temp & PORT_OCC))
 215                         status |= USB_PORT_STAT_C_OVERCURRENT << 16;
 216                 if (temp & PORT_CONNECT) {
 217                         status |= USB_PORT_STAT_CONNECTION;
 218                         status |= xhci_port_speed(temp);
 219                 }
 220                 if (temp & PORT_PE)
 221                         status |= USB_PORT_STAT_ENABLE;
 222                 if (temp & PORT_OC)
 223                         status |= USB_PORT_STAT_OVERCURRENT;
 224                 if (temp & PORT_RESET)
 225                         status |= USB_PORT_STAT_RESET;
 226                 if (temp & PORT_POWER)
 227                         status |= USB_PORT_STAT_POWER;
 228                 xhci_dbg(xhci, "Get port status returned 0x%x\n", status);
 229                 put_unaligned(cpu_to_le32(status), (__le32 *) buf);
 230                 break;
 231         case SetPortFeature:
 232                 wIndex &= 0xff;
 233                 if (!wIndex || wIndex > ports)
 234                         goto error;
 235                 wIndex--;
 236                 addr = &xhci->op_regs->port_status_base + NUM_PORT_REGS*(wIndex & 0xff);
 237                 temp = xhci_readl(xhci, addr);
 238                 temp = xhci_port_state_to_neutral(temp);
 239                 switch (wValue) {
 240                 case USB_PORT_FEAT_POWER:
 241                         printk(KERN_INFO "[xhci-hub] usb2mode:[%d]\n", usb2mode);
 242                         /*
 243                          * Turn on ports, even if there isn't per-port switching.
 244                          * HC will report connect events even before this is set.
 245                          * However, khubd will ignore the roothub events until
 246                          * the roothub is registered.
 247                          */
 248                         if(usb2mode==1){
 249                                 printk(KERN_INFO "[xhci] USB3 port power off\n");
 250                                 xhci_writel(xhci, (temp | PORT_PE), addr);
 251                                 xhci_writel(xhci, (temp & ~(PORT_POWER)), addr);
 252                                 xhci_writel(xhci, ((temp & ~PORT_PLS_MASK) | PORT_WR | PORT_PLC | XDEV_U0 | PORT_RESET | PORT_LINK_STROBE), addr);
 253                         }else if(usb2mode==2){
 254                                 printk(KERN_INFO "[xhci] USB3 port power off\n");
 255                                 xhci_writel(xhci, (temp | PORT_PE), addr);
 256                                 xhci_writel(xhci, (temp | PORT_POWER), addr);
 257                                 xhci_writel(xhci, ((temp & ~PORT_PLS_MASK) | PORT_WR | PORT_PLC | XDEV_U0 | PORT_RESET | PORT_LINK_STROBE), addr);
 258                         }else{
 259                                 xhci_writel(xhci, temp | PORT_POWER, addr);
 260                         }
 261
 262                         temp = xhci_readl(xhci, addr);
 263                         xhci_dbg(xhci, "set port power, actual port %d status  = 0x%x\n", wIndex, temp);
 264                         break;
 265                 case USB_PORT_FEAT_RESET:
 266                         temp = (temp | PORT_RESET);
 267                         xhci_writel(xhci, temp, addr);
 268
 269                         temp = xhci_readl(xhci, addr);
 270                         xhci_dbg(xhci, "set port reset, actual port %d status  = 0x%x\n", wIndex, temp);
 271                         break;
 272                 default:
 273                         goto error;
 274                 }
 275                 temp = xhci_readl(xhci, addr); /* unblock any posted writes */
 276                 break;
 277         case ClearPortFeature:
 278                 if (!wIndex || wIndex > ports)
 279                         goto error;
 280                 wIndex--;
 281                 addr = &xhci->op_regs->port_status_base +
 282                         NUM_PORT_REGS*(wIndex & 0xff);
 283                 temp = xhci_readl(xhci, addr);
 284                 temp = xhci_port_state_to_neutral(temp);
 285                 switch (wValue) {
 286                 case USB_PORT_FEAT_C_RESET:
 287                 case USB_PORT_FEAT_C_CONNECTION:
 288                 case USB_PORT_FEAT_C_OVER_CURRENT:
 289                 case USB_PORT_FEAT_C_ENABLE:
 290                         xhci_clear_port_change_bit(xhci, wValue, wIndex,
 291                                         addr, temp);
 292                         break;
 293                 case USB_PORT_FEAT_ENABLE:
 294                         xhci_disable_port(xhci, wIndex, addr, temp);
 295                         break;
 296                 default:
 297                         goto error;
 298                 }
 299                 break;
 300         default:
 301 error:
 302                 /* "stall" on error */
 303                 retval = -EPIPE;
 304         }
 305         spin_unlock_irqrestore(&xhci->lock, flags);
 306         return retval;
 307 }
 308
 309 /*
 310  * Returns 0 if the status hasn't changed, or the number of bytes in buf.
 311  * Ports are 0-indexed from the HCD point of view,
 312  * and 1-indexed from the USB core pointer of view.
 313  *
 314  * Note that the status change bits will be cleared as soon as a port status
 315  * change event is generated, so we use the saved status from that event.
 316  */
 317 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf)
 318 {
 319         unsigned long flags;
 320         u32 temp, status;
 321         int i, retval;
 322         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 323         int ports;
 324         u32 __iomem *addr;
 325
 326         ports = HCS_MAX_PORTS(xhci->hcs_params1);
 327
 328         /* Initial status is no changes */
 329         retval = (ports + 8) / 8;
 330         memset(buf, 0, retval);
 331         status = 0;
 332
 333         spin_lock_irqsave(&xhci->lock, flags);
 334         /* For each port, did anything change?  If so, set that bit in buf. */
 335         for (i = 0; i < ports; i++) {
 336                 addr = &xhci->op_regs->port_status_base +
 337                         NUM_PORT_REGS*i;
 338                 temp = xhci_readl(xhci, addr);
 339                 if (temp & (PORT_CSC | PORT_PEC | PORT_OCC)) {
 340                         buf[(i + 1) / 8] |= 1 << (i + 1) % 8;
 341                         status = 1;
 342                 }
 343         }
 344         spin_unlock_irqrestore(&xhci->lock, flags);
 345         return status ? retval : 0;
 346 }