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GUI: Fix Tomato RAF theme for all builds. Compilation typo.
[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / drivers / staging / rtl8192e / r8192E.h
blob03ed24ffacc63f020af42aa23f261ff6f6734d26
1 /*
2 This is part of rtl8187 OpenSource driver.
3 Copyright (C) Andrea Merello 2004-2005 <andreamrl@tiscali.it>
4 Released under the terms of GPL (General Public Licence)
5
6 Parts of this driver are based on the GPL part of the
7 official realtek driver
8
9 Parts of this driver are based on the rtl8192 driver skeleton
10 from Patric Schenke & Andres Salomon
11
12 Parts of this driver are based on the Intel Pro Wireless 2100 GPL driver
13
14 We want to tanks the Authors of those projects and the Ndiswrapper
15 project Authors.
16 */
17
18 #ifndef R819xU_H
19 #define R819xU_H
20
21 #include <linux/module.h>
22 #include <linux/kernel.h>
23 //#include <linux/config.h>
24 #include <linux/init.h>
25 #include <linux/ioport.h>
26 #include <linux/sched.h>
27 #include <linux/types.h>
28 #include <linux/slab.h>
29 #include <linux/netdevice.h>
30 #include <linux/pci.h>
31 //#include <linux/usb.h>
32 #include <linux/etherdevice.h>
33 #include <linux/delay.h>
34 #include <linux/rtnetlink.h> //for rtnl_lock()
35 #include <linux/wireless.h>
36 #include <linux/timer.h>
37 #include <linux/proc_fs.h> // Necessary because we use the proc fs
38 #include <linux/if_arp.h>
39 #include <linux/random.h>
40 #include <linux/version.h>
41 #include <asm/io.h>
42 #include "ieee80211/ieee80211.h"
43
44
45
46
47 #define RTL819xE_MODULE_NAME "rtl819xE"
48 //added for HW security, john.0629
49 #define FALSE 0
50 #define TRUE 1
51 #define MAX_KEY_LEN 61
52 #define KEY_BUF_SIZE 5
53
54 #define BIT0 0x00000001
55 #define BIT1 0x00000002
56 #define BIT2 0x00000004
57 #define BIT3 0x00000008
58 #define BIT4 0x00000010
59 #define BIT5 0x00000020
60 #define BIT6 0x00000040
61 #define BIT7 0x00000080
62 #define BIT8 0x00000100
63 #define BIT9 0x00000200
64 #define BIT10 0x00000400
65 #define BIT11 0x00000800
66 #define BIT12 0x00001000
67 #define BIT13 0x00002000
68 #define BIT14 0x00004000
69 #define BIT15 0x00008000
70 #define BIT16 0x00010000
71 #define BIT17 0x00020000
72 #define BIT18 0x00040000
73 #define BIT19 0x00080000
74 #define BIT20 0x00100000
75 #define BIT21 0x00200000
76 #define BIT22 0x00400000
77 #define BIT23 0x00800000
78 #define BIT24 0x01000000
79 #define BIT25 0x02000000
80 #define BIT26 0x04000000
81 #define BIT27 0x08000000
82 #define BIT28 0x10000000
83 #define BIT29 0x20000000
84 #define BIT30 0x40000000
85 #define BIT31 0x80000000
86 // Rx smooth factor
87 #define Rx_Smooth_Factor 20
88 /* 2007/06/04 MH Define sliding window for RSSI history. */
89 #define PHY_RSSI_SLID_WIN_MAX 100
90 #define PHY_Beacon_RSSI_SLID_WIN_MAX 10
91
92 #define IC_VersionCut_D 0x3
93 #define IC_VersionCut_E 0x4
94
95 #define DMESG(x,a...)
96 #define DMESGW(x,a...)
97 #define DMESGE(x,a...)
98 extern u32 rt_global_debug_component;
99 #define RT_TRACE(component, x, args...) \
100 do { if(rt_global_debug_component & component) \
101 printk(KERN_DEBUG RTL819xE_MODULE_NAME ":" x "\n" , \
102 ##args);\
103 }while(0);
104
105 #define COMP_TRACE BIT0 // For function call tracing.
106 #define COMP_DBG BIT1 // Only for temporary debug message.
107 #define COMP_INIT BIT2 // during driver initialization / halt / reset.
108
109
110 #define COMP_RECV BIT3 // Reveive part data path.
111 #define COMP_SEND BIT4 // Send part path.
112 #define COMP_IO BIT5 // I/O Related. Added by Annie, 2006-03-02.
113 #define COMP_POWER BIT6 // 802.11 Power Save mode or System/Device Power state related.
114 #define COMP_EPROM BIT7 // 802.11 link related: join/start BSS, leave BSS.
115 #define COMP_SWBW BIT8 // For bandwidth switch.
116 #define COMP_SEC BIT9// For Security.
117
118
119 #define COMP_TURBO BIT10 // For Turbo Mode related. By Annie, 2005-10-21.
120 #define COMP_QOS BIT11 // For QoS.
121
122 #define COMP_RATE BIT12 // For Rate Adaptive mechanism, 2006.07.02, by rcnjko. #define COMP_EVENTS 0x00000080 // Event handling
123 #define COMP_RXDESC BIT13 // Show Rx desc information for SD3 debug. Added by Annie, 2006-07-15.
124 #define COMP_PHY BIT14
125 #define COMP_DIG BIT15 // For DIG, 2006.09.25, by rcnjko.
126 #define COMP_TXAGC BIT16 // For Tx power, 060928, by rcnjko.
127 #define COMP_HALDM BIT17 // For HW Dynamic Mechanism, 061010, by rcnjko.
128 #define COMP_POWER_TRACKING BIT18 //FOR 8190 TX POWER TRACKING
129 #define COMP_EVENTS BIT19 // Event handling
130
131 #define COMP_RF BIT20 // For RF.
132 //1!!!!!!!!!!!!!!!!!!!!!!!!!!!
133 //1//1Attention Please!!!<11n or 8190 specific code should be put below this line>
134 //1!!!!!!!!!!!!!!!!!!!!!!!!!!!
135
136 #define COMP_FIRMWARE BIT21 //for firmware downloading
137 #define COMP_HT BIT22 // For 802.11n HT related information. by Emily 2006-8-11
138
139 #define COMP_RESET BIT23
140 #define COMP_CMDPKT BIT24
141 #define COMP_SCAN BIT25
142 #define COMP_IPS BIT26
143 #define COMP_DOWN BIT27 // for rm driver module
144 #define COMP_INTR BIT28 // for interrupt
145 #define COMP_ERR BIT31 // for error out, always on
146
147 #define RTL819x_DEBUG
148 #ifdef RTL819x_DEBUG
149 #define assert(expr) \
150 if (!(expr)) { \
151 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
152 #expr,__FILE__,__FUNCTION__,__LINE__); \
153 }
154 //wb added to debug out data buf
155 //if you want print DATA buffer related BA, please set ieee80211_debug_level to DATA|BA
156 #define RT_DEBUG_DATA(level, data, datalen) \
157 do{ if ((rt_global_debug_component & (level)) == (level)) \
158 { \
159 int i; \
160 u8* pdata = (u8*) data; \
161 printk(KERN_DEBUG RTL819xE_MODULE_NAME ": %s()\n", __FUNCTION__); \
162 for(i=0; i<(int)(datalen); i++) \
163 { \
164 printk("%2x ", pdata[i]); \
165 if ((i+1)%16 == 0) printk("\n"); \
166 } \
167 printk("\n"); \
168 } \
169 } while (0)
170 #else
171 #define assert(expr) do {} while (0)
172 #define RT_DEBUG_DATA(level, data, datalen) do {} while(0)
173 #endif /* RTL8169_DEBUG */
174
175
176 //
177 // Queue Select Value in TxDesc
178 //
179 #define QSLT_BK 0x1
180 #define QSLT_BE 0x0
181 #define QSLT_VI 0x4
182 #define QSLT_VO 0x6
183 #define QSLT_BEACON 0x10
184 #define QSLT_HIGH 0x11
185 #define QSLT_MGNT 0x12
186 #define QSLT_CMD 0x13
187
188 #define DESC90_RATE1M 0x00
189 #define DESC90_RATE2M 0x01
190 #define DESC90_RATE5_5M 0x02
191 #define DESC90_RATE11M 0x03
192 #define DESC90_RATE6M 0x04
193 #define DESC90_RATE9M 0x05
194 #define DESC90_RATE12M 0x06
195 #define DESC90_RATE18M 0x07
196 #define DESC90_RATE24M 0x08
197 #define DESC90_RATE36M 0x09
198 #define DESC90_RATE48M 0x0a
199 #define DESC90_RATE54M 0x0b
200 #define DESC90_RATEMCS0 0x00
201 #define DESC90_RATEMCS1 0x01
202 #define DESC90_RATEMCS2 0x02
203 #define DESC90_RATEMCS3 0x03
204 #define DESC90_RATEMCS4 0x04
205 #define DESC90_RATEMCS5 0x05
206 #define DESC90_RATEMCS6 0x06
207 #define DESC90_RATEMCS7 0x07
208 #define DESC90_RATEMCS8 0x08
209 #define DESC90_RATEMCS9 0x09
210 #define DESC90_RATEMCS10 0x0a
211 #define DESC90_RATEMCS11 0x0b
212 #define DESC90_RATEMCS12 0x0c
213 #define DESC90_RATEMCS13 0x0d
214 #define DESC90_RATEMCS14 0x0e
215 #define DESC90_RATEMCS15 0x0f
216 #define DESC90_RATEMCS32 0x20
217
218 #define RTL819X_DEFAULT_RF_TYPE RF_1T2R
219 #define EEPROM_Default_LegacyHTTxPowerDiff 0x4
220 #define IEEE80211_WATCH_DOG_TIME 2000
221
222 /* For rtl819x */
223 typedef struct _tx_desc_819x_pci {
224 //DWORD 0
225 u16 PktSize;
226 u8 Offset;
227 u8 Reserved1:3;
228 u8 CmdInit:1;
229 u8 LastSeg:1;
230 u8 FirstSeg:1;
231 u8 LINIP:1;
232 u8 OWN:1;
233
234 //DWORD 1
235 u8 TxFWInfoSize;
236 u8 RATid:3;
237 u8 DISFB:1;
238 u8 USERATE:1;
239 u8 MOREFRAG:1;
240 u8 NoEnc:1;
241 u8 PIFS:1;
242 u8 QueueSelect:5;
243 u8 NoACM:1;
244 u8 Resv:2;
245 u8 SecCAMID:5;
246 u8 SecDescAssign:1;
247 u8 SecType:2;
248
249 //DWORD 2
250 u16 TxBufferSize;
251 u8 PktId:7;
252 u8 Resv1:1;
253 u8 Reserved2;
254
255 //DWORD 3
256 u32 TxBuffAddr;
257
258 //DWORD 4
259 u32 NextDescAddress;
260
261 //DWORD 5,6,7
262 u32 Reserved5;
263 u32 Reserved6;
264 u32 Reserved7;
265 }tx_desc_819x_pci, *ptx_desc_819x_pci;
266
267
268 typedef struct _tx_desc_cmd_819x_pci {
269 //DWORD 0
270 u16 PktSize;
271 u8 Reserved1;
272 u8 CmdType:3;
273 u8 CmdInit:1;
274 u8 LastSeg:1;
275 u8 FirstSeg:1;
276 u8 LINIP:1;
277 u8 OWN:1;
278
279 //DOWRD 1
280 u16 ElementReport;
281 u16 Reserved2;
282
283 //DOWRD 2
284 u16 TxBufferSize;
285 u16 Reserved3;
286
287 //DWORD 3,4,5
288 u32 TxBufferAddr;
289 u32 NextDescAddress;
290 u32 Reserved4;
291 u32 Reserved5;
292 u32 Reserved6;
293 }tx_desc_cmd_819x_pci, *ptx_desc_cmd_819x_pci;
294
295
296 typedef struct _tx_fwinfo_819x_pci {
297 //DOWRD 0
298 u8 TxRate:7;
299 u8 CtsEnable:1;
300 u8 RtsRate:7;
301 u8 RtsEnable:1;
302 u8 TxHT:1;
303 u8 Short:1; //Short PLCP for CCK, or short GI for 11n MCS
304 u8 TxBandwidth:1; // This is used for HT MCS rate only.
305 u8 TxSubCarrier:2; // This is used for legacy OFDM rate only.
306 u8 STBC:2;
307 u8 AllowAggregation:1;
308 u8 RtsHT:1; //Interpre RtsRate field as high throughput data rate
309 u8 RtsShort:1; //Short PLCP for CCK, or short GI for 11n MCS
310 u8 RtsBandwidth:1; // This is used for HT MCS rate only.
311 u8 RtsSubcarrier:2; // This is used for legacy OFDM rate only.
312 u8 RtsSTBC:2;
313 u8 EnableCPUDur:1; //Enable firmware to recalculate and assign packet duration
314
315 //DWORD 1
316 u8 RxMF:2;
317 u8 RxAMD:3;
318 u8 Reserved1:3;
319 u8 Reserved2;
320 u8 Reserved3;
321 u8 Reserved4;
322
323 //u32 Reserved;
324 }tx_fwinfo_819x_pci, *ptx_fwinfo_819x_pci;
325
326 typedef struct rtl8192_rx_info {
327 struct urb *urb;
328 struct net_device *dev;
329 u8 out_pipe;
330 }rtl8192_rx_info ;
331 typedef struct _rx_desc_819x_pci{
332 //DOWRD 0
333 u16 Length:14;
334 u16 CRC32:1;
335 u16 ICV:1;
336 u8 RxDrvInfoSize;
337 u8 Shift:2;
338 u8 PHYStatus:1;
339 u8 SWDec:1;
340 u8 LastSeg:1;
341 u8 FirstSeg:1;
342 u8 EOR:1;
343 u8 OWN:1;
344
345 //DWORD 1
346 u32 Reserved2;
347
348 //DWORD 2
349 u32 Reserved3;
350
351 //DWORD 3
352 u32 BufferAddress;
353
354 }rx_desc_819x_pci, *prx_desc_819x_pci;
355
356 typedef struct _rx_fwinfo_819x_pci{
357 //DWORD 0
358 u16 Reserved1:12;
359 u16 PartAggr:1;
360 u16 FirstAGGR:1;
361 u16 Reserved2:2;
362
363 u8 RxRate:7;
364 u8 RxHT:1;
365
366 u8 BW:1;
367 u8 SPLCP:1;
368 u8 Reserved3:2;
369 u8 PAM:1;
370 u8 Mcast:1;
371 u8 Bcast:1;
372 u8 Reserved4:1;
373
374 //DWORD 1
375 u32 TSFL;
376
377 }rx_fwinfo_819x_pci, *prx_fwinfo_819x_pci;
378
379 #define MAX_DEV_ADDR_SIZE 8 /* support till 64 bit bus width OS */
380 #define MAX_FIRMWARE_INFORMATION_SIZE 32 /*2006/04/30 by Emily forRTL8190*/
381 #define MAX_802_11_HEADER_LENGTH (40 + MAX_FIRMWARE_INFORMATION_SIZE)
382 #define ENCRYPTION_MAX_OVERHEAD 128
383 //#define USB_HWDESC_HEADER_LEN sizeof(tx_desc_819x_usb)
384 //#define TX_PACKET_SHIFT_BYTES (USB_HWDESC_HEADER_LEN + sizeof(tx_fwinfo_819x_usb))
385 #define MAX_FRAGMENT_COUNT 8
386 #define MAX_TRANSMIT_BUFFER_SIZE (1600+(MAX_802_11_HEADER_LENGTH+ENCRYPTION_MAX_OVERHEAD)*MAX_FRAGMENT_COUNT)
387
388 #define scrclng 4 // octets for crc32 (FCS, ICV)
389 /* 8190 Loopback Mode definition */
390 typedef enum _rtl819x_loopback{
391 RTL819X_NO_LOOPBACK = 0,
392 RTL819X_MAC_LOOPBACK = 1,
393 RTL819X_DMA_LOOPBACK = 2,
394 RTL819X_CCK_LOOPBACK = 3,
395 }rtl819x_loopback_e;
396
397 /* due to rtl8192 firmware */
398 typedef enum _desc_packet_type_e{
399 DESC_PACKET_TYPE_INIT = 0,
400 DESC_PACKET_TYPE_NORMAL = 1,
401 }desc_packet_type_e;
402
403 typedef enum _firmware_source{
404 FW_SOURCE_IMG_FILE = 0,
405 FW_SOURCE_HEADER_FILE = 1, //from header file
406 }firmware_source_e, *pfirmware_source_e;
407
408 typedef enum _firmware_status{
409 FW_STATUS_0_INIT = 0,
410 FW_STATUS_1_MOVE_BOOT_CODE = 1,
411 FW_STATUS_2_MOVE_MAIN_CODE = 2,
412 FW_STATUS_3_TURNON_CPU = 3,
413 FW_STATUS_4_MOVE_DATA_CODE = 4,
414 FW_STATUS_5_READY = 5,
415 }firmware_status_e;
416
417 typedef struct _rt_firmare_seg_container {
418 u16 seg_size;
419 u8 *seg_ptr;
420 }fw_seg_container, *pfw_seg_container;
421
422 typedef struct _rt_firmware{
423 firmware_status_e firmware_status;
424 u16 cmdpacket_frag_thresold;
425 #define RTL8190_MAX_FIRMWARE_CODE_SIZE 64000 //64k
426 #define MAX_FW_INIT_STEP 3
427 u8 firmware_buf[MAX_FW_INIT_STEP][RTL8190_MAX_FIRMWARE_CODE_SIZE];
428 u16 firmware_buf_size[MAX_FW_INIT_STEP];
429 }rt_firmware, *prt_firmware;
430 //+by amy 080507
431 #define MAX_RECEIVE_BUFFER_SIZE 9100 // Add this to 9100 bytes to receive A-MSDU from RT-AP
432
433 /* Firmware Queue Layout */
434 #define NUM_OF_FIRMWARE_QUEUE 10
435 #define NUM_OF_PAGES_IN_FW 0x100
436 #define NUM_OF_PAGE_IN_FW_QUEUE_BE 0x0aa
437 #define NUM_OF_PAGE_IN_FW_QUEUE_BK 0x007
438 #define NUM_OF_PAGE_IN_FW_QUEUE_VI 0x024
439 #define NUM_OF_PAGE_IN_FW_QUEUE_VO 0x007
440 #define NUM_OF_PAGE_IN_FW_QUEUE_HCCA 0
441 #define NUM_OF_PAGE_IN_FW_QUEUE_CMD 0x2
442 #define NUM_OF_PAGE_IN_FW_QUEUE_MGNT 0x10
443 #define NUM_OF_PAGE_IN_FW_QUEUE_HIGH 0
444 #define NUM_OF_PAGE_IN_FW_QUEUE_BCN 0x4
445 #define NUM_OF_PAGE_IN_FW_QUEUE_PUB 0xd
446 #define APPLIED_RESERVED_QUEUE_IN_FW 0x80000000
447 #define RSVD_FW_QUEUE_PAGE_BK_SHIFT 0x00
448 #define RSVD_FW_QUEUE_PAGE_BE_SHIFT 0x08
449 #define RSVD_FW_QUEUE_PAGE_VI_SHIFT 0x10
450 #define RSVD_FW_QUEUE_PAGE_VO_SHIFT 0x18
451 #define RSVD_FW_QUEUE_PAGE_MGNT_SHIFT 0x10
452 #define RSVD_FW_QUEUE_PAGE_CMD_SHIFT 0x08
453 #define RSVD_FW_QUEUE_PAGE_BCN_SHIFT 0x00
454 #define RSVD_FW_QUEUE_PAGE_PUB_SHIFT 0x08
455
456 //8187B Security
457 //#define RWCAM 0xA0 // Software read/write CAM config
458 //#define WCAMI 0xA4 // Software write CAM input content
459 //#define RCAMO 0xA8 // Output value from CAM according to 0xa0 setting
460 #define DCAM 0xAC // Debug CAM Interface
461 #define AESMSK_FC 0xB2 // AES Mask register for frame control (0xB2~0xB3). Added by Annie, 2006-03-06.
462
463
464 #define CAM_CONTENT_COUNT 8
465 //#define CFG_DEFAULT_KEY BIT5
466 #define CFG_VALID BIT15
467 #define EPROM_93c46 0
468 #define EPROM_93c56 1
469
470 #define DEFAULT_FRAG_THRESHOLD 2342U
471 #define MIN_FRAG_THRESHOLD 256U
472 #define DEFAULT_BEACONINTERVAL 0x64U
473 #define DEFAULT_BEACON_ESSID "Rtl819xU"
474
475 #define DEFAULT_SSID ""
476 #define DEFAULT_RETRY_RTS 7
477 #define DEFAULT_RETRY_DATA 7
478 #define PRISM_HDR_SIZE 64
479
480 #define PHY_RSSI_SLID_WIN_MAX 100
481
482
483 typedef enum _WIRELESS_MODE {
484 WIRELESS_MODE_UNKNOWN = 0x00,
485 WIRELESS_MODE_A = 0x01,
486 WIRELESS_MODE_B = 0x02,
487 WIRELESS_MODE_G = 0x04,
488 WIRELESS_MODE_AUTO = 0x08,
489 WIRELESS_MODE_N_24G = 0x10,
490 WIRELESS_MODE_N_5G = 0x20
491 } WIRELESS_MODE;
492
493 #define RTL_IOCTL_WPA_SUPPLICANT SIOCIWFIRSTPRIV+30
494
495 typedef struct buffer
496 {
497 struct buffer *next;
498 u32 *buf;
499 dma_addr_t dma;
500
501 } buffer;
502
503 typedef struct rtl_reg_debug{
504 unsigned int cmd;
505 struct {
506 unsigned char type;
507 unsigned char addr;
508 unsigned char page;
509 unsigned char length;
510 } head;
511 unsigned char buf[0xff];
512 }rtl_reg_debug;
513
514
515 typedef struct _rt_9x_tx_rate_history {
516 u32 cck[4];
517 u32 ofdm[8];
518 // HT_MCS[0][]: BW=0 SG=0
519 // HT_MCS[1][]: BW=1 SG=0
520 // HT_MCS[2][]: BW=0 SG=1
521 // HT_MCS[3][]: BW=1 SG=1
522 u32 ht_mcs[4][16];
523 }rt_tx_rahis_t, *prt_tx_rahis_t;
524
525 typedef struct _RT_SMOOTH_DATA_4RF {
526 char elements[4][100];//array to store values
527 u32 index; //index to current array to store
528 u32 TotalNum; //num of valid elements
529 u32 TotalVal[4]; //sum of valid elements
530 }RT_SMOOTH_DATA_4RF, *PRT_SMOOTH_DATA_4RF;
531
532 typedef enum _tag_TxCmd_Config_Index{
533 TXCMD_TXRA_HISTORY_CTRL = 0xFF900000,
534 TXCMD_RESET_TX_PKT_BUFF = 0xFF900001,
535 TXCMD_RESET_RX_PKT_BUFF = 0xFF900002,
536 TXCMD_SET_TX_DURATION = 0xFF900003,
537 TXCMD_SET_RX_RSSI = 0xFF900004,
538 TXCMD_SET_TX_PWR_TRACKING = 0xFF900005,
539 TXCMD_XXXX_CTRL,
540 }DCMD_TXCMD_OP;
541
542 typedef struct Stats
543 {
544 unsigned long txrdu;
545 unsigned long rxrdu;
546 //unsigned long rxnolast;
547 //unsigned long rxnodata;
548 // unsigned long rxreset;
549 // unsigned long rxnopointer;
550 unsigned long rxok;
551 unsigned long rxframgment;
552 unsigned long rxcmdpkt[4]; //08/05/08 amy rx cmd element txfeedback/bcn report/cfg set/query
553 unsigned long rxurberr;
554 unsigned long rxstaterr;
555 unsigned long rxcrcerrmin;//crc error (0-500)
556 unsigned long rxcrcerrmid;//crc error (500-1000)
557 unsigned long rxcrcerrmax;//crc error (>1000)
558 unsigned long received_rate_histogram[4][32]; //0: Total, 1:OK, 2:CRC, 3:ICV, 2007 07 03 cosa
559 unsigned long received_preamble_GI[2][32]; //0: Long preamble/GI, 1:Short preamble/GI
560 unsigned long rx_AMPDUsize_histogram[5]; // level: (<4K), (4K~8K), (8K~16K), (16K~32K), (32K~64K)
561 unsigned long rx_AMPDUnum_histogram[5]; // level: (<5), (5~10), (10~20), (20~40), (>40)
562 unsigned long numpacket_matchbssid; // debug use only.
563 unsigned long numpacket_toself; // debug use only.
564 unsigned long num_process_phyinfo; // debug use only.
565 unsigned long numqry_phystatus;
566 unsigned long numqry_phystatusCCK;
567 unsigned long numqry_phystatusHT;
568 unsigned long received_bwtype[5]; //0: 20M, 1: funn40M, 2: upper20M, 3: lower20M, 4: duplicate
569 unsigned long txnperr;
570 unsigned long txnpdrop;
571 unsigned long txresumed;
572 // unsigned long rxerr;
573 unsigned long rxoverflow;
574 unsigned long rxint;
575 unsigned long txnpokint;
576 // unsigned long txhpokint;
577 // unsigned long txhperr;
578 unsigned long ints;
579 unsigned long shints;
580 unsigned long txoverflow;
581 // unsigned long rxdmafail;
582 // unsigned long txbeacon;
583 // unsigned long txbeaconerr;
584 unsigned long txlpokint;
585 unsigned long txlpdrop;
586 unsigned long txlperr;
587 unsigned long txbeokint;
588 unsigned long txbedrop;
589 unsigned long txbeerr;
590 unsigned long txbkokint;
591 unsigned long txbkdrop;
592 unsigned long txbkerr;
593 unsigned long txviokint;
594 unsigned long txvidrop;
595 unsigned long txvierr;
596 unsigned long txvookint;
597 unsigned long txvodrop;
598 unsigned long txvoerr;
599 unsigned long txbeaconokint;
600 unsigned long txbeacondrop;
601 unsigned long txbeaconerr;
602 unsigned long txmanageokint;
603 unsigned long txmanagedrop;
604 unsigned long txmanageerr;
605 unsigned long txcmdpktokint;
606 unsigned long txdatapkt;
607 unsigned long txfeedback;
608 unsigned long txfeedbackok;
609 unsigned long txoktotal;
610 unsigned long txokbytestotal;
611 unsigned long txokinperiod;
612 unsigned long txmulticast;
613 unsigned long txbytesmulticast;
614 unsigned long txbroadcast;
615 unsigned long txbytesbroadcast;
616 unsigned long txunicast;
617 unsigned long txbytesunicast;
618 unsigned long rxbytesunicast;
619 unsigned long txfeedbackfail;
620 unsigned long txerrtotal;
621 unsigned long txerrbytestotal;
622 unsigned long txerrmulticast;
623 unsigned long txerrbroadcast;
624 unsigned long txerrunicast;
625 unsigned long txretrycount;
626 unsigned long txfeedbackretry;
627 u8 last_packet_rate;
628 unsigned long slide_signal_strength[100];
629 unsigned long slide_evm[100];
630 unsigned long slide_rssi_total; // For recording sliding window's RSSI value
631 unsigned long slide_evm_total; // For recording sliding window's EVM value
632 long signal_strength; // Transformed, in dbm. Beautified signal strength for UI, not correct.
633 long signal_quality;
634 long last_signal_strength_inpercent;
635 long recv_signal_power; // Correct smoothed ss in Dbm, only used in driver to report real power now.
636 u8 rx_rssi_percentage[4];
637 u8 rx_evm_percentage[2];
638 long rxSNRdB[4];
639 rt_tx_rahis_t txrate;
640 u32 Slide_Beacon_pwdb[100]; //cosa add for beacon rssi
641 u32 Slide_Beacon_Total; //cosa add for beacon rssi
642 RT_SMOOTH_DATA_4RF cck_adc_pwdb;
643 u32 CurrentShowTxate;
644
645
646 } Stats;
647
648
649 // Bandwidth Offset
650 #define HAL_PRIME_CHNL_OFFSET_DONT_CARE 0
651 #define HAL_PRIME_CHNL_OFFSET_LOWER 1
652 #define HAL_PRIME_CHNL_OFFSET_UPPER 2
653
654 //+by amy 080507
655
656 typedef struct ChnlAccessSetting {
657 u16 SIFS_Timer;
658 u16 DIFS_Timer;
659 u16 SlotTimeTimer;
660 u16 EIFS_Timer;
661 u16 CWminIndex;
662 u16 CWmaxIndex;
663 }*PCHANNEL_ACCESS_SETTING,CHANNEL_ACCESS_SETTING;
664
665 typedef struct _BB_REGISTER_DEFINITION{
666 u32 rfintfs; // set software control: // 0x870~0x877[8 bytes]
667 u32 rfintfi; // readback data: // 0x8e0~0x8e7[8 bytes]
668 u32 rfintfo; // output data: // 0x860~0x86f [16 bytes]
669 u32 rfintfe; // output enable: // 0x860~0x86f [16 bytes]
670 u32 rf3wireOffset; // LSSI data: // 0x840~0x84f [16 bytes]
671 u32 rfLSSI_Select; // BB Band Select: // 0x878~0x87f [8 bytes]
672 u32 rfTxGainStage; // Tx gain stage: // 0x80c~0x80f [4 bytes]
673 u32 rfHSSIPara1; // wire parameter control1 : // 0x820~0x823,0x828~0x82b, 0x830~0x833, 0x838~0x83b [16 bytes]
674 u32 rfHSSIPara2; // wire parameter control2 : // 0x824~0x827,0x82c~0x82f, 0x834~0x837, 0x83c~0x83f [16 bytes]
675 u32 rfSwitchControl; //Tx Rx antenna control : // 0x858~0x85f [16 bytes]
676 u32 rfAGCControl1; //AGC parameter control1 : // 0xc50~0xc53,0xc58~0xc5b, 0xc60~0xc63, 0xc68~0xc6b [16 bytes]
677 u32 rfAGCControl2; //AGC parameter control2 : // 0xc54~0xc57,0xc5c~0xc5f, 0xc64~0xc67, 0xc6c~0xc6f [16 bytes]
678 u32 rfRxIQImbalance; //OFDM Rx IQ imbalance matrix : // 0xc14~0xc17,0xc1c~0xc1f, 0xc24~0xc27, 0xc2c~0xc2f [16 bytes]
679 u32 rfRxAFE; //Rx IQ DC ofset and Rx digital filter, Rx DC notch filter : // 0xc10~0xc13,0xc18~0xc1b, 0xc20~0xc23, 0xc28~0xc2b [16 bytes]
680 u32 rfTxIQImbalance; //OFDM Tx IQ imbalance matrix // 0xc80~0xc83,0xc88~0xc8b, 0xc90~0xc93, 0xc98~0xc9b [16 bytes]
681 u32 rfTxAFE; //Tx IQ DC Offset and Tx DFIR type // 0xc84~0xc87,0xc8c~0xc8f, 0xc94~0xc97, 0xc9c~0xc9f [16 bytes]
682 u32 rfLSSIReadBack; //LSSI RF readback data // 0x8a0~0x8af [16 bytes]
683 }BB_REGISTER_DEFINITION_T, *PBB_REGISTER_DEFINITION_T;
684
685 typedef enum _RT_RF_TYPE_819xU{
686 RF_TYPE_MIN = 0,
687 RF_8225,
688 RF_8256,
689 RF_8258,
690 RF_PSEUDO_11N = 4,
691 }RT_RF_TYPE_819xU, *PRT_RF_TYPE_819xU;
692
693
694 typedef struct _rate_adaptive
695 {
696 u8 rate_adaptive_disabled;
697 u8 ratr_state;
698 u16 reserve;
699
700 u32 high_rssi_thresh_for_ra;
701 u32 high2low_rssi_thresh_for_ra;
702 u8 low2high_rssi_thresh_for_ra40M;
703 u32 low_rssi_thresh_for_ra40M;
704 u8 low2high_rssi_thresh_for_ra20M;
705 u32 low_rssi_thresh_for_ra20M;
706 u32 upper_rssi_threshold_ratr;
707 u32 middle_rssi_threshold_ratr;
708 u32 low_rssi_threshold_ratr;
709 u32 low_rssi_threshold_ratr_40M;
710 u32 low_rssi_threshold_ratr_20M;
711 u8 ping_rssi_enable; //cosa add for test
712 u32 ping_rssi_ratr; //cosa add for test
713 u32 ping_rssi_thresh_for_ra;//cosa add for test
714 u32 last_ratr;
715
716 } rate_adaptive, *prate_adaptive;
717 #define TxBBGainTableLength 37
718 #define CCKTxBBGainTableLength 23
719 typedef struct _txbbgain_struct
720 {
721 long txbb_iq_amplifygain;
722 u32 txbbgain_value;
723 } txbbgain_struct, *ptxbbgain_struct;
724
725 typedef struct _ccktxbbgain_struct
726 {
727 //The Value is from a22 to a29 one Byte one time is much Safer
728 u8 ccktxbb_valuearray[8];
729 } ccktxbbgain_struct,*pccktxbbgain_struct;
730
731
732 typedef struct _init_gain
733 {
734 u8 xaagccore1;
735 u8 xbagccore1;
736 u8 xcagccore1;
737 u8 xdagccore1;
738 u8 cca;
739
740 } init_gain, *pinit_gain;
741
742 /* 2007/11/02 MH Define RF mode temporarily for test. */
743 typedef enum tag_Rf_Operatetion_State
744 {
745 RF_STEP_INIT = 0,
746 RF_STEP_NORMAL,
747 RF_STEP_MAX
748 }RF_STEP_E;
749
750 typedef enum _RT_STATUS{
751 RT_STATUS_SUCCESS,
752 RT_STATUS_FAILURE,
753 RT_STATUS_PENDING,
754 RT_STATUS_RESOURCE
755 }RT_STATUS,*PRT_STATUS;
756
757 typedef enum _RT_CUSTOMER_ID
758 {
759 RT_CID_DEFAULT = 0,
760 RT_CID_8187_ALPHA0 = 1,
761 RT_CID_8187_SERCOMM_PS = 2,
762 RT_CID_8187_HW_LED = 3,
763 RT_CID_8187_NETGEAR = 4,
764 RT_CID_WHQL = 5,
765 RT_CID_819x_CAMEO = 6,
766 RT_CID_819x_RUNTOP = 7,
767 RT_CID_819x_Senao = 8,
768 RT_CID_TOSHIBA = 9, // Merge by Jacken, 2008/01/31.
769 RT_CID_819x_Netcore = 10,
770 RT_CID_Nettronix = 11,
771 RT_CID_DLINK = 12,
772 RT_CID_PRONET = 13,
773 RT_CID_COREGA = 14,
774 }RT_CUSTOMER_ID, *PRT_CUSTOMER_ID;
775
776 //================================================================================
777 // LED customization.
778 //================================================================================
779
780 typedef enum _LED_STRATEGY_8190{
781 SW_LED_MODE0, // SW control 1 LED via GPIO0. It is default option.
782 SW_LED_MODE1, // SW control for PCI Express
783 SW_LED_MODE2, // SW control for Cameo.
784 SW_LED_MODE3, // SW contorl for RunTop.
785 SW_LED_MODE4, // SW control for Netcore
786 SW_LED_MODE5, //added by vivi, for led new mode, DLINK
787 SW_LED_MODE6, //added by vivi, for led new mode, PRONET
788 HW_LED, // HW control 2 LEDs, LED0 and LED1 (there are 4 different control modes)
789 }LED_STRATEGY_8190, *PLED_STRATEGY_8190;
790
791 #define CHANNEL_PLAN_LEN 10
792
793 #define sCrcLng 4
794
795 typedef struct _TX_FWINFO_STRUCUTRE{
796 //DOWRD 0
797 u8 TxRate:7;
798 u8 CtsEnable:1;
799 u8 RtsRate:7;
800 u8 RtsEnable:1;
801 u8 TxHT:1;
802 u8 Short:1;
803 u8 TxBandwidth:1;
804 u8 TxSubCarrier:2;
805 u8 STBC:2;
806 u8 AllowAggregation:1;
807 u8 RtsHT:1;
808 u8 RtsShort:1;
809 u8 RtsBandwidth:1;
810 u8 RtsSubcarrier:2;
811 u8 RtsSTBC:2;
812 u8 EnableCPUDur:1;
813
814 //DWORD 1
815 u32 RxMF:2;
816 u32 RxAMD:3;
817 u32 Reserved1:3;
818 u32 TxAGCOffset:4;
819 u32 TxAGCSign:1;
820 u32 Tx_INFO_RSVD:6;
821 u32 PacketID:13;
822 }TX_FWINFO_T;
823
824
825 typedef struct _TX_FWINFO_8190PCI{
826 //DOWRD 0
827 u8 TxRate:7;
828 u8 CtsEnable:1;
829 u8 RtsRate:7;
830 u8 RtsEnable:1;
831 u8 TxHT:1;
832 u8 Short:1; //Short PLCP for CCK, or short GI for 11n MCS
833 u8 TxBandwidth:1; // This is used for HT MCS rate only.
834 u8 TxSubCarrier:2; // This is used for legacy OFDM rate only.
835 u8 STBC:2;
836 u8 AllowAggregation:1;
837 u8 RtsHT:1; //Interpre RtsRate field as high throughput data rate
838 u8 RtsShort:1; //Short PLCP for CCK, or short GI for 11n MCS
839 u8 RtsBandwidth:1; // This is used for HT MCS rate only.
840 u8 RtsSubcarrier:2; // This is used for legacy OFDM rate only.
841 u8 RtsSTBC:2;
842 u8 EnableCPUDur:1; //Enable firmware to recalculate and assign packet duration
843
844 //DWORD 1
845 u32 RxMF:2;
846 u32 RxAMD:3;
847 u32 TxPerPktInfoFeedback:1; // 1: indicate that the transimission info of this packet should be gathered by Firmware and retured by Rx Cmd.
848 u32 Reserved1:2;
849 u32 TxAGCOffset:4; // Only 90 support
850 u32 TxAGCSign:1; // Only 90 support
851 u32 RAW_TXD:1; // MAC will send data in txpktbuffer without any processing,such as CRC check
852 u32 Retry_Limit:4; // CCX Support relative retry limit FW page only support 4 bits now.
853 u32 Reserved2:1;
854 u32 PacketID:13;
855
856 // DW 2
857
858 }TX_FWINFO_8190PCI, *PTX_FWINFO_8190PCI;
859
860 typedef struct _phy_ofdm_rx_status_report_819xpci
861 {
862 u8 trsw_gain_X[4];
863 u8 pwdb_all;
864 u8 cfosho_X[4];
865 u8 cfotail_X[4];
866 u8 rxevm_X[2];
867 u8 rxsnr_X[4];
868 u8 pdsnr_X[2];
869 u8 csi_current_X[2];
870 u8 csi_target_X[2];
871 u8 sigevm;
872 u8 max_ex_pwr;
873 u8 sgi_en;
874 u8 rxsc_sgien_exflg;
875 }phy_sts_ofdm_819xpci_t;
876
877 typedef struct _phy_cck_rx_status_report_819xpci
878 {
879 /* For CCK rate descriptor. This is a unsigned 8:1 variable. LSB bit presend
880 0.5. And MSB 7 bts presend a signed value. Range from -64~+63.5. */
881 u8 adc_pwdb_X[4];
882 u8 sq_rpt;
883 u8 cck_agc_rpt;
884 }phy_sts_cck_819xpci_t;
885
886 typedef struct _phy_ofdm_rx_status_rxsc_sgien_exintfflag{
887 u8 reserved:4;
888 u8 rxsc:2;
889 u8 sgi_en:1;
890 u8 ex_intf_flag:1;
891 }phy_ofdm_rx_status_rxsc_sgien_exintfflag;
892
893 typedef enum _RT_OP_MODE{
894 RT_OP_MODE_AP,
895 RT_OP_MODE_INFRASTRUCTURE,
896 RT_OP_MODE_IBSS,
897 RT_OP_MODE_NO_LINK,
898 }RT_OP_MODE, *PRT_OP_MODE;
899
900
901 /* 2007/11/02 MH Define RF mode temporarily for test. */
902 typedef enum tag_Rf_OpType
903 {
904 RF_OP_By_SW_3wire = 0,
905 RF_OP_By_FW,
906 RF_OP_MAX
907 }RF_OpType_E;
908
909 typedef enum _RESET_TYPE {
910 RESET_TYPE_NORESET = 0x00,
911 RESET_TYPE_NORMAL = 0x01,
912 RESET_TYPE_SILENT = 0x02
913 } RESET_TYPE;
914
915 typedef struct _tx_ring{
916 u32 * desc;
917 u8 nStuckCount;
918 struct _tx_ring * next;
919 }__attribute__ ((packed)) tx_ring, * ptx_ring;
920
921 struct rtl8192_tx_ring {
922 tx_desc_819x_pci *desc;
923 dma_addr_t dma;
924 unsigned int idx;
925 unsigned int entries;
926 struct sk_buff_head queue;
927 };
928
929 #define NIC_SEND_HANG_THRESHOLD_NORMAL 4
930 #define NIC_SEND_HANG_THRESHOLD_POWERSAVE 8
931 #define MAX_TX_QUEUE 9 // BK, BE, VI, VO, HCCA, MANAGEMENT, COMMAND, HIGH, BEACON.
932
933 #define MAX_RX_COUNT 64
934 #define MAX_TX_QUEUE_COUNT 9
935
936 typedef struct r8192_priv
937 {
938 struct pci_dev *pdev;
939 //added for maintain info from eeprom
940 short epromtype;
941 u16 eeprom_vid;
942 u16 eeprom_did;
943 u8 eeprom_CustomerID;
944 u16 eeprom_ChannelPlan;
945 RT_CUSTOMER_ID CustomerID;
946 LED_STRATEGY_8190 LedStrategy;
947 //bool bDcut;
948 u8 IC_Cut;
949 int irq;
950 short irq_enabled;
951 struct ieee80211_device *ieee80211;
952 #ifdef ENABLE_LPS
953 bool ps_force;
954 bool force_lps;
955 bool bdisable_nic;
956 #endif
957 bool being_init_adapter;
958 u8 Rf_Mode;
959 short card_8192; /* O: rtl8192, 1:rtl8185 V B/C, 2:rtl8185 V D */
960 u8 card_8192_version; /* if TCR reports card V B/C this discriminates */
961 // short phy_ver; /* meaningful for rtl8225 1:A 2:B 3:C */
962 short enable_gpio0;
963 enum card_type {PCI,MINIPCI,CARDBUS,USB/*rtl8187*/}card_type;
964 short hw_plcp_len;
965 short plcp_preamble_mode;
966 u8 ScanDelay;
967 spinlock_t irq_lock;
968 spinlock_t irq_th_lock;
969 spinlock_t tx_lock;
970 spinlock_t rf_ps_lock;
971 struct mutex mutex;
972 spinlock_t rf_lock; //used to lock rf write operation added by wb
973 spinlock_t ps_lock;
974
975 u32 irq_mask;
976 // short irq_enabled;
977 // struct net_device *dev; //comment this out.
978 short chan;
979 short sens;
980 short max_sens;
981 u32 rx_prevlen;
982 /*RX stuff*/
983 rx_desc_819x_pci *rx_ring;
984 dma_addr_t rx_ring_dma;
985 unsigned int rx_idx;
986 struct sk_buff *rx_buf[MAX_RX_COUNT];
987 int rxringcount;
988 u16 rxbuffersize;
989
990
991 struct sk_buff *rx_skb;
992 u32 *rxring;
993 u32 *rxringtail;
994 dma_addr_t rxringdma;
995 struct buffer *rxbuffer;
996 struct buffer *rxbufferhead;
997 short rx_skb_complete;
998 /*TX stuff*/
999 struct rtl8192_tx_ring tx_ring[MAX_TX_QUEUE_COUNT];
1000 int txringcount;
1001 //{
1002 int txbuffsize;
1003 int txfwbuffersize;
1004 //struct tx_pendingbuf txnp_pending;
1005 //struct tasklet_struct irq_tx_tasklet;
1006 struct tasklet_struct irq_rx_tasklet;
1007 struct tasklet_struct irq_tx_tasklet;
1008 struct tasklet_struct irq_prepare_beacon_tasklet;
1009 struct buffer *txmapbufs;
1010 struct buffer *txbkpbufs;
1011 struct buffer *txbepbufs;
1012 struct buffer *txvipbufs;
1013 struct buffer *txvopbufs;
1014 struct buffer *txcmdbufs;
1015 struct buffer *txmapbufstail;
1016 struct buffer *txbkpbufstail;
1017 struct buffer *txbepbufstail;
1018 struct buffer *txvipbufstail;
1019 struct buffer *txvopbufstail;
1020 struct buffer *txcmdbufstail;
1021 /* adhoc/master mode stuff */
1022 ptx_ring txbeaconringtail;
1023 dma_addr_t txbeaconringdma;
1024 ptx_ring txbeaconring;
1025 int txbeaconcount;
1026 struct buffer *txbeaconbufs;
1027 struct buffer *txbeaconbufstail;
1028 ptx_ring txmapring;
1029 ptx_ring txbkpring;
1030 ptx_ring txbepring;
1031 ptx_ring txvipring;
1032 ptx_ring txvopring;
1033 ptx_ring txcmdring;
1034 ptx_ring txmapringtail;
1035 ptx_ring txbkpringtail;
1036 ptx_ring txbepringtail;
1037 ptx_ring txvipringtail;
1038 ptx_ring txvopringtail;
1039 ptx_ring txcmdringtail;
1040 ptx_ring txmapringhead;
1041 ptx_ring txbkpringhead;
1042 ptx_ring txbepringhead;
1043 ptx_ring txvipringhead;
1044 ptx_ring txvopringhead;
1045 ptx_ring txcmdringhead;
1046 dma_addr_t txmapringdma;
1047 dma_addr_t txbkpringdma;
1048 dma_addr_t txbepringdma;
1049 dma_addr_t txvipringdma;
1050 dma_addr_t txvopringdma;
1051 dma_addr_t txcmdringdma;
1052 // u8 chtxpwr[15]; //channels from 1 to 14, 0 not used
1053 // u8 chtxpwr_ofdm[15]; //channels from 1 to 14, 0 not used
1054 // u8 cck_txpwr_base;
1055 // u8 ofdm_txpwr_base;
1056 // u8 challow[15]; //channels from 1 to 14, 0 not used
1057 short up;
1058 short crcmon; //if 1 allow bad crc frame reception in monitor mode
1059 // short prism_hdr;
1060
1061 // struct timer_list scan_timer;
1062 /*short scanpending;
1063 short stopscan;*/
1064 // spinlock_t scan_lock;
1065 // u8 active_probe;
1066 //u8 active_scan_num;
1067 struct semaphore wx_sem;
1068 struct semaphore rf_sem; //used to lock rf write operation added by wb, modified by david
1069 // short hw_wep;
1070
1071 // short digphy;
1072 // short antb;
1073 // short diversity;
1074 // u8 cs_treshold;
1075 // short rcr_csense;
1076 u8 rf_type; //0 means 1T2R, 1 means 2T4R
1077 RT_RF_TYPE_819xU rf_chip;
1078
1079 // u32 key0[4];
1080 short (*rf_set_sens)(struct net_device *dev,short sens);
1081 u8 (*rf_set_chan)(struct net_device *dev,u8 ch);
1082 void (*rf_close)(struct net_device *dev);
1083 void (*rf_init)(struct net_device *dev);
1084 //short rate;
1085 short promisc;
1086 /*stats*/
1087 struct Stats stats;
1088 struct iw_statistics wstats;
1089 struct proc_dir_entry *dir_dev;
1090
1091 /*RX stuff*/
1092 // u32 *rxring;
1093 // u32 *rxringtail;
1094 // dma_addr_t rxringdma;
1095
1096 #ifdef THOMAS_BEACON
1097 u32 *oldaddr;
1098 #endif
1099 #ifdef THOMAS_TASKLET
1100 atomic_t irt_counter;//count for irq_rx_tasklet
1101 #endif
1102 #ifdef JACKSON_NEW_RX
1103 struct sk_buff **pp_rxskb;
1104 int rx_inx;
1105 #endif
1106
1107 /* modified by davad for Rx process */
1108 struct sk_buff_head rx_queue;
1109 struct sk_buff_head skb_queue;
1110 struct work_struct qos_activate;
1111 short tx_urb_index;
1112 atomic_t tx_pending[0x10];//UART_PRIORITY+1
1113
1114 struct urb *rxurb_task;
1115
1116 //2 Tx Related variables
1117 u16 ShortRetryLimit;
1118 u16 LongRetryLimit;
1119 u32 TransmitConfig;
1120 u8 RegCWinMin; // For turbo mode CW adaptive. Added by Annie, 2005-10-27.
1121
1122 u32 LastRxDescTSFHigh;
1123 u32 LastRxDescTSFLow;
1124
1125
1126 //2 Rx Related variables
1127 u16 EarlyRxThreshold;
1128 u32 ReceiveConfig;
1129 u8 AcmControl;
1130
1131 u8 RFProgType;
1132
1133 u8 retry_data;
1134 u8 retry_rts;
1135 u16 rts;
1136
1137 struct ChnlAccessSetting ChannelAccessSetting;
1138
1139 struct work_struct reset_wq;
1140
1141 /**********************************************************/
1142 //for rtl819xPci
1143 // Data Rate Config. Added by Annie, 2006-04-13.
1144 u16 basic_rate;
1145 u8 short_preamble;
1146 u8 slot_time;
1147 u16 SifsTime;
1148 /* WirelessMode*/
1149 u8 RegWirelessMode;
1150 /*Firmware*/
1151 prt_firmware pFirmware;
1152 rtl819x_loopback_e LoopbackMode;
1153 firmware_source_e firmware_source;
1154 bool AutoloadFailFlag;
1155 u16 EEPROMTxPowerDiff;
1156 u16 EEPROMAntPwDiff; // Antenna gain offset from B/C/D to A
1157 u8 EEPROMThermalMeter;
1158 u8 EEPROMPwDiff;
1159 u8 EEPROMCrystalCap;
1160 u8 EEPROM_Def_Ver;
1161 u8 EEPROMTxPowerLevelCCK[14];// CCK channel 1~14
1162 // The following definition is for eeprom 93c56
1163 u8 EEPROMRfACCKChnl1TxPwLevel[3]; //RF-A CCK Tx Power Level at channel 7
1164 u8 EEPROMRfAOfdmChnlTxPwLevel[3];//RF-A CCK Tx Power Level at [0],[1],[2] = channel 1,7,13
1165 u8 EEPROMRfCCCKChnl1TxPwLevel[3]; //RF-C CCK Tx Power Level at channel 7
1166 u8 EEPROMRfCOfdmChnlTxPwLevel[3];//RF-C CCK Tx Power Level at [0],[1],[2] = channel 1,7,13
1167 u8 EEPROMTxPowerLevelCCK_V1[3];
1168 u8 EEPROMTxPowerLevelOFDM24G[14]; // OFDM 2.4G channel 1~14
1169 u8 EEPROMTxPowerLevelOFDM5G[24]; // OFDM 5G
1170 u8 EEPROMLegacyHTTxPowerDiff; // Legacy to HT rate power diff
1171 bool bTXPowerDataReadFromEEPORM;
1172 /*channel plan*/
1173 u16 RegChannelPlan; // Channel Plan specifed by user, 15: following setting of EEPROM, 0-14: default channel plan index specified by user.
1174 u16 ChannelPlan;
1175 /*PS related*/
1176 bool RegRfOff;
1177 // Rf off action for power save
1178 u8 bHwRfOffAction; //0:No action, 1:By GPIO, 2:By Disable
1179 /*PHY related*/
1180 BB_REGISTER_DEFINITION_T PHYRegDef[4]; //Radio A/B/C/D
1181 // Read/write are allow for following hardware information variables
1182 u32 MCSTxPowerLevelOriginalOffset[6];
1183 u32 CCKTxPowerLevelOriginalOffset;
1184 u8 TxPowerLevelCCK[14]; // CCK channel 1~14
1185 u8 TxPowerLevelCCK_A[14]; // RF-A, CCK channel 1~14
1186 u8 TxPowerLevelCCK_C[14];
1187 u8 TxPowerLevelOFDM24G[14]; // OFDM 2.4G channel 1~14
1188 u8 TxPowerLevelOFDM5G[14]; // OFDM 5G
1189 u8 TxPowerLevelOFDM24G_A[14]; // RF-A, OFDM 2.4G channel 1~14
1190 u8 TxPowerLevelOFDM24G_C[14]; // RF-C, OFDM 2.4G channel 1~14
1191 u8 LegacyHTTxPowerDiff; // Legacy to HT rate power diff
1192 u8 TxPowerDiff;
1193 char RF_C_TxPwDiff; // Antenna gain offset, rf-c to rf-a
1194 u8 AntennaTxPwDiff[3]; // Antenna gain offset, index 0 for B, 1 for C, and 2 for D
1195 u8 CrystalCap; // CrystalCap.
1196 u8 ThermalMeter[2]; // ThermalMeter, index 0 for RFIC0, and 1 for RFIC1
1197 //05/27/2008 cck power enlarge
1198 u8 CckPwEnl;
1199 u16 TSSI_13dBm;
1200 u32 Pwr_Track;
1201 u8 CCKPresentAttentuation_20Mdefault;
1202 u8 CCKPresentAttentuation_40Mdefault;
1203 char CCKPresentAttentuation_difference;
1204 char CCKPresentAttentuation;
1205 // Use to calculate PWBD.
1206 u8 bCckHighPower;
1207 long undecorated_smoothed_pwdb;
1208 long undecorated_smoothed_cck_adc_pwdb[4];
1209 //for set channel
1210 u8 SwChnlInProgress;
1211 u8 SwChnlStage;
1212 u8 SwChnlStep;
1213 u8 SetBWModeInProgress;
1214 HT_CHANNEL_WIDTH CurrentChannelBW;
1215
1216 // 8190 40MHz mode
1217 //
1218 u8 nCur40MhzPrimeSC; // Control channel sub-carrier
1219 // Joseph test for shorten RF configuration time.
1220 // We save RF reg0 in this variable to reduce RF reading.
1221 //
1222 u32 RfReg0Value[4];
1223 u8 NumTotalRFPath;
1224 bool brfpath_rxenable[4];
1225 //+by amy 080507
1226 struct timer_list watch_dog_timer;
1227
1228 //+by amy 080515 for dynamic mechenism
1229 //Add by amy Tx Power Control for Near/Far Range 2008/05/15
1230 bool bdynamic_txpower; //bDynamicTxPower
1231 bool bDynamicTxHighPower; // Tx high power state
1232 bool bDynamicTxLowPower; // Tx low power state
1233 bool bLastDTPFlag_High;
1234 bool bLastDTPFlag_Low;
1235
1236 bool bstore_last_dtpflag;
1237 bool bstart_txctrl_bydtp; //Define to discriminate on High power State or on sitesuvey to change Tx gain index
1238 //Add by amy for Rate Adaptive
1239 rate_adaptive rate_adaptive;
1240 //Add by amy for TX power tracking
1241 //2008/05/15 Mars OPEN/CLOSE TX POWER TRACKING
1242 txbbgain_struct txbbgain_table[TxBBGainTableLength];
1243 u8 txpower_count;//For 6 sec do tracking again
1244 bool btxpower_trackingInit;
1245 u8 OFDM_index;
1246 u8 CCK_index;
1247 u8 Record_CCK_20Mindex;
1248 u8 Record_CCK_40Mindex;
1249 //2007/09/10 Mars Add CCK TX Power Tracking
1250 ccktxbbgain_struct cck_txbbgain_table[CCKTxBBGainTableLength];
1251 ccktxbbgain_struct cck_txbbgain_ch14_table[CCKTxBBGainTableLength];
1252 u8 rfa_txpowertrackingindex;
1253 u8 rfa_txpowertrackingindex_real;
1254 u8 rfa_txpowertracking_default;
1255 u8 rfc_txpowertrackingindex;
1256 u8 rfc_txpowertrackingindex_real;
1257 u8 rfc_txpowertracking_default;
1258 bool btxpower_tracking;
1259 bool bcck_in_ch14;
1260
1261 //For Backup Initial Gain
1262 init_gain initgain_backup;
1263 u8 DefaultInitialGain[4];
1264 // For EDCA Turbo mode, Added by amy 080515.
1265 bool bis_any_nonbepkts;
1266 bool bcurrent_turbo_EDCA;
1267
1268 bool bis_cur_rdlstate;
1269 struct timer_list fsync_timer;
1270 bool bfsync_processing; // 500ms Fsync timer is active or not
1271 u32 rate_record;
1272 u32 rateCountDiffRecord;
1273 u32 ContiuneDiffCount;
1274 bool bswitch_fsync;
1275
1276 u8 framesync;
1277 u32 framesyncC34;
1278 u8 framesyncMonitor;
1279 //Added by amy 080516 for RX related
1280 u16 nrxAMPDU_size;
1281 u8 nrxAMPDU_aggr_num;
1282
1283 /*Last RxDesc TSF value*/
1284 u32 last_rxdesc_tsf_high;
1285 u32 last_rxdesc_tsf_low;
1286
1287 //by amy for gpio
1288 bool bHwRadioOff;
1289 //by amy for ps
1290 bool RFChangeInProgress; // RF Chnage in progress, by Bruce, 2007-10-30
1291 bool SetRFPowerStateInProgress;
1292 RT_OP_MODE OpMode;
1293 //by amy for reset_count
1294 u32 reset_count;
1295 bool bpbc_pressed;
1296 //by amy for debug
1297 u32 txpower_checkcnt;
1298 u32 txpower_tracking_callback_cnt;
1299 u8 thermal_read_val[40];
1300 u8 thermal_readback_index;
1301 u32 ccktxpower_adjustcnt_not_ch14;
1302 u32 ccktxpower_adjustcnt_ch14;
1303 u8 tx_fwinfo_force_subcarriermode;
1304 u8 tx_fwinfo_force_subcarrierval;
1305
1306 //by amy for silent reset
1307 RESET_TYPE ResetProgress;
1308 bool bForcedSilentReset;
1309 bool bDisableNormalResetCheck;
1310 u16 TxCounter;
1311 u16 RxCounter;
1312 int IrpPendingCount;
1313 bool bResetInProgress;
1314 bool force_reset;
1315 u8 InitialGainOperateType;
1316
1317 //define work item by amy 080526
1318 struct delayed_work update_beacon_wq;
1319 struct delayed_work watch_dog_wq;
1320 struct delayed_work txpower_tracking_wq;
1321 struct delayed_work rfpath_check_wq;
1322 struct delayed_work gpio_change_rf_wq;
1323 struct delayed_work initialgain_operate_wq;
1324 struct workqueue_struct *priv_wq;
1325 }r8192_priv;
1326
1327 // for rtl8187
1328 // now mirging to rtl8187B
1329 /*
1330 typedef enum{
1331 LOW_PRIORITY = 0x02,
1332 NORM_PRIORITY
1333 } priority_t;
1334 */
1335 //for rtl8187B
1336 typedef enum{
1337 NIC_8192E = 1,
1338 } nic_t;
1339
1340
1341 bool init_firmware(struct net_device *dev);
1342 short rtl8192_tx(struct net_device *dev, struct sk_buff* skb);
1343 u32 read_cam(struct net_device *dev, u8 addr);
1344 void write_cam(struct net_device *dev, u8 addr, u32 data);
1345 u8 read_nic_byte(struct net_device *dev, int x);
1346 u8 read_nic_byte_E(struct net_device *dev, int x);
1347 u32 read_nic_dword(struct net_device *dev, int x);
1348 u16 read_nic_word(struct net_device *dev, int x) ;
1349 void write_nic_byte(struct net_device *dev, int x,u8 y);
1350 void write_nic_byte_E(struct net_device *dev, int x,u8 y);
1351 void write_nic_word(struct net_device *dev, int x,u16 y);
1352 void write_nic_dword(struct net_device *dev, int x,u32 y);
1353 void force_pci_posting(struct net_device *dev);
1354
1355 void rtl8192_halt_adapter(struct net_device *dev, bool reset);
1356 void rtl8192_rx_enable(struct net_device *);
1357 void rtl8192_tx_enable(struct net_device *);
1358
1359 void rtl8192_disassociate(struct net_device *dev);
1360 //void fix_rx_fifo(struct net_device *dev);
1361 void rtl8185_set_rf_pins_enable(struct net_device *dev,u32 a);
1362
1363 void rtl8192_set_anaparam(struct net_device *dev,u32 a);
1364 void rtl8185_set_anaparam2(struct net_device *dev,u32 a);
1365 void rtl8192_update_msr(struct net_device *dev);
1366 int rtl8192_down(struct net_device *dev);
1367 int rtl8192_up(struct net_device *dev);
1368 void rtl8192_commit(struct net_device *dev);
1369 void rtl8192_set_chan(struct net_device *dev,short ch);
1370 void write_phy(struct net_device *dev, u8 adr, u8 data);
1371 void write_phy_cck(struct net_device *dev, u8 adr, u32 data);
1372 void write_phy_ofdm(struct net_device *dev, u8 adr, u32 data);
1373 void rtl8185_tx_antenna(struct net_device *dev, u8 ant);
1374 void rtl8187_set_rxconf(struct net_device *dev);
1375 //short check_nic_enough_desc(struct net_device *dev, priority_t priority);
1376 void CamResetAllEntry(struct net_device* dev);
1377 void EnableHWSecurityConfig8192(struct net_device *dev);
1378 void setKey(struct net_device *dev, u8 EntryNo, u8 KeyIndex, u16 KeyType, const u8 *MacAddr, u8 DefaultKey, u32 *KeyContent );
1379 void CamPrintDbgReg(struct net_device* dev);
1380 extern void dm_cck_txpower_adjust(struct net_device *dev,bool binch14);
1381 extern void firmware_init_param(struct net_device *dev);
1382 extern RT_STATUS cmpk_message_handle_tx(struct net_device *dev, u8* codevirtualaddress, u32 packettype, u32 buffer_len);
1383 void rtl8192_hw_wakeup_wq (struct work_struct *work);
1384
1385 short rtl8192_is_tx_queue_empty(struct net_device *dev);
1386 #ifdef ENABLE_IPS
1387 void IPSEnter(struct net_device *dev);
1388 void IPSLeave(struct net_device *dev);
1389 void InactivePsWorkItemCallback(struct net_device *dev);
1390 void IPSLeave_wq(void *data);
1391 void ieee80211_ips_leave_wq(struct net_device *dev);
1392 void ieee80211_ips_leave(struct net_device *dev);
1393 #endif
1394 #ifdef ENABLE_LPS
1395 void LeisurePSEnter(struct net_device *dev);
1396 void LeisurePSLeave(struct net_device *dev);
1397 #endif
1398
1399 bool NicIFEnableNIC(struct net_device* dev);
1400 bool NicIFDisableNIC(struct net_device* dev);
1401
1402 void rtl8192_irq_disable(struct net_device *dev);
1403 void PHY_SetRtl8192eRfOff(struct net_device* dev);
1404 #endif
Tomato firmware and modifications.