1 /***********************license start***************
2 * Author: Cavium Networks
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
7 * Copyright (c) 2003-2009 Cavium Networks
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
29 * Typedefs and defines for working with Octeon physical addresses.
32 #ifndef __CVMX_ADDRESS_H__
33 #define __CVMX_ADDRESS_H__
37 CVMX_MIPS_XKSEG_SPACE_KSEG0
= 0LL,
38 CVMX_MIPS_XKSEG_SPACE_KSEG1
= 1LL,
39 CVMX_MIPS_XKSEG_SPACE_SSEG
= 2LL,
40 CVMX_MIPS_XKSEG_SPACE_KSEG3
= 3LL
41 } cvmx_mips_xkseg_space_t
;
43 /* decodes <14:13> of a kseg3 window address */
45 CVMX_ADD_WIN_SCR
= 0L,
46 /* see cvmx_add_win_dma_dec_t for further decode */
47 CVMX_ADD_WIN_DMA
= 1L,
48 CVMX_ADD_WIN_UNUSED
= 2L,
49 CVMX_ADD_WIN_UNUSED2
= 3L
52 /* decode within DMA space */
55 * Add store data to the write buffer entry, allocating it if
58 CVMX_ADD_WIN_DMA_ADD
= 0L,
59 /* send out the write buffer entry to DRAM */
60 CVMX_ADD_WIN_DMA_SENDMEM
= 1L,
61 /* store data must be normal DRAM memory space address in this case */
62 /* send out the write buffer entry as an IOBDMA command */
63 CVMX_ADD_WIN_DMA_SENDDMA
= 2L,
64 /* see CVMX_ADD_WIN_DMA_SEND_DEC for data contents */
65 /* send out the write buffer entry as an IO write */
66 CVMX_ADD_WIN_DMA_SENDIO
= 3L,
67 /* store data must be normal IO space address in this case */
68 /* send out a single-tick command on the NCB bus */
69 CVMX_ADD_WIN_DMA_SENDSINGLE
= 4L,
70 /* no write buffer data needed/used */
71 } cvmx_add_win_dma_dec_t
;
74 * Physical Address Decode
76 * Octeon-I HW never interprets this X (<39:36> reserved
77 * for future expansion), software should set to 0.
79 * - 0x0 XXX0 0000 0000 to DRAM Cached
80 * - 0x0 XXX0 0FFF FFFF
82 * - 0x0 XXX0 1000 0000 to Boot Bus Uncached (Converted to 0x1 00X0 1000 0000
83 * - 0x0 XXX0 1FFF FFFF + EJTAG to 0x1 00X0 1FFF FFFF)
85 * - 0x0 XXX0 2000 0000 to DRAM Cached
86 * - 0x0 XXXF FFFF FFFF
88 * - 0x1 00X0 0000 0000 to Boot Bus Uncached
89 * - 0x1 00XF FFFF FFFF
91 * - 0x1 01X0 0000 0000 to Other NCB Uncached
92 * - 0x1 FFXF FFFF FFFF devices
94 * Decode of all Octeon addresses
99 /* mapped or unmapped virtual address */
105 /* mapped USEG virtual addresses (typically) */
111 /* mapped or unmapped virtual address */
119 * physical address accessed through xkphys unmapped virtual
123 uint64_t R
:2; /* CVMX_MIPS_SPACE_XKPHYS in this case */
124 uint64_t cca
:3; /* ignored by octeon */
126 uint64_t pa
:49; /* physical address */
129 /* physical address */
132 /* if set, the address is uncached and resides on MCB bus */
135 * the hardware ignores this field when is_io==0, else
139 /* the hardware ignores <39:36> in Octeon I */
144 /* physical mem address */
146 /* techically, <47:40> are dont-cares */
148 /* the hardware ignores <39:36> in Octeon I */
153 /* physical IO address */
155 uint64_t mem_region
:2;
160 * The hardware ignores this field when is_io==0, else
164 /* the hardware ignores <39:36> in Octeon I */
170 * Scratchpad virtual address - accessed through a window at
175 /* CVMX_ADD_WIN_SCR (0) in this case */
176 cvmx_add_win_dec_t csrdec
:2;
180 /* there should only be stores to IOBDMA space, no loads */
182 * IOBDMA virtual address - accessed through a window at the
187 uint64_t csrdec
:2; /* CVMX_ADD_WIN_DMA (1) in this case */
194 uint64_t didspace
:24;
200 /* These macros for used by 32 bit applications */
202 #define CVMX_MIPS32_SPACE_KSEG0 1l
203 #define CVMX_ADD_SEG32(segment, add) \
204 (((int32_t)segment << 31) | (int32_t)(add))
207 * Currently all IOs are performed using XKPHYS addressing. Linux uses
208 * the CvmMemCtl register to enable XKPHYS addressing to IO space from
209 * user mode. Future OSes may need to change the upper bits of IO
210 * addresses. The following define controls the upper two bits for all
211 * IO addresses generated by the simple executive library.
213 #define CVMX_IO_SEG CVMX_MIPS_SPACE_XKPHYS
215 /* These macros simplify the process of creating common IO addresses */
216 #define CVMX_ADD_SEG(segment, add) ((((uint64_t)segment) << 62) | (add))
217 #ifndef CVMX_ADD_IO_SEG
218 #define CVMX_ADD_IO_SEG(add) CVMX_ADD_SEG(CVMX_IO_SEG, (add))
220 #define CVMX_ADDR_DIDSPACE(did) (((CVMX_IO_SEG) << 22) | ((1ULL) << 8) | (did))
221 #define CVMX_ADDR_DID(did) (CVMX_ADDR_DIDSPACE(did) << 40)
222 #define CVMX_FULL_DID(did, subdid) (((did) << 3) | (subdid))
224 /* from include/ncb_rsl_id.v */
225 #define CVMX_OCT_DID_MIS 0ULL /* misc stuff */
226 #define CVMX_OCT_DID_GMX0 1ULL
227 #define CVMX_OCT_DID_GMX1 2ULL
228 #define CVMX_OCT_DID_PCI 3ULL
229 #define CVMX_OCT_DID_KEY 4ULL
230 #define CVMX_OCT_DID_FPA 5ULL
231 #define CVMX_OCT_DID_DFA 6ULL
232 #define CVMX_OCT_DID_ZIP 7ULL
233 #define CVMX_OCT_DID_RNG 8ULL
234 #define CVMX_OCT_DID_IPD 9ULL
235 #define CVMX_OCT_DID_PKT 10ULL
236 #define CVMX_OCT_DID_TIM 11ULL
237 #define CVMX_OCT_DID_TAG 12ULL
238 /* the rest are not on the IO bus */
239 #define CVMX_OCT_DID_L2C 16ULL
240 #define CVMX_OCT_DID_LMC 17ULL
241 #define CVMX_OCT_DID_SPX0 18ULL
242 #define CVMX_OCT_DID_SPX1 19ULL
243 #define CVMX_OCT_DID_PIP 20ULL
244 #define CVMX_OCT_DID_ASX0 22ULL
245 #define CVMX_OCT_DID_ASX1 23ULL
246 #define CVMX_OCT_DID_IOB 30ULL
248 #define CVMX_OCT_DID_PKT_SEND CVMX_FULL_DID(CVMX_OCT_DID_PKT, 2ULL)
249 #define CVMX_OCT_DID_TAG_SWTAG CVMX_FULL_DID(CVMX_OCT_DID_TAG, 0ULL)
250 #define CVMX_OCT_DID_TAG_TAG1 CVMX_FULL_DID(CVMX_OCT_DID_TAG, 1ULL)
251 #define CVMX_OCT_DID_TAG_TAG2 CVMX_FULL_DID(CVMX_OCT_DID_TAG, 2ULL)
252 #define CVMX_OCT_DID_TAG_TAG3 CVMX_FULL_DID(CVMX_OCT_DID_TAG, 3ULL)
253 #define CVMX_OCT_DID_TAG_NULL_RD CVMX_FULL_DID(CVMX_OCT_DID_TAG, 4ULL)
254 #define CVMX_OCT_DID_TAG_CSR CVMX_FULL_DID(CVMX_OCT_DID_TAG, 7ULL)
255 #define CVMX_OCT_DID_FAU_FAI CVMX_FULL_DID(CVMX_OCT_DID_IOB, 0ULL)
256 #define CVMX_OCT_DID_TIM_CSR CVMX_FULL_DID(CVMX_OCT_DID_TIM, 0ULL)
257 #define CVMX_OCT_DID_KEY_RW CVMX_FULL_DID(CVMX_OCT_DID_KEY, 0ULL)
258 #define CVMX_OCT_DID_PCI_6 CVMX_FULL_DID(CVMX_OCT_DID_PCI, 6ULL)
259 #define CVMX_OCT_DID_MIS_BOO CVMX_FULL_DID(CVMX_OCT_DID_MIS, 0ULL)
260 #define CVMX_OCT_DID_PCI_RML CVMX_FULL_DID(CVMX_OCT_DID_PCI, 0ULL)
261 #define CVMX_OCT_DID_IPD_CSR CVMX_FULL_DID(CVMX_OCT_DID_IPD, 7ULL)
262 #define CVMX_OCT_DID_DFA_CSR CVMX_FULL_DID(CVMX_OCT_DID_DFA, 7ULL)
263 #define CVMX_OCT_DID_MIS_CSR CVMX_FULL_DID(CVMX_OCT_DID_MIS, 7ULL)
264 #define CVMX_OCT_DID_ZIP_CSR CVMX_FULL_DID(CVMX_OCT_DID_ZIP, 0ULL)
266 #endif /* __CVMX_ADDRESS_H__ */