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GUI: Fix Tomato RAF theme for all builds. Compilation typo.
[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / drivers / staging / comedi / drivers / ni_pcimio.c
blob845ec55f60ffab31b4d0fe898e2f18eacc8d5ce8
1 /*
2 comedi/drivers/ni_pcimio.c
3 Hardware driver for NI PCI-MIO E series cards
4
5 COMEDI - Linux Control and Measurement Device Interface
6 Copyright (C) 1997-8 David A. Schleef <ds@schleef.org>
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22 /*
23 Driver: ni_pcimio
24 Description: National Instruments PCI-MIO-E series and M series (all boards)
25 Author: ds, John Hallen, Frank Mori Hess, Rolf Mueller, Herbert Peremans,
26 Herman Bruyninckx, Terry Barnaby
27 Status: works
28 Devices: [National Instruments] PCI-MIO-16XE-50 (ni_pcimio),
29 PCI-MIO-16XE-10, PXI-6030E, PCI-MIO-16E-1, PCI-MIO-16E-4, PCI-6014, PCI-6040E,
30 PXI-6040E, PCI-6030E, PCI-6031E, PCI-6032E, PCI-6033E, PCI-6071E, PCI-6023E,
31 PCI-6024E, PCI-6025E, PXI-6025E, PCI-6034E, PCI-6035E, PCI-6052E,
32 PCI-6110, PCI-6111, PCI-6220, PCI-6221, PCI-6224, PXI-6224, PCI-6225, PXI-6225,
33 PCI-6229, PCI-6250, PCI-6251, PCIe-6251, PCI-6254, PCI-6259, PCIe-6259,
34 PCI-6280, PCI-6281, PXI-6281, PCI-6284, PCI-6289,
35 PCI-6711, PXI-6711, PCI-6713, PXI-6713,
36 PXI-6071E, PCI-6070E, PXI-6070E,
37 PXI-6052E, PCI-6036E, PCI-6731, PCI-6733, PXI-6733,
38 PCI-6143, PXI-6143
39 Updated: Wed, 03 Dec 2008 10:51:47 +0000
40
41 These boards are almost identical to the AT-MIO E series, except that
42 they use the PCI bus instead of ISA (i.e., AT). See the notes for
43 the ni_atmio.o driver for additional information about these boards.
44
45 Autocalibration is supported on many of the devices, using the
46 comedi_calibrate (or comedi_soft_calibrate for m-series) utility.
47 M-Series boards do analog input and analog output calibration entirely
48 in software. The software calibration corrects
49 the analog input for offset, gain and
50 nonlinearity. The analog outputs are corrected for offset and gain.
51 See the comedilib documentation on comedi_get_softcal_converter() for
52 more information.
53
54 By default, the driver uses DMA to transfer analog input data to
55 memory. When DMA is enabled, not all triggering features are
56 supported.
57
58 Digital I/O may not work on 673x.
59
60 Note that the PCI-6143 is a simultaineous sampling device with 8 convertors.
61 With this board all of the convertors perform one simultaineous sample during
62 a scan interval. The period for a scan is used for the convert time in a
63 Comedi cmd. The convert trigger source is normally set to TRIG_NOW by default.
64
65 The RTSI trigger bus is supported on these cards on
66 subdevice 10. See the comedilib documentation for details.
67
68 Information (number of channels, bits, etc.) for some devices may be
69 incorrect. Please check this and submit a bug if there are problems
70 for your device.
71
72 SCXI is probably broken for m-series boards.
73
74 Bugs:
75 - When DMA is enabled, COMEDI_EV_CONVERT does
76 not work correctly.
77
78 */
79 /*
80 The PCI-MIO E series driver was originally written by
81 Tomasz Motylewski <...>, and ported to comedi by ds.
82
83 References:
84
85 341079b.pdf PCI E Series Register-Level Programmer Manual
86 340934b.pdf DAQ-STC reference manual
87
88 322080b.pdf 6711/6713/6715 User Manual
89
90 320945c.pdf PCI E Series User Manual
91 322138a.pdf PCI-6052E and DAQPad-6052E User Manual
92
93 ISSUES:
94
95 need to deal with external reference for DAC, and other DAC
96 properties in board properties
97
98 deal with at-mio-16de-10 revision D to N changes, etc.
99
100 need to add other CALDAC type
101
102 need to slow down DAC loading. I don't trust NI's claim that
103 two writes to the PCI bus slows IO enough. I would prefer to
104 use udelay(). Timing specs: (clock)
105 AD8522 30ns
106 DAC8043 120ns
107 DAC8800 60ns
108 MB88341 ?
109
110 */
111
112 #include "../comedidev.h"
113
114 #include <asm/byteorder.h>
115 #include <linux/delay.h>
116
117 #include "ni_stc.h"
118 #include "mite.h"
119
120 /* #define PCI_DEBUG */
121
122 #define PCIDMA
123
124 #define PCIMIO 1
125 #undef ATMIO
126
127 #define MAX_N_CALDACS (16+16+2)
128
129 #define DRV_NAME "ni_pcimio"
130
131 /* The following two tables must be in the same order */
132 static DEFINE_PCI_DEVICE_TABLE(ni_pci_table) = {
133 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x0162)},
134 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1170)},
135 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1180)},
136 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1190)},
137 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x11b0)},
138 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x11c0)},
139 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x11d0)},
140 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1270)},
141 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1330)},
142 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1340)},
143 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1350)},
144 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x14e0)},
145 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x14f0)},
146 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1580)},
147 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x15b0)},
148 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1880)},
149 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1870)},
150 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x18b0)},
151 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x18c0)},
152 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2410)},
153 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2420)},
154 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2430)},
155 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2890)},
156 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x28c0)},
157 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2a60)},
158 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2a70)},
159 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2a80)},
160 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2ab0)},
161 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2b80)},
162 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2b90)},
163 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2c80)},
164 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2ca0)},
165 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70aa)},
166 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70ab)},
167 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70ac)},
168 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70af)},
169 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70b0)},
170 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70b4)},
171 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70b6)},
172 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70b7)},
173 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70b8)},
174 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70bc)},
175 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70bd)},
176 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70bf)},
177 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70c0)},
178 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70f2)},
179 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x710d)},
180 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x716c)},
181 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x716d)},
182 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x717f)},
183 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x71bc)},
184 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x717d)},
185 {0}
186 };
187
188 MODULE_DEVICE_TABLE(pci, ni_pci_table);
189
190 /* These are not all the possible ao ranges for 628x boards.
191 They can do OFFSET +- REFERENCE where OFFSET can be
192 0V, 5V, APFI<0,1>, or AO<0...3> and RANGE can
193 be 10V, 5V, 2V, 1V, APFI<0,1>, AO<0...3>. That's
194 63 different possibilities. An AO channel
195 can not act as it's own OFFSET or REFERENCE.
196 */
197 static const struct comedi_lrange range_ni_M_628x_ao = { 8, {
198 RANGE(-10, 10),
199 RANGE(-5, 5),
200 RANGE(-2, 2),
201 RANGE(-1, 1),
202 RANGE(-5, 15),
203 RANGE(0, 10),
204 RANGE(3, 7),
205 RANGE(4, 6),
206 RANGE_ext(-1, 1)
207 }
208 };
209
210 static const struct comedi_lrange range_ni_M_625x_ao = { 3, {
211 RANGE(-10, 10),
212 RANGE(-5, 5),
213 RANGE_ext(-1, 1)
214 }
215 };
216
217 static const struct comedi_lrange range_ni_M_622x_ao = { 1, {
218 RANGE(-10, 10),
219 }
220 };
221
222 static const struct ni_board_struct ni_boards[] = {
223 {
224 .device_id = 0x0162, /* NI also says 0x1620. typo? */
225 .name = "pci-mio-16xe-50",
226 .n_adchan = 16,
227 .adbits = 16,
228 .ai_fifo_depth = 2048,
229 .alwaysdither = 1,
230 .gainlkup = ai_gain_8,
231 .ai_speed = 50000,
232 .n_aochan = 2,
233 .aobits = 12,
234 .ao_fifo_depth = 0,
235 .ao_range_table = &range_bipolar10,
236 .ao_unipolar = 0,
237 .ao_speed = 50000,
238 .num_p0_dio_channels = 8,
239 .caldac = {dac8800, dac8043},
240 .has_8255 = 0,
241 },
242 {
243 .device_id = 0x1170,
244 .name = "pci-mio-16xe-10", /* aka pci-6030E */
245 .n_adchan = 16,
246 .adbits = 16,
247 .ai_fifo_depth = 512,
248 .alwaysdither = 1,
249 .gainlkup = ai_gain_14,
250 .ai_speed = 10000,
251 .n_aochan = 2,
252 .aobits = 16,
253 .ao_fifo_depth = 2048,
254 .ao_range_table = &range_ni_E_ao_ext,
255 .ao_unipolar = 1,
256 .ao_speed = 10000,
257 .num_p0_dio_channels = 8,
258 .caldac = {dac8800, dac8043, ad8522},
259 .has_8255 = 0,
260 },
261 {
262 .device_id = 0x28c0,
263 .name = "pci-6014",
264 .n_adchan = 16,
265 .adbits = 16,
266 .ai_fifo_depth = 512,
267 .alwaysdither = 1,
268 .gainlkup = ai_gain_4,
269 .ai_speed = 5000,
270 .n_aochan = 2,
271 .aobits = 16,
272 .ao_fifo_depth = 0,
273 .ao_range_table = &range_bipolar10,
274 .ao_unipolar = 0,
275 .ao_speed = 100000,
276 .num_p0_dio_channels = 8,
277 .caldac = {ad8804_debug},
278 .has_8255 = 0,
279 },
280 {
281 .device_id = 0x11d0,
282 .name = "pxi-6030e",
283 .n_adchan = 16,
284 .adbits = 16,
285 .ai_fifo_depth = 512,
286 .alwaysdither = 1,
287 .gainlkup = ai_gain_14,
288 .ai_speed = 10000,
289 .n_aochan = 2,
290 .aobits = 16,
291 .ao_fifo_depth = 2048,
292 .ao_range_table = &range_ni_E_ao_ext,
293 .ao_unipolar = 1,
294 .ao_speed = 10000,
295 .num_p0_dio_channels = 8,
296 .caldac = {dac8800, dac8043, ad8522},
297 .has_8255 = 0,
298 },
299 {
300 .device_id = 0x1180,
301 .name = "pci-mio-16e-1", /* aka pci-6070e */
302 .n_adchan = 16,
303 .adbits = 12,
304 .ai_fifo_depth = 512,
305 .alwaysdither = 0,
306 .gainlkup = ai_gain_16,
307 .ai_speed = 800,
308 .n_aochan = 2,
309 .aobits = 12,
310 .ao_fifo_depth = 2048,
311 .ao_range_table = &range_ni_E_ao_ext,
312 .ao_unipolar = 1,
313 .ao_speed = 1000,
314 .num_p0_dio_channels = 8,
315 .caldac = {mb88341},
316 .has_8255 = 0,
317 },
318 {
319 .device_id = 0x1190,
320 .name = "pci-mio-16e-4", /* aka pci-6040e */
321 .n_adchan = 16,
322 .adbits = 12,
323 .ai_fifo_depth = 512,
324 .alwaysdither = 0,
325 .gainlkup = ai_gain_16,
326 /* .Note = there have been reported problems with full speed
327 * on this board */
328 .ai_speed = 2000,
329 .n_aochan = 2,
330 .aobits = 12,
331 .ao_fifo_depth = 512,
332 .ao_range_table = &range_ni_E_ao_ext,
333 .ao_unipolar = 1,
334 .ao_speed = 1000,
335 .num_p0_dio_channels = 8,
336 .caldac = {ad8804_debug}, /* doc says mb88341 */
337 .has_8255 = 0,
338 },
339 {
340 .device_id = 0x11c0,
341 .name = "pxi-6040e",
342 .n_adchan = 16,
343 .adbits = 12,
344 .ai_fifo_depth = 512,
345 .alwaysdither = 0,
346 .gainlkup = ai_gain_16,
347 .ai_speed = 2000,
348 .n_aochan = 2,
349 .aobits = 12,
350 .ao_fifo_depth = 512,
351 .ao_range_table = &range_ni_E_ao_ext,
352 .ao_unipolar = 1,
353 .ao_speed = 1000,
354 .num_p0_dio_channels = 8,
355 .caldac = {mb88341},
356 .has_8255 = 0,
357 },
358
359 {
360 .device_id = 0x1330,
361 .name = "pci-6031e",
362 .n_adchan = 64,
363 .adbits = 16,
364 .ai_fifo_depth = 512,
365 .alwaysdither = 1,
366 .gainlkup = ai_gain_14,
367 .ai_speed = 10000,
368 .n_aochan = 2,
369 .aobits = 16,
370 .ao_fifo_depth = 2048,
371 .ao_range_table = &range_ni_E_ao_ext,
372 .ao_unipolar = 1,
373 .ao_speed = 10000,
374 .num_p0_dio_channels = 8,
375 .caldac = {dac8800, dac8043, ad8522},
376 .has_8255 = 0,
377 },
378 {
379 .device_id = 0x1270,
380 .name = "pci-6032e",
381 .n_adchan = 16,
382 .adbits = 16,
383 .ai_fifo_depth = 512,
384 .alwaysdither = 1,
385 .gainlkup = ai_gain_14,
386 .ai_speed = 10000,
387 .n_aochan = 0,
388 .aobits = 0,
389 .ao_fifo_depth = 0,
390 .ao_unipolar = 0,
391 .num_p0_dio_channels = 8,
392 .caldac = {dac8800, dac8043, ad8522},
393 .has_8255 = 0,
394 },
395 {
396 .device_id = 0x1340,
397 .name = "pci-6033e",
398 .n_adchan = 64,
399 .adbits = 16,
400 .ai_fifo_depth = 512,
401 .alwaysdither = 1,
402 .gainlkup = ai_gain_14,
403 .ai_speed = 10000,
404 .n_aochan = 0,
405 .aobits = 0,
406 .ao_fifo_depth = 0,
407 .ao_unipolar = 0,
408 .num_p0_dio_channels = 8,
409 .caldac = {dac8800, dac8043, ad8522},
410 .has_8255 = 0,
411 },
412 {
413 .device_id = 0x1350,
414 .name = "pci-6071e",
415 .n_adchan = 64,
416 .adbits = 12,
417 .ai_fifo_depth = 512,
418 .alwaysdither = 1,
419 .gainlkup = ai_gain_16,
420 .ai_speed = 800,
421 .n_aochan = 2,
422 .aobits = 12,
423 .ao_fifo_depth = 2048,
424 .ao_range_table = &range_ni_E_ao_ext,
425 .ao_unipolar = 1,
426 .ao_speed = 1000,
427 .num_p0_dio_channels = 8,
428 .caldac = {ad8804_debug},
429 .has_8255 = 0,
430 },
431 {
432 .device_id = 0x2a60,
433 .name = "pci-6023e",
434 .n_adchan = 16,
435 .adbits = 12,
436 .ai_fifo_depth = 512,
437 .alwaysdither = 0,
438 .gainlkup = ai_gain_4,
439 .ai_speed = 5000,
440 .n_aochan = 0,
441 .aobits = 0,
442 .ao_unipolar = 0,
443 .num_p0_dio_channels = 8,
444 .caldac = {ad8804_debug}, /* manual is wrong */
445 .has_8255 = 0,
446 },
447 {
448 .device_id = 0x2a70,
449 .name = "pci-6024e",
450 .n_adchan = 16,
451 .adbits = 12,
452 .ai_fifo_depth = 512,
453 .alwaysdither = 0,
454 .gainlkup = ai_gain_4,
455 .ai_speed = 5000,
456 .n_aochan = 2,
457 .aobits = 12,
458 .ao_fifo_depth = 0,
459 .ao_range_table = &range_bipolar10,
460 .ao_unipolar = 0,
461 .ao_speed = 100000,
462 .num_p0_dio_channels = 8,
463 .caldac = {ad8804_debug}, /* manual is wrong */
464 .has_8255 = 0,
465 },
466 {
467 .device_id = 0x2a80,
468 .name = "pci-6025e",
469 .n_adchan = 16,
470 .adbits = 12,
471 .ai_fifo_depth = 512,
472 .alwaysdither = 0,
473 .gainlkup = ai_gain_4,
474 .ai_speed = 5000,
475 .n_aochan = 2,
476 .aobits = 12,
477 .ao_fifo_depth = 0,
478 .ao_range_table = &range_bipolar10,
479 .ao_unipolar = 0,
480 .ao_speed = 100000,
481 .num_p0_dio_channels = 8,
482 .caldac = {ad8804_debug}, /* manual is wrong */
483 .has_8255 = 1,
484 },
485 {
486 .device_id = 0x2ab0,
487 .name = "pxi-6025e",
488 .n_adchan = 16,
489 .adbits = 12,
490 .ai_fifo_depth = 512,
491 .alwaysdither = 0,
492 .gainlkup = ai_gain_4,
493 .ai_speed = 5000,
494 .n_aochan = 2,
495 .aobits = 12,
496 .ao_fifo_depth = 0,
497 .ao_range_table = &range_ni_E_ao_ext,
498 .ao_unipolar = 1,
499 .ao_speed = 100000,
500 .num_p0_dio_channels = 8,
501 .caldac = {ad8804_debug}, /* manual is wrong */
502 .has_8255 = 1,
503 },
504
505 {
506 .device_id = 0x2ca0,
507 .name = "pci-6034e",
508 .n_adchan = 16,
509 .adbits = 16,
510 .ai_fifo_depth = 512,
511 .alwaysdither = 1,
512 .gainlkup = ai_gain_4,
513 .ai_speed = 5000,
514 .n_aochan = 0,
515 .aobits = 0,
516 .ao_fifo_depth = 0,
517 .ao_unipolar = 0,
518 .num_p0_dio_channels = 8,
519 .caldac = {ad8804_debug},
520 .has_8255 = 0,
521 },
522 {
523 .device_id = 0x2c80,
524 .name = "pci-6035e",
525 .n_adchan = 16,
526 .adbits = 16,
527 .ai_fifo_depth = 512,
528 .alwaysdither = 1,
529 .gainlkup = ai_gain_4,
530 .ai_speed = 5000,
531 .n_aochan = 2,
532 .aobits = 12,
533 .ao_fifo_depth = 0,
534 .ao_range_table = &range_bipolar10,
535 .ao_unipolar = 0,
536 .ao_speed = 100000,
537 .num_p0_dio_channels = 8,
538 .caldac = {ad8804_debug},
539 .has_8255 = 0,
540 },
541 {
542 .device_id = 0x18b0,
543 .name = "pci-6052e",
544 .n_adchan = 16,
545 .adbits = 16,
546 .ai_fifo_depth = 512,
547 .alwaysdither = 1,
548 .gainlkup = ai_gain_16,
549 .ai_speed = 3000,
550 .n_aochan = 2,
551 .aobits = 16,
552 .ao_unipolar = 1,
553 .ao_fifo_depth = 2048,
554 .ao_range_table = &range_ni_E_ao_ext,
555 .ao_speed = 3000,
556 .num_p0_dio_channels = 8,
557 .caldac = {ad8804_debug, ad8804_debug, ad8522}, /* manual is wrong */
558 },
559 {.device_id = 0x14e0,
560 .name = "pci-6110",
561 .n_adchan = 4,
562 .adbits = 12,
563 .ai_fifo_depth = 8192,
564 .alwaysdither = 0,
565 .gainlkup = ai_gain_611x,
566 .ai_speed = 200,
567 .n_aochan = 2,
568 .aobits = 16,
569 .reg_type = ni_reg_611x,
570 .ao_range_table = &range_bipolar10,
571 .ao_unipolar = 0,
572 .ao_fifo_depth = 2048,
573 .ao_speed = 250,
574 .num_p0_dio_channels = 8,
575 .caldac = {ad8804, ad8804},
576 },
577 {
578 .device_id = 0x14f0,
579 .name = "pci-6111",
580 .n_adchan = 2,
581 .adbits = 12,
582 .ai_fifo_depth = 8192,
583 .alwaysdither = 0,
584 .gainlkup = ai_gain_611x,
585 .ai_speed = 200,
586 .n_aochan = 2,
587 .aobits = 16,
588 .reg_type = ni_reg_611x,
589 .ao_range_table = &range_bipolar10,
590 .ao_unipolar = 0,
591 .ao_fifo_depth = 2048,
592 .ao_speed = 250,
593 .num_p0_dio_channels = 8,
594 .caldac = {ad8804, ad8804},
595 },
596 {
597 .device_id = 0x1880,
598 .name = "pci-6711",
599 .n_adchan = 0, /* no analog input */
600 .n_aochan = 4,
601 .aobits = 12,
602 .ao_unipolar = 0,
603 .ao_fifo_depth = 16384,
604 /* data sheet says 8192, but fifo really holds 16384 samples */
605 .ao_range_table = &range_bipolar10,
606 .ao_speed = 1000,
607 .num_p0_dio_channels = 8,
608 .reg_type = ni_reg_6711,
609 .caldac = {ad8804_debug},
610 },
611 {
612 .device_id = 0x2b90,
613 .name = "pxi-6711",
614 .n_adchan = 0, /* no analog input */
615 .n_aochan = 4,
616 .aobits = 12,
617 .ao_unipolar = 0,
618 .ao_fifo_depth = 16384,
619 .ao_range_table = &range_bipolar10,
620 .ao_speed = 1000,
621 .num_p0_dio_channels = 8,
622 .reg_type = ni_reg_6711,
623 .caldac = {ad8804_debug},
624 },
625 {
626 .device_id = 0x1870,
627 .name = "pci-6713",
628 .n_adchan = 0, /* no analog input */
629 .n_aochan = 8,
630 .aobits = 12,
631 .ao_unipolar = 0,
632 .ao_fifo_depth = 16384,
633 .ao_range_table = &range_bipolar10,
634 .ao_speed = 1000,
635 .num_p0_dio_channels = 8,
636 .reg_type = ni_reg_6713,
637 .caldac = {ad8804_debug, ad8804_debug},
638 },
639 {
640 .device_id = 0x2b80,
641 .name = "pxi-6713",
642 .n_adchan = 0, /* no analog input */
643 .n_aochan = 8,
644 .aobits = 12,
645 .ao_unipolar = 0,
646 .ao_fifo_depth = 16384,
647 .ao_range_table = &range_bipolar10,
648 .ao_speed = 1000,
649 .num_p0_dio_channels = 8,
650 .reg_type = ni_reg_6713,
651 .caldac = {ad8804_debug, ad8804_debug},
652 },
653 {
654 .device_id = 0x2430,
655 .name = "pci-6731",
656 .n_adchan = 0, /* no analog input */
657 .n_aochan = 4,
658 .aobits = 16,
659 .ao_unipolar = 0,
660 .ao_fifo_depth = 8192,
661 .ao_range_table = &range_bipolar10,
662 .ao_speed = 1000,
663 .num_p0_dio_channels = 8,
664 .reg_type = ni_reg_6711,
665 .caldac = {ad8804_debug},
666 },
667 {
668 .device_id = 0x2410,
669 .name = "pci-6733",
670 .n_adchan = 0, /* no analog input */
671 .n_aochan = 8,
672 .aobits = 16,
673 .ao_unipolar = 0,
674 .ao_fifo_depth = 16384,
675 .ao_range_table = &range_bipolar10,
676 .ao_speed = 1000,
677 .num_p0_dio_channels = 8,
678 .reg_type = ni_reg_6713,
679 .caldac = {ad8804_debug, ad8804_debug},
680 },
681 {
682 .device_id = 0x2420,
683 .name = "pxi-6733",
684 .n_adchan = 0, /* no analog input */
685 .n_aochan = 8,
686 .aobits = 16,
687 .ao_unipolar = 0,
688 .ao_fifo_depth = 16384,
689 .ao_range_table = &range_bipolar10,
690 .ao_speed = 1000,
691 .num_p0_dio_channels = 8,
692 .reg_type = ni_reg_6713,
693 .caldac = {ad8804_debug, ad8804_debug},
694 },
695 {
696 .device_id = 0x15b0,
697 .name = "pxi-6071e",
698 .n_adchan = 64,
699 .adbits = 12,
700 .ai_fifo_depth = 512,
701 .alwaysdither = 1,
702 .gainlkup = ai_gain_16,
703 .ai_speed = 800,
704 .n_aochan = 2,
705 .aobits = 12,
706 .ao_fifo_depth = 2048,
707 .ao_range_table = &range_ni_E_ao_ext,
708 .ao_unipolar = 1,
709 .ao_speed = 1000,
710 .num_p0_dio_channels = 8,
711 .caldac = {ad8804_debug},
712 .has_8255 = 0,
713 },
714 {
715 .device_id = 0x11b0,
716 .name = "pxi-6070e",
717 .n_adchan = 16,
718 .adbits = 12,
719 .ai_fifo_depth = 512,
720 .alwaysdither = 1,
721 .gainlkup = ai_gain_16,
722 .ai_speed = 800,
723 .n_aochan = 2,
724 .aobits = 12,
725 .ao_fifo_depth = 2048,
726 .ao_range_table = &range_ni_E_ao_ext,
727 .ao_unipolar = 1,
728 .ao_speed = 1000,
729 .num_p0_dio_channels = 8,
730 .caldac = {ad8804_debug},
731 .has_8255 = 0,
732 },
733 {
734 .device_id = 0x18c0,
735 .name = "pxi-6052e",
736 .n_adchan = 16,
737 .adbits = 16,
738 .ai_fifo_depth = 512,
739 .alwaysdither = 1,
740 .gainlkup = ai_gain_16,
741 .ai_speed = 3000,
742 .n_aochan = 2,
743 .aobits = 16,
744 .ao_unipolar = 1,
745 .ao_fifo_depth = 2048,
746 .ao_range_table = &range_ni_E_ao_ext,
747 .ao_speed = 3000,
748 .num_p0_dio_channels = 8,
749 .caldac = {mb88341, mb88341, ad8522},
750 },
751 {
752 .device_id = 0x1580,
753 .name = "pxi-6031e",
754 .n_adchan = 64,
755 .adbits = 16,
756 .ai_fifo_depth = 512,
757 .alwaysdither = 1,
758 .gainlkup = ai_gain_14,
759 .ai_speed = 10000,
760 .n_aochan = 2,
761 .aobits = 16,
762 .ao_fifo_depth = 2048,
763 .ao_range_table = &range_ni_E_ao_ext,
764 .ao_unipolar = 1,
765 .ao_speed = 10000,
766 .num_p0_dio_channels = 8,
767 .caldac = {dac8800, dac8043, ad8522},
768 },
769 {
770 .device_id = 0x2890,
771 .name = "pci-6036e",
772 .n_adchan = 16,
773 .adbits = 16,
774 .ai_fifo_depth = 512,
775 .alwaysdither = 1,
776 .gainlkup = ai_gain_4,
777 .ai_speed = 5000,
778 .n_aochan = 2,
779 .aobits = 16,
780 .ao_fifo_depth = 0,
781 .ao_range_table = &range_bipolar10,
782 .ao_unipolar = 0,
783 .ao_speed = 100000,
784 .num_p0_dio_channels = 8,
785 .caldac = {ad8804_debug},
786 .has_8255 = 0,
787 },
788 {
789 .device_id = 0x70b0,
790 .name = "pci-6220",
791 .n_adchan = 16,
792 .adbits = 16,
793 .ai_fifo_depth = 512,
794 .gainlkup = ai_gain_622x,
795 .ai_speed = 4000,
796 .n_aochan = 0,
797 .aobits = 0,
798 .ao_fifo_depth = 0,
799 .num_p0_dio_channels = 8,
800 .reg_type = ni_reg_622x,
801 .ao_unipolar = 0,
802 .caldac = {caldac_none},
803 .has_8255 = 0,
804 },
805 {
806 .device_id = 0x70af,
807 .name = "pci-6221",
808 .n_adchan = 16,
809 .adbits = 16,
810 .ai_fifo_depth = 4095,
811 .gainlkup = ai_gain_622x,
812 .ai_speed = 4000,
813 .n_aochan = 2,
814 .aobits = 16,
815 .ao_fifo_depth = 8191,
816 .ao_range_table = &range_ni_M_622x_ao,
817 .reg_type = ni_reg_622x,
818 .ao_unipolar = 0,
819 .ao_speed = 1200,
820 .num_p0_dio_channels = 8,
821 .caldac = {caldac_none},
822 .has_8255 = 0,
823 },
824 {
825 .device_id = 0x71bc,
826 .name = "pci-6221_37pin",
827 .n_adchan = 16,
828 .adbits = 16,
829 .ai_fifo_depth = 4095,
830 .gainlkup = ai_gain_622x,
831 .ai_speed = 4000,
832 .n_aochan = 2,
833 .aobits = 16,
834 .ao_fifo_depth = 8191,
835 .ao_range_table = &range_ni_M_622x_ao,
836 .reg_type = ni_reg_622x,
837 .ao_unipolar = 0,
838 .ao_speed = 1200,
839 .num_p0_dio_channels = 8,
840 .caldac = {caldac_none},
841 .has_8255 = 0,
842 },
843 {
844 .device_id = 0x70f2,
845 .name = "pci-6224",
846 .n_adchan = 32,
847 .adbits = 16,
848 .ai_fifo_depth = 4095,
849 .gainlkup = ai_gain_622x,
850 .ai_speed = 4000,
851 .n_aochan = 0,
852 .aobits = 0,
853 .ao_fifo_depth = 0,
854 .reg_type = ni_reg_622x,
855 .ao_unipolar = 0,
856 .num_p0_dio_channels = 32,
857 .caldac = {caldac_none},
858 .has_8255 = 0,
859 },
860 {
861 .device_id = 0x70f3,
862 .name = "pxi-6224",
863 .n_adchan = 32,
864 .adbits = 16,
865 .ai_fifo_depth = 4095,
866 .gainlkup = ai_gain_622x,
867 .ai_speed = 4000,
868 .n_aochan = 0,
869 .aobits = 0,
870 .ao_fifo_depth = 0,
871 .reg_type = ni_reg_622x,
872 .ao_unipolar = 0,
873 .num_p0_dio_channels = 32,
874 .caldac = {caldac_none},
875 .has_8255 = 0,
876 },
877 {
878 .device_id = 0x716c,
879 .name = "pci-6225",
880 .n_adchan = 80,
881 .adbits = 16,
882 .ai_fifo_depth = 4095,
883 .gainlkup = ai_gain_622x,
884 .ai_speed = 4000,
885 .n_aochan = 2,
886 .aobits = 16,
887 .ao_fifo_depth = 8191,
888 .ao_range_table = &range_ni_M_622x_ao,
889 .reg_type = ni_reg_622x,
890 .ao_unipolar = 0,
891 .ao_speed = 1200,
892 .num_p0_dio_channels = 32,
893 .caldac = {caldac_none},
894 .has_8255 = 0,
895 },
896 {
897 .device_id = 0x716d,
898 .name = "pxi-6225",
899 .n_adchan = 80,
900 .adbits = 16,
901 .ai_fifo_depth = 4095,
902 .gainlkup = ai_gain_622x,
903 .ai_speed = 4000,
904 .n_aochan = 2,
905 .aobits = 16,
906 .ao_fifo_depth = 8191,
907 .ao_range_table = &range_ni_M_622x_ao,
908 .reg_type = ni_reg_622x,
909 .ao_unipolar = 0,
910 .ao_speed = 1200,
911 .num_p0_dio_channels = 32,
912 .caldac = {caldac_none},
913 .has_8255 = 0,
914 },
915 {
916 .device_id = 0x70aa,
917 .name = "pci-6229",
918 .n_adchan = 32,
919 .adbits = 16,
920 .ai_fifo_depth = 4095,
921 .gainlkup = ai_gain_622x,
922 .ai_speed = 4000,
923 .n_aochan = 4,
924 .aobits = 16,
925 .ao_fifo_depth = 8191,
926 .ao_range_table = &range_ni_M_622x_ao,
927 .reg_type = ni_reg_622x,
928 .ao_unipolar = 0,
929 .ao_speed = 1200,
930 .num_p0_dio_channels = 32,
931 .caldac = {caldac_none},
932 .has_8255 = 0,
933 },
934 {
935 .device_id = 0x70b4,
936 .name = "pci-6250",
937 .n_adchan = 16,
938 .adbits = 16,
939 .ai_fifo_depth = 4095,
940 .gainlkup = ai_gain_628x,
941 .ai_speed = 800,
942 .n_aochan = 0,
943 .aobits = 0,
944 .ao_fifo_depth = 0,
945 .reg_type = ni_reg_625x,
946 .ao_unipolar = 0,
947 .num_p0_dio_channels = 8,
948 .caldac = {caldac_none},
949 .has_8255 = 0,
950 },
951 {
952 .device_id = 0x70b8,
953 .name = "pci-6251",
954 .n_adchan = 16,
955 .adbits = 16,
956 .ai_fifo_depth = 4095,
957 .gainlkup = ai_gain_628x,
958 .ai_speed = 800,
959 .n_aochan = 2,
960 .aobits = 16,
961 .ao_fifo_depth = 8191,
962 .ao_range_table = &range_ni_M_625x_ao,
963 .reg_type = ni_reg_625x,
964 .ao_unipolar = 0,
965 .ao_speed = 357,
966 .num_p0_dio_channels = 8,
967 .caldac = {caldac_none},
968 .has_8255 = 0,
969 },
970 {
971 .device_id = 0x717d,
972 .name = "pcie-6251",
973 .n_adchan = 16,
974 .adbits = 16,
975 .ai_fifo_depth = 4095,
976 .gainlkup = ai_gain_628x,
977 .ai_speed = 800,
978 .n_aochan = 2,
979 .aobits = 16,
980 .ao_fifo_depth = 8191,
981 .ao_range_table = &range_ni_M_625x_ao,
982 .reg_type = ni_reg_625x,
983 .ao_unipolar = 0,
984 .ao_speed = 357,
985 .num_p0_dio_channels = 8,
986 .caldac = {caldac_none},
987 .has_8255 = 0,
988 },
989 {
990 .device_id = 0x70b7,
991 .name = "pci-6254",
992 .n_adchan = 32,
993 .adbits = 16,
994 .ai_fifo_depth = 4095,
995 .gainlkup = ai_gain_628x,
996 .ai_speed = 800,
997 .n_aochan = 0,
998 .aobits = 0,
999 .ao_fifo_depth = 0,
1000 .reg_type = ni_reg_625x,
1001 .ao_unipolar = 0,
1002 .num_p0_dio_channels = 32,
1003 .caldac = {caldac_none},
1004 .has_8255 = 0,
1005 },
1006 {
1007 .device_id = 0x70ab,
1008 .name = "pci-6259",
1009 .n_adchan = 32,
1010 .adbits = 16,
1011 .ai_fifo_depth = 4095,
1012 .gainlkup = ai_gain_628x,
1013 .ai_speed = 800,
1014 .n_aochan = 4,
1015 .aobits = 16,
1016 .ao_fifo_depth = 8191,
1017 .ao_range_table = &range_ni_M_625x_ao,
1018 .reg_type = ni_reg_625x,
1019 .ao_unipolar = 0,
1020 .ao_speed = 357,
1021 .num_p0_dio_channels = 32,
1022 .caldac = {caldac_none},
1023 .has_8255 = 0,
1024 },
1025 {
1026 .device_id = 0x717f,
1027 .name = "pcie-6259",
1028 .n_adchan = 32,
1029 .adbits = 16,
1030 .ai_fifo_depth = 4095,
1031 .gainlkup = ai_gain_628x,
1032 .ai_speed = 800,
1033 .n_aochan = 4,
1034 .aobits = 16,
1035 .ao_fifo_depth = 8191,
1036 .ao_range_table = &range_ni_M_625x_ao,
1037 .reg_type = ni_reg_625x,
1038 .ao_unipolar = 0,
1039 .ao_speed = 357,
1040 .num_p0_dio_channels = 32,
1041 .caldac = {caldac_none},
1042 .has_8255 = 0,
1043 },
1044 {
1045 .device_id = 0x70b6,
1046 .name = "pci-6280",
1047 .n_adchan = 16,
1048 .adbits = 18,
1049 .ai_fifo_depth = 2047,
1050 .gainlkup = ai_gain_628x,
1051 .ai_speed = 1600,
1052 .n_aochan = 0,
1053 .aobits = 0,
1054 .ao_fifo_depth = 8191,
1055 .reg_type = ni_reg_628x,
1056 .ao_unipolar = 0,
1057 .num_p0_dio_channels = 8,
1058 .caldac = {caldac_none},
1059 .has_8255 = 0,
1060 },
1061 {
1062 .device_id = 0x70bd,
1063 .name = "pci-6281",
1064 .n_adchan = 16,
1065 .adbits = 18,
1066 .ai_fifo_depth = 2047,
1067 .gainlkup = ai_gain_628x,
1068 .ai_speed = 1600,
1069 .n_aochan = 2,
1070 .aobits = 16,
1071 .ao_fifo_depth = 8191,
1072 .ao_range_table = &range_ni_M_628x_ao,
1073 .reg_type = ni_reg_628x,
1074 .ao_unipolar = 1,
1075 .ao_speed = 357,
1076 .num_p0_dio_channels = 8,
1077 .caldac = {caldac_none},
1078 .has_8255 = 0,
1079 },
1080 {
1081 .device_id = 0x70bf,
1082 .name = "pxi-6281",
1083 .n_adchan = 16,
1084 .adbits = 18,
1085 .ai_fifo_depth = 2047,
1086 .gainlkup = ai_gain_628x,
1087 .ai_speed = 1600,
1088 .n_aochan = 2,
1089 .aobits = 16,
1090 .ao_fifo_depth = 8191,
1091 .ao_range_table = &range_ni_M_628x_ao,
1092 .reg_type = ni_reg_628x,
1093 .ao_unipolar = 1,
1094 .ao_speed = 357,
1095 .num_p0_dio_channels = 8,
1096 .caldac = {caldac_none},
1097 .has_8255 = 0,
1098 },
1099 {
1100 .device_id = 0x70bc,
1101 .name = "pci-6284",
1102 .n_adchan = 32,
1103 .adbits = 18,
1104 .ai_fifo_depth = 2047,
1105 .gainlkup = ai_gain_628x,
1106 .ai_speed = 1600,
1107 .n_aochan = 0,
1108 .aobits = 0,
1109 .ao_fifo_depth = 0,
1110 .reg_type = ni_reg_628x,
1111 .ao_unipolar = 0,
1112 .num_p0_dio_channels = 32,
1113 .caldac = {caldac_none},
1114 .has_8255 = 0,
1115 },
1116 {
1117 .device_id = 0x70ac,
1118 .name = "pci-6289",
1119 .n_adchan = 32,
1120 .adbits = 18,
1121 .ai_fifo_depth = 2047,
1122 .gainlkup = ai_gain_628x,
1123 .ai_speed = 1600,
1124 .n_aochan = 4,
1125 .aobits = 16,
1126 .ao_fifo_depth = 8191,
1127 .ao_range_table = &range_ni_M_628x_ao,
1128 .reg_type = ni_reg_628x,
1129 .ao_unipolar = 1,
1130 .ao_speed = 357,
1131 .num_p0_dio_channels = 32,
1132 .caldac = {caldac_none},
1133 .has_8255 = 0,
1134 },
1135 {
1136 .device_id = 0x70C0,
1137 .name = "pci-6143",
1138 .n_adchan = 8,
1139 .adbits = 16,
1140 .ai_fifo_depth = 1024,
1141 .alwaysdither = 0,
1142 .gainlkup = ai_gain_6143,
1143 .ai_speed = 4000,
1144 .n_aochan = 0,
1145 .aobits = 0,
1146 .reg_type = ni_reg_6143,
1147 .ao_unipolar = 0,
1148 .ao_fifo_depth = 0,
1149 .num_p0_dio_channels = 8,
1150 .caldac = {ad8804_debug, ad8804_debug},
1151 },
1152 {
1153 .device_id = 0x710D,
1154 .name = "pxi-6143",
1155 .n_adchan = 8,
1156 .adbits = 16,
1157 .ai_fifo_depth = 1024,
1158 .alwaysdither = 0,
1159 .gainlkup = ai_gain_6143,
1160 .ai_speed = 4000,
1161 .n_aochan = 0,
1162 .aobits = 0,
1163 .reg_type = ni_reg_6143,
1164 .ao_unipolar = 0,
1165 .ao_fifo_depth = 0,
1166 .num_p0_dio_channels = 8,
1167 .caldac = {ad8804_debug, ad8804_debug},
1168 },
1169 };
1170
1171 #define n_pcimio_boards ARRAY_SIZE(ni_boards)
1172
1173 static int pcimio_attach(struct comedi_device *dev,
1174 struct comedi_devconfig *it);
1175 static int pcimio_detach(struct comedi_device *dev);
1176 static struct comedi_driver driver_pcimio = {
1177 .driver_name = DRV_NAME,
1178 .module = THIS_MODULE,
1179 .attach = pcimio_attach,
1180 .detach = pcimio_detach,
1181 };
1182
1183 static int __devinit driver_pcimio_pci_probe(struct pci_dev *dev,
1184 const struct pci_device_id *ent)
1185 {
1186 return comedi_pci_auto_config(dev, driver_pcimio.driver_name);
1187 }
1188
1189 static void __devexit driver_pcimio_pci_remove(struct pci_dev *dev)
1190 {
1191 comedi_pci_auto_unconfig(dev);
1192 }
1193
1194 static struct pci_driver driver_pcimio_pci_driver = {
1195 .id_table = ni_pci_table,
1196 .probe = &driver_pcimio_pci_probe,
1197 .remove = __devexit_p(&driver_pcimio_pci_remove)
1198 };
1199
1200 static int __init driver_pcimio_init_module(void)
1201 {
1202 int retval;
1203
1204 retval = comedi_driver_register(&driver_pcimio);
1205 if (retval < 0)
1206 return retval;
1207
1208 driver_pcimio_pci_driver.name = (char *)driver_pcimio.driver_name;
1209 return pci_register_driver(&driver_pcimio_pci_driver);
1210 }
1211
1212 static void __exit driver_pcimio_cleanup_module(void)
1213 {
1214 pci_unregister_driver(&driver_pcimio_pci_driver);
1215 comedi_driver_unregister(&driver_pcimio);
1216 }
1217
1218 module_init(driver_pcimio_init_module);
1219 module_exit(driver_pcimio_cleanup_module);
1220
1221 struct ni_private {
1222 NI_PRIVATE_COMMON};
1223 #define devpriv ((struct ni_private *)dev->private)
1224
1225 /* How we access registers */
1226
1227 #define ni_writel(a, b) (writel((a), devpriv->mite->daq_io_addr + (b)))
1228 #define ni_readl(a) (readl(devpriv->mite->daq_io_addr + (a)))
1229 #define ni_writew(a, b) (writew((a), devpriv->mite->daq_io_addr + (b)))
1230 #define ni_readw(a) (readw(devpriv->mite->daq_io_addr + (a)))
1231 #define ni_writeb(a, b) (writeb((a), devpriv->mite->daq_io_addr + (b)))
1232 #define ni_readb(a) (readb(devpriv->mite->daq_io_addr + (a)))
1233
1234 /* How we access STC registers */
1235
1236 /* We automatically take advantage of STC registers that can be
1237 * read/written directly in the I/O space of the board. Most
1238 * PCIMIO devices map the low 8 STC registers to iobase+addr*2.
1239 * The 611x devices map the write registers to iobase+addr*2, and
1240 * the read registers to iobase+(addr-1)*2. */
1241 /* However, the 611x boards still aren't working, so I'm disabling
1242 * non-windowed STC access temporarily */
1243
1244 static void e_series_win_out(struct comedi_device *dev, uint16_t data, int reg)
1245 {
1246 unsigned long flags;
1247
1248 spin_lock_irqsave(&devpriv->window_lock, flags);
1249 ni_writew(reg, Window_Address);
1250 ni_writew(data, Window_Data);
1251 spin_unlock_irqrestore(&devpriv->window_lock, flags);
1252 }
1253
1254 static uint16_t e_series_win_in(struct comedi_device *dev, int reg)
1255 {
1256 unsigned long flags;
1257 uint16_t ret;
1258
1259 spin_lock_irqsave(&devpriv->window_lock, flags);
1260 ni_writew(reg, Window_Address);
1261 ret = ni_readw(Window_Data);
1262 spin_unlock_irqrestore(&devpriv->window_lock, flags);
1263
1264 return ret;
1265 }
1266
1267 static void m_series_stc_writew(struct comedi_device *dev, uint16_t data,
1268 int reg)
1269 {
1270 unsigned offset;
1271 switch (reg) {
1272 case ADC_FIFO_Clear:
1273 offset = M_Offset_AI_FIFO_Clear;
1274 break;
1275 case AI_Command_1_Register:
1276 offset = M_Offset_AI_Command_1;
1277 break;
1278 case AI_Command_2_Register:
1279 offset = M_Offset_AI_Command_2;
1280 break;
1281 case AI_Mode_1_Register:
1282 offset = M_Offset_AI_Mode_1;
1283 break;
1284 case AI_Mode_2_Register:
1285 offset = M_Offset_AI_Mode_2;
1286 break;
1287 case AI_Mode_3_Register:
1288 offset = M_Offset_AI_Mode_3;
1289 break;
1290 case AI_Output_Control_Register:
1291 offset = M_Offset_AI_Output_Control;
1292 break;
1293 case AI_Personal_Register:
1294 offset = M_Offset_AI_Personal;
1295 break;
1296 case AI_SI2_Load_A_Register:
1297 /* this is actually a 32 bit register on m series boards */
1298 ni_writel(data, M_Offset_AI_SI2_Load_A);
1299 return;
1300 break;
1301 case AI_SI2_Load_B_Register:
1302 /* this is actually a 32 bit register on m series boards */
1303 ni_writel(data, M_Offset_AI_SI2_Load_B);
1304 return;
1305 break;
1306 case AI_START_STOP_Select_Register:
1307 offset = M_Offset_AI_START_STOP_Select;
1308 break;
1309 case AI_Trigger_Select_Register:
1310 offset = M_Offset_AI_Trigger_Select;
1311 break;
1312 case Analog_Trigger_Etc_Register:
1313 offset = M_Offset_Analog_Trigger_Etc;
1314 break;
1315 case AO_Command_1_Register:
1316 offset = M_Offset_AO_Command_1;
1317 break;
1318 case AO_Command_2_Register:
1319 offset = M_Offset_AO_Command_2;
1320 break;
1321 case AO_Mode_1_Register:
1322 offset = M_Offset_AO_Mode_1;
1323 break;
1324 case AO_Mode_2_Register:
1325 offset = M_Offset_AO_Mode_2;
1326 break;
1327 case AO_Mode_3_Register:
1328 offset = M_Offset_AO_Mode_3;
1329 break;
1330 case AO_Output_Control_Register:
1331 offset = M_Offset_AO_Output_Control;
1332 break;
1333 case AO_Personal_Register:
1334 offset = M_Offset_AO_Personal;
1335 break;
1336 case AO_Start_Select_Register:
1337 offset = M_Offset_AO_Start_Select;
1338 break;
1339 case AO_Trigger_Select_Register:
1340 offset = M_Offset_AO_Trigger_Select;
1341 break;
1342 case Clock_and_FOUT_Register:
1343 offset = M_Offset_Clock_and_FOUT;
1344 break;
1345 case Configuration_Memory_Clear:
1346 offset = M_Offset_Configuration_Memory_Clear;
1347 break;
1348 case DAC_FIFO_Clear:
1349 offset = M_Offset_AO_FIFO_Clear;
1350 break;
1351 case DIO_Control_Register:
1352 printk
1353 ("%s: FIXME: register 0x%x does not map cleanly on to m-series boards.\n",
1354 __func__, reg);
1355 return;
1356 break;
1357 case G_Autoincrement_Register(0):
1358 offset = M_Offset_G0_Autoincrement;
1359 break;
1360 case G_Autoincrement_Register(1):
1361 offset = M_Offset_G1_Autoincrement;
1362 break;
1363 case G_Command_Register(0):
1364 offset = M_Offset_G0_Command;
1365 break;
1366 case G_Command_Register(1):
1367 offset = M_Offset_G1_Command;
1368 break;
1369 case G_Input_Select_Register(0):
1370 offset = M_Offset_G0_Input_Select;
1371 break;
1372 case G_Input_Select_Register(1):
1373 offset = M_Offset_G1_Input_Select;
1374 break;
1375 case G_Mode_Register(0):
1376 offset = M_Offset_G0_Mode;
1377 break;
1378 case G_Mode_Register(1):
1379 offset = M_Offset_G1_Mode;
1380 break;
1381 case Interrupt_A_Ack_Register:
1382 offset = M_Offset_Interrupt_A_Ack;
1383 break;
1384 case Interrupt_A_Enable_Register:
1385 offset = M_Offset_Interrupt_A_Enable;
1386 break;
1387 case Interrupt_B_Ack_Register:
1388 offset = M_Offset_Interrupt_B_Ack;
1389 break;
1390 case Interrupt_B_Enable_Register:
1391 offset = M_Offset_Interrupt_B_Enable;
1392 break;
1393 case Interrupt_Control_Register:
1394 offset = M_Offset_Interrupt_Control;
1395 break;
1396 case IO_Bidirection_Pin_Register:
1397 offset = M_Offset_IO_Bidirection_Pin;
1398 break;
1399 case Joint_Reset_Register:
1400 offset = M_Offset_Joint_Reset;
1401 break;
1402 case RTSI_Trig_A_Output_Register:
1403 offset = M_Offset_RTSI_Trig_A_Output;
1404 break;
1405 case RTSI_Trig_B_Output_Register:
1406 offset = M_Offset_RTSI_Trig_B_Output;
1407 break;
1408 case RTSI_Trig_Direction_Register:
1409 offset = M_Offset_RTSI_Trig_Direction;
1410 break;
1411 default:
1412 printk("%s: bug! unhandled register=0x%x in switch.\n",
1413 __func__, reg);
1414 BUG();
1415 return;
1416 break;
1417 }
1418 ni_writew(data, offset);
1419 }
1420
1421 static uint16_t m_series_stc_readw(struct comedi_device *dev, int reg)
1422 {
1423 unsigned offset;
1424 switch (reg) {
1425 case AI_Status_1_Register:
1426 offset = M_Offset_AI_Status_1;
1427 break;
1428 case AO_Status_1_Register:
1429 offset = M_Offset_AO_Status_1;
1430 break;
1431 case AO_Status_2_Register:
1432 offset = M_Offset_AO_Status_2;
1433 break;
1434 case DIO_Serial_Input_Register:
1435 return ni_readb(M_Offset_SCXI_Serial_Data_In);
1436 break;
1437 case Joint_Status_1_Register:
1438 offset = M_Offset_Joint_Status_1;
1439 break;
1440 case Joint_Status_2_Register:
1441 offset = M_Offset_Joint_Status_2;
1442 break;
1443 case G_Status_Register:
1444 offset = M_Offset_G01_Status;
1445 break;
1446 default:
1447 printk("%s: bug! unhandled register=0x%x in switch.\n",
1448 __func__, reg);
1449 BUG();
1450 return 0;
1451 break;
1452 }
1453 return ni_readw(offset);
1454 }
1455
1456 static void m_series_stc_writel(struct comedi_device *dev, uint32_t data,
1457 int reg)
1458 {
1459 unsigned offset;
1460 switch (reg) {
1461 case AI_SC_Load_A_Registers:
1462 offset = M_Offset_AI_SC_Load_A;
1463 break;
1464 case AI_SI_Load_A_Registers:
1465 offset = M_Offset_AI_SI_Load_A;
1466 break;
1467 case AO_BC_Load_A_Register:
1468 offset = M_Offset_AO_BC_Load_A;
1469 break;
1470 case AO_UC_Load_A_Register:
1471 offset = M_Offset_AO_UC_Load_A;
1472 break;
1473 case AO_UI_Load_A_Register:
1474 offset = M_Offset_AO_UI_Load_A;
1475 break;
1476 case G_Load_A_Register(0):
1477 offset = M_Offset_G0_Load_A;
1478 break;
1479 case G_Load_A_Register(1):
1480 offset = M_Offset_G1_Load_A;
1481 break;
1482 case G_Load_B_Register(0):
1483 offset = M_Offset_G0_Load_B;
1484 break;
1485 case G_Load_B_Register(1):
1486 offset = M_Offset_G1_Load_B;
1487 break;
1488 default:
1489 printk("%s: bug! unhandled register=0x%x in switch.\n",
1490 __func__, reg);
1491 BUG();
1492 return;
1493 break;
1494 }
1495 ni_writel(data, offset);
1496 }
1497
1498 static uint32_t m_series_stc_readl(struct comedi_device *dev, int reg)
1499 {
1500 unsigned offset;
1501 switch (reg) {
1502 case G_HW_Save_Register(0):
1503 offset = M_Offset_G0_HW_Save;
1504 break;
1505 case G_HW_Save_Register(1):
1506 offset = M_Offset_G1_HW_Save;
1507 break;
1508 case G_Save_Register(0):
1509 offset = M_Offset_G0_Save;
1510 break;
1511 case G_Save_Register(1):
1512 offset = M_Offset_G1_Save;
1513 break;
1514 default:
1515 printk("%s: bug! unhandled register=0x%x in switch.\n",
1516 __func__, reg);
1517 BUG();
1518 return 0;
1519 break;
1520 }
1521 return ni_readl(offset);
1522 }
1523
1524 #define interrupt_pin(a) 0
1525 #define IRQ_POLARITY 1
1526
1527 #define NI_E_IRQ_FLAGS IRQF_SHARED
1528
1529 #include "ni_mio_common.c"
1530
1531 static int pcimio_find_device(struct comedi_device *dev, int bus, int slot);
1532 static int pcimio_ai_change(struct comedi_device *dev,
1533 struct comedi_subdevice *s, unsigned long new_size);
1534 static int pcimio_ao_change(struct comedi_device *dev,
1535 struct comedi_subdevice *s, unsigned long new_size);
1536 static int pcimio_gpct0_change(struct comedi_device *dev,
1537 struct comedi_subdevice *s,
1538 unsigned long new_size);
1539 static int pcimio_gpct1_change(struct comedi_device *dev,
1540 struct comedi_subdevice *s,
1541 unsigned long new_size);
1542 static int pcimio_dio_change(struct comedi_device *dev,
1543 struct comedi_subdevice *s,
1544 unsigned long new_size);
1545
1546 static void m_series_init_eeprom_buffer(struct comedi_device *dev)
1547 {
1548 static const int Start_Cal_EEPROM = 0x400;
1549 static const unsigned window_size = 10;
1550 static const int serial_number_eeprom_offset = 0x4;
1551 static const int serial_number_eeprom_length = 0x4;
1552 unsigned old_iodwbsr_bits;
1553 unsigned old_iodwbsr1_bits;
1554 unsigned old_iodwcr1_bits;
1555 int i;
1556
1557 old_iodwbsr_bits = readl(devpriv->mite->mite_io_addr + MITE_IODWBSR);
1558 old_iodwbsr1_bits = readl(devpriv->mite->mite_io_addr + MITE_IODWBSR_1);
1559 old_iodwcr1_bits = readl(devpriv->mite->mite_io_addr + MITE_IODWCR_1);
1560 writel(0x0, devpriv->mite->mite_io_addr + MITE_IODWBSR);
1561 writel(((0x80 | window_size) | devpriv->mite->daq_phys_addr),
1562 devpriv->mite->mite_io_addr + MITE_IODWBSR_1);
1563 writel(0x1 | old_iodwcr1_bits,
1564 devpriv->mite->mite_io_addr + MITE_IODWCR_1);
1565 writel(0xf, devpriv->mite->mite_io_addr + 0x30);
1566
1567 BUG_ON(serial_number_eeprom_length > sizeof(devpriv->serial_number));
1568 for (i = 0; i < serial_number_eeprom_length; ++i) {
1569 char *byte_ptr = (char *)&devpriv->serial_number + i;
1570 *byte_ptr = ni_readb(serial_number_eeprom_offset + i);
1571 }
1572 devpriv->serial_number = be32_to_cpu(devpriv->serial_number);
1573
1574 for (i = 0; i < M_SERIES_EEPROM_SIZE; ++i) {
1575 devpriv->eeprom_buffer[i] = ni_readb(Start_Cal_EEPROM + i);
1576 }
1577
1578 writel(old_iodwbsr1_bits, devpriv->mite->mite_io_addr + MITE_IODWBSR_1);
1579 writel(old_iodwbsr_bits, devpriv->mite->mite_io_addr + MITE_IODWBSR);
1580 writel(old_iodwcr1_bits, devpriv->mite->mite_io_addr + MITE_IODWCR_1);
1581 writel(0x0, devpriv->mite->mite_io_addr + 0x30);
1582 }
1583
1584 static void init_6143(struct comedi_device *dev)
1585 {
1586 /* Disable interrupts */
1587 devpriv->stc_writew(dev, 0, Interrupt_Control_Register);
1588
1589 /* Initialise 6143 AI specific bits */
1590 ni_writeb(0x00, Magic_6143); /* Set G0,G1 DMA mode to E series version */
1591 ni_writeb(0x80, PipelineDelay_6143); /* Set EOCMode, ADCMode and pipelinedelay */
1592 ni_writeb(0x00, EOC_Set_6143); /* Set EOC Delay */
1593
1594 ni_writel(boardtype.ai_fifo_depth / 2, AIFIFO_Flag_6143); /* Set the FIFO half full level */
1595
1596 /* Strobe Relay disable bit */
1597 devpriv->ai_calib_source_enabled = 0;
1598 ni_writew(devpriv->ai_calib_source | Calibration_Channel_6143_RelayOff,
1599 Calibration_Channel_6143);
1600 ni_writew(devpriv->ai_calib_source, Calibration_Channel_6143);
1601 }
1602
1603 /* cleans up allocated resources */
1604 static int pcimio_detach(struct comedi_device *dev)
1605 {
1606 mio_common_detach(dev);
1607 if (dev->irq) {
1608 free_irq(dev->irq, dev);
1609 }
1610 if (dev->private) {
1611 mite_free_ring(devpriv->ai_mite_ring);
1612 mite_free_ring(devpriv->ao_mite_ring);
1613 mite_free_ring(devpriv->cdo_mite_ring);
1614 mite_free_ring(devpriv->gpct_mite_ring[0]);
1615 mite_free_ring(devpriv->gpct_mite_ring[1]);
1616 if (devpriv->mite)
1617 mite_unsetup(devpriv->mite);
1618 }
1619
1620 return 0;
1621 }
1622
1623 static int pcimio_attach(struct comedi_device *dev, struct comedi_devconfig *it)
1624 {
1625 int ret;
1626
1627 printk("comedi%d: ni_pcimio:", dev->minor);
1628
1629 ret = ni_alloc_private(dev);
1630 if (ret < 0)
1631 return ret;
1632
1633 ret = pcimio_find_device(dev, it->options[0], it->options[1]);
1634 if (ret < 0)
1635 return ret;
1636
1637 printk(" %s", boardtype.name);
1638 dev->board_name = boardtype.name;
1639
1640 if (boardtype.reg_type & ni_reg_m_series_mask) {
1641 devpriv->stc_writew = &m_series_stc_writew;
1642 devpriv->stc_readw = &m_series_stc_readw;
1643 devpriv->stc_writel = &m_series_stc_writel;
1644 devpriv->stc_readl = &m_series_stc_readl;
1645 } else {
1646 devpriv->stc_writew = &e_series_win_out;
1647 devpriv->stc_readw = &e_series_win_in;
1648 devpriv->stc_writel = &win_out2;
1649 devpriv->stc_readl = &win_in2;
1650 }
1651
1652 ret = mite_setup(devpriv->mite);
1653 if (ret < 0) {
1654 printk(" error setting up mite\n");
1655 return ret;
1656 }
1657 comedi_set_hw_dev(dev, &devpriv->mite->pcidev->dev);
1658 devpriv->ai_mite_ring = mite_alloc_ring(devpriv->mite);
1659 if (devpriv->ai_mite_ring == NULL)
1660 return -ENOMEM;
1661 devpriv->ao_mite_ring = mite_alloc_ring(devpriv->mite);
1662 if (devpriv->ao_mite_ring == NULL)
1663 return -ENOMEM;
1664 devpriv->cdo_mite_ring = mite_alloc_ring(devpriv->mite);
1665 if (devpriv->cdo_mite_ring == NULL)
1666 return -ENOMEM;
1667 devpriv->gpct_mite_ring[0] = mite_alloc_ring(devpriv->mite);
1668 if (devpriv->gpct_mite_ring[0] == NULL)
1669 return -ENOMEM;
1670 devpriv->gpct_mite_ring[1] = mite_alloc_ring(devpriv->mite);
1671 if (devpriv->gpct_mite_ring[1] == NULL)
1672 return -ENOMEM;
1673
1674 if (boardtype.reg_type & ni_reg_m_series_mask)
1675 m_series_init_eeprom_buffer(dev);
1676 if (boardtype.reg_type == ni_reg_6143)
1677 init_6143(dev);
1678
1679 dev->irq = mite_irq(devpriv->mite);
1680
1681 if (dev->irq == 0) {
1682 printk(" unknown irq (bad)\n");
1683 } else {
1684 printk(" ( irq = %u )", dev->irq);
1685 ret = request_irq(dev->irq, ni_E_interrupt, NI_E_IRQ_FLAGS,
1686 DRV_NAME, dev);
1687 if (ret < 0) {
1688 printk(" irq not available\n");
1689 dev->irq = 0;
1690 }
1691 }
1692
1693 ret = ni_E_init(dev, it);
1694 if (ret < 0)
1695 return ret;
1696
1697 dev->subdevices[NI_AI_SUBDEV].buf_change = &pcimio_ai_change;
1698 dev->subdevices[NI_AO_SUBDEV].buf_change = &pcimio_ao_change;
1699 dev->subdevices[NI_GPCT_SUBDEV(0)].buf_change = &pcimio_gpct0_change;
1700 dev->subdevices[NI_GPCT_SUBDEV(1)].buf_change = &pcimio_gpct1_change;
1701 dev->subdevices[NI_DIO_SUBDEV].buf_change = &pcimio_dio_change;
1702
1703 return ret;
1704 }
1705
1706 static int pcimio_find_device(struct comedi_device *dev, int bus, int slot)
1707 {
1708 struct mite_struct *mite;
1709 int i;
1710
1711 for (mite = mite_devices; mite; mite = mite->next) {
1712 if (mite->used)
1713 continue;
1714 if (bus || slot) {
1715 if (bus != mite->pcidev->bus->number ||
1716 slot != PCI_SLOT(mite->pcidev->devfn))
1717 continue;
1718 }
1719
1720 for (i = 0; i < n_pcimio_boards; i++) {
1721 if (mite_device_id(mite) == ni_boards[i].device_id) {
1722 dev->board_ptr = ni_boards + i;
1723 devpriv->mite = mite;
1724
1725 return 0;
1726 }
1727 }
1728 }
1729 printk("no device found\n");
1730 mite_list_devices();
1731 return -EIO;
1732 }
1733
1734 static int pcimio_ai_change(struct comedi_device *dev,
1735 struct comedi_subdevice *s, unsigned long new_size)
1736 {
1737 int ret;
1738
1739 ret = mite_buf_change(devpriv->ai_mite_ring, s->async);
1740 if (ret < 0)
1741 return ret;
1742
1743 return 0;
1744 }
1745
1746 static int pcimio_ao_change(struct comedi_device *dev,
1747 struct comedi_subdevice *s, unsigned long new_size)
1748 {
1749 int ret;
1750
1751 ret = mite_buf_change(devpriv->ao_mite_ring, s->async);
1752 if (ret < 0)
1753 return ret;
1754
1755 return 0;
1756 }
1757
1758 static int pcimio_gpct0_change(struct comedi_device *dev,
1759 struct comedi_subdevice *s,
1760 unsigned long new_size)
1761 {
1762 int ret;
1763
1764 ret = mite_buf_change(devpriv->gpct_mite_ring[0], s->async);
1765 if (ret < 0)
1766 return ret;
1767
1768 return 0;
1769 }
1770
1771 static int pcimio_gpct1_change(struct comedi_device *dev,
1772 struct comedi_subdevice *s,
1773 unsigned long new_size)
1774 {
1775 int ret;
1776
1777 ret = mite_buf_change(devpriv->gpct_mite_ring[1], s->async);
1778 if (ret < 0)
1779 return ret;
1780
1781 return 0;
1782 }
1783
1784 static int pcimio_dio_change(struct comedi_device *dev,
1785 struct comedi_subdevice *s, unsigned long new_size)
1786 {
1787 int ret;
1788
1789 ret = mite_buf_change(devpriv->cdo_mite_ring, s->async);
1790 if (ret < 0)
1791 return ret;
1792
1793 return 0;
1794 }
Tomato firmware and modifications.