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GUI: Fix Tomato RAF theme for all builds. Compilation typo.
[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / drivers / staging / comedi / drivers / gsc_hpdi.c
blob03b443289c6d6d7bfec754c672de44e2f1d5cfe1
1 /*
2 comedi/drivers/gsc_hpdi.c
3 This is a driver for the General Standards Corporation High
4 Speed Parallel Digital Interface rs485 boards.
5
6 Author: Frank Mori Hess <fmhess@users.sourceforge.net>
7 Copyright (C) 2003 Coherent Imaging Systems
8
9 COMEDI - Linux Control and Measurement Device Interface
10 Copyright (C) 1997-8 David A. Schleef <ds@schleef.org>
11
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
16
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
21
22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the Free Software
24 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25
26 ************************************************************************/
27
28 /*
29
30 Driver: gsc_hpdi
31 Description: General Standards Corporation High
32 Speed Parallel Digital Interface rs485 boards
33 Author: Frank Mori Hess <fmhess@users.sourceforge.net>
34 Status: only receive mode works, transmit not supported
35 Updated: 2003-02-20
36 Devices: [General Standards Corporation] PCI-HPDI32 (gsc_hpdi),
37 PMC-HPDI32
38
39 Configuration options:
40 [0] - PCI bus of device (optional)
41 [1] - PCI slot of device (optional)
42
43 There are some additional hpdi models available from GSC for which
44 support could be added to this driver.
45
46 */
47
48 #include <linux/interrupt.h>
49 #include "../comedidev.h"
50 #include <linux/delay.h>
51
52 #include "comedi_pci.h"
53 #include "plx9080.h"
54 #include "comedi_fc.h"
55
56 static int hpdi_attach(struct comedi_device *dev, struct comedi_devconfig *it);
57 static int hpdi_detach(struct comedi_device *dev);
58 static void abort_dma(struct comedi_device *dev, unsigned int channel);
59 static int hpdi_cmd(struct comedi_device *dev, struct comedi_subdevice *s);
60 static int hpdi_cmd_test(struct comedi_device *dev, struct comedi_subdevice *s,
61 struct comedi_cmd *cmd);
62 static int hpdi_cancel(struct comedi_device *dev, struct comedi_subdevice *s);
63 static irqreturn_t handle_interrupt(int irq, void *d);
64 static int dio_config_block_size(struct comedi_device *dev, unsigned int *data);
65
66 #undef HPDI_DEBUG /* disable debugging messages */
67 /* #define HPDI_DEBUG enable debugging code */
68
69 #ifdef HPDI_DEBUG
70 #define DEBUG_PRINT(format, args...) printk(format , ## args)
71 #else
72 #define DEBUG_PRINT(format, args...)
73 #endif
74
75 #define TIMER_BASE 50 /* 20MHz master clock */
76 #define DMA_BUFFER_SIZE 0x10000
77 #define NUM_DMA_BUFFERS 4
78 #define NUM_DMA_DESCRIPTORS 256
79
80 /* indices of base address regions */
81 enum base_address_regions {
82 PLX9080_BADDRINDEX = 0,
83 HPDI_BADDRINDEX = 2,
84 };
85
86 enum hpdi_registers {
87 FIRMWARE_REV_REG = 0x0,
88 BOARD_CONTROL_REG = 0x4,
89 BOARD_STATUS_REG = 0x8,
90 TX_PROG_ALMOST_REG = 0xc,
91 RX_PROG_ALMOST_REG = 0x10,
92 FEATURES_REG = 0x14,
93 FIFO_REG = 0x18,
94 TX_STATUS_COUNT_REG = 0x1c,
95 TX_LINE_VALID_COUNT_REG = 0x20,
96 TX_LINE_INVALID_COUNT_REG = 0x24,
97 RX_STATUS_COUNT_REG = 0x28,
98 RX_LINE_COUNT_REG = 0x2c,
99 INTERRUPT_CONTROL_REG = 0x30,
100 INTERRUPT_STATUS_REG = 0x34,
101 TX_CLOCK_DIVIDER_REG = 0x38,
102 TX_FIFO_SIZE_REG = 0x40,
103 RX_FIFO_SIZE_REG = 0x44,
104 TX_FIFO_WORDS_REG = 0x48,
105 RX_FIFO_WORDS_REG = 0x4c,
106 INTERRUPT_EDGE_LEVEL_REG = 0x50,
107 INTERRUPT_POLARITY_REG = 0x54,
108 };
109
110 int command_channel_valid(unsigned int channel)
111 {
112 if (channel == 0 || channel > 6) {
113 printk(KERN_WARNING
114 "gsc_hpdi: bug! invalid cable command channel\n");
115 return 0;
116 }
117 return 1;
118 }
119
120 /* bit definitions */
121
122 enum firmware_revision_bits {
123 FEATURES_REG_PRESENT_BIT = 0x8000,
124 };
125 int firmware_revision(uint32_t fwr_bits)
126 {
127 return fwr_bits & 0xff;
128 }
129
130 int pcb_revision(uint32_t fwr_bits)
131 {
132 return (fwr_bits >> 8) & 0xff;
133 }
134
135 int hpdi_subid(uint32_t fwr_bits)
136 {
137 return (fwr_bits >> 16) & 0xff;
138 }
139
140 enum board_control_bits {
141 BOARD_RESET_BIT = 0x1, /* wait 10usec before accessing fifos */
142 TX_FIFO_RESET_BIT = 0x2,
143 RX_FIFO_RESET_BIT = 0x4,
144 TX_ENABLE_BIT = 0x10,
145 RX_ENABLE_BIT = 0x20,
146 DEMAND_DMA_DIRECTION_TX_BIT = 0x40,
147 /* for ch 0, ch 1 can only transmit (when present) */
148 LINE_VALID_ON_STATUS_VALID_BIT = 0x80,
149 START_TX_BIT = 0x10,
150 CABLE_THROTTLE_ENABLE_BIT = 0x20,
151 TEST_MODE_ENABLE_BIT = 0x80000000,
152 };
153 uint32_t command_discrete_output_bits(unsigned int channel, int output,
154 int output_value)
155 {
156 uint32_t bits = 0;
157
158 if (command_channel_valid(channel) == 0)
159 return 0;
160 if (output) {
161 bits |= 0x1 << (16 + channel);
162 if (output_value)
163 bits |= 0x1 << (24 + channel);
164 } else
165 bits |= 0x1 << (24 + channel);
166
167 return bits;
168 }
169
170 enum board_status_bits {
171 COMMAND_LINE_STATUS_MASK = 0x7f,
172 TX_IN_PROGRESS_BIT = 0x80,
173 TX_NOT_EMPTY_BIT = 0x100,
174 TX_NOT_ALMOST_EMPTY_BIT = 0x200,
175 TX_NOT_ALMOST_FULL_BIT = 0x400,
176 TX_NOT_FULL_BIT = 0x800,
177 RX_NOT_EMPTY_BIT = 0x1000,
178 RX_NOT_ALMOST_EMPTY_BIT = 0x2000,
179 RX_NOT_ALMOST_FULL_BIT = 0x4000,
180 RX_NOT_FULL_BIT = 0x8000,
181 BOARD_JUMPER0_INSTALLED_BIT = 0x10000,
182 BOARD_JUMPER1_INSTALLED_BIT = 0x20000,
183 TX_OVERRUN_BIT = 0x200000,
184 RX_UNDERRUN_BIT = 0x400000,
185 RX_OVERRUN_BIT = 0x800000,
186 };
187
188 uint32_t almost_full_bits(unsigned int num_words)
189 {
190 return (num_words << 16) & 0xff0000;
191 }
192
193 uint32_t almost_empty_bits(unsigned int num_words)
194 {
195 return num_words & 0xffff;
196 }
197
198 unsigned int almost_full_num_words(uint32_t bits)
199 {
200 return (bits >> 16) & 0xffff;
201 }
202
203 unsigned int almost_empty_num_words(uint32_t bits)
204 {
205 return bits & 0xffff;
206 }
207
208 enum features_bits {
209 FIFO_SIZE_PRESENT_BIT = 0x1,
210 FIFO_WORDS_PRESENT_BIT = 0x2,
211 LEVEL_EDGE_INTERRUPTS_PRESENT_BIT = 0x4,
212 GPIO_SUPPORTED_BIT = 0x8,
213 PLX_DMA_CH1_SUPPORTED_BIT = 0x10,
214 OVERRUN_UNDERRUN_SUPPORTED_BIT = 0x20,
215 };
216
217 enum interrupt_sources {
218 FRAME_VALID_START_INTR = 0,
219 FRAME_VALID_END_INTR = 1,
220 TX_FIFO_EMPTY_INTR = 8,
221 TX_FIFO_ALMOST_EMPTY_INTR = 9,
222 TX_FIFO_ALMOST_FULL_INTR = 10,
223 TX_FIFO_FULL_INTR = 11,
224 RX_EMPTY_INTR = 12,
225 RX_ALMOST_EMPTY_INTR = 13,
226 RX_ALMOST_FULL_INTR = 14,
227 RX_FULL_INTR = 15,
228 };
229 int command_intr_source(unsigned int channel)
230 {
231 if (command_channel_valid(channel) == 0)
232 channel = 1;
233 return channel + 1;
234 }
235
236 uint32_t intr_bit(int interrupt_source)
237 {
238 return 0x1 << interrupt_source;
239 }
240
241 uint32_t tx_clock_divisor_bits(unsigned int divisor)
242 {
243 return divisor & 0xff;
244 }
245
246 unsigned int fifo_size(uint32_t fifo_size_bits)
247 {
248 return fifo_size_bits & 0xfffff;
249 }
250
251 unsigned int fifo_words(uint32_t fifo_words_bits)
252 {
253 return fifo_words_bits & 0xfffff;
254 }
255
256 uint32_t intr_edge_bit(int interrupt_source)
257 {
258 return 0x1 << interrupt_source;
259 }
260
261 uint32_t intr_active_high_bit(int interrupt_source)
262 {
263 return 0x1 << interrupt_source;
264 }
265
266 struct hpdi_board {
267
268 char *name;
269 int device_id; /* pci device id */
270 int subdevice_id; /* pci subdevice id */
271 };
272
273 static const struct hpdi_board hpdi_boards[] = {
274 {
275 .name = "pci-hpdi32",
276 .device_id = PCI_DEVICE_ID_PLX_9080,
277 .subdevice_id = 0x2400,
278 },
279 };
280
281 static DEFINE_PCI_DEVICE_TABLE(hpdi_pci_table) = {
282 {
283 PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9080, PCI_VENDOR_ID_PLX,
284 0x2400, 0, 0, 0}, {
285 0}
286 };
287
288 MODULE_DEVICE_TABLE(pci, hpdi_pci_table);
289
290 static inline struct hpdi_board *board(const struct comedi_device *dev)
291 {
292 return (struct hpdi_board *)dev->board_ptr;
293 }
294
295 struct hpdi_private {
296
297 struct pci_dev *hw_dev; /* pointer to board's pci_dev struct */
298 /* base addresses (physical) */
299 resource_size_t plx9080_phys_iobase;
300 resource_size_t hpdi_phys_iobase;
301 /* base addresses (ioremapped) */
302 void *plx9080_iobase;
303 void *hpdi_iobase;
304 uint32_t *dio_buffer[NUM_DMA_BUFFERS]; /* dma buffers */
305 /* physical addresses of dma buffers */
306 dma_addr_t dio_buffer_phys_addr[NUM_DMA_BUFFERS];
307 /* array of dma descriptors read by plx9080, allocated to get proper
308 * alignment */
309 struct plx_dma_desc *dma_desc;
310 /* physical address of dma descriptor array */
311 dma_addr_t dma_desc_phys_addr;
312 unsigned int num_dma_descriptors;
313 /* pointer to start of buffers indexed by descriptor */
314 uint32_t *desc_dio_buffer[NUM_DMA_DESCRIPTORS];
315 /* index of the dma descriptor that is currently being used */
316 volatile unsigned int dma_desc_index;
317 unsigned int tx_fifo_size;
318 unsigned int rx_fifo_size;
319 volatile unsigned long dio_count;
320 /* software copies of values written to hpdi registers */
321 volatile uint32_t bits[24];
322 /* number of bytes at which to generate COMEDI_CB_BLOCK events */
323 volatile unsigned int block_size;
324 unsigned dio_config_output:1;
325 };
326
327 static inline struct hpdi_private *priv(struct comedi_device *dev)
328 {
329 return dev->private;
330 }
331
332 static struct comedi_driver driver_hpdi = {
333 .driver_name = "gsc_hpdi",
334 .module = THIS_MODULE,
335 .attach = hpdi_attach,
336 .detach = hpdi_detach,
337 };
338
339 static int __devinit driver_hpdi_pci_probe(struct pci_dev *dev,
340 const struct pci_device_id *ent)
341 {
342 return comedi_pci_auto_config(dev, driver_hpdi.driver_name);
343 }
344
345 static void __devexit driver_hpdi_pci_remove(struct pci_dev *dev)
346 {
347 comedi_pci_auto_unconfig(dev);
348 }
349
350 static struct pci_driver driver_hpdi_pci_driver = {
351 .id_table = hpdi_pci_table,
352 .probe = &driver_hpdi_pci_probe,
353 .remove = __devexit_p(&driver_hpdi_pci_remove)
354 };
355
356 static int __init driver_hpdi_init_module(void)
357 {
358 int retval;
359
360 retval = comedi_driver_register(&driver_hpdi);
361 if (retval < 0)
362 return retval;
363
364 driver_hpdi_pci_driver.name = (char *)driver_hpdi.driver_name;
365 return pci_register_driver(&driver_hpdi_pci_driver);
366 }
367
368 static void __exit driver_hpdi_cleanup_module(void)
369 {
370 pci_unregister_driver(&driver_hpdi_pci_driver);
371 comedi_driver_unregister(&driver_hpdi);
372 }
373
374 module_init(driver_hpdi_init_module);
375 module_exit(driver_hpdi_cleanup_module);
376
377 static int dio_config_insn(struct comedi_device *dev,
378 struct comedi_subdevice *s, struct comedi_insn *insn,
379 unsigned int *data)
380 {
381 switch (data[0]) {
382 case INSN_CONFIG_DIO_OUTPUT:
383 priv(dev)->dio_config_output = 1;
384 return insn->n;
385 break;
386 case INSN_CONFIG_DIO_INPUT:
387 priv(dev)->dio_config_output = 0;
388 return insn->n;
389 break;
390 case INSN_CONFIG_DIO_QUERY:
391 data[1] =
392 priv(dev)->dio_config_output ? COMEDI_OUTPUT : COMEDI_INPUT;
393 return insn->n;
394 break;
395 case INSN_CONFIG_BLOCK_SIZE:
396 return dio_config_block_size(dev, data);
397 break;
398 default:
399 break;
400 }
401
402 return -EINVAL;
403 }
404
405 static void disable_plx_interrupts(struct comedi_device *dev)
406 {
407 writel(0, priv(dev)->plx9080_iobase + PLX_INTRCS_REG);
408 }
409
410 /* initialize plx9080 chip */
411 static void init_plx9080(struct comedi_device *dev)
412 {
413 uint32_t bits;
414 void *plx_iobase = priv(dev)->plx9080_iobase;
415
416 /* plx9080 dump */
417 DEBUG_PRINT(" plx interrupt status 0x%x\n",
418 readl(plx_iobase + PLX_INTRCS_REG));
419 DEBUG_PRINT(" plx id bits 0x%x\n", readl(plx_iobase + PLX_ID_REG));
420 DEBUG_PRINT(" plx control reg 0x%x\n",
421 readl(priv(dev)->plx9080_iobase + PLX_CONTROL_REG));
422
423 DEBUG_PRINT(" plx revision 0x%x\n",
424 readl(plx_iobase + PLX_REVISION_REG));
425 DEBUG_PRINT(" plx dma channel 0 mode 0x%x\n",
426 readl(plx_iobase + PLX_DMA0_MODE_REG));
427 DEBUG_PRINT(" plx dma channel 1 mode 0x%x\n",
428 readl(plx_iobase + PLX_DMA1_MODE_REG));
429 DEBUG_PRINT(" plx dma channel 0 pci address 0x%x\n",
430 readl(plx_iobase + PLX_DMA0_PCI_ADDRESS_REG));
431 DEBUG_PRINT(" plx dma channel 0 local address 0x%x\n",
432 readl(plx_iobase + PLX_DMA0_LOCAL_ADDRESS_REG));
433 DEBUG_PRINT(" plx dma channel 0 transfer size 0x%x\n",
434 readl(plx_iobase + PLX_DMA0_TRANSFER_SIZE_REG));
435 DEBUG_PRINT(" plx dma channel 0 descriptor 0x%x\n",
436 readl(plx_iobase + PLX_DMA0_DESCRIPTOR_REG));
437 DEBUG_PRINT(" plx dma channel 0 command status 0x%x\n",
438 readb(plx_iobase + PLX_DMA0_CS_REG));
439 DEBUG_PRINT(" plx dma channel 0 threshold 0x%x\n",
440 readl(plx_iobase + PLX_DMA0_THRESHOLD_REG));
441 DEBUG_PRINT(" plx bigend 0x%x\n", readl(plx_iobase + PLX_BIGEND_REG));
442 #ifdef __BIG_ENDIAN
443 bits = BIGEND_DMA0 | BIGEND_DMA1;
444 #else
445 bits = 0;
446 #endif
447 writel(bits, priv(dev)->plx9080_iobase + PLX_BIGEND_REG);
448
449 disable_plx_interrupts(dev);
450
451 abort_dma(dev, 0);
452 abort_dma(dev, 1);
453
454 /* configure dma0 mode */
455 bits = 0;
456 /* enable ready input */
457 bits |= PLX_DMA_EN_READYIN_BIT;
458 /* enable dma chaining */
459 bits |= PLX_EN_CHAIN_BIT;
460 /* enable interrupt on dma done
461 * (probably don't need this, since chain never finishes) */
462 bits |= PLX_EN_DMA_DONE_INTR_BIT;
463 /* don't increment local address during transfers
464 * (we are transferring from a fixed fifo register) */
465 bits |= PLX_LOCAL_ADDR_CONST_BIT;
466 /* route dma interrupt to pci bus */
467 bits |= PLX_DMA_INTR_PCI_BIT;
468 /* enable demand mode */
469 bits |= PLX_DEMAND_MODE_BIT;
470 /* enable local burst mode */
471 bits |= PLX_DMA_LOCAL_BURST_EN_BIT;
472 bits |= PLX_LOCAL_BUS_32_WIDE_BITS;
473 writel(bits, plx_iobase + PLX_DMA0_MODE_REG);
474 }
475
476 /* Allocate and initialize the subdevice structures.
477 */
478 static int setup_subdevices(struct comedi_device *dev)
479 {
480 struct comedi_subdevice *s;
481
482 if (alloc_subdevices(dev, 1) < 0)
483 return -ENOMEM;
484
485 s = dev->subdevices + 0;
486 /* analog input subdevice */
487 dev->read_subdev = s;
488 /* dev->write_subdev = s; */
489 s->type = COMEDI_SUBD_DIO;
490 s->subdev_flags =
491 SDF_READABLE | SDF_WRITEABLE | SDF_LSAMPL | SDF_CMD_READ;
492 s->n_chan = 32;
493 s->len_chanlist = 32;
494 s->maxdata = 1;
495 s->range_table = &range_digital;
496 s->insn_config = dio_config_insn;
497 s->do_cmd = hpdi_cmd;
498 s->do_cmdtest = hpdi_cmd_test;
499 s->cancel = hpdi_cancel;
500
501 return 0;
502 }
503
504 static int init_hpdi(struct comedi_device *dev)
505 {
506 uint32_t plx_intcsr_bits;
507
508 writel(BOARD_RESET_BIT, priv(dev)->hpdi_iobase + BOARD_CONTROL_REG);
509 udelay(10);
510
511 writel(almost_empty_bits(32) | almost_full_bits(32),
512 priv(dev)->hpdi_iobase + RX_PROG_ALMOST_REG);
513 writel(almost_empty_bits(32) | almost_full_bits(32),
514 priv(dev)->hpdi_iobase + TX_PROG_ALMOST_REG);
515
516 priv(dev)->tx_fifo_size = fifo_size(readl(priv(dev)->hpdi_iobase +
517 TX_FIFO_SIZE_REG));
518 priv(dev)->rx_fifo_size = fifo_size(readl(priv(dev)->hpdi_iobase +
519 RX_FIFO_SIZE_REG));
520
521 writel(0, priv(dev)->hpdi_iobase + INTERRUPT_CONTROL_REG);
522
523 /* enable interrupts */
524 plx_intcsr_bits =
525 ICS_AERR | ICS_PERR | ICS_PIE | ICS_PLIE | ICS_PAIE | ICS_LIE |
526 ICS_DMA0_E;
527 writel(plx_intcsr_bits, priv(dev)->plx9080_iobase + PLX_INTRCS_REG);
528
529 return 0;
530 }
531
532 /* setup dma descriptors so a link completes every 'transfer_size' bytes */
533 static int setup_dma_descriptors(struct comedi_device *dev,
534 unsigned int transfer_size)
535 {
536 unsigned int buffer_index, buffer_offset;
537 uint32_t next_bits = PLX_DESC_IN_PCI_BIT | PLX_INTR_TERM_COUNT |
538 PLX_XFER_LOCAL_TO_PCI;
539 unsigned int i;
540
541 if (transfer_size > DMA_BUFFER_SIZE)
542 transfer_size = DMA_BUFFER_SIZE;
543 transfer_size -= transfer_size % sizeof(uint32_t);
544 if (transfer_size == 0)
545 return -1;
546
547 DEBUG_PRINT(" transfer_size %i\n", transfer_size);
548 DEBUG_PRINT(" descriptors at 0x%lx\n",
549 (unsigned long)priv(dev)->dma_desc_phys_addr);
550
551 buffer_offset = 0;
552 buffer_index = 0;
553 for (i = 0; i < NUM_DMA_DESCRIPTORS &&
554 buffer_index < NUM_DMA_BUFFERS; i++) {
555 priv(dev)->dma_desc[i].pci_start_addr =
556 cpu_to_le32(priv(dev)->dio_buffer_phys_addr[buffer_index] +
557 buffer_offset);
558 priv(dev)->dma_desc[i].local_start_addr = cpu_to_le32(FIFO_REG);
559 priv(dev)->dma_desc[i].transfer_size =
560 cpu_to_le32(transfer_size);
561 priv(dev)->dma_desc[i].next =
562 cpu_to_le32((priv(dev)->dma_desc_phys_addr + (i +
563 1) *
564 sizeof(priv(dev)->dma_desc[0])) | next_bits);
565
566 priv(dev)->desc_dio_buffer[i] =
567 priv(dev)->dio_buffer[buffer_index] +
568 (buffer_offset / sizeof(uint32_t));
569
570 buffer_offset += transfer_size;
571 if (transfer_size + buffer_offset > DMA_BUFFER_SIZE) {
572 buffer_offset = 0;
573 buffer_index++;
574 }
575
576 DEBUG_PRINT(" desc %i\n", i);
577 DEBUG_PRINT(" start addr virt 0x%p, phys 0x%lx\n",
578 priv(dev)->desc_dio_buffer[i],
579 (unsigned long)priv(dev)->dma_desc[i].
580 pci_start_addr);
581 DEBUG_PRINT(" next 0x%lx\n",
582 (unsigned long)priv(dev)->dma_desc[i].next);
583 }
584 priv(dev)->num_dma_descriptors = i;
585 /* fix last descriptor to point back to first */
586 priv(dev)->dma_desc[i - 1].next =
587 cpu_to_le32(priv(dev)->dma_desc_phys_addr | next_bits);
588 DEBUG_PRINT(" desc %i next fixup 0x%lx\n", i - 1,
589 (unsigned long)priv(dev)->dma_desc[i - 1].next);
590
591 priv(dev)->block_size = transfer_size;
592
593 return transfer_size;
594 }
595
596 static int hpdi_attach(struct comedi_device *dev, struct comedi_devconfig *it)
597 {
598 struct pci_dev *pcidev;
599 int i;
600 int retval;
601
602 printk(KERN_WARNING "comedi%d: gsc_hpdi\n", dev->minor);
603
604 if (alloc_private(dev, sizeof(struct hpdi_private)) < 0)
605 return -ENOMEM;
606
607 pcidev = NULL;
608 for (i = 0; i < ARRAY_SIZE(hpdi_boards) &&
609 dev->board_ptr == NULL; i++) {
610 do {
611 pcidev = pci_get_subsys(PCI_VENDOR_ID_PLX,
612 hpdi_boards[i].device_id,
613 PCI_VENDOR_ID_PLX,
614 hpdi_boards[i].subdevice_id,
615 pcidev);
616 /* was a particular bus/slot requested? */
617 if (it->options[0] || it->options[1]) {
618 /* are we on the wrong bus/slot? */
619 if (pcidev->bus->number != it->options[0] ||
620 PCI_SLOT(pcidev->devfn) != it->options[1])
621 continue;
622 }
623 if (pcidev) {
624 priv(dev)->hw_dev = pcidev;
625 dev->board_ptr = hpdi_boards + i;
626 break;
627 }
628 } while (pcidev != NULL);
629 }
630 if (dev->board_ptr == NULL) {
631 printk(KERN_WARNING "gsc_hpdi: no hpdi card found\n");
632 return -EIO;
633 }
634
635 printk(KERN_WARNING
636 "gsc_hpdi: found %s on bus %i, slot %i\n", board(dev)->name,
637 pcidev->bus->number, PCI_SLOT(pcidev->devfn));
638
639 if (comedi_pci_enable(pcidev, driver_hpdi.driver_name)) {
640 printk(KERN_WARNING
641 " failed enable PCI device and request regions\n");
642 return -EIO;
643 }
644 pci_set_master(pcidev);
645
646 /* Initialize dev->board_name */
647 dev->board_name = board(dev)->name;
648
649 priv(dev)->plx9080_phys_iobase =
650 pci_resource_start(pcidev, PLX9080_BADDRINDEX);
651 priv(dev)->hpdi_phys_iobase =
652 pci_resource_start(pcidev, HPDI_BADDRINDEX);
653
654 /* remap, won't work with 2.0 kernels but who cares */
655 priv(dev)->plx9080_iobase = ioremap(priv(dev)->plx9080_phys_iobase,
656 pci_resource_len(pcidev,
657 PLX9080_BADDRINDEX));
658 priv(dev)->hpdi_iobase =
659 ioremap(priv(dev)->hpdi_phys_iobase,
660 pci_resource_len(pcidev, HPDI_BADDRINDEX));
661 if (!priv(dev)->plx9080_iobase || !priv(dev)->hpdi_iobase) {
662 printk(KERN_WARNING " failed to remap io memory\n");
663 return -ENOMEM;
664 }
665
666 DEBUG_PRINT(" plx9080 remapped to 0x%p\n", priv(dev)->plx9080_iobase);
667 DEBUG_PRINT(" hpdi remapped to 0x%p\n", priv(dev)->hpdi_iobase);
668
669 init_plx9080(dev);
670
671 /* get irq */
672 if (request_irq(pcidev->irq, handle_interrupt, IRQF_SHARED,
673 driver_hpdi.driver_name, dev)) {
674 printk(KERN_WARNING
675 " unable to allocate irq %u\n", pcidev->irq);
676 return -EINVAL;
677 }
678 dev->irq = pcidev->irq;
679
680 printk(KERN_WARNING " irq %u\n", dev->irq);
681
682 /* alocate pci dma buffers */
683 for (i = 0; i < NUM_DMA_BUFFERS; i++) {
684 priv(dev)->dio_buffer[i] =
685 pci_alloc_consistent(priv(dev)->hw_dev, DMA_BUFFER_SIZE,
686 &priv(dev)->dio_buffer_phys_addr[i]);
687 DEBUG_PRINT("dio_buffer at virt 0x%p, phys 0x%lx\n",
688 priv(dev)->dio_buffer[i],
689 (unsigned long)priv(dev)->dio_buffer_phys_addr[i]);
690 }
691 /* allocate dma descriptors */
692 priv(dev)->dma_desc = pci_alloc_consistent(priv(dev)->hw_dev,
693 sizeof(struct plx_dma_desc) *
694 NUM_DMA_DESCRIPTORS,
695 &priv(dev)->
696 dma_desc_phys_addr);
697 if (priv(dev)->dma_desc_phys_addr & 0xf) {
698 printk(KERN_WARNING
699 " dma descriptors not quad-word aligned (bug)\n");
700 return -EIO;
701 }
702
703 retval = setup_dma_descriptors(dev, 0x1000);
704 if (retval < 0)
705 return retval;
706
707 retval = setup_subdevices(dev);
708 if (retval < 0)
709 return retval;
710
711 return init_hpdi(dev);
712 }
713
714 static int hpdi_detach(struct comedi_device *dev)
715 {
716 unsigned int i;
717
718 printk(KERN_WARNING "comedi%d: gsc_hpdi: remove\n", dev->minor);
719
720 if (dev->irq)
721 free_irq(dev->irq, dev);
722 if ((priv(dev)) && (priv(dev)->hw_dev)) {
723 if (priv(dev)->plx9080_iobase) {
724 disable_plx_interrupts(dev);
725 iounmap((void *)priv(dev)->plx9080_iobase);
726 }
727 if (priv(dev)->hpdi_iobase)
728 iounmap((void *)priv(dev)->hpdi_iobase);
729 /* free pci dma buffers */
730 for (i = 0; i < NUM_DMA_BUFFERS; i++) {
731 if (priv(dev)->dio_buffer[i])
732 pci_free_consistent(priv(dev)->hw_dev,
733 DMA_BUFFER_SIZE,
734 priv(dev)->
735 dio_buffer[i],
736 priv
737 (dev)->dio_buffer_phys_addr
738 [i]);
739 }
740 /* free dma descriptors */
741 if (priv(dev)->dma_desc)
742 pci_free_consistent(priv(dev)->hw_dev,
743 sizeof(struct plx_dma_desc)
744 * NUM_DMA_DESCRIPTORS,
745 priv(dev)->dma_desc,
746 priv(dev)->
747 dma_desc_phys_addr);
748 if (priv(dev)->hpdi_phys_iobase)
749 comedi_pci_disable(priv(dev)->hw_dev);
750 pci_dev_put(priv(dev)->hw_dev);
751 }
752 return 0;
753 }
754
755 static int dio_config_block_size(struct comedi_device *dev, unsigned int *data)
756 {
757 unsigned int requested_block_size;
758 int retval;
759
760 requested_block_size = data[1];
761
762 retval = setup_dma_descriptors(dev, requested_block_size);
763 if (retval < 0)
764 return retval;
765
766 data[1] = retval;
767
768 return 2;
769 }
770
771 static int di_cmd_test(struct comedi_device *dev, struct comedi_subdevice *s,
772 struct comedi_cmd *cmd)
773 {
774 int err = 0;
775 int tmp;
776 int i;
777
778 /* step 1: make sure trigger sources are trivially valid */
779
780 tmp = cmd->start_src;
781 cmd->start_src &= TRIG_NOW;
782 if (!cmd->start_src || tmp != cmd->start_src)
783 err++;
784
785 tmp = cmd->scan_begin_src;
786 cmd->scan_begin_src &= TRIG_EXT;
787 if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src)
788 err++;
789
790 tmp = cmd->convert_src;
791 cmd->convert_src &= TRIG_NOW;
792 if (!cmd->convert_src || tmp != cmd->convert_src)
793 err++;
794
795 tmp = cmd->scan_end_src;
796 cmd->scan_end_src &= TRIG_COUNT;
797 if (!cmd->scan_end_src || tmp != cmd->scan_end_src)
798 err++;
799
800 tmp = cmd->stop_src;
801 cmd->stop_src &= TRIG_COUNT | TRIG_NONE;
802 if (!cmd->stop_src || tmp != cmd->stop_src)
803 err++;
804
805 if (err)
806 return 1;
807
808 /* step 2: make sure trigger sources are unique and mutually
809 * compatible */
810
811 /* uniqueness check */
812 if (cmd->stop_src != TRIG_COUNT && cmd->stop_src != TRIG_NONE)
813 err++;
814
815 if (err)
816 return 2;
817
818 /* step 3: make sure arguments are trivially compatible */
819
820 if (!cmd->chanlist_len) {
821 cmd->chanlist_len = 32;
822 err++;
823 }
824 if (cmd->scan_end_arg != cmd->chanlist_len) {
825 cmd->scan_end_arg = cmd->chanlist_len;
826 err++;
827 }
828
829 switch (cmd->stop_src) {
830 case TRIG_COUNT:
831 if (!cmd->stop_arg) {
832 cmd->stop_arg = 1;
833 err++;
834 }
835 break;
836 case TRIG_NONE:
837 if (cmd->stop_arg != 0) {
838 cmd->stop_arg = 0;
839 err++;
840 }
841 break;
842 default:
843 break;
844 }
845
846 if (err)
847 return 3;
848
849 /* step 4: fix up any arguments */
850
851 if (err)
852 return 4;
853
854 if (!cmd->chanlist)
855 return 0;
856
857 for (i = 1; i < cmd->chanlist_len; i++) {
858 if (CR_CHAN(cmd->chanlist[i]) != i) {
859 comedi_error(dev,
860 "chanlist must be ch 0 to 31 in order");
861 err++;
862 break;
863 }
864 }
865
866 if (err)
867 return 5;
868
869 return 0;
870 }
871
872 static int hpdi_cmd_test(struct comedi_device *dev, struct comedi_subdevice *s,
873 struct comedi_cmd *cmd)
874 {
875 if (priv(dev)->dio_config_output)
876 return -EINVAL;
877 else
878 return di_cmd_test(dev, s, cmd);
879 }
880
881 static inline void hpdi_writel(struct comedi_device *dev, uint32_t bits,
882 unsigned int offset)
883 {
884 writel(bits | priv(dev)->bits[offset / sizeof(uint32_t)],
885 priv(dev)->hpdi_iobase + offset);
886 }
887
888 static int di_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
889 {
890 uint32_t bits;
891 unsigned long flags;
892 struct comedi_async *async = s->async;
893 struct comedi_cmd *cmd = &async->cmd;
894
895 hpdi_writel(dev, RX_FIFO_RESET_BIT, BOARD_CONTROL_REG);
896
897 DEBUG_PRINT("hpdi: in di_cmd\n");
898
899 abort_dma(dev, 0);
900
901 priv(dev)->dma_desc_index = 0;
902
903 /* These register are supposedly unused during chained dma,
904 * but I have found that left over values from last operation
905 * occasionally cause problems with transfer of first dma
906 * block. Initializing them to zero seems to fix the problem. */
907 writel(0, priv(dev)->plx9080_iobase + PLX_DMA0_TRANSFER_SIZE_REG);
908 writel(0, priv(dev)->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG);
909 writel(0, priv(dev)->plx9080_iobase + PLX_DMA0_LOCAL_ADDRESS_REG);
910 /* give location of first dma descriptor */
911 bits =
912 priv(dev)->dma_desc_phys_addr | PLX_DESC_IN_PCI_BIT |
913 PLX_INTR_TERM_COUNT | PLX_XFER_LOCAL_TO_PCI;
914 writel(bits, priv(dev)->plx9080_iobase + PLX_DMA0_DESCRIPTOR_REG);
915
916 /* spinlock for plx dma control/status reg */
917 spin_lock_irqsave(&dev->spinlock, flags);
918 /* enable dma transfer */
919 writeb(PLX_DMA_EN_BIT | PLX_DMA_START_BIT | PLX_CLEAR_DMA_INTR_BIT,
920 priv(dev)->plx9080_iobase + PLX_DMA0_CS_REG);
921 spin_unlock_irqrestore(&dev->spinlock, flags);
922
923 if (cmd->stop_src == TRIG_COUNT)
924 priv(dev)->dio_count = cmd->stop_arg;
925 else
926 priv(dev)->dio_count = 1;
927
928 /* clear over/under run status flags */
929 writel(RX_UNDERRUN_BIT | RX_OVERRUN_BIT,
930 priv(dev)->hpdi_iobase + BOARD_STATUS_REG);
931 /* enable interrupts */
932 writel(intr_bit(RX_FULL_INTR),
933 priv(dev)->hpdi_iobase + INTERRUPT_CONTROL_REG);
934
935 DEBUG_PRINT("hpdi: starting rx\n");
936 hpdi_writel(dev, RX_ENABLE_BIT, BOARD_CONTROL_REG);
937
938 return 0;
939 }
940
941 static int hpdi_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
942 {
943 if (priv(dev)->dio_config_output)
944 return -EINVAL;
945 else
946 return di_cmd(dev, s);
947 }
948
949 static void drain_dma_buffers(struct comedi_device *dev, unsigned int channel)
950 {
951 struct comedi_async *async = dev->read_subdev->async;
952 uint32_t next_transfer_addr;
953 int j;
954 int num_samples = 0;
955 void *pci_addr_reg;
956
957 if (channel)
958 pci_addr_reg =
959 priv(dev)->plx9080_iobase + PLX_DMA1_PCI_ADDRESS_REG;
960 else
961 pci_addr_reg =
962 priv(dev)->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG;
963
964 /* loop until we have read all the full buffers */
965 j = 0;
966 for (next_transfer_addr = readl(pci_addr_reg);
967 (next_transfer_addr <
968 le32_to_cpu(priv(dev)->dma_desc[priv(dev)->dma_desc_index].
969 pci_start_addr)
970 || next_transfer_addr >=
971 le32_to_cpu(priv(dev)->dma_desc[priv(dev)->dma_desc_index].
972 pci_start_addr) + priv(dev)->block_size)
973 && j < priv(dev)->num_dma_descriptors; j++) {
974 /* transfer data from dma buffer to comedi buffer */
975 num_samples = priv(dev)->block_size / sizeof(uint32_t);
976 if (async->cmd.stop_src == TRIG_COUNT) {
977 if (num_samples > priv(dev)->dio_count)
978 num_samples = priv(dev)->dio_count;
979 priv(dev)->dio_count -= num_samples;
980 }
981 cfc_write_array_to_buffer(dev->read_subdev,
982 priv(dev)->desc_dio_buffer[priv(dev)->
983 dma_desc_index],
984 num_samples * sizeof(uint32_t));
985 priv(dev)->dma_desc_index++;
986 priv(dev)->dma_desc_index %= priv(dev)->num_dma_descriptors;
987
988 DEBUG_PRINT("next desc addr 0x%lx\n", (unsigned long)
989 priv(dev)->dma_desc[priv(dev)->dma_desc_index].
990 next);
991 DEBUG_PRINT("pci addr reg 0x%x\n", next_transfer_addr);
992 }
993 }
994
995 static irqreturn_t handle_interrupt(int irq, void *d)
996 {
997 struct comedi_device *dev = d;
998 struct comedi_subdevice *s = dev->read_subdev;
999 struct comedi_async *async = s->async;
1000 uint32_t hpdi_intr_status, hpdi_board_status;
1001 uint32_t plx_status;
1002 uint32_t plx_bits;
1003 uint8_t dma0_status, dma1_status;
1004 unsigned long flags;
1005
1006 if (!dev->attached)
1007 return IRQ_NONE;
1008
1009 plx_status = readl(priv(dev)->plx9080_iobase + PLX_INTRCS_REG);
1010 if ((plx_status & (ICS_DMA0_A | ICS_DMA1_A | ICS_LIA)) == 0)
1011 return IRQ_NONE;
1012
1013 hpdi_intr_status = readl(priv(dev)->hpdi_iobase + INTERRUPT_STATUS_REG);
1014 hpdi_board_status = readl(priv(dev)->hpdi_iobase + BOARD_STATUS_REG);
1015
1016 async->events = 0;
1017
1018 if (hpdi_intr_status) {
1019 DEBUG_PRINT("hpdi: intr status 0x%x, ", hpdi_intr_status);
1020 writel(hpdi_intr_status,
1021 priv(dev)->hpdi_iobase + INTERRUPT_STATUS_REG);
1022 }
1023 /* spin lock makes sure noone else changes plx dma control reg */
1024 spin_lock_irqsave(&dev->spinlock, flags);
1025 dma0_status = readb(priv(dev)->plx9080_iobase + PLX_DMA0_CS_REG);
1026 if (plx_status & ICS_DMA0_A) { /* dma chan 0 interrupt */
1027 writeb((dma0_status & PLX_DMA_EN_BIT) | PLX_CLEAR_DMA_INTR_BIT,
1028 priv(dev)->plx9080_iobase + PLX_DMA0_CS_REG);
1029
1030 DEBUG_PRINT("dma0 status 0x%x\n", dma0_status);
1031 if (dma0_status & PLX_DMA_EN_BIT)
1032 drain_dma_buffers(dev, 0);
1033 DEBUG_PRINT(" cleared dma ch0 interrupt\n");
1034 }
1035 spin_unlock_irqrestore(&dev->spinlock, flags);
1036
1037 /* spin lock makes sure noone else changes plx dma control reg */
1038 spin_lock_irqsave(&dev->spinlock, flags);
1039 dma1_status = readb(priv(dev)->plx9080_iobase + PLX_DMA1_CS_REG);
1040 if (plx_status & ICS_DMA1_A) {/* dma chan 1 interrupt */
1041 writeb((dma1_status & PLX_DMA_EN_BIT) | PLX_CLEAR_DMA_INTR_BIT,
1042 priv(dev)->plx9080_iobase + PLX_DMA1_CS_REG);
1043 DEBUG_PRINT("dma1 status 0x%x\n", dma1_status);
1044
1045 DEBUG_PRINT(" cleared dma ch1 interrupt\n");
1046 }
1047 spin_unlock_irqrestore(&dev->spinlock, flags);
1048
1049 /* clear possible plx9080 interrupt sources */
1050 if (plx_status & ICS_LDIA) { /* clear local doorbell interrupt */
1051 plx_bits = readl(priv(dev)->plx9080_iobase + PLX_DBR_OUT_REG);
1052 writel(plx_bits, priv(dev)->plx9080_iobase + PLX_DBR_OUT_REG);
1053 DEBUG_PRINT(" cleared local doorbell bits 0x%x\n", plx_bits);
1054 }
1055
1056 if (hpdi_board_status & RX_OVERRUN_BIT) {
1057 comedi_error(dev, "rx fifo overrun");
1058 async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
1059 DEBUG_PRINT("dma0_status 0x%x\n",
1060 (int)readb(priv(dev)->plx9080_iobase +
1061 PLX_DMA0_CS_REG));
1062 }
1063
1064 if (hpdi_board_status & RX_UNDERRUN_BIT) {
1065 comedi_error(dev, "rx fifo underrun");
1066 async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
1067 }
1068
1069 if (priv(dev)->dio_count == 0)
1070 async->events |= COMEDI_CB_EOA;
1071
1072 DEBUG_PRINT("board status 0x%x, ", hpdi_board_status);
1073 DEBUG_PRINT("plx status 0x%x\n", plx_status);
1074 if (async->events)
1075 DEBUG_PRINT(" events 0x%x\n", async->events);
1076
1077 cfc_handle_events(dev, s);
1078
1079 return IRQ_HANDLED;
1080 }
1081
1082 static void abort_dma(struct comedi_device *dev, unsigned int channel)
1083 {
1084 unsigned long flags;
1085
1086 /* spinlock for plx dma control/status reg */
1087 spin_lock_irqsave(&dev->spinlock, flags);
1088
1089 plx9080_abort_dma(priv(dev)->plx9080_iobase, channel);
1090
1091 spin_unlock_irqrestore(&dev->spinlock, flags);
1092 }
1093
1094 static int hpdi_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
1095 {
1096 hpdi_writel(dev, 0, BOARD_CONTROL_REG);
1097
1098 writel(0, priv(dev)->hpdi_iobase + INTERRUPT_CONTROL_REG);
1099
1100 abort_dma(dev, 0);
1101
1102 return 0;
1103 }
1104
1105 MODULE_AUTHOR("Comedi http://www.comedi.org");
1106 MODULE_DESCRIPTION("Comedi low-level driver");
1107 MODULE_LICENSE("GPL");
Tomato firmware and modifications.