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GUI: Fix Tomato RAF theme for all builds. Compilation typo.
[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / drivers / serial / netx-serial.c
blob558a2de0d032b1988ab88b97a3eb83f3f7124e37
1 /*
2 * drivers/serial/netx-serial.c
3 *
4 * Copyright (c) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2
8 * as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20 #if defined(CONFIG_SERIAL_NETX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
21 #define SUPPORT_SYSRQ
22 #endif
23
24 #include <linux/device.h>
25 #include <linux/module.h>
26 #include <linux/ioport.h>
27 #include <linux/init.h>
28 #include <linux/console.h>
29 #include <linux/sysrq.h>
30 #include <linux/platform_device.h>
31 #include <linux/tty.h>
32 #include <linux/tty_flip.h>
33 #include <linux/serial_core.h>
34 #include <linux/serial.h>
35
36 #include <asm/io.h>
37 #include <asm/irq.h>
38 #include <mach/hardware.h>
39 #include <mach/netx-regs.h>
40
41 /* We've been assigned a range on the "Low-density serial ports" major */
42 #define SERIAL_NX_MAJOR 204
43 #define MINOR_START 170
44
45 enum uart_regs {
46 UART_DR = 0x00,
47 UART_SR = 0x04,
48 UART_LINE_CR = 0x08,
49 UART_BAUDDIV_MSB = 0x0c,
50 UART_BAUDDIV_LSB = 0x10,
51 UART_CR = 0x14,
52 UART_FR = 0x18,
53 UART_IIR = 0x1c,
54 UART_ILPR = 0x20,
55 UART_RTS_CR = 0x24,
56 UART_RTS_LEAD = 0x28,
57 UART_RTS_TRAIL = 0x2c,
58 UART_DRV_ENABLE = 0x30,
59 UART_BRM_CR = 0x34,
60 UART_RXFIFO_IRQLEVEL = 0x38,
61 UART_TXFIFO_IRQLEVEL = 0x3c,
62 };
63
64 #define SR_FE (1<<0)
65 #define SR_PE (1<<1)
66 #define SR_BE (1<<2)
67 #define SR_OE (1<<3)
68
69 #define LINE_CR_BRK (1<<0)
70 #define LINE_CR_PEN (1<<1)
71 #define LINE_CR_EPS (1<<2)
72 #define LINE_CR_STP2 (1<<3)
73 #define LINE_CR_FEN (1<<4)
74 #define LINE_CR_5BIT (0<<5)
75 #define LINE_CR_6BIT (1<<5)
76 #define LINE_CR_7BIT (2<<5)
77 #define LINE_CR_8BIT (3<<5)
78 #define LINE_CR_BITS_MASK (3<<5)
79
80 #define CR_UART_EN (1<<0)
81 #define CR_SIREN (1<<1)
82 #define CR_SIRLP (1<<2)
83 #define CR_MSIE (1<<3)
84 #define CR_RIE (1<<4)
85 #define CR_TIE (1<<5)
86 #define CR_RTIE (1<<6)
87 #define CR_LBE (1<<7)
88
89 #define FR_CTS (1<<0)
90 #define FR_DSR (1<<1)
91 #define FR_DCD (1<<2)
92 #define FR_BUSY (1<<3)
93 #define FR_RXFE (1<<4)
94 #define FR_TXFF (1<<5)
95 #define FR_RXFF (1<<6)
96 #define FR_TXFE (1<<7)
97
98 #define IIR_MIS (1<<0)
99 #define IIR_RIS (1<<1)
100 #define IIR_TIS (1<<2)
101 #define IIR_RTIS (1<<3)
102 #define IIR_MASK 0xf
103
104 #define RTS_CR_AUTO (1<<0)
105 #define RTS_CR_RTS (1<<1)
106 #define RTS_CR_COUNT (1<<2)
107 #define RTS_CR_MOD2 (1<<3)
108 #define RTS_CR_RTS_POL (1<<4)
109 #define RTS_CR_CTS_CTR (1<<5)
110 #define RTS_CR_CTS_POL (1<<6)
111 #define RTS_CR_STICK (1<<7)
112
113 #define UART_PORT_SIZE 0x40
114 #define DRIVER_NAME "netx-uart"
115
116 struct netx_port {
117 struct uart_port port;
118 };
119
120 static void netx_stop_tx(struct uart_port *port)
121 {
122 unsigned int val;
123 val = readl(port->membase + UART_CR);
124 writel(val & ~CR_TIE, port->membase + UART_CR);
125 }
126
127 static void netx_stop_rx(struct uart_port *port)
128 {
129 unsigned int val;
130 val = readl(port->membase + UART_CR);
131 writel(val & ~CR_RIE, port->membase + UART_CR);
132 }
133
134 static void netx_enable_ms(struct uart_port *port)
135 {
136 unsigned int val;
137 val = readl(port->membase + UART_CR);
138 writel(val | CR_MSIE, port->membase + UART_CR);
139 }
140
141 static inline void netx_transmit_buffer(struct uart_port *port)
142 {
143 struct circ_buf *xmit = &port->state->xmit;
144
145 if (port->x_char) {
146 writel(port->x_char, port->membase + UART_DR);
147 port->icount.tx++;
148 port->x_char = 0;
149 return;
150 }
151
152 if (uart_tx_stopped(port) || uart_circ_empty(xmit)) {
153 netx_stop_tx(port);
154 return;
155 }
156
157 do {
158 /* send xmit->buf[xmit->tail]
159 * out the port here */
160 writel(xmit->buf[xmit->tail], port->membase + UART_DR);
161 xmit->tail = (xmit->tail + 1) &
162 (UART_XMIT_SIZE - 1);
163 port->icount.tx++;
164 if (uart_circ_empty(xmit))
165 break;
166 } while (!(readl(port->membase + UART_FR) & FR_TXFF));
167
168 if (uart_circ_empty(xmit))
169 netx_stop_tx(port);
170 }
171
172 static void netx_start_tx(struct uart_port *port)
173 {
174 writel(
175 readl(port->membase + UART_CR) | CR_TIE, port->membase + UART_CR);
176
177 if (!(readl(port->membase + UART_FR) & FR_TXFF))
178 netx_transmit_buffer(port);
179 }
180
181 static unsigned int netx_tx_empty(struct uart_port *port)
182 {
183 return readl(port->membase + UART_FR) & FR_BUSY ? 0 : TIOCSER_TEMT;
184 }
185
186 static void netx_txint(struct uart_port *port)
187 {
188 struct circ_buf *xmit = &port->state->xmit;
189
190 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
191 netx_stop_tx(port);
192 return;
193 }
194
195 netx_transmit_buffer(port);
196
197 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
198 uart_write_wakeup(port);
199 }
200
201 static void netx_rxint(struct uart_port *port)
202 {
203 unsigned char rx, flg, status;
204 struct tty_struct *tty = port->state->port.tty;
205
206 while (!(readl(port->membase + UART_FR) & FR_RXFE)) {
207 rx = readl(port->membase + UART_DR);
208 flg = TTY_NORMAL;
209 port->icount.rx++;
210 status = readl(port->membase + UART_SR);
211 if (status & SR_BE) {
212 writel(0, port->membase + UART_SR);
213 if (uart_handle_break(port))
214 continue;
215 }
216
217 if (unlikely(status & (SR_FE | SR_PE | SR_OE))) {
218
219 if (status & SR_PE)
220 port->icount.parity++;
221 else if (status & SR_FE)
222 port->icount.frame++;
223 if (status & SR_OE)
224 port->icount.overrun++;
225
226 status &= port->read_status_mask;
227
228 if (status & SR_BE)
229 flg = TTY_BREAK;
230 else if (status & SR_PE)
231 flg = TTY_PARITY;
232 else if (status & SR_FE)
233 flg = TTY_FRAME;
234 }
235
236 if (uart_handle_sysrq_char(port, rx))
237 continue;
238
239 uart_insert_char(port, status, SR_OE, rx, flg);
240 }
241
242 tty_flip_buffer_push(tty);
243 return;
244 }
245
246 static irqreturn_t netx_int(int irq, void *dev_id)
247 {
248 struct uart_port *port = dev_id;
249 unsigned long flags;
250 unsigned char status;
251
252 spin_lock_irqsave(&port->lock,flags);
253
254 status = readl(port->membase + UART_IIR) & IIR_MASK;
255 while (status) {
256 if (status & IIR_RIS)
257 netx_rxint(port);
258 if (status & IIR_TIS)
259 netx_txint(port);
260 if (status & IIR_MIS) {
261 if (readl(port->membase + UART_FR) & FR_CTS)
262 uart_handle_cts_change(port, 1);
263 else
264 uart_handle_cts_change(port, 0);
265 }
266 writel(0, port->membase + UART_IIR);
267 status = readl(port->membase + UART_IIR) & IIR_MASK;
268 }
269
270 spin_unlock_irqrestore(&port->lock,flags);
271 return IRQ_HANDLED;
272 }
273
274 static unsigned int netx_get_mctrl(struct uart_port *port)
275 {
276 unsigned int ret = TIOCM_DSR | TIOCM_CAR;
277
278 if (readl(port->membase + UART_FR) & FR_CTS)
279 ret |= TIOCM_CTS;
280
281 return ret;
282 }
283
284 static void netx_set_mctrl(struct uart_port *port, unsigned int mctrl)
285 {
286 unsigned int val;
287
288 if (mctrl & TIOCM_RTS) {
289 val = readl(port->membase + UART_RTS_CR);
290 writel(val | RTS_CR_RTS, port->membase + UART_RTS_CR);
291 }
292 }
293
294 static void netx_break_ctl(struct uart_port *port, int break_state)
295 {
296 unsigned int line_cr;
297 spin_lock_irq(&port->lock);
298
299 line_cr = readl(port->membase + UART_LINE_CR);
300 if (break_state != 0)
301 line_cr |= LINE_CR_BRK;
302 else
303 line_cr &= ~LINE_CR_BRK;
304 writel(line_cr, port->membase + UART_LINE_CR);
305
306 spin_unlock_irq(&port->lock);
307 }
308
309 static int netx_startup(struct uart_port *port)
310 {
311 int ret;
312
313 ret = request_irq(port->irq, netx_int, 0,
314 DRIVER_NAME, port);
315 if (ret) {
316 dev_err(port->dev, "unable to grab irq%d\n",port->irq);
317 goto exit;
318 }
319
320 writel(readl(port->membase + UART_LINE_CR) | LINE_CR_FEN,
321 port->membase + UART_LINE_CR);
322
323 writel(CR_MSIE | CR_RIE | CR_TIE | CR_RTIE | CR_UART_EN,
324 port->membase + UART_CR);
325
326 exit:
327 return ret;
328 }
329
330 static void netx_shutdown(struct uart_port *port)
331 {
332 writel(0, port->membase + UART_CR) ;
333
334 free_irq(port->irq, port);
335 }
336
337 static void
338 netx_set_termios(struct uart_port *port, struct ktermios *termios,
339 struct ktermios *old)
340 {
341 unsigned int baud, quot;
342 unsigned char old_cr;
343 unsigned char line_cr = LINE_CR_FEN;
344 unsigned char rts_cr = 0;
345
346 switch (termios->c_cflag & CSIZE) {
347 case CS5:
348 line_cr |= LINE_CR_5BIT;
349 break;
350 case CS6:
351 line_cr |= LINE_CR_6BIT;
352 break;
353 case CS7:
354 line_cr |= LINE_CR_7BIT;
355 break;
356 case CS8:
357 line_cr |= LINE_CR_8BIT;
358 break;
359 }
360
361 if (termios->c_cflag & CSTOPB)
362 line_cr |= LINE_CR_STP2;
363
364 if (termios->c_cflag & PARENB) {
365 line_cr |= LINE_CR_PEN;
366 if (!(termios->c_cflag & PARODD))
367 line_cr |= LINE_CR_EPS;
368 }
369
370 if (termios->c_cflag & CRTSCTS)
371 rts_cr = RTS_CR_AUTO | RTS_CR_CTS_CTR | RTS_CR_RTS_POL;
372
373 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
374 quot = baud * 4096;
375 quot /= 1000;
376 quot *= 256;
377 quot /= 100000;
378
379 spin_lock_irq(&port->lock);
380
381 uart_update_timeout(port, termios->c_cflag, baud);
382
383 old_cr = readl(port->membase + UART_CR);
384
385 /* disable interrupts */
386 writel(old_cr & ~(CR_MSIE | CR_RIE | CR_TIE | CR_RTIE),
387 port->membase + UART_CR);
388
389 /* drain transmitter */
390 while (readl(port->membase + UART_FR) & FR_BUSY);
391
392 /* disable UART */
393 writel(old_cr & ~CR_UART_EN, port->membase + UART_CR);
394
395 /* modem status interrupts */
396 old_cr &= ~CR_MSIE;
397 if (UART_ENABLE_MS(port, termios->c_cflag))
398 old_cr |= CR_MSIE;
399
400 writel((quot>>8) & 0xff, port->membase + UART_BAUDDIV_MSB);
401 writel(quot & 0xff, port->membase + UART_BAUDDIV_LSB);
402 writel(line_cr, port->membase + UART_LINE_CR);
403
404 writel(rts_cr, port->membase + UART_RTS_CR);
405
406 /*
407 * Characters to ignore
408 */
409 port->ignore_status_mask = 0;
410 if (termios->c_iflag & IGNPAR)
411 port->ignore_status_mask |= SR_PE;
412 if (termios->c_iflag & IGNBRK) {
413 port->ignore_status_mask |= SR_BE;
414 /*
415 * If we're ignoring parity and break indicators,
416 * ignore overruns too (for real raw support).
417 */
418 if (termios->c_iflag & IGNPAR)
419 port->ignore_status_mask |= SR_PE;
420 }
421
422 port->read_status_mask = 0;
423 if (termios->c_iflag & (BRKINT | PARMRK))
424 port->read_status_mask |= SR_BE;
425 if (termios->c_iflag & INPCK)
426 port->read_status_mask |= SR_PE | SR_FE;
427
428 writel(old_cr, port->membase + UART_CR);
429
430 spin_unlock_irq(&port->lock);
431 }
432
433 static const char *netx_type(struct uart_port *port)
434 {
435 return port->type == PORT_NETX ? "NETX" : NULL;
436 }
437
438 static void netx_release_port(struct uart_port *port)
439 {
440 release_mem_region(port->mapbase, UART_PORT_SIZE);
441 }
442
443 static int netx_request_port(struct uart_port *port)
444 {
445 return request_mem_region(port->mapbase, UART_PORT_SIZE,
446 DRIVER_NAME) != NULL ? 0 : -EBUSY;
447 }
448
449 static void netx_config_port(struct uart_port *port, int flags)
450 {
451 if (flags & UART_CONFIG_TYPE && netx_request_port(port) == 0)
452 port->type = PORT_NETX;
453 }
454
455 static int
456 netx_verify_port(struct uart_port *port, struct serial_struct *ser)
457 {
458 int ret = 0;
459
460 if (ser->type != PORT_UNKNOWN && ser->type != PORT_NETX)
461 ret = -EINVAL;
462
463 return ret;
464 }
465
466 static struct uart_ops netx_pops = {
467 .tx_empty = netx_tx_empty,
468 .set_mctrl = netx_set_mctrl,
469 .get_mctrl = netx_get_mctrl,
470 .stop_tx = netx_stop_tx,
471 .start_tx = netx_start_tx,
472 .stop_rx = netx_stop_rx,
473 .enable_ms = netx_enable_ms,
474 .break_ctl = netx_break_ctl,
475 .startup = netx_startup,
476 .shutdown = netx_shutdown,
477 .set_termios = netx_set_termios,
478 .type = netx_type,
479 .release_port = netx_release_port,
480 .request_port = netx_request_port,
481 .config_port = netx_config_port,
482 .verify_port = netx_verify_port,
483 };
484
485 static struct netx_port netx_ports[] = {
486 {
487 .port = {
488 .type = PORT_NETX,
489 .iotype = UPIO_MEM,
490 .membase = (char __iomem *)io_p2v(NETX_PA_UART0),
491 .mapbase = NETX_PA_UART0,
492 .irq = NETX_IRQ_UART0,
493 .uartclk = 100000000,
494 .fifosize = 16,
495 .flags = UPF_BOOT_AUTOCONF,
496 .ops = &netx_pops,
497 .line = 0,
498 },
499 }, {
500 .port = {
501 .type = PORT_NETX,
502 .iotype = UPIO_MEM,
503 .membase = (char __iomem *)io_p2v(NETX_PA_UART1),
504 .mapbase = NETX_PA_UART1,
505 .irq = NETX_IRQ_UART1,
506 .uartclk = 100000000,
507 .fifosize = 16,
508 .flags = UPF_BOOT_AUTOCONF,
509 .ops = &netx_pops,
510 .line = 1,
511 },
512 }, {
513 .port = {
514 .type = PORT_NETX,
515 .iotype = UPIO_MEM,
516 .membase = (char __iomem *)io_p2v(NETX_PA_UART2),
517 .mapbase = NETX_PA_UART2,
518 .irq = NETX_IRQ_UART2,
519 .uartclk = 100000000,
520 .fifosize = 16,
521 .flags = UPF_BOOT_AUTOCONF,
522 .ops = &netx_pops,
523 .line = 2,
524 },
525 }
526 };
527
528 #ifdef CONFIG_SERIAL_NETX_CONSOLE
529
530 static void netx_console_putchar(struct uart_port *port, int ch)
531 {
532 while (readl(port->membase + UART_FR) & FR_BUSY);
533 writel(ch, port->membase + UART_DR);
534 }
535
536 static void
537 netx_console_write(struct console *co, const char *s, unsigned int count)
538 {
539 struct uart_port *port = &netx_ports[co->index].port;
540 unsigned char cr_save;
541
542 cr_save = readl(port->membase + UART_CR);
543 writel(cr_save | CR_UART_EN, port->membase + UART_CR);
544
545 uart_console_write(port, s, count, netx_console_putchar);
546
547 while (readl(port->membase + UART_FR) & FR_BUSY);
548 writel(cr_save, port->membase + UART_CR);
549 }
550
551 static void __init
552 netx_console_get_options(struct uart_port *port, int *baud,
553 int *parity, int *bits, int *flow)
554 {
555 unsigned char line_cr;
556
557 *baud = (readl(port->membase + UART_BAUDDIV_MSB) << 8) |
558 readl(port->membase + UART_BAUDDIV_LSB);
559 *baud *= 1000;
560 *baud /= 4096;
561 *baud *= 1000;
562 *baud /= 256;
563 *baud *= 100;
564
565 line_cr = readl(port->membase + UART_LINE_CR);
566 *parity = 'n';
567 if (line_cr & LINE_CR_PEN) {
568 if (line_cr & LINE_CR_EPS)
569 *parity = 'e';
570 else
571 *parity = 'o';
572 }
573
574 switch (line_cr & LINE_CR_BITS_MASK) {
575 case LINE_CR_8BIT:
576 *bits = 8;
577 break;
578 case LINE_CR_7BIT:
579 *bits = 7;
580 break;
581 case LINE_CR_6BIT:
582 *bits = 6;
583 break;
584 case LINE_CR_5BIT:
585 *bits = 5;
586 break;
587 }
588
589 if (readl(port->membase + UART_RTS_CR) & RTS_CR_AUTO)
590 *flow = 'r';
591 }
592
593 static int __init
594 netx_console_setup(struct console *co, char *options)
595 {
596 struct netx_port *sport;
597 int baud = 9600;
598 int bits = 8;
599 int parity = 'n';
600 int flow = 'n';
601
602 /*
603 * Check whether an invalid uart number has been specified, and
604 * if so, search for the first available port that does have
605 * console support.
606 */
607 if (co->index == -1 || co->index >= ARRAY_SIZE(netx_ports))
608 co->index = 0;
609 sport = &netx_ports[co->index];
610
611 if (options) {
612 uart_parse_options(options, &baud, &parity, &bits, &flow);
613 } else {
614 /* if the UART is enabled, assume it has been correctly setup
615 * by the bootloader and get the options
616 */
617 if (readl(sport->port.membase + UART_CR) & CR_UART_EN) {
618 netx_console_get_options(&sport->port, &baud,
619 &parity, &bits, &flow);
620 }
621
622 }
623
624 return uart_set_options(&sport->port, co, baud, parity, bits, flow);
625 }
626
627 static struct uart_driver netx_reg;
628 static struct console netx_console = {
629 .name = "ttyNX",
630 .write = netx_console_write,
631 .device = uart_console_device,
632 .setup = netx_console_setup,
633 .flags = CON_PRINTBUFFER,
634 .index = -1,
635 .data = &netx_reg,
636 };
637
638 static int __init netx_console_init(void)
639 {
640 register_console(&netx_console);
641 return 0;
642 }
643 console_initcall(netx_console_init);
644
645 #define NETX_CONSOLE &netx_console
646 #else
647 #define NETX_CONSOLE NULL
648 #endif
649
650 static struct uart_driver netx_reg = {
651 .owner = THIS_MODULE,
652 .driver_name = DRIVER_NAME,
653 .dev_name = "ttyNX",
654 .major = SERIAL_NX_MAJOR,
655 .minor = MINOR_START,
656 .nr = ARRAY_SIZE(netx_ports),
657 .cons = NETX_CONSOLE,
658 };
659
660 static int serial_netx_suspend(struct platform_device *pdev, pm_message_t state)
661 {
662 struct netx_port *sport = platform_get_drvdata(pdev);
663
664 if (sport)
665 uart_suspend_port(&netx_reg, &sport->port);
666
667 return 0;
668 }
669
670 static int serial_netx_resume(struct platform_device *pdev)
671 {
672 struct netx_port *sport = platform_get_drvdata(pdev);
673
674 if (sport)
675 uart_resume_port(&netx_reg, &sport->port);
676
677 return 0;
678 }
679
680 static int serial_netx_probe(struct platform_device *pdev)
681 {
682 struct uart_port *port = &netx_ports[pdev->id].port;
683
684 dev_info(&pdev->dev, "initialising\n");
685
686 port->dev = &pdev->dev;
687
688 writel(1, port->membase + UART_RXFIFO_IRQLEVEL);
689 uart_add_one_port(&netx_reg, &netx_ports[pdev->id].port);
690 platform_set_drvdata(pdev, &netx_ports[pdev->id]);
691
692 return 0;
693 }
694
695 static int serial_netx_remove(struct platform_device *pdev)
696 {
697 struct netx_port *sport = platform_get_drvdata(pdev);
698
699 platform_set_drvdata(pdev, NULL);
700
701 if (sport)
702 uart_remove_one_port(&netx_reg, &sport->port);
703
704 return 0;
705 }
706
707 static struct platform_driver serial_netx_driver = {
708 .probe = serial_netx_probe,
709 .remove = serial_netx_remove,
710
711 .suspend = serial_netx_suspend,
712 .resume = serial_netx_resume,
713
714 .driver = {
715 .name = DRIVER_NAME,
716 .owner = THIS_MODULE,
717 },
718 };
719
720 static int __init netx_serial_init(void)
721 {
722 int ret;
723
724 printk(KERN_INFO "Serial: NetX driver\n");
725
726 ret = uart_register_driver(&netx_reg);
727 if (ret)
728 return ret;
729
730 ret = platform_driver_register(&serial_netx_driver);
731 if (ret != 0)
732 uart_unregister_driver(&netx_reg);
733
734 return 0;
735 }
736
737 static void __exit netx_serial_exit(void)
738 {
739 platform_driver_unregister(&serial_netx_driver);
740 uart_unregister_driver(&netx_reg);
741 }
742
743 module_init(netx_serial_init);
744 module_exit(netx_serial_exit);
745
746 MODULE_AUTHOR("Sascha Hauer");
747 MODULE_DESCRIPTION("NetX serial port driver");
748 MODULE_LICENSE("GPL");
749 MODULE_ALIAS("platform:" DRIVER_NAME);
Tomato firmware and modifications.