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GUI: Fix Tomato RAF theme for all builds. Compilation typo.
[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / drivers / serial / crisv10.c
blob3af8d836a26cfedb518e6a7ecdd46f49dc575e55
1 /*
2 * Serial port driver for the ETRAX 100LX chip
3 *
4 * Copyright (C) 1998-2007 Axis Communications AB
5 *
6 * Many, many authors. Based once upon a time on serial.c for 16x50.
7 *
8 */
9
10 static char *serial_version = "$Revision: 1.25 $";
11
12 #include <linux/types.h>
13 #include <linux/errno.h>
14 #include <linux/signal.h>
15 #include <linux/sched.h>
16 #include <linux/timer.h>
17 #include <linux/interrupt.h>
18 #include <linux/tty.h>
19 #include <linux/tty_flip.h>
20 #include <linux/major.h>
21 #include <linux/smp_lock.h>
22 #include <linux/string.h>
23 #include <linux/fcntl.h>
24 #include <linux/mm.h>
25 #include <linux/slab.h>
26 #include <linux/init.h>
27 #include <linux/kernel.h>
28 #include <linux/mutex.h>
29 #include <linux/bitops.h>
30 #include <linux/seq_file.h>
31 #include <linux/delay.h>
32 #include <linux/module.h>
33 #include <linux/uaccess.h>
34 #include <linux/io.h>
35
36 #include <asm/irq.h>
37 #include <asm/dma.h>
38 #include <asm/system.h>
39
40 #include <arch/svinto.h>
41
42 /* non-arch dependent serial structures are in linux/serial.h */
43 #include <linux/serial.h>
44 /* while we keep our own stuff (struct e100_serial) in a local .h file */
45 #include "crisv10.h"
46 #include <asm/fasttimer.h>
47 #include <arch/io_interface_mux.h>
48
49 #ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER
50 #ifndef CONFIG_ETRAX_FAST_TIMER
51 #error "Enable FAST_TIMER to use SERIAL_FAST_TIMER"
52 #endif
53 #endif
54
55 #if defined(CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS) && \
56 (CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS == 0)
57 #error "RX_TIMEOUT_TICKS == 0 not allowed, use 1"
58 #endif
59
60 #if defined(CONFIG_ETRAX_RS485_ON_PA) && defined(CONFIG_ETRAX_RS485_ON_PORT_G)
61 #error "Disable either CONFIG_ETRAX_RS485_ON_PA or CONFIG_ETRAX_RS485_ON_PORT_G"
62 #endif
63
64 /*
65 * All of the compatibilty code so we can compile serial.c against
66 * older kernels is hidden in serial_compat.h
67 */
68 #if defined(LOCAL_HEADERS)
69 #include "serial_compat.h"
70 #endif
71
72 struct tty_driver *serial_driver;
73
74 /* number of characters left in xmit buffer before we ask for more */
75 #define WAKEUP_CHARS 256
76
77 //#define SERIAL_DEBUG_INTR
78 //#define SERIAL_DEBUG_OPEN
79 //#define SERIAL_DEBUG_FLOW
80 //#define SERIAL_DEBUG_DATA
81 //#define SERIAL_DEBUG_THROTTLE
82 //#define SERIAL_DEBUG_IO /* Debug for Extra control and status pins */
83 //#define SERIAL_DEBUG_LINE 0 /* What serport we want to debug */
84
85 /* Enable this to use serial interrupts to handle when you
86 expect the first received event on the serial port to
87 be an error, break or similar. Used to be able to flash IRMA
88 from eLinux */
89 #define SERIAL_HANDLE_EARLY_ERRORS
90
91 /* Currently 16 descriptors x 128 bytes = 2048 bytes */
92 #define SERIAL_DESCR_BUF_SIZE 256
93
94 #define SERIAL_PRESCALE_BASE 3125000 /* 3.125MHz */
95 #define DEF_BAUD_BASE SERIAL_PRESCALE_BASE
96
97 /* We don't want to load the system with massive fast timer interrupt
98 * on high baudrates so limit it to 250 us (4kHz) */
99 #define MIN_FLUSH_TIME_USEC 250
100
101 /* Add an x here to log a lot of timer stuff */
102 #define TIMERD(x)
103 /* Debug details of interrupt handling */
104 #define DINTR1(x) /* irq on/off, errors */
105 #define DINTR2(x) /* tx and rx */
106 /* Debug flip buffer stuff */
107 #define DFLIP(x)
108 /* Debug flow control and overview of data flow */
109 #define DFLOW(x)
110 #define DBAUD(x)
111 #define DLOG_INT_TRIG(x)
112
113 //#define DEBUG_LOG_INCLUDED
114 #ifndef DEBUG_LOG_INCLUDED
115 #define DEBUG_LOG(line, string, value)
116 #else
117 struct debug_log_info
118 {
119 unsigned long time;
120 unsigned long timer_data;
121 // int line;
122 const char *string;
123 int value;
124 };
125 #define DEBUG_LOG_SIZE 4096
126
127 struct debug_log_info debug_log[DEBUG_LOG_SIZE];
128 int debug_log_pos = 0;
129
130 #define DEBUG_LOG(_line, _string, _value) do { \
131 if ((_line) == SERIAL_DEBUG_LINE) {\
132 debug_log_func(_line, _string, _value); \
133 }\
134 }while(0)
135
136 void debug_log_func(int line, const char *string, int value)
137 {
138 if (debug_log_pos < DEBUG_LOG_SIZE) {
139 debug_log[debug_log_pos].time = jiffies;
140 debug_log[debug_log_pos].timer_data = *R_TIMER_DATA;
141 // debug_log[debug_log_pos].line = line;
142 debug_log[debug_log_pos].string = string;
143 debug_log[debug_log_pos].value = value;
144 debug_log_pos++;
145 }
146 /*printk(string, value);*/
147 }
148 #endif
149
150 #ifndef CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS
151 /* Default number of timer ticks before flushing rx fifo
152 * When using "little data, low latency applications: use 0
153 * When using "much data applications (PPP)" use ~5
154 */
155 #define CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS 5
156 #endif
157
158 unsigned long timer_data_to_ns(unsigned long timer_data);
159
160 static void change_speed(struct e100_serial *info);
161 static void rs_throttle(struct tty_struct * tty);
162 static void rs_wait_until_sent(struct tty_struct *tty, int timeout);
163 static int rs_write(struct tty_struct *tty,
164 const unsigned char *buf, int count);
165 #ifdef CONFIG_ETRAX_RS485
166 static int e100_write_rs485(struct tty_struct *tty,
167 const unsigned char *buf, int count);
168 #endif
169 static int get_lsr_info(struct e100_serial *info, unsigned int *value);
170
171
172 #define DEF_BAUD 115200 /* 115.2 kbit/s */
173 #define STD_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST)
174 #define DEF_RX 0x20 /* or SERIAL_CTRL_W >> 8 */
175 /* Default value of tx_ctrl register: has txd(bit 7)=1 (idle) as default */
176 #define DEF_TX 0x80 /* or SERIAL_CTRL_B */
177
178 /* offsets from R_SERIALx_CTRL */
179
180 #define REG_DATA 0
181 #define REG_DATA_STATUS32 0 /* this is the 32 bit register R_SERIALx_READ */
182 #define REG_TR_DATA 0
183 #define REG_STATUS 1
184 #define REG_TR_CTRL 1
185 #define REG_REC_CTRL 2
186 #define REG_BAUD 3
187 #define REG_XOFF 4 /* this is a 32 bit register */
188
189 /* The bitfields are the same for all serial ports */
190 #define SER_RXD_MASK IO_MASK(R_SERIAL0_STATUS, rxd)
191 #define SER_DATA_AVAIL_MASK IO_MASK(R_SERIAL0_STATUS, data_avail)
192 #define SER_FRAMING_ERR_MASK IO_MASK(R_SERIAL0_STATUS, framing_err)
193 #define SER_PAR_ERR_MASK IO_MASK(R_SERIAL0_STATUS, par_err)
194 #define SER_OVERRUN_MASK IO_MASK(R_SERIAL0_STATUS, overrun)
195
196 #define SER_ERROR_MASK (SER_OVERRUN_MASK | SER_PAR_ERR_MASK | SER_FRAMING_ERR_MASK)
197
198 /* Values for info->errorcode */
199 #define ERRCODE_SET_BREAK (TTY_BREAK)
200 #define ERRCODE_INSERT 0x100
201 #define ERRCODE_INSERT_BREAK (ERRCODE_INSERT | TTY_BREAK)
202
203 #define FORCE_EOP(info) *R_SET_EOP = 1U << info->iseteop;
204
205 /*
206 * General note regarding the use of IO_* macros in this file:
207 *
208 * We will use the bits defined for DMA channel 6 when using various
209 * IO_* macros (e.g. IO_STATE, IO_MASK, IO_EXTRACT) and _assume_ they are
210 * the same for all channels (which of course they are).
211 *
212 * We will also use the bits defined for serial port 0 when writing commands
213 * to the different ports, as these bits too are the same for all ports.
214 */
215
216
217 /* Mask for the irqs possibly enabled in R_IRQ_MASK1_RD etc. */
218 static const unsigned long e100_ser_int_mask = 0
219 #ifdef CONFIG_ETRAX_SERIAL_PORT0
220 | IO_MASK(R_IRQ_MASK1_RD, ser0_data) | IO_MASK(R_IRQ_MASK1_RD, ser0_ready)
221 #endif
222 #ifdef CONFIG_ETRAX_SERIAL_PORT1
223 | IO_MASK(R_IRQ_MASK1_RD, ser1_data) | IO_MASK(R_IRQ_MASK1_RD, ser1_ready)
224 #endif
225 #ifdef CONFIG_ETRAX_SERIAL_PORT2
226 | IO_MASK(R_IRQ_MASK1_RD, ser2_data) | IO_MASK(R_IRQ_MASK1_RD, ser2_ready)
227 #endif
228 #ifdef CONFIG_ETRAX_SERIAL_PORT3
229 | IO_MASK(R_IRQ_MASK1_RD, ser3_data) | IO_MASK(R_IRQ_MASK1_RD, ser3_ready)
230 #endif
231 ;
232 unsigned long r_alt_ser_baudrate_shadow = 0;
233
234 /* this is the data for the four serial ports in the etrax100 */
235 /* DMA2(ser2), DMA4(ser3), DMA6(ser0) or DMA8(ser1) */
236 /* R_DMA_CHx_CLR_INTR, R_DMA_CHx_FIRST, R_DMA_CHx_CMD */
237
238 static struct e100_serial rs_table[] = {
239 { .baud = DEF_BAUD,
240 .ioport = (unsigned char *)R_SERIAL0_CTRL,
241 .irq = 1U << 12, /* uses DMA 6 and 7 */
242 .oclrintradr = R_DMA_CH6_CLR_INTR,
243 .ofirstadr = R_DMA_CH6_FIRST,
244 .ocmdadr = R_DMA_CH6_CMD,
245 .ostatusadr = R_DMA_CH6_STATUS,
246 .iclrintradr = R_DMA_CH7_CLR_INTR,
247 .ifirstadr = R_DMA_CH7_FIRST,
248 .icmdadr = R_DMA_CH7_CMD,
249 .idescradr = R_DMA_CH7_DESCR,
250 .flags = STD_FLAGS,
251 .rx_ctrl = DEF_RX,
252 .tx_ctrl = DEF_TX,
253 .iseteop = 2,
254 .dma_owner = dma_ser0,
255 .io_if = if_serial_0,
256 #ifdef CONFIG_ETRAX_SERIAL_PORT0
257 .enabled = 1,
258 #ifdef CONFIG_ETRAX_SERIAL_PORT0_DMA6_OUT
259 .dma_out_enabled = 1,
260 .dma_out_nbr = SER0_TX_DMA_NBR,
261 .dma_out_irq_nbr = SER0_DMA_TX_IRQ_NBR,
262 .dma_out_irq_flags = IRQF_DISABLED,
263 .dma_out_irq_description = "serial 0 dma tr",
264 #else
265 .dma_out_enabled = 0,
266 .dma_out_nbr = UINT_MAX,
267 .dma_out_irq_nbr = 0,
268 .dma_out_irq_flags = 0,
269 .dma_out_irq_description = NULL,
270 #endif
271 #ifdef CONFIG_ETRAX_SERIAL_PORT0_DMA7_IN
272 .dma_in_enabled = 1,
273 .dma_in_nbr = SER0_RX_DMA_NBR,
274 .dma_in_irq_nbr = SER0_DMA_RX_IRQ_NBR,
275 .dma_in_irq_flags = IRQF_DISABLED,
276 .dma_in_irq_description = "serial 0 dma rec",
277 #else
278 .dma_in_enabled = 0,
279 .dma_in_nbr = UINT_MAX,
280 .dma_in_irq_nbr = 0,
281 .dma_in_irq_flags = 0,
282 .dma_in_irq_description = NULL,
283 #endif
284 #else
285 .enabled = 0,
286 .io_if_description = NULL,
287 .dma_out_enabled = 0,
288 .dma_in_enabled = 0
289 #endif
290
291 }, /* ttyS0 */
292 #ifndef CONFIG_SVINTO_SIM
293 { .baud = DEF_BAUD,
294 .ioport = (unsigned char *)R_SERIAL1_CTRL,
295 .irq = 1U << 16, /* uses DMA 8 and 9 */
296 .oclrintradr = R_DMA_CH8_CLR_INTR,
297 .ofirstadr = R_DMA_CH8_FIRST,
298 .ocmdadr = R_DMA_CH8_CMD,
299 .ostatusadr = R_DMA_CH8_STATUS,
300 .iclrintradr = R_DMA_CH9_CLR_INTR,
301 .ifirstadr = R_DMA_CH9_FIRST,
302 .icmdadr = R_DMA_CH9_CMD,
303 .idescradr = R_DMA_CH9_DESCR,
304 .flags = STD_FLAGS,
305 .rx_ctrl = DEF_RX,
306 .tx_ctrl = DEF_TX,
307 .iseteop = 3,
308 .dma_owner = dma_ser1,
309 .io_if = if_serial_1,
310 #ifdef CONFIG_ETRAX_SERIAL_PORT1
311 .enabled = 1,
312 .io_if_description = "ser1",
313 #ifdef CONFIG_ETRAX_SERIAL_PORT1_DMA8_OUT
314 .dma_out_enabled = 1,
315 .dma_out_nbr = SER1_TX_DMA_NBR,
316 .dma_out_irq_nbr = SER1_DMA_TX_IRQ_NBR,
317 .dma_out_irq_flags = IRQF_DISABLED,
318 .dma_out_irq_description = "serial 1 dma tr",
319 #else
320 .dma_out_enabled = 0,
321 .dma_out_nbr = UINT_MAX,
322 .dma_out_irq_nbr = 0,
323 .dma_out_irq_flags = 0,
324 .dma_out_irq_description = NULL,
325 #endif
326 #ifdef CONFIG_ETRAX_SERIAL_PORT1_DMA9_IN
327 .dma_in_enabled = 1,
328 .dma_in_nbr = SER1_RX_DMA_NBR,
329 .dma_in_irq_nbr = SER1_DMA_RX_IRQ_NBR,
330 .dma_in_irq_flags = IRQF_DISABLED,
331 .dma_in_irq_description = "serial 1 dma rec",
332 #else
333 .dma_in_enabled = 0,
334 .dma_in_enabled = 0,
335 .dma_in_nbr = UINT_MAX,
336 .dma_in_irq_nbr = 0,
337 .dma_in_irq_flags = 0,
338 .dma_in_irq_description = NULL,
339 #endif
340 #else
341 .enabled = 0,
342 .io_if_description = NULL,
343 .dma_in_irq_nbr = 0,
344 .dma_out_enabled = 0,
345 .dma_in_enabled = 0
346 #endif
347 }, /* ttyS1 */
348
349 { .baud = DEF_BAUD,
350 .ioport = (unsigned char *)R_SERIAL2_CTRL,
351 .irq = 1U << 4, /* uses DMA 2 and 3 */
352 .oclrintradr = R_DMA_CH2_CLR_INTR,
353 .ofirstadr = R_DMA_CH2_FIRST,
354 .ocmdadr = R_DMA_CH2_CMD,
355 .ostatusadr = R_DMA_CH2_STATUS,
356 .iclrintradr = R_DMA_CH3_CLR_INTR,
357 .ifirstadr = R_DMA_CH3_FIRST,
358 .icmdadr = R_DMA_CH3_CMD,
359 .idescradr = R_DMA_CH3_DESCR,
360 .flags = STD_FLAGS,
361 .rx_ctrl = DEF_RX,
362 .tx_ctrl = DEF_TX,
363 .iseteop = 0,
364 .dma_owner = dma_ser2,
365 .io_if = if_serial_2,
366 #ifdef CONFIG_ETRAX_SERIAL_PORT2
367 .enabled = 1,
368 .io_if_description = "ser2",
369 #ifdef CONFIG_ETRAX_SERIAL_PORT2_DMA2_OUT
370 .dma_out_enabled = 1,
371 .dma_out_nbr = SER2_TX_DMA_NBR,
372 .dma_out_irq_nbr = SER2_DMA_TX_IRQ_NBR,
373 .dma_out_irq_flags = IRQF_DISABLED,
374 .dma_out_irq_description = "serial 2 dma tr",
375 #else
376 .dma_out_enabled = 0,
377 .dma_out_nbr = UINT_MAX,
378 .dma_out_irq_nbr = 0,
379 .dma_out_irq_flags = 0,
380 .dma_out_irq_description = NULL,
381 #endif
382 #ifdef CONFIG_ETRAX_SERIAL_PORT2_DMA3_IN
383 .dma_in_enabled = 1,
384 .dma_in_nbr = SER2_RX_DMA_NBR,
385 .dma_in_irq_nbr = SER2_DMA_RX_IRQ_NBR,
386 .dma_in_irq_flags = IRQF_DISABLED,
387 .dma_in_irq_description = "serial 2 dma rec",
388 #else
389 .dma_in_enabled = 0,
390 .dma_in_nbr = UINT_MAX,
391 .dma_in_irq_nbr = 0,
392 .dma_in_irq_flags = 0,
393 .dma_in_irq_description = NULL,
394 #endif
395 #else
396 .enabled = 0,
397 .io_if_description = NULL,
398 .dma_out_enabled = 0,
399 .dma_in_enabled = 0
400 #endif
401 }, /* ttyS2 */
402
403 { .baud = DEF_BAUD,
404 .ioport = (unsigned char *)R_SERIAL3_CTRL,
405 .irq = 1U << 8, /* uses DMA 4 and 5 */
406 .oclrintradr = R_DMA_CH4_CLR_INTR,
407 .ofirstadr = R_DMA_CH4_FIRST,
408 .ocmdadr = R_DMA_CH4_CMD,
409 .ostatusadr = R_DMA_CH4_STATUS,
410 .iclrintradr = R_DMA_CH5_CLR_INTR,
411 .ifirstadr = R_DMA_CH5_FIRST,
412 .icmdadr = R_DMA_CH5_CMD,
413 .idescradr = R_DMA_CH5_DESCR,
414 .flags = STD_FLAGS,
415 .rx_ctrl = DEF_RX,
416 .tx_ctrl = DEF_TX,
417 .iseteop = 1,
418 .dma_owner = dma_ser3,
419 .io_if = if_serial_3,
420 #ifdef CONFIG_ETRAX_SERIAL_PORT3
421 .enabled = 1,
422 .io_if_description = "ser3",
423 #ifdef CONFIG_ETRAX_SERIAL_PORT3_DMA4_OUT
424 .dma_out_enabled = 1,
425 .dma_out_nbr = SER3_TX_DMA_NBR,
426 .dma_out_irq_nbr = SER3_DMA_TX_IRQ_NBR,
427 .dma_out_irq_flags = IRQF_DISABLED,
428 .dma_out_irq_description = "serial 3 dma tr",
429 #else
430 .dma_out_enabled = 0,
431 .dma_out_nbr = UINT_MAX,
432 .dma_out_irq_nbr = 0,
433 .dma_out_irq_flags = 0,
434 .dma_out_irq_description = NULL,
435 #endif
436 #ifdef CONFIG_ETRAX_SERIAL_PORT3_DMA5_IN
437 .dma_in_enabled = 1,
438 .dma_in_nbr = SER3_RX_DMA_NBR,
439 .dma_in_irq_nbr = SER3_DMA_RX_IRQ_NBR,
440 .dma_in_irq_flags = IRQF_DISABLED,
441 .dma_in_irq_description = "serial 3 dma rec",
442 #else
443 .dma_in_enabled = 0,
444 .dma_in_nbr = UINT_MAX,
445 .dma_in_irq_nbr = 0,
446 .dma_in_irq_flags = 0,
447 .dma_in_irq_description = NULL
448 #endif
449 #else
450 .enabled = 0,
451 .io_if_description = NULL,
452 .dma_out_enabled = 0,
453 .dma_in_enabled = 0
454 #endif
455 } /* ttyS3 */
456 #endif
457 };
458
459
460 #define NR_PORTS (sizeof(rs_table)/sizeof(struct e100_serial))
461
462 #ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER
463 static struct fast_timer fast_timers[NR_PORTS];
464 #endif
465
466 #ifdef CONFIG_ETRAX_SERIAL_PROC_ENTRY
467 #define PROCSTAT(x) x
468 struct ser_statistics_type {
469 int overrun_cnt;
470 int early_errors_cnt;
471 int ser_ints_ok_cnt;
472 int errors_cnt;
473 unsigned long int processing_flip;
474 unsigned long processing_flip_still_room;
475 unsigned long int timeout_flush_cnt;
476 int rx_dma_ints;
477 int tx_dma_ints;
478 int rx_tot;
479 int tx_tot;
480 };
481
482 static struct ser_statistics_type ser_stat[NR_PORTS];
483
484 #else
485
486 #define PROCSTAT(x)
487
488 #endif /* CONFIG_ETRAX_SERIAL_PROC_ENTRY */
489
490 /* RS-485 */
491 #if defined(CONFIG_ETRAX_RS485)
492 #ifdef CONFIG_ETRAX_FAST_TIMER
493 static struct fast_timer fast_timers_rs485[NR_PORTS];
494 #endif
495 #if defined(CONFIG_ETRAX_RS485_ON_PA)
496 static int rs485_pa_bit = CONFIG_ETRAX_RS485_ON_PA_BIT;
497 #endif
498 #if defined(CONFIG_ETRAX_RS485_ON_PORT_G)
499 static int rs485_port_g_bit = CONFIG_ETRAX_RS485_ON_PORT_G_BIT;
500 #endif
501 #endif
502
503 /* Info and macros needed for each ports extra control/status signals. */
504 #define E100_STRUCT_PORT(line, pinname) \
505 ((CONFIG_ETRAX_SER##line##_##pinname##_ON_PA_BIT >= 0)? \
506 (R_PORT_PA_DATA): ( \
507 (CONFIG_ETRAX_SER##line##_##pinname##_ON_PB_BIT >= 0)? \
508 (R_PORT_PB_DATA):&dummy_ser[line]))
509
510 #define E100_STRUCT_SHADOW(line, pinname) \
511 ((CONFIG_ETRAX_SER##line##_##pinname##_ON_PA_BIT >= 0)? \
512 (&port_pa_data_shadow): ( \
513 (CONFIG_ETRAX_SER##line##_##pinname##_ON_PB_BIT >= 0)? \
514 (&port_pb_data_shadow):&dummy_ser[line]))
515 #define E100_STRUCT_MASK(line, pinname) \
516 ((CONFIG_ETRAX_SER##line##_##pinname##_ON_PA_BIT >= 0)? \
517 (1<<CONFIG_ETRAX_SER##line##_##pinname##_ON_PA_BIT): ( \
518 (CONFIG_ETRAX_SER##line##_##pinname##_ON_PB_BIT >= 0)? \
519 (1<<CONFIG_ETRAX_SER##line##_##pinname##_ON_PB_BIT):DUMMY_##pinname##_MASK))
520
521 #define DUMMY_DTR_MASK 1
522 #define DUMMY_RI_MASK 2
523 #define DUMMY_DSR_MASK 4
524 #define DUMMY_CD_MASK 8
525 static unsigned char dummy_ser[NR_PORTS] = {0xFF, 0xFF, 0xFF,0xFF};
526
527 /* If not all status pins are used or disabled, use mixed mode */
528 #ifdef CONFIG_ETRAX_SERIAL_PORT0
529
530 #define SER0_PA_BITSUM (CONFIG_ETRAX_SER0_DTR_ON_PA_BIT+CONFIG_ETRAX_SER0_RI_ON_PA_BIT+CONFIG_ETRAX_SER0_DSR_ON_PA_BIT+CONFIG_ETRAX_SER0_CD_ON_PA_BIT)
531
532 #if SER0_PA_BITSUM != -4
533 # if CONFIG_ETRAX_SER0_DTR_ON_PA_BIT == -1
534 # ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
535 # define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
536 # endif
537 # endif
538 # if CONFIG_ETRAX_SER0_RI_ON_PA_BIT == -1
539 # ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
540 # define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
541 # endif
542 # endif
543 # if CONFIG_ETRAX_SER0_DSR_ON_PA_BIT == -1
544 # ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
545 # define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
546 # endif
547 # endif
548 # if CONFIG_ETRAX_SER0_CD_ON_PA_BIT == -1
549 # ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
550 # define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
551 # endif
552 # endif
553 #endif
554
555 #define SER0_PB_BITSUM (CONFIG_ETRAX_SER0_DTR_ON_PB_BIT+CONFIG_ETRAX_SER0_RI_ON_PB_BIT+CONFIG_ETRAX_SER0_DSR_ON_PB_BIT+CONFIG_ETRAX_SER0_CD_ON_PB_BIT)
556
557 #if SER0_PB_BITSUM != -4
558 # if CONFIG_ETRAX_SER0_DTR_ON_PB_BIT == -1
559 # ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
560 # define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
561 # endif
562 # endif
563 # if CONFIG_ETRAX_SER0_RI_ON_PB_BIT == -1
564 # ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
565 # define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
566 # endif
567 # endif
568 # if CONFIG_ETRAX_SER0_DSR_ON_PB_BIT == -1
569 # ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
570 # define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
571 # endif
572 # endif
573 # if CONFIG_ETRAX_SER0_CD_ON_PB_BIT == -1
574 # ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
575 # define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
576 # endif
577 # endif
578 #endif
579
580 #endif /* PORT0 */
581
582
583 #ifdef CONFIG_ETRAX_SERIAL_PORT1
584
585 #define SER1_PA_BITSUM (CONFIG_ETRAX_SER1_DTR_ON_PA_BIT+CONFIG_ETRAX_SER1_RI_ON_PA_BIT+CONFIG_ETRAX_SER1_DSR_ON_PA_BIT+CONFIG_ETRAX_SER1_CD_ON_PA_BIT)
586
587 #if SER1_PA_BITSUM != -4
588 # if CONFIG_ETRAX_SER1_DTR_ON_PA_BIT == -1
589 # ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
590 # define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
591 # endif
592 # endif
593 # if CONFIG_ETRAX_SER1_RI_ON_PA_BIT == -1
594 # ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
595 # define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
596 # endif
597 # endif
598 # if CONFIG_ETRAX_SER1_DSR_ON_PA_BIT == -1
599 # ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
600 # define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
601 # endif
602 # endif
603 # if CONFIG_ETRAX_SER1_CD_ON_PA_BIT == -1
604 # ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
605 # define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
606 # endif
607 # endif
608 #endif
609
610 #define SER1_PB_BITSUM (CONFIG_ETRAX_SER1_DTR_ON_PB_BIT+CONFIG_ETRAX_SER1_RI_ON_PB_BIT+CONFIG_ETRAX_SER1_DSR_ON_PB_BIT+CONFIG_ETRAX_SER1_CD_ON_PB_BIT)
611
612 #if SER1_PB_BITSUM != -4
613 # if CONFIG_ETRAX_SER1_DTR_ON_PB_BIT == -1
614 # ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
615 # define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
616 # endif
617 # endif
618 # if CONFIG_ETRAX_SER1_RI_ON_PB_BIT == -1
619 # ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
620 # define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
621 # endif
622 # endif
623 # if CONFIG_ETRAX_SER1_DSR_ON_PB_BIT == -1
624 # ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
625 # define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
626 # endif
627 # endif
628 # if CONFIG_ETRAX_SER1_CD_ON_PB_BIT == -1
629 # ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
630 # define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
631 # endif
632 # endif
633 #endif
634
635 #endif /* PORT1 */
636
637 #ifdef CONFIG_ETRAX_SERIAL_PORT2
638
639 #define SER2_PA_BITSUM (CONFIG_ETRAX_SER2_DTR_ON_PA_BIT+CONFIG_ETRAX_SER2_RI_ON_PA_BIT+CONFIG_ETRAX_SER2_DSR_ON_PA_BIT+CONFIG_ETRAX_SER2_CD_ON_PA_BIT)
640
641 #if SER2_PA_BITSUM != -4
642 # if CONFIG_ETRAX_SER2_DTR_ON_PA_BIT == -1
643 # ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
644 # define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
645 # endif
646 # endif
647 # if CONFIG_ETRAX_SER2_RI_ON_PA_BIT == -1
648 # ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
649 # define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
650 # endif
651 # endif
652 # if CONFIG_ETRAX_SER2_DSR_ON_PA_BIT == -1
653 # ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
654 # define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
655 # endif
656 # endif
657 # if CONFIG_ETRAX_SER2_CD_ON_PA_BIT == -1
658 # ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
659 # define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
660 # endif
661 # endif
662 #endif
663
664 #define SER2_PB_BITSUM (CONFIG_ETRAX_SER2_DTR_ON_PB_BIT+CONFIG_ETRAX_SER2_RI_ON_PB_BIT+CONFIG_ETRAX_SER2_DSR_ON_PB_BIT+CONFIG_ETRAX_SER2_CD_ON_PB_BIT)
665
666 #if SER2_PB_BITSUM != -4
667 # if CONFIG_ETRAX_SER2_DTR_ON_PB_BIT == -1
668 # ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
669 # define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
670 # endif
671 # endif
672 # if CONFIG_ETRAX_SER2_RI_ON_PB_BIT == -1
673 # ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
674 # define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
675 # endif
676 # endif
677 # if CONFIG_ETRAX_SER2_DSR_ON_PB_BIT == -1
678 # ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
679 # define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
680 # endif
681 # endif
682 # if CONFIG_ETRAX_SER2_CD_ON_PB_BIT == -1
683 # ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
684 # define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
685 # endif
686 # endif
687 #endif
688
689 #endif /* PORT2 */
690
691 #ifdef CONFIG_ETRAX_SERIAL_PORT3
692
693 #define SER3_PA_BITSUM (CONFIG_ETRAX_SER3_DTR_ON_PA_BIT+CONFIG_ETRAX_SER3_RI_ON_PA_BIT+CONFIG_ETRAX_SER3_DSR_ON_PA_BIT+CONFIG_ETRAX_SER3_CD_ON_PA_BIT)
694
695 #if SER3_PA_BITSUM != -4
696 # if CONFIG_ETRAX_SER3_DTR_ON_PA_BIT == -1
697 # ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
698 # define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
699 # endif
700 # endif
701 # if CONFIG_ETRAX_SER3_RI_ON_PA_BIT == -1
702 # ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
703 # define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
704 # endif
705 # endif
706 # if CONFIG_ETRAX_SER3_DSR_ON_PA_BIT == -1
707 # ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
708 # define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
709 # endif
710 # endif
711 # if CONFIG_ETRAX_SER3_CD_ON_PA_BIT == -1
712 # ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
713 # define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
714 # endif
715 # endif
716 #endif
717
718 #define SER3_PB_BITSUM (CONFIG_ETRAX_SER3_DTR_ON_PB_BIT+CONFIG_ETRAX_SER3_RI_ON_PB_BIT+CONFIG_ETRAX_SER3_DSR_ON_PB_BIT+CONFIG_ETRAX_SER3_CD_ON_PB_BIT)
719
720 #if SER3_PB_BITSUM != -4
721 # if CONFIG_ETRAX_SER3_DTR_ON_PB_BIT == -1
722 # ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
723 # define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
724 # endif
725 # endif
726 # if CONFIG_ETRAX_SER3_RI_ON_PB_BIT == -1
727 # ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
728 # define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
729 # endif
730 # endif
731 # if CONFIG_ETRAX_SER3_DSR_ON_PB_BIT == -1
732 # ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
733 # define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
734 # endif
735 # endif
736 # if CONFIG_ETRAX_SER3_CD_ON_PB_BIT == -1
737 # ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
738 # define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
739 # endif
740 # endif
741 #endif
742
743 #endif /* PORT3 */
744
745
746 #if defined(CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED) || \
747 defined(CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED) || \
748 defined(CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED) || \
749 defined(CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED)
750 #define CONFIG_ETRAX_SERX_DTR_RI_DSR_CD_MIXED
751 #endif
752
753 #ifdef CONFIG_ETRAX_SERX_DTR_RI_DSR_CD_MIXED
754 /* The pins can be mixed on PA and PB */
755 #define CONTROL_PINS_PORT_NOT_USED(line) \
756 &dummy_ser[line], &dummy_ser[line], \
757 &dummy_ser[line], &dummy_ser[line], \
758 &dummy_ser[line], &dummy_ser[line], \
759 &dummy_ser[line], &dummy_ser[line], \
760 DUMMY_DTR_MASK, DUMMY_RI_MASK, DUMMY_DSR_MASK, DUMMY_CD_MASK
761
762
763 struct control_pins
764 {
765 volatile unsigned char *dtr_port;
766 unsigned char *dtr_shadow;
767 volatile unsigned char *ri_port;
768 unsigned char *ri_shadow;
769 volatile unsigned char *dsr_port;
770 unsigned char *dsr_shadow;
771 volatile unsigned char *cd_port;
772 unsigned char *cd_shadow;
773
774 unsigned char dtr_mask;
775 unsigned char ri_mask;
776 unsigned char dsr_mask;
777 unsigned char cd_mask;
778 };
779
780 static const struct control_pins e100_modem_pins[NR_PORTS] =
781 {
782 /* Ser 0 */
783 {
784 #ifdef CONFIG_ETRAX_SERIAL_PORT0
785 E100_STRUCT_PORT(0,DTR), E100_STRUCT_SHADOW(0,DTR),
786 E100_STRUCT_PORT(0,RI), E100_STRUCT_SHADOW(0,RI),
787 E100_STRUCT_PORT(0,DSR), E100_STRUCT_SHADOW(0,DSR),
788 E100_STRUCT_PORT(0,CD), E100_STRUCT_SHADOW(0,CD),
789 E100_STRUCT_MASK(0,DTR),
790 E100_STRUCT_MASK(0,RI),
791 E100_STRUCT_MASK(0,DSR),
792 E100_STRUCT_MASK(0,CD)
793 #else
794 CONTROL_PINS_PORT_NOT_USED(0)
795 #endif
796 },
797
798 /* Ser 1 */
799 {
800 #ifdef CONFIG_ETRAX_SERIAL_PORT1
801 E100_STRUCT_PORT(1,DTR), E100_STRUCT_SHADOW(1,DTR),
802 E100_STRUCT_PORT(1,RI), E100_STRUCT_SHADOW(1,RI),
803 E100_STRUCT_PORT(1,DSR), E100_STRUCT_SHADOW(1,DSR),
804 E100_STRUCT_PORT(1,CD), E100_STRUCT_SHADOW(1,CD),
805 E100_STRUCT_MASK(1,DTR),
806 E100_STRUCT_MASK(1,RI),
807 E100_STRUCT_MASK(1,DSR),
808 E100_STRUCT_MASK(1,CD)
809 #else
810 CONTROL_PINS_PORT_NOT_USED(1)
811 #endif
812 },
813
814 /* Ser 2 */
815 {
816 #ifdef CONFIG_ETRAX_SERIAL_PORT2
817 E100_STRUCT_PORT(2,DTR), E100_STRUCT_SHADOW(2,DTR),
818 E100_STRUCT_PORT(2,RI), E100_STRUCT_SHADOW(2,RI),
819 E100_STRUCT_PORT(2,DSR), E100_STRUCT_SHADOW(2,DSR),
820 E100_STRUCT_PORT(2,CD), E100_STRUCT_SHADOW(2,CD),
821 E100_STRUCT_MASK(2,DTR),
822 E100_STRUCT_MASK(2,RI),
823 E100_STRUCT_MASK(2,DSR),
824 E100_STRUCT_MASK(2,CD)
825 #else
826 CONTROL_PINS_PORT_NOT_USED(2)
827 #endif
828 },
829
830 /* Ser 3 */
831 {
832 #ifdef CONFIG_ETRAX_SERIAL_PORT3
833 E100_STRUCT_PORT(3,DTR), E100_STRUCT_SHADOW(3,DTR),
834 E100_STRUCT_PORT(3,RI), E100_STRUCT_SHADOW(3,RI),
835 E100_STRUCT_PORT(3,DSR), E100_STRUCT_SHADOW(3,DSR),
836 E100_STRUCT_PORT(3,CD), E100_STRUCT_SHADOW(3,CD),
837 E100_STRUCT_MASK(3,DTR),
838 E100_STRUCT_MASK(3,RI),
839 E100_STRUCT_MASK(3,DSR),
840 E100_STRUCT_MASK(3,CD)
841 #else
842 CONTROL_PINS_PORT_NOT_USED(3)
843 #endif
844 }
845 };
846 #else /* CONFIG_ETRAX_SERX_DTR_RI_DSR_CD_MIXED */
847
848 /* All pins are on either PA or PB for each serial port */
849 #define CONTROL_PINS_PORT_NOT_USED(line) \
850 &dummy_ser[line], &dummy_ser[line], \
851 DUMMY_DTR_MASK, DUMMY_RI_MASK, DUMMY_DSR_MASK, DUMMY_CD_MASK
852
853
854 struct control_pins
855 {
856 volatile unsigned char *port;
857 unsigned char *shadow;
858
859 unsigned char dtr_mask;
860 unsigned char ri_mask;
861 unsigned char dsr_mask;
862 unsigned char cd_mask;
863 };
864
865 #define dtr_port port
866 #define dtr_shadow shadow
867 #define ri_port port
868 #define ri_shadow shadow
869 #define dsr_port port
870 #define dsr_shadow shadow
871 #define cd_port port
872 #define cd_shadow shadow
873
874 static const struct control_pins e100_modem_pins[NR_PORTS] =
875 {
876 /* Ser 0 */
877 {
878 #ifdef CONFIG_ETRAX_SERIAL_PORT0
879 E100_STRUCT_PORT(0,DTR), E100_STRUCT_SHADOW(0,DTR),
880 E100_STRUCT_MASK(0,DTR),
881 E100_STRUCT_MASK(0,RI),
882 E100_STRUCT_MASK(0,DSR),
883 E100_STRUCT_MASK(0,CD)
884 #else
885 CONTROL_PINS_PORT_NOT_USED(0)
886 #endif
887 },
888
889 /* Ser 1 */
890 {
891 #ifdef CONFIG_ETRAX_SERIAL_PORT1
892 E100_STRUCT_PORT(1,DTR), E100_STRUCT_SHADOW(1,DTR),
893 E100_STRUCT_MASK(1,DTR),
894 E100_STRUCT_MASK(1,RI),
895 E100_STRUCT_MASK(1,DSR),
896 E100_STRUCT_MASK(1,CD)
897 #else
898 CONTROL_PINS_PORT_NOT_USED(1)
899 #endif
900 },
901
902 /* Ser 2 */
903 {
904 #ifdef CONFIG_ETRAX_SERIAL_PORT2
905 E100_STRUCT_PORT(2,DTR), E100_STRUCT_SHADOW(2,DTR),
906 E100_STRUCT_MASK(2,DTR),
907 E100_STRUCT_MASK(2,RI),
908 E100_STRUCT_MASK(2,DSR),
909 E100_STRUCT_MASK(2,CD)
910 #else
911 CONTROL_PINS_PORT_NOT_USED(2)
912 #endif
913 },
914
915 /* Ser 3 */
916 {
917 #ifdef CONFIG_ETRAX_SERIAL_PORT3
918 E100_STRUCT_PORT(3,DTR), E100_STRUCT_SHADOW(3,DTR),
919 E100_STRUCT_MASK(3,DTR),
920 E100_STRUCT_MASK(3,RI),
921 E100_STRUCT_MASK(3,DSR),
922 E100_STRUCT_MASK(3,CD)
923 #else
924 CONTROL_PINS_PORT_NOT_USED(3)
925 #endif
926 }
927 };
928 #endif /* !CONFIG_ETRAX_SERX_DTR_RI_DSR_CD_MIXED */
929
930 #define E100_RTS_MASK 0x20
931 #define E100_CTS_MASK 0x40
932
933 /* All serial port signals are active low:
934 * active = 0 -> 3.3V to RS-232 driver -> -12V on RS-232 level
935 * inactive = 1 -> 0V to RS-232 driver -> +12V on RS-232 level
936 *
937 * These macros returns the pin value: 0=0V, >=1 = 3.3V on ETRAX chip
938 */
939
940 /* Output */
941 #define E100_RTS_GET(info) ((info)->rx_ctrl & E100_RTS_MASK)
942 /* Input */
943 #define E100_CTS_GET(info) ((info)->ioport[REG_STATUS] & E100_CTS_MASK)
944
945 /* These are typically PA or PB and 0 means 0V, 1 means 3.3V */
946 /* Is an output */
947 #define E100_DTR_GET(info) ((*e100_modem_pins[(info)->line].dtr_shadow) & e100_modem_pins[(info)->line].dtr_mask)
948
949 /* Normally inputs */
950 #define E100_RI_GET(info) ((*e100_modem_pins[(info)->line].ri_port) & e100_modem_pins[(info)->line].ri_mask)
951 #define E100_CD_GET(info) ((*e100_modem_pins[(info)->line].cd_port) & e100_modem_pins[(info)->line].cd_mask)
952
953 /* Input */
954 #define E100_DSR_GET(info) ((*e100_modem_pins[(info)->line].dsr_port) & e100_modem_pins[(info)->line].dsr_mask)
955
956
957 /*
958 * tmp_buf is used as a temporary buffer by serial_write. We need to
959 * lock it in case the memcpy_fromfs blocks while swapping in a page,
960 * and some other program tries to do a serial write at the same time.
961 * Since the lock will only come under contention when the system is
962 * swapping and available memory is low, it makes sense to share one
963 * buffer across all the serial ports, since it significantly saves
964 * memory if large numbers of serial ports are open.
965 */
966 static unsigned char *tmp_buf;
967 static DEFINE_MUTEX(tmp_buf_mutex);
968
969 /* Calculate the chartime depending on baudrate, numbor of bits etc. */
970 static void update_char_time(struct e100_serial * info)
971 {
972 tcflag_t cflags = info->port.tty->termios->c_cflag;
973 int bits;
974
975 /* calc. number of bits / data byte */
976 /* databits + startbit and 1 stopbit */
977 if ((cflags & CSIZE) == CS7)
978 bits = 9;
979 else
980 bits = 10;
981
982 if (cflags & CSTOPB) /* 2 stopbits ? */
983 bits++;
984
985 if (cflags & PARENB) /* parity bit ? */
986 bits++;
987
988 /* calc timeout */
989 info->char_time_usec = ((bits * 1000000) / info->baud) + 1;
990 info->flush_time_usec = 4*info->char_time_usec;
991 if (info->flush_time_usec < MIN_FLUSH_TIME_USEC)
992 info->flush_time_usec = MIN_FLUSH_TIME_USEC;
993
994 }
995
996 /*
997 * This function maps from the Bxxxx defines in asm/termbits.h into real
998 * baud rates.
999 */
1000
1001 static int
1002 cflag_to_baud(unsigned int cflag)
1003 {
1004 static int baud_table[] = {
1005 0, 50, 75, 110, 134, 150, 200, 300, 600, 1200, 1800, 2400,
1006 4800, 9600, 19200, 38400 };
1007
1008 static int ext_baud_table[] = {
1009 0, 57600, 115200, 230400, 460800, 921600, 1843200, 6250000,
1010 0, 0, 0, 0, 0, 0, 0, 0 };
1011
1012 if (cflag & CBAUDEX)
1013 return ext_baud_table[(cflag & CBAUD) & ~CBAUDEX];
1014 else
1015 return baud_table[cflag & CBAUD];
1016 }
1017
1018 /* and this maps to an etrax100 hardware baud constant */
1019
1020 static unsigned char
1021 cflag_to_etrax_baud(unsigned int cflag)
1022 {
1023 char retval;
1024
1025 static char baud_table[] = {
1026 -1, -1, -1, -1, -1, -1, -1, 0, 1, 2, -1, 3, 4, 5, 6, 7 };
1027
1028 static char ext_baud_table[] = {
1029 -1, 8, 9, 10, 11, 12, 13, 14, -1, -1, -1, -1, -1, -1, -1, -1 };
1030
1031 if (cflag & CBAUDEX)
1032 retval = ext_baud_table[(cflag & CBAUD) & ~CBAUDEX];
1033 else
1034 retval = baud_table[cflag & CBAUD];
1035
1036 if (retval < 0) {
1037 printk(KERN_WARNING "serdriver tried setting invalid baud rate, flags %x.\n", cflag);
1038 retval = 5; /* choose default 9600 instead */
1039 }
1040
1041 return retval | (retval << 4); /* choose same for both TX and RX */
1042 }
1043
1044
1045 /* Various static support functions */
1046
1047 /* Functions to set or clear DTR/RTS on the requested line */
1048 /* It is complicated by the fact that RTS is a serial port register, while
1049 * DTR might not be implemented in the HW at all, and if it is, it can be on
1050 * any general port.
1051 */
1052
1053
1054 static inline void
1055 e100_dtr(struct e100_serial *info, int set)
1056 {
1057 #ifndef CONFIG_SVINTO_SIM
1058 unsigned char mask = e100_modem_pins[info->line].dtr_mask;
1059
1060 #ifdef SERIAL_DEBUG_IO
1061 printk("ser%i dtr %i mask: 0x%02X\n", info->line, set, mask);
1062 printk("ser%i shadow before 0x%02X get: %i\n",
1063 info->line, *e100_modem_pins[info->line].dtr_shadow,
1064 E100_DTR_GET(info));
1065 #endif
1066 /* DTR is active low */
1067 {
1068 unsigned long flags;
1069
1070 local_irq_save(flags);
1071 *e100_modem_pins[info->line].dtr_shadow &= ~mask;
1072 *e100_modem_pins[info->line].dtr_shadow |= (set ? 0 : mask);
1073 *e100_modem_pins[info->line].dtr_port = *e100_modem_pins[info->line].dtr_shadow;
1074 local_irq_restore(flags);
1075 }
1076
1077 #ifdef SERIAL_DEBUG_IO
1078 printk("ser%i shadow after 0x%02X get: %i\n",
1079 info->line, *e100_modem_pins[info->line].dtr_shadow,
1080 E100_DTR_GET(info));
1081 #endif
1082 #endif
1083 }
1084
1085 /* set = 0 means 3.3V on the pin, bitvalue: 0=active, 1=inactive
1086 * 0=0V , 1=3.3V
1087 */
1088 static inline void
1089 e100_rts(struct e100_serial *info, int set)
1090 {
1091 #ifndef CONFIG_SVINTO_SIM
1092 unsigned long flags;
1093 local_irq_save(flags);
1094 info->rx_ctrl &= ~E100_RTS_MASK;
1095 info->rx_ctrl |= (set ? 0 : E100_RTS_MASK); /* RTS is active low */
1096 info->ioport[REG_REC_CTRL] = info->rx_ctrl;
1097 local_irq_restore(flags);
1098 #ifdef SERIAL_DEBUG_IO
1099 printk("ser%i rts %i\n", info->line, set);
1100 #endif
1101 #endif
1102 }
1103
1104
1105 /* If this behaves as a modem, RI and CD is an output */
1106 static inline void
1107 e100_ri_out(struct e100_serial *info, int set)
1108 {
1109 #ifndef CONFIG_SVINTO_SIM
1110 /* RI is active low */
1111 {
1112 unsigned char mask = e100_modem_pins[info->line].ri_mask;
1113 unsigned long flags;
1114
1115 local_irq_save(flags);
1116 *e100_modem_pins[info->line].ri_shadow &= ~mask;
1117 *e100_modem_pins[info->line].ri_shadow |= (set ? 0 : mask);
1118 *e100_modem_pins[info->line].ri_port = *e100_modem_pins[info->line].ri_shadow;
1119 local_irq_restore(flags);
1120 }
1121 #endif
1122 }
1123 static inline void
1124 e100_cd_out(struct e100_serial *info, int set)
1125 {
1126 #ifndef CONFIG_SVINTO_SIM
1127 /* CD is active low */
1128 {
1129 unsigned char mask = e100_modem_pins[info->line].cd_mask;
1130 unsigned long flags;
1131
1132 local_irq_save(flags);
1133 *e100_modem_pins[info->line].cd_shadow &= ~mask;
1134 *e100_modem_pins[info->line].cd_shadow |= (set ? 0 : mask);
1135 *e100_modem_pins[info->line].cd_port = *e100_modem_pins[info->line].cd_shadow;
1136 local_irq_restore(flags);
1137 }
1138 #endif
1139 }
1140
1141 static inline void
1142 e100_disable_rx(struct e100_serial *info)
1143 {
1144 #ifndef CONFIG_SVINTO_SIM
1145 /* disable the receiver */
1146 info->ioport[REG_REC_CTRL] =
1147 (info->rx_ctrl &= ~IO_MASK(R_SERIAL0_REC_CTRL, rec_enable));
1148 #endif
1149 }
1150
1151 static inline void
1152 e100_enable_rx(struct e100_serial *info)
1153 {
1154 #ifndef CONFIG_SVINTO_SIM
1155 /* enable the receiver */
1156 info->ioport[REG_REC_CTRL] =
1157 (info->rx_ctrl |= IO_MASK(R_SERIAL0_REC_CTRL, rec_enable));
1158 #endif
1159 }
1160
1161 /* the rx DMA uses both the dma_descr and the dma_eop interrupts */
1162
1163 static inline void
1164 e100_disable_rxdma_irq(struct e100_serial *info)
1165 {
1166 #ifdef SERIAL_DEBUG_INTR
1167 printk("rxdma_irq(%d): 0\n",info->line);
1168 #endif
1169 DINTR1(DEBUG_LOG(info->line,"IRQ disable_rxdma_irq %i\n", info->line));
1170 *R_IRQ_MASK2_CLR = (info->irq << 2) | (info->irq << 3);
1171 }
1172
1173 static inline void
1174 e100_enable_rxdma_irq(struct e100_serial *info)
1175 {
1176 #ifdef SERIAL_DEBUG_INTR
1177 printk("rxdma_irq(%d): 1\n",info->line);
1178 #endif
1179 DINTR1(DEBUG_LOG(info->line,"IRQ enable_rxdma_irq %i\n", info->line));
1180 *R_IRQ_MASK2_SET = (info->irq << 2) | (info->irq << 3);
1181 }
1182
1183 /* the tx DMA uses only dma_descr interrupt */
1184
1185 static void e100_disable_txdma_irq(struct e100_serial *info)
1186 {
1187 #ifdef SERIAL_DEBUG_INTR
1188 printk("txdma_irq(%d): 0\n",info->line);
1189 #endif
1190 DINTR1(DEBUG_LOG(info->line,"IRQ disable_txdma_irq %i\n", info->line));
1191 *R_IRQ_MASK2_CLR = info->irq;
1192 }
1193
1194 static void e100_enable_txdma_irq(struct e100_serial *info)
1195 {
1196 #ifdef SERIAL_DEBUG_INTR
1197 printk("txdma_irq(%d): 1\n",info->line);
1198 #endif
1199 DINTR1(DEBUG_LOG(info->line,"IRQ enable_txdma_irq %i\n", info->line));
1200 *R_IRQ_MASK2_SET = info->irq;
1201 }
1202
1203 static void e100_disable_txdma_channel(struct e100_serial *info)
1204 {
1205 unsigned long flags;
1206
1207 /* Disable output DMA channel for the serial port in question
1208 * ( set to something other than serialX)
1209 */
1210 local_irq_save(flags);
1211 DFLOW(DEBUG_LOG(info->line, "disable_txdma_channel %i\n", info->line));
1212 if (info->line == 0) {
1213 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma6)) ==
1214 IO_STATE(R_GEN_CONFIG, dma6, serial0)) {
1215 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma6);
1216 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma6, unused);
1217 }
1218 } else if (info->line == 1) {
1219 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma8)) ==
1220 IO_STATE(R_GEN_CONFIG, dma8, serial1)) {
1221 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma8);
1222 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma8, usb);
1223 }
1224 } else if (info->line == 2) {
1225 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma2)) ==
1226 IO_STATE(R_GEN_CONFIG, dma2, serial2)) {
1227 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma2);
1228 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma2, par0);
1229 }
1230 } else if (info->line == 3) {
1231 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma4)) ==
1232 IO_STATE(R_GEN_CONFIG, dma4, serial3)) {
1233 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma4);
1234 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma4, par1);
1235 }
1236 }
1237 *R_GEN_CONFIG = genconfig_shadow;
1238 local_irq_restore(flags);
1239 }
1240
1241
1242 static void e100_enable_txdma_channel(struct e100_serial *info)
1243 {
1244 unsigned long flags;
1245
1246 local_irq_save(flags);
1247 DFLOW(DEBUG_LOG(info->line, "enable_txdma_channel %i\n", info->line));
1248 /* Enable output DMA channel for the serial port in question */
1249 if (info->line == 0) {
1250 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma6);
1251 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma6, serial0);
1252 } else if (info->line == 1) {
1253 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma8);
1254 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma8, serial1);
1255 } else if (info->line == 2) {
1256 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma2);
1257 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma2, serial2);
1258 } else if (info->line == 3) {
1259 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma4);
1260 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma4, serial3);
1261 }
1262 *R_GEN_CONFIG = genconfig_shadow;
1263 local_irq_restore(flags);
1264 }
1265
1266 static void e100_disable_rxdma_channel(struct e100_serial *info)
1267 {
1268 unsigned long flags;
1269
1270 /* Disable input DMA channel for the serial port in question
1271 * ( set to something other than serialX)
1272 */
1273 local_irq_save(flags);
1274 if (info->line == 0) {
1275 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma7)) ==
1276 IO_STATE(R_GEN_CONFIG, dma7, serial0)) {
1277 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma7);
1278 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma7, unused);
1279 }
1280 } else if (info->line == 1) {
1281 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma9)) ==
1282 IO_STATE(R_GEN_CONFIG, dma9, serial1)) {
1283 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma9);
1284 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma9, usb);
1285 }
1286 } else if (info->line == 2) {
1287 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma3)) ==
1288 IO_STATE(R_GEN_CONFIG, dma3, serial2)) {
1289 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma3);
1290 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma3, par0);
1291 }
1292 } else if (info->line == 3) {
1293 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma5)) ==
1294 IO_STATE(R_GEN_CONFIG, dma5, serial3)) {
1295 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma5);
1296 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma5, par1);
1297 }
1298 }
1299 *R_GEN_CONFIG = genconfig_shadow;
1300 local_irq_restore(flags);
1301 }
1302
1303
1304 static void e100_enable_rxdma_channel(struct e100_serial *info)
1305 {
1306 unsigned long flags;
1307
1308 local_irq_save(flags);
1309 /* Enable input DMA channel for the serial port in question */
1310 if (info->line == 0) {
1311 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma7);
1312 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma7, serial0);
1313 } else if (info->line == 1) {
1314 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma9);
1315 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma9, serial1);
1316 } else if (info->line == 2) {
1317 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma3);
1318 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma3, serial2);
1319 } else if (info->line == 3) {
1320 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma5);
1321 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma5, serial3);
1322 }
1323 *R_GEN_CONFIG = genconfig_shadow;
1324 local_irq_restore(flags);
1325 }
1326
1327 #ifdef SERIAL_HANDLE_EARLY_ERRORS
1328 /* in order to detect and fix errors on the first byte
1329 we have to use the serial interrupts as well. */
1330
1331 static inline void
1332 e100_disable_serial_data_irq(struct e100_serial *info)
1333 {
1334 #ifdef SERIAL_DEBUG_INTR
1335 printk("ser_irq(%d): 0\n",info->line);
1336 #endif
1337 DINTR1(DEBUG_LOG(info->line,"IRQ disable data_irq %i\n", info->line));
1338 *R_IRQ_MASK1_CLR = (1U << (8+2*info->line));
1339 }
1340
1341 static inline void
1342 e100_enable_serial_data_irq(struct e100_serial *info)
1343 {
1344 #ifdef SERIAL_DEBUG_INTR
1345 printk("ser_irq(%d): 1\n",info->line);
1346 printk("**** %d = %d\n",
1347 (8+2*info->line),
1348 (1U << (8+2*info->line)));
1349 #endif
1350 DINTR1(DEBUG_LOG(info->line,"IRQ enable data_irq %i\n", info->line));
1351 *R_IRQ_MASK1_SET = (1U << (8+2*info->line));
1352 }
1353 #endif
1354
1355 static inline void
1356 e100_disable_serial_tx_ready_irq(struct e100_serial *info)
1357 {
1358 #ifdef SERIAL_DEBUG_INTR
1359 printk("ser_tx_irq(%d): 0\n",info->line);
1360 #endif
1361 DINTR1(DEBUG_LOG(info->line,"IRQ disable ready_irq %i\n", info->line));
1362 *R_IRQ_MASK1_CLR = (1U << (8+1+2*info->line));
1363 }
1364
1365 static inline void
1366 e100_enable_serial_tx_ready_irq(struct e100_serial *info)
1367 {
1368 #ifdef SERIAL_DEBUG_INTR
1369 printk("ser_tx_irq(%d): 1\n",info->line);
1370 printk("**** %d = %d\n",
1371 (8+1+2*info->line),
1372 (1U << (8+1+2*info->line)));
1373 #endif
1374 DINTR2(DEBUG_LOG(info->line,"IRQ enable ready_irq %i\n", info->line));
1375 *R_IRQ_MASK1_SET = (1U << (8+1+2*info->line));
1376 }
1377
1378 static inline void e100_enable_rx_irq(struct e100_serial *info)
1379 {
1380 if (info->uses_dma_in)
1381 e100_enable_rxdma_irq(info);
1382 else
1383 e100_enable_serial_data_irq(info);
1384 }
1385 static inline void e100_disable_rx_irq(struct e100_serial *info)
1386 {
1387 if (info->uses_dma_in)
1388 e100_disable_rxdma_irq(info);
1389 else
1390 e100_disable_serial_data_irq(info);
1391 }
1392
1393 #if defined(CONFIG_ETRAX_RS485)
1394 /* Enable RS-485 mode on selected port. This is UGLY. */
1395 static int
1396 e100_enable_rs485(struct tty_struct *tty, struct serial_rs485 *r)
1397 {
1398 struct e100_serial * info = (struct e100_serial *)tty->driver_data;
1399
1400 #if defined(CONFIG_ETRAX_RS485_ON_PA)
1401 *R_PORT_PA_DATA = port_pa_data_shadow |= (1 << rs485_pa_bit);
1402 #endif
1403 #if defined(CONFIG_ETRAX_RS485_ON_PORT_G)
1404 REG_SHADOW_SET(R_PORT_G_DATA, port_g_data_shadow,
1405 rs485_port_g_bit, 1);
1406 #endif
1407 #if defined(CONFIG_ETRAX_RS485_LTC1387)
1408 REG_SHADOW_SET(R_PORT_G_DATA, port_g_data_shadow,
1409 CONFIG_ETRAX_RS485_LTC1387_DXEN_PORT_G_BIT, 1);
1410 REG_SHADOW_SET(R_PORT_G_DATA, port_g_data_shadow,
1411 CONFIG_ETRAX_RS485_LTC1387_RXEN_PORT_G_BIT, 1);
1412 #endif
1413
1414 info->rs485.flags = r->flags;
1415 if (r->delay_rts_before_send >= 1000)
1416 info->rs485.delay_rts_before_send = 1000;
1417 else
1418 info->rs485.delay_rts_before_send = r->delay_rts_before_send;
1419 /* printk("rts: on send = %i, after = %i, enabled = %i",
1420 info->rs485.rts_on_send,
1421 info->rs485.rts_after_sent,
1422 info->rs485.enabled
1423 );
1424 */
1425 return 0;
1426 }
1427
1428 static int
1429 e100_write_rs485(struct tty_struct *tty,
1430 const unsigned char *buf, int count)
1431 {
1432 struct e100_serial * info = (struct e100_serial *)tty->driver_data;
1433 int old_value = (info->rs485.flags) & SER_RS485_ENABLED;
1434
1435 /* rs485 is always implicitly enabled if we're using the ioctl()
1436 * but it doesn't have to be set in the serial_rs485
1437 * (to be backward compatible with old apps)
1438 * So we store, set and restore it.
1439 */
1440 info->rs485.flags |= SER_RS485_ENABLED;
1441 /* rs_write now deals with RS485 if enabled */
1442 count = rs_write(tty, buf, count);
1443 if (!old_value)
1444 info->rs485.flags &= ~(SER_RS485_ENABLED);
1445 return count;
1446 }
1447
1448 #ifdef CONFIG_ETRAX_FAST_TIMER
1449 /* Timer function to toggle RTS when using FAST_TIMER */
1450 static void rs485_toggle_rts_timer_function(unsigned long data)
1451 {
1452 struct e100_serial *info = (struct e100_serial *)data;
1453
1454 fast_timers_rs485[info->line].function = NULL;
1455 e100_rts(info, (info->rs485.flags & SER_RS485_RTS_AFTER_SEND));
1456 #if defined(CONFIG_ETRAX_RS485_DISABLE_RECEIVER)
1457 e100_enable_rx(info);
1458 e100_enable_rx_irq(info);
1459 #endif
1460 }
1461 #endif
1462 #endif /* CONFIG_ETRAX_RS485 */
1463
1464 /*
1465 * ------------------------------------------------------------
1466 * rs_stop() and rs_start()
1467 *
1468 * This routines are called before setting or resetting tty->stopped.
1469 * They enable or disable transmitter using the XOFF registers, as necessary.
1470 * ------------------------------------------------------------
1471 */
1472
1473 static void
1474 rs_stop(struct tty_struct *tty)
1475 {
1476 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
1477 if (info) {
1478 unsigned long flags;
1479 unsigned long xoff;
1480
1481 local_irq_save(flags);
1482 DFLOW(DEBUG_LOG(info->line, "XOFF rs_stop xmit %i\n",
1483 CIRC_CNT(info->xmit.head,
1484 info->xmit.tail,SERIAL_XMIT_SIZE)));
1485
1486 xoff = IO_FIELD(R_SERIAL0_XOFF, xoff_char,
1487 STOP_CHAR(info->port.tty));
1488 xoff |= IO_STATE(R_SERIAL0_XOFF, tx_stop, stop);
1489 if (tty->termios->c_iflag & IXON ) {
1490 xoff |= IO_STATE(R_SERIAL0_XOFF, auto_xoff, enable);
1491 }
1492
1493 *((unsigned long *)&info->ioport[REG_XOFF]) = xoff;
1494 local_irq_restore(flags);
1495 }
1496 }
1497
1498 static void
1499 rs_start(struct tty_struct *tty)
1500 {
1501 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
1502 if (info) {
1503 unsigned long flags;
1504 unsigned long xoff;
1505
1506 local_irq_save(flags);
1507 DFLOW(DEBUG_LOG(info->line, "XOFF rs_start xmit %i\n",
1508 CIRC_CNT(info->xmit.head,
1509 info->xmit.tail,SERIAL_XMIT_SIZE)));
1510 xoff = IO_FIELD(R_SERIAL0_XOFF, xoff_char, STOP_CHAR(tty));
1511 xoff |= IO_STATE(R_SERIAL0_XOFF, tx_stop, enable);
1512 if (tty->termios->c_iflag & IXON ) {
1513 xoff |= IO_STATE(R_SERIAL0_XOFF, auto_xoff, enable);
1514 }
1515
1516 *((unsigned long *)&info->ioport[REG_XOFF]) = xoff;
1517 if (!info->uses_dma_out &&
1518 info->xmit.head != info->xmit.tail && info->xmit.buf)
1519 e100_enable_serial_tx_ready_irq(info);
1520
1521 local_irq_restore(flags);
1522 }
1523 }
1524
1525 /*
1526 * ----------------------------------------------------------------------
1527 *
1528 * Here starts the interrupt handling routines. All of the following
1529 * subroutines are declared as inline and are folded into
1530 * rs_interrupt(). They were separated out for readability's sake.
1531 *
1532 * Note: rs_interrupt() is a "fast" interrupt, which means that it
1533 * runs with interrupts turned off. People who may want to modify
1534 * rs_interrupt() should try to keep the interrupt handler as fast as
1535 * possible. After you are done making modifications, it is not a bad
1536 * idea to do:
1537 *
1538 * gcc -S -DKERNEL -Wall -Wstrict-prototypes -O6 -fomit-frame-pointer serial.c
1539 *
1540 * and look at the resulting assemble code in serial.s.
1541 *
1542 * - Ted Ts'o (tytso@mit.edu), 7-Mar-93
1543 * -----------------------------------------------------------------------
1544 */
1545
1546 /*
1547 * This routine is used by the interrupt handler to schedule
1548 * processing in the software interrupt portion of the driver.
1549 */
1550 static void rs_sched_event(struct e100_serial *info, int event)
1551 {
1552 if (info->event & (1 << event))
1553 return;
1554 info->event |= 1 << event;
1555 schedule_work(&info->work);
1556 }
1557
1558 /* The output DMA channel is free - use it to send as many chars as possible
1559 * NOTES:
1560 * We don't pay attention to info->x_char, which means if the TTY wants to
1561 * use XON/XOFF it will set info->x_char but we won't send any X char!
1562 *
1563 * To implement this, we'd just start a DMA send of 1 byte pointing at a
1564 * buffer containing the X char, and skip updating xmit. We'd also have to
1565 * check if the last sent char was the X char when we enter this function
1566 * the next time, to avoid updating xmit with the sent X value.
1567 */
1568
1569 static void
1570 transmit_chars_dma(struct e100_serial *info)
1571 {
1572 unsigned int c, sentl;
1573 struct etrax_dma_descr *descr;
1574
1575 #ifdef CONFIG_SVINTO_SIM
1576 /* This will output too little if tail is not 0 always since
1577 * we don't reloop to send the other part. Anyway this SHOULD be a
1578 * no-op - transmit_chars_dma would never really be called during sim
1579 * since rs_write does not write into the xmit buffer then.
1580 */
1581 if (info->xmit.tail)
1582 printk("Error in serial.c:transmit_chars-dma(), tail!=0\n");
1583 if (info->xmit.head != info->xmit.tail) {
1584 SIMCOUT(info->xmit.buf + info->xmit.tail,
1585 CIRC_CNT(info->xmit.head,
1586 info->xmit.tail,
1587 SERIAL_XMIT_SIZE));
1588 info->xmit.head = info->xmit.tail; /* move back head */
1589 info->tr_running = 0;
1590 }
1591 return;
1592 #endif
1593 /* acknowledge both dma_descr and dma_eop irq in R_DMA_CHx_CLR_INTR */
1594 *info->oclrintradr =
1595 IO_STATE(R_DMA_CH6_CLR_INTR, clr_descr, do) |
1596 IO_STATE(R_DMA_CH6_CLR_INTR, clr_eop, do);
1597
1598 #ifdef SERIAL_DEBUG_INTR
1599 if (info->line == SERIAL_DEBUG_LINE)
1600 printk("tc\n");
1601 #endif
1602 if (!info->tr_running) {
1603 /* weirdo... we shouldn't get here! */
1604 printk(KERN_WARNING "Achtung: transmit_chars_dma with !tr_running\n");
1605 return;
1606 }
1607
1608 descr = &info->tr_descr;
1609
1610 /* first get the amount of bytes sent during the last DMA transfer,
1611 and update xmit accordingly */
1612
1613 /* if the stop bit was not set, all data has been sent */
1614 if (!(descr->status & d_stop)) {
1615 sentl = descr->sw_len;
1616 } else
1617 /* otherwise we find the amount of data sent here */
1618 sentl = descr->hw_len;
1619
1620 DFLOW(DEBUG_LOG(info->line, "TX %i done\n", sentl));
1621
1622 /* update stats */
1623 info->icount.tx += sentl;
1624
1625 /* update xmit buffer */
1626 info->xmit.tail = (info->xmit.tail + sentl) & (SERIAL_XMIT_SIZE - 1);
1627
1628 /* if there is only a few chars left in the buf, wake up the blocked
1629 write if any */
1630 if (CIRC_CNT(info->xmit.head,
1631 info->xmit.tail,
1632 SERIAL_XMIT_SIZE) < WAKEUP_CHARS)
1633 rs_sched_event(info, RS_EVENT_WRITE_WAKEUP);
1634
1635 /* find out the largest amount of consecutive bytes we want to send now */
1636
1637 c = CIRC_CNT_TO_END(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE);
1638
1639 /* Don't send all in one DMA transfer - divide it so we wake up
1640 * application before all is sent
1641 */
1642
1643 if (c >= 4*WAKEUP_CHARS)
1644 c = c/2;
1645
1646 if (c <= 0) {
1647 /* our job here is done, don't schedule any new DMA transfer */
1648 info->tr_running = 0;
1649
1650 #if defined(CONFIG_ETRAX_RS485) && defined(CONFIG_ETRAX_FAST_TIMER)
1651 if (info->rs485.flags & SER_RS485_ENABLED) {
1652 /* Set a short timer to toggle RTS */
1653 start_one_shot_timer(&fast_timers_rs485[info->line],
1654 rs485_toggle_rts_timer_function,
1655 (unsigned long)info,
1656 info->char_time_usec*2,
1657 "RS-485");
1658 }
1659 #endif /* RS485 */
1660 return;
1661 }
1662
1663 /* ok we can schedule a dma send of c chars starting at info->xmit.tail */
1664 /* set up the descriptor correctly for output */
1665 DFLOW(DEBUG_LOG(info->line, "TX %i\n", c));
1666 descr->ctrl = d_int | d_eol | d_wait; /* Wait needed for tty_wait_until_sent() */
1667 descr->sw_len = c;
1668 descr->buf = virt_to_phys(info->xmit.buf + info->xmit.tail);
1669 descr->status = 0;
1670
1671 *info->ofirstadr = virt_to_phys(descr); /* write to R_DMAx_FIRST */
1672 *info->ocmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, start);
1673
1674 /* DMA is now running (hopefully) */
1675 } /* transmit_chars_dma */
1676
1677 static void
1678 start_transmit(struct e100_serial *info)
1679 {
1680
1681 info->tr_descr.sw_len = 0;
1682 info->tr_descr.hw_len = 0;
1683 info->tr_descr.status = 0;
1684 info->tr_running = 1;
1685 if (info->uses_dma_out)
1686 transmit_chars_dma(info);
1687 else
1688 e100_enable_serial_tx_ready_irq(info);
1689 } /* start_transmit */
1690
1691 #ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER
1692 static int serial_fast_timer_started = 0;
1693 static int serial_fast_timer_expired = 0;
1694 static void flush_timeout_function(unsigned long data);
1695 #define START_FLUSH_FAST_TIMER_TIME(info, string, usec) {\
1696 unsigned long timer_flags; \
1697 local_irq_save(timer_flags); \
1698 if (fast_timers[info->line].function == NULL) { \
1699 serial_fast_timer_started++; \
1700 TIMERD(DEBUG_LOG(info->line, "start_timer %i ", info->line)); \
1701 TIMERD(DEBUG_LOG(info->line, "num started: %i\n", serial_fast_timer_started)); \
1702 start_one_shot_timer(&fast_timers[info->line], \
1703 flush_timeout_function, \
1704 (unsigned long)info, \
1705 (usec), \
1706 string); \
1707 } \
1708 else { \
1709 TIMERD(DEBUG_LOG(info->line, "timer %i already running\n", info->line)); \
1710 } \
1711 local_irq_restore(timer_flags); \
1712 }
1713 #define START_FLUSH_FAST_TIMER(info, string) START_FLUSH_FAST_TIMER_TIME(info, string, info->flush_time_usec)
1714
1715 #else
1716 #define START_FLUSH_FAST_TIMER_TIME(info, string, usec)
1717 #define START_FLUSH_FAST_TIMER(info, string)
1718 #endif
1719
1720 static struct etrax_recv_buffer *
1721 alloc_recv_buffer(unsigned int size)
1722 {
1723 struct etrax_recv_buffer *buffer;
1724
1725 if (!(buffer = kmalloc(sizeof *buffer + size, GFP_ATOMIC)))
1726 return NULL;
1727
1728 buffer->next = NULL;
1729 buffer->length = 0;
1730 buffer->error = TTY_NORMAL;
1731
1732 return buffer;
1733 }
1734
1735 static void
1736 append_recv_buffer(struct e100_serial *info, struct etrax_recv_buffer *buffer)
1737 {
1738 unsigned long flags;
1739
1740 local_irq_save(flags);
1741
1742 if (!info->first_recv_buffer)
1743 info->first_recv_buffer = buffer;
1744 else
1745 info->last_recv_buffer->next = buffer;
1746
1747 info->last_recv_buffer = buffer;
1748
1749 info->recv_cnt += buffer->length;
1750 if (info->recv_cnt > info->max_recv_cnt)
1751 info->max_recv_cnt = info->recv_cnt;
1752
1753 local_irq_restore(flags);
1754 }
1755
1756 static int
1757 add_char_and_flag(struct e100_serial *info, unsigned char data, unsigned char flag)
1758 {
1759 struct etrax_recv_buffer *buffer;
1760 if (info->uses_dma_in) {
1761 if (!(buffer = alloc_recv_buffer(4)))
1762 return 0;
1763
1764 buffer->length = 1;
1765 buffer->error = flag;
1766 buffer->buffer[0] = data;
1767
1768 append_recv_buffer(info, buffer);
1769
1770 info->icount.rx++;
1771 } else {
1772 struct tty_struct *tty = info->port.tty;
1773 tty_insert_flip_char(tty, data, flag);
1774 info->icount.rx++;
1775 }
1776
1777 return 1;
1778 }
1779
1780 static unsigned int handle_descr_data(struct e100_serial *info,
1781 struct etrax_dma_descr *descr,
1782 unsigned int recvl)
1783 {
1784 struct etrax_recv_buffer *buffer = phys_to_virt(descr->buf) - sizeof *buffer;
1785
1786 if (info->recv_cnt + recvl > 65536) {
1787 printk(KERN_CRIT
1788 "%s: Too much pending incoming serial data! Dropping %u bytes.\n", __func__, recvl);
1789 return 0;
1790 }
1791
1792 buffer->length = recvl;
1793
1794 if (info->errorcode == ERRCODE_SET_BREAK)
1795 buffer->error = TTY_BREAK;
1796 info->errorcode = 0;
1797
1798 append_recv_buffer(info, buffer);
1799
1800 if (!(buffer = alloc_recv_buffer(SERIAL_DESCR_BUF_SIZE)))
1801 panic("%s: Failed to allocate memory for receive buffer!\n", __func__);
1802
1803 descr->buf = virt_to_phys(buffer->buffer);
1804
1805 return recvl;
1806 }
1807
1808 static unsigned int handle_all_descr_data(struct e100_serial *info)
1809 {
1810 struct etrax_dma_descr *descr;
1811 unsigned int recvl;
1812 unsigned int ret = 0;
1813
1814 while (1)
1815 {
1816 descr = &info->rec_descr[info->cur_rec_descr];
1817
1818 if (descr == phys_to_virt(*info->idescradr))
1819 break;
1820
1821 if (++info->cur_rec_descr == SERIAL_RECV_DESCRIPTORS)
1822 info->cur_rec_descr = 0;
1823
1824 /* find out how many bytes were read */
1825
1826 /* if the eop bit was not set, all data has been received */
1827 if (!(descr->status & d_eop)) {
1828 recvl = descr->sw_len;
1829 } else {
1830 /* otherwise we find the amount of data received here */
1831 recvl = descr->hw_len;
1832 }
1833
1834 /* Reset the status information */
1835 descr->status = 0;
1836
1837 DFLOW( DEBUG_LOG(info->line, "RX %lu\n", recvl);
1838 if (info->port.tty->stopped) {
1839 unsigned char *buf = phys_to_virt(descr->buf);
1840 DEBUG_LOG(info->line, "rx 0x%02X\n", buf[0]);
1841 DEBUG_LOG(info->line, "rx 0x%02X\n", buf[1]);
1842 DEBUG_LOG(info->line, "rx 0x%02X\n", buf[2]);
1843 }
1844 );
1845
1846 /* update stats */
1847 info->icount.rx += recvl;
1848
1849 ret += handle_descr_data(info, descr, recvl);
1850 }
1851
1852 return ret;
1853 }
1854
1855 static void receive_chars_dma(struct e100_serial *info)
1856 {
1857 struct tty_struct *tty;
1858 unsigned char rstat;
1859
1860 #ifdef CONFIG_SVINTO_SIM
1861 /* No receive in the simulator. Will probably be when the rest of
1862 * the serial interface works, and this piece will just be removed.
1863 */
1864 return;
1865 #endif
1866
1867 /* Acknowledge both dma_descr and dma_eop irq in R_DMA_CHx_CLR_INTR */
1868 *info->iclrintradr =
1869 IO_STATE(R_DMA_CH6_CLR_INTR, clr_descr, do) |
1870 IO_STATE(R_DMA_CH6_CLR_INTR, clr_eop, do);
1871
1872 tty = info->port.tty;
1873 if (!tty) /* Something wrong... */
1874 return;
1875
1876 #ifdef SERIAL_HANDLE_EARLY_ERRORS
1877 if (info->uses_dma_in)
1878 e100_enable_serial_data_irq(info);
1879 #endif
1880
1881 if (info->errorcode == ERRCODE_INSERT_BREAK)
1882 add_char_and_flag(info, '\0', TTY_BREAK);
1883
1884 handle_all_descr_data(info);
1885
1886 /* Read the status register to detect errors */
1887 rstat = info->ioport[REG_STATUS];
1888 if (rstat & IO_MASK(R_SERIAL0_STATUS, xoff_detect) ) {
1889 DFLOW(DEBUG_LOG(info->line, "XOFF detect stat %x\n", rstat));
1890 }
1891
1892 if (rstat & SER_ERROR_MASK) {
1893 /* If we got an error, we must reset it by reading the
1894 * data_in field
1895 */
1896 unsigned char data = info->ioport[REG_DATA];
1897
1898 PROCSTAT(ser_stat[info->line].errors_cnt++);
1899 DEBUG_LOG(info->line, "#dERR: s d 0x%04X\n",
1900 ((rstat & SER_ERROR_MASK) << 8) | data);
1901
1902 if (rstat & SER_PAR_ERR_MASK)
1903 add_char_and_flag(info, data, TTY_PARITY);
1904 else if (rstat & SER_OVERRUN_MASK)
1905 add_char_and_flag(info, data, TTY_OVERRUN);
1906 else if (rstat & SER_FRAMING_ERR_MASK)
1907 add_char_and_flag(info, data, TTY_FRAME);
1908 }
1909
1910 START_FLUSH_FAST_TIMER(info, "receive_chars");
1911
1912 /* Restart the receiving DMA */
1913 *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, restart);
1914 }
1915
1916 static int start_recv_dma(struct e100_serial *info)
1917 {
1918 struct etrax_dma_descr *descr = info->rec_descr;
1919 struct etrax_recv_buffer *buffer;
1920 int i;
1921
1922 /* Set up the receiving descriptors */
1923 for (i = 0; i < SERIAL_RECV_DESCRIPTORS; i++) {
1924 if (!(buffer = alloc_recv_buffer(SERIAL_DESCR_BUF_SIZE)))
1925 panic("%s: Failed to allocate memory for receive buffer!\n", __func__);
1926
1927 descr[i].ctrl = d_int;
1928 descr[i].buf = virt_to_phys(buffer->buffer);
1929 descr[i].sw_len = SERIAL_DESCR_BUF_SIZE;
1930 descr[i].hw_len = 0;
1931 descr[i].status = 0;
1932 descr[i].next = virt_to_phys(&descr[i+1]);
1933 }
1934
1935 /* Link the last descriptor to the first */
1936 descr[i-1].next = virt_to_phys(&descr[0]);
1937
1938 /* Start with the first descriptor in the list */
1939 info->cur_rec_descr = 0;
1940
1941 /* Start the DMA */
1942 *info->ifirstadr = virt_to_phys(&descr[info->cur_rec_descr]);
1943 *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, start);
1944
1945 /* Input DMA should be running now */
1946 return 1;
1947 }
1948
1949 static void
1950 start_receive(struct e100_serial *info)
1951 {
1952 #ifdef CONFIG_SVINTO_SIM
1953 /* No receive in the simulator. Will probably be when the rest of
1954 * the serial interface works, and this piece will just be removed.
1955 */
1956 return;
1957 #endif
1958 if (info->uses_dma_in) {
1959 /* reset the input dma channel to be sure it works */
1960
1961 *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, reset);
1962 while (IO_EXTRACT(R_DMA_CH6_CMD, cmd, *info->icmdadr) ==
1963 IO_STATE_VALUE(R_DMA_CH6_CMD, cmd, reset));
1964
1965 start_recv_dma(info);
1966 }
1967 }
1968
1969
1970 /* the bits in the MASK2 register are laid out like this:
1971 DMAI_EOP DMAI_DESCR DMAO_EOP DMAO_DESCR
1972 where I is the input channel and O is the output channel for the port.
1973 info->irq is the bit number for the DMAO_DESCR so to check the others we
1974 shift info->irq to the left.
1975 */
1976
1977 /* dma output channel interrupt handler
1978 this interrupt is called from DMA2(ser2), DMA4(ser3), DMA6(ser0) or
1979 DMA8(ser1) when they have finished a descriptor with the intr flag set.
1980 */
1981
1982 static irqreturn_t
1983 tr_interrupt(int irq, void *dev_id)
1984 {
1985 struct e100_serial *info;
1986 unsigned long ireg;
1987 int i;
1988 int handled = 0;
1989
1990 #ifdef CONFIG_SVINTO_SIM
1991 /* No receive in the simulator. Will probably be when the rest of
1992 * the serial interface works, and this piece will just be removed.
1993 */
1994 {
1995 const char *s = "What? tr_interrupt in simulator??\n";
1996 SIMCOUT(s,strlen(s));
1997 }
1998 return IRQ_HANDLED;
1999 #endif
2000
2001 /* find out the line that caused this irq and get it from rs_table */
2002
2003 ireg = *R_IRQ_MASK2_RD; /* get the active irq bits for the dma channels */
2004
2005 for (i = 0; i < NR_PORTS; i++) {
2006 info = rs_table + i;
2007 if (!info->enabled || !info->uses_dma_out)
2008 continue;
2009 /* check for dma_descr (don't need to check for dma_eop in output dma for serial */
2010 if (ireg & info->irq) {
2011 handled = 1;
2012 /* we can send a new dma bunch. make it so. */
2013 DINTR2(DEBUG_LOG(info->line, "tr_interrupt %i\n", i));
2014 /* Read jiffies_usec first,
2015 * we want this time to be as late as possible
2016 */
2017 PROCSTAT(ser_stat[info->line].tx_dma_ints++);
2018 info->last_tx_active_usec = GET_JIFFIES_USEC();
2019 info->last_tx_active = jiffies;
2020 transmit_chars_dma(info);
2021 }
2022
2023 }
2024 return IRQ_RETVAL(handled);
2025 } /* tr_interrupt */
2026
2027 /* dma input channel interrupt handler */
2028
2029 static irqreturn_t
2030 rec_interrupt(int irq, void *dev_id)
2031 {
2032 struct e100_serial *info;
2033 unsigned long ireg;
2034 int i;
2035 int handled = 0;
2036
2037 #ifdef CONFIG_SVINTO_SIM
2038 /* No receive in the simulator. Will probably be when the rest of
2039 * the serial interface works, and this piece will just be removed.
2040 */
2041 {
2042 const char *s = "What? rec_interrupt in simulator??\n";
2043 SIMCOUT(s,strlen(s));
2044 }
2045 return IRQ_HANDLED;
2046 #endif
2047
2048 /* find out the line that caused this irq and get it from rs_table */
2049
2050 ireg = *R_IRQ_MASK2_RD; /* get the active irq bits for the dma channels */
2051
2052 for (i = 0; i < NR_PORTS; i++) {
2053 info = rs_table + i;
2054 if (!info->enabled || !info->uses_dma_in)
2055 continue;
2056 /* check for both dma_eop and dma_descr for the input dma channel */
2057 if (ireg & ((info->irq << 2) | (info->irq << 3))) {
2058 handled = 1;
2059 /* we have received something */
2060 receive_chars_dma(info);
2061 }
2062
2063 }
2064 return IRQ_RETVAL(handled);
2065 } /* rec_interrupt */
2066
2067 static int force_eop_if_needed(struct e100_serial *info)
2068 {
2069 /* We check data_avail bit to determine if data has
2070 * arrived since last time
2071 */
2072 unsigned char rstat = info->ioport[REG_STATUS];
2073
2074 /* error or datavail? */
2075 if (rstat & SER_ERROR_MASK) {
2076 /* Some error has occurred. If there has been valid data, an
2077 * EOP interrupt will be made automatically. If no data, the
2078 * normal ser_interrupt should be enabled and handle it.
2079 * So do nothing!
2080 */
2081 DEBUG_LOG(info->line, "timeout err: rstat 0x%03X\n",
2082 rstat | (info->line << 8));
2083 return 0;
2084 }
2085
2086 if (rstat & SER_DATA_AVAIL_MASK) {
2087 /* Ok data, no error, count it */
2088 TIMERD(DEBUG_LOG(info->line, "timeout: rstat 0x%03X\n",
2089 rstat | (info->line << 8)));
2090 /* Read data to clear status flags */
2091 (void)info->ioport[REG_DATA];
2092
2093 info->forced_eop = 0;
2094 START_FLUSH_FAST_TIMER(info, "magic");
2095 return 0;
2096 }
2097
2098 /* hit the timeout, force an EOP for the input
2099 * dma channel if we haven't already
2100 */
2101 if (!info->forced_eop) {
2102 info->forced_eop = 1;
2103 PROCSTAT(ser_stat[info->line].timeout_flush_cnt++);
2104 TIMERD(DEBUG_LOG(info->line, "timeout EOP %i\n", info->line));
2105 FORCE_EOP(info);
2106 }
2107
2108 return 1;
2109 }
2110
2111 static void flush_to_flip_buffer(struct e100_serial *info)
2112 {
2113 struct tty_struct *tty;
2114 struct etrax_recv_buffer *buffer;
2115 unsigned long flags;
2116
2117 local_irq_save(flags);
2118 tty = info->port.tty;
2119
2120 if (!tty) {
2121 local_irq_restore(flags);
2122 return;
2123 }
2124
2125 while ((buffer = info->first_recv_buffer) != NULL) {
2126 unsigned int count = buffer->length;
2127
2128 tty_insert_flip_string(tty, buffer->buffer, count);
2129 info->recv_cnt -= count;
2130
2131 if (count == buffer->length) {
2132 info->first_recv_buffer = buffer->next;
2133 kfree(buffer);
2134 } else {
2135 buffer->length -= count;
2136 memmove(buffer->buffer, buffer->buffer + count, buffer->length);
2137 buffer->error = TTY_NORMAL;
2138 }
2139 }
2140
2141 if (!info->first_recv_buffer)
2142 info->last_recv_buffer = NULL;
2143
2144 local_irq_restore(flags);
2145
2146 /* This includes a check for low-latency */
2147 tty_flip_buffer_push(tty);
2148 }
2149
2150 static void check_flush_timeout(struct e100_serial *info)
2151 {
2152 /* Flip what we've got (if we can) */
2153 flush_to_flip_buffer(info);
2154
2155 /* We might need to flip later, but not to fast
2156 * since the system is busy processing input... */
2157 if (info->first_recv_buffer)
2158 START_FLUSH_FAST_TIMER_TIME(info, "flip", 2000);
2159
2160 /* Force eop last, since data might have come while we're processing
2161 * and if we started the slow timer above, we won't start a fast
2162 * below.
2163 */
2164 force_eop_if_needed(info);
2165 }
2166
2167 #ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER
2168 static void flush_timeout_function(unsigned long data)
2169 {
2170 struct e100_serial *info = (struct e100_serial *)data;
2171
2172 fast_timers[info->line].function = NULL;
2173 serial_fast_timer_expired++;
2174 TIMERD(DEBUG_LOG(info->line, "flush_timout %i ", info->line));
2175 TIMERD(DEBUG_LOG(info->line, "num expired: %i\n", serial_fast_timer_expired));
2176 check_flush_timeout(info);
2177 }
2178
2179 #else
2180
2181 /* dma fifo/buffer timeout handler
2182 forces an end-of-packet for the dma input channel if no chars
2183 have been received for CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS/100 s.
2184 */
2185
2186 static struct timer_list flush_timer;
2187
2188 static void
2189 timed_flush_handler(unsigned long ptr)
2190 {
2191 struct e100_serial *info;
2192 int i;
2193
2194 #ifdef CONFIG_SVINTO_SIM
2195 return;
2196 #endif
2197
2198 for (i = 0; i < NR_PORTS; i++) {
2199 info = rs_table + i;
2200 if (info->uses_dma_in)
2201 check_flush_timeout(info);
2202 }
2203
2204 /* restart flush timer */
2205 mod_timer(&flush_timer, jiffies + CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS);
2206 }
2207 #endif
2208
2209 #ifdef SERIAL_HANDLE_EARLY_ERRORS
2210
2211 /* If there is an error (ie break) when the DMA is running and
2212 * there are no bytes in the fifo the DMA is stopped and we get no
2213 * eop interrupt. Thus we have to monitor the first bytes on a DMA
2214 * transfer, and if it is without error we can turn the serial
2215 * interrupts off.
2216 */
2217
2218 /*
2219 BREAK handling on ETRAX 100:
2220 ETRAX will generate interrupt although there is no stop bit between the
2221 characters.
2222
2223 Depending on how long the break sequence is, the end of the breaksequence
2224 will look differently:
2225 | indicates start/end of a character.
2226
2227 B= Break character (0x00) with framing error.
2228 E= Error byte with parity error received after B characters.
2229 F= "Faked" valid byte received immediately after B characters.
2230 V= Valid byte
2231
2232 1.
2233 B BL ___________________________ V
2234 .._|__________|__________| |valid data |
2235
2236 Multiple frame errors with data == 0x00 (B),
2237 the timing matches up "perfectly" so no extra ending char is detected.
2238 The RXD pin is 1 in the last interrupt, in that case
2239 we set info->errorcode = ERRCODE_INSERT_BREAK, but we can't really
2240 know if another byte will come and this really is case 2. below
2241 (e.g F=0xFF or 0xFE)
2242 If RXD pin is 0 we can expect another character (see 2. below).
2243
2244
2245 2.
2246
2247 B B E or F__________________..__ V
2248 .._|__________|__________|______ | |valid data
2249 "valid" or
2250 parity error
2251
2252 Multiple frame errors with data == 0x00 (B),
2253 but the part of the break trigs is interpreted as a start bit (and possibly
2254 some 0 bits followed by a number of 1 bits and a stop bit).
2255 Depending on parity settings etc. this last character can be either
2256 a fake "valid" char (F) or have a parity error (E).
2257
2258 If the character is valid it will be put in the buffer,
2259 we set info->errorcode = ERRCODE_SET_BREAK so the receive interrupt
2260 will set the flags so the tty will handle it,
2261 if it's an error byte it will not be put in the buffer
2262 and we set info->errorcode = ERRCODE_INSERT_BREAK.
2263
2264 To distinguish a V byte in 1. from an F byte in 2. we keep a timestamp
2265 of the last faulty char (B) and compares it with the current time:
2266 If the time elapsed time is less then 2*char_time_usec we will assume
2267 it's a faked F char and not a Valid char and set
2268 info->errorcode = ERRCODE_SET_BREAK.
2269
2270 Flaws in the above solution:
2271 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2272 We use the timer to distinguish a F character from a V character,
2273 if a V character is to close after the break we might make the wrong decision.
2274
2275 TODO: The break will be delayed until an F or V character is received.
2276
2277 */
2278
2279 static
2280 struct e100_serial * handle_ser_rx_interrupt_no_dma(struct e100_serial *info)
2281 {
2282 unsigned long data_read;
2283 struct tty_struct *tty = info->port.tty;
2284
2285 if (!tty) {
2286 printk("!NO TTY!\n");
2287 return info;
2288 }
2289
2290 /* Read data and status at the same time */
2291 data_read = *((unsigned long *)&info->ioport[REG_DATA_STATUS32]);
2292 more_data:
2293 if (data_read & IO_MASK(R_SERIAL0_READ, xoff_detect) ) {
2294 DFLOW(DEBUG_LOG(info->line, "XOFF detect\n", 0));
2295 }
2296 DINTR2(DEBUG_LOG(info->line, "ser_rx %c\n", IO_EXTRACT(R_SERIAL0_READ, data_in, data_read)));
2297
2298 if (data_read & ( IO_MASK(R_SERIAL0_READ, framing_err) |
2299 IO_MASK(R_SERIAL0_READ, par_err) |
2300 IO_MASK(R_SERIAL0_READ, overrun) )) {
2301 /* An error */
2302 info->last_rx_active_usec = GET_JIFFIES_USEC();
2303 info->last_rx_active = jiffies;
2304 DINTR1(DEBUG_LOG(info->line, "ser_rx err stat_data %04X\n", data_read));
2305 DLOG_INT_TRIG(
2306 if (!log_int_trig1_pos) {
2307 log_int_trig1_pos = log_int_pos;
2308 log_int(rdpc(), 0, 0);
2309 }
2310 );
2311
2312
2313 if ( ((data_read & IO_MASK(R_SERIAL0_READ, data_in)) == 0) &&
2314 (data_read & IO_MASK(R_SERIAL0_READ, framing_err)) ) {
2315 /* Most likely a break, but we get interrupts over and
2316 * over again.
2317 */
2318
2319 if (!info->break_detected_cnt) {
2320 DEBUG_LOG(info->line, "#BRK start\n", 0);
2321 }
2322 if (data_read & IO_MASK(R_SERIAL0_READ, rxd)) {
2323 /* The RX pin is high now, so the break
2324 * must be over, but....
2325 * we can't really know if we will get another
2326 * last byte ending the break or not.
2327 * And we don't know if the byte (if any) will
2328 * have an error or look valid.
2329 */
2330 DEBUG_LOG(info->line, "# BL BRK\n", 0);
2331 info->errorcode = ERRCODE_INSERT_BREAK;
2332 }
2333 info->break_detected_cnt++;
2334 } else {
2335 /* The error does not look like a break, but could be
2336 * the end of one
2337 */
2338 if (info->break_detected_cnt) {
2339 DEBUG_LOG(info->line, "EBRK %i\n", info->break_detected_cnt);
2340 info->errorcode = ERRCODE_INSERT_BREAK;
2341 } else {
2342 unsigned char data = IO_EXTRACT(R_SERIAL0_READ,
2343 data_in, data_read);
2344 char flag = TTY_NORMAL;
2345 if (info->errorcode == ERRCODE_INSERT_BREAK) {
2346 struct tty_struct *tty = info->port.tty;
2347 tty_insert_flip_char(tty, 0, flag);
2348 info->icount.rx++;
2349 }
2350
2351 if (data_read & IO_MASK(R_SERIAL0_READ, par_err)) {
2352 info->icount.parity++;
2353 flag = TTY_PARITY;
2354 } else if (data_read & IO_MASK(R_SERIAL0_READ, overrun)) {
2355 info->icount.overrun++;
2356 flag = TTY_OVERRUN;
2357 } else if (data_read & IO_MASK(R_SERIAL0_READ, framing_err)) {
2358 info->icount.frame++;
2359 flag = TTY_FRAME;
2360 }
2361 tty_insert_flip_char(tty, data, flag);
2362 info->errorcode = 0;
2363 }
2364 info->break_detected_cnt = 0;
2365 }
2366 } else if (data_read & IO_MASK(R_SERIAL0_READ, data_avail)) {
2367 /* No error */
2368 DLOG_INT_TRIG(
2369 if (!log_int_trig1_pos) {
2370 if (log_int_pos >= log_int_size) {
2371 log_int_pos = 0;
2372 }
2373 log_int_trig0_pos = log_int_pos;
2374 log_int(rdpc(), 0, 0);
2375 }
2376 );
2377 tty_insert_flip_char(tty,
2378 IO_EXTRACT(R_SERIAL0_READ, data_in, data_read),
2379 TTY_NORMAL);
2380 } else {
2381 DEBUG_LOG(info->line, "ser_rx int but no data_avail %08lX\n", data_read);
2382 }
2383
2384
2385 info->icount.rx++;
2386 data_read = *((unsigned long *)&info->ioport[REG_DATA_STATUS32]);
2387 if (data_read & IO_MASK(R_SERIAL0_READ, data_avail)) {
2388 DEBUG_LOG(info->line, "ser_rx %c in loop\n", IO_EXTRACT(R_SERIAL0_READ, data_in, data_read));
2389 goto more_data;
2390 }
2391
2392 tty_flip_buffer_push(info->port.tty);
2393 return info;
2394 }
2395
2396 static struct e100_serial* handle_ser_rx_interrupt(struct e100_serial *info)
2397 {
2398 unsigned char rstat;
2399
2400 #ifdef SERIAL_DEBUG_INTR
2401 printk("Interrupt from serport %d\n", i);
2402 #endif
2403 /* DEBUG_LOG(info->line, "ser_interrupt stat %03X\n", rstat | (i << 8)); */
2404 if (!info->uses_dma_in) {
2405 return handle_ser_rx_interrupt_no_dma(info);
2406 }
2407 /* DMA is used */
2408 rstat = info->ioport[REG_STATUS];
2409 if (rstat & IO_MASK(R_SERIAL0_STATUS, xoff_detect) ) {
2410 DFLOW(DEBUG_LOG(info->line, "XOFF detect\n", 0));
2411 }
2412
2413 if (rstat & SER_ERROR_MASK) {
2414 unsigned char data;
2415
2416 info->last_rx_active_usec = GET_JIFFIES_USEC();
2417 info->last_rx_active = jiffies;
2418 /* If we got an error, we must reset it by reading the
2419 * data_in field
2420 */
2421 data = info->ioport[REG_DATA];
2422 DINTR1(DEBUG_LOG(info->line, "ser_rx! %c\n", data));
2423 DINTR1(DEBUG_LOG(info->line, "ser_rx err stat %02X\n", rstat));
2424 if (!data && (rstat & SER_FRAMING_ERR_MASK)) {
2425 /* Most likely a break, but we get interrupts over and
2426 * over again.
2427 */
2428
2429 if (!info->break_detected_cnt) {
2430 DEBUG_LOG(info->line, "#BRK start\n", 0);
2431 }
2432 if (rstat & SER_RXD_MASK) {
2433 /* The RX pin is high now, so the break
2434 * must be over, but....
2435 * we can't really know if we will get another
2436 * last byte ending the break or not.
2437 * And we don't know if the byte (if any) will
2438 * have an error or look valid.
2439 */
2440 DEBUG_LOG(info->line, "# BL BRK\n", 0);
2441 info->errorcode = ERRCODE_INSERT_BREAK;
2442 }
2443 info->break_detected_cnt++;
2444 } else {
2445 /* The error does not look like a break, but could be
2446 * the end of one
2447 */
2448 if (info->break_detected_cnt) {
2449 DEBUG_LOG(info->line, "EBRK %i\n", info->break_detected_cnt);
2450 info->errorcode = ERRCODE_INSERT_BREAK;
2451 } else {
2452 if (info->errorcode == ERRCODE_INSERT_BREAK) {
2453 info->icount.brk++;
2454 add_char_and_flag(info, '\0', TTY_BREAK);
2455 }
2456
2457 if (rstat & SER_PAR_ERR_MASK) {
2458 info->icount.parity++;
2459 add_char_and_flag(info, data, TTY_PARITY);
2460 } else if (rstat & SER_OVERRUN_MASK) {
2461 info->icount.overrun++;
2462 add_char_and_flag(info, data, TTY_OVERRUN);
2463 } else if (rstat & SER_FRAMING_ERR_MASK) {
2464 info->icount.frame++;
2465 add_char_and_flag(info, data, TTY_FRAME);
2466 }
2467
2468 info->errorcode = 0;
2469 }
2470 info->break_detected_cnt = 0;
2471 DEBUG_LOG(info->line, "#iERR s d %04X\n",
2472 ((rstat & SER_ERROR_MASK) << 8) | data);
2473 }
2474 PROCSTAT(ser_stat[info->line].early_errors_cnt++);
2475 } else { /* It was a valid byte, now let the DMA do the rest */
2476 unsigned long curr_time_u = GET_JIFFIES_USEC();
2477 unsigned long curr_time = jiffies;
2478
2479 if (info->break_detected_cnt) {
2480 /* Detect if this character is a new valid char or the
2481 * last char in a break sequence: If LSBits are 0 and
2482 * MSBits are high AND the time is close to the
2483 * previous interrupt we should discard it.
2484 */
2485 long elapsed_usec =
2486 (curr_time - info->last_rx_active) * (1000000/HZ) +
2487 curr_time_u - info->last_rx_active_usec;
2488 if (elapsed_usec < 2*info->char_time_usec) {
2489 DEBUG_LOG(info->line, "FBRK %i\n", info->line);
2490 /* Report as BREAK (error) and let
2491 * receive_chars_dma() handle it
2492 */
2493 info->errorcode = ERRCODE_SET_BREAK;
2494 } else {
2495 DEBUG_LOG(info->line, "Not end of BRK (V)%i\n", info->line);
2496 }
2497 DEBUG_LOG(info->line, "num brk %i\n", info->break_detected_cnt);
2498 }
2499
2500 #ifdef SERIAL_DEBUG_INTR
2501 printk("** OK, disabling ser_interrupts\n");
2502 #endif
2503 e100_disable_serial_data_irq(info);
2504 DINTR2(DEBUG_LOG(info->line, "ser_rx OK %d\n", info->line));
2505 info->break_detected_cnt = 0;
2506
2507 PROCSTAT(ser_stat[info->line].ser_ints_ok_cnt++);
2508 }
2509 /* Restarting the DMA never hurts */
2510 *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, restart);
2511 START_FLUSH_FAST_TIMER(info, "ser_int");
2512 return info;
2513 } /* handle_ser_rx_interrupt */
2514
2515 static void handle_ser_tx_interrupt(struct e100_serial *info)
2516 {
2517 unsigned long flags;
2518
2519 if (info->x_char) {
2520 unsigned char rstat;
2521 DFLOW(DEBUG_LOG(info->line, "tx_int: xchar 0x%02X\n", info->x_char));
2522 local_irq_save(flags);
2523 rstat = info->ioport[REG_STATUS];
2524 DFLOW(DEBUG_LOG(info->line, "stat %x\n", rstat));
2525
2526 info->ioport[REG_TR_DATA] = info->x_char;
2527 info->icount.tx++;
2528 info->x_char = 0;
2529 /* We must enable since it is disabled in ser_interrupt */
2530 e100_enable_serial_tx_ready_irq(info);
2531 local_irq_restore(flags);
2532 return;
2533 }
2534 if (info->uses_dma_out) {
2535 unsigned char rstat;
2536 int i;
2537 /* We only use normal tx interrupt when sending x_char */
2538 DFLOW(DEBUG_LOG(info->line, "tx_int: xchar sent\n", 0));
2539 local_irq_save(flags);
2540 rstat = info->ioport[REG_STATUS];
2541 DFLOW(DEBUG_LOG(info->line, "stat %x\n", rstat));
2542 e100_disable_serial_tx_ready_irq(info);
2543 if (info->port.tty->stopped)
2544 rs_stop(info->port.tty);
2545 /* Enable the DMA channel and tell it to continue */
2546 e100_enable_txdma_channel(info);
2547 /* Wait 12 cycles before doing the DMA command */
2548 for(i = 6; i > 0; i--)
2549 nop();
2550
2551 *info->ocmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, continue);
2552 local_irq_restore(flags);
2553 return;
2554 }
2555 /* Normal char-by-char interrupt */
2556 if (info->xmit.head == info->xmit.tail
2557 || info->port.tty->stopped
2558 || info->port.tty->hw_stopped) {
2559 DFLOW(DEBUG_LOG(info->line, "tx_int: stopped %i\n",
2560 info->port.tty->stopped));
2561 e100_disable_serial_tx_ready_irq(info);
2562 info->tr_running = 0;
2563 return;
2564 }
2565 DINTR2(DEBUG_LOG(info->line, "tx_int %c\n", info->xmit.buf[info->xmit.tail]));
2566 /* Send a byte, rs485 timing is critical so turn of ints */
2567 local_irq_save(flags);
2568 info->ioport[REG_TR_DATA] = info->xmit.buf[info->xmit.tail];
2569 info->xmit.tail = (info->xmit.tail + 1) & (SERIAL_XMIT_SIZE-1);
2570 info->icount.tx++;
2571 if (info->xmit.head == info->xmit.tail) {
2572 #if defined(CONFIG_ETRAX_RS485) && defined(CONFIG_ETRAX_FAST_TIMER)
2573 if (info->rs485.flags & SER_RS485_ENABLED) {
2574 /* Set a short timer to toggle RTS */
2575 start_one_shot_timer(&fast_timers_rs485[info->line],
2576 rs485_toggle_rts_timer_function,
2577 (unsigned long)info,
2578 info->char_time_usec*2,
2579 "RS-485");
2580 }
2581 #endif /* RS485 */
2582 info->last_tx_active_usec = GET_JIFFIES_USEC();
2583 info->last_tx_active = jiffies;
2584 e100_disable_serial_tx_ready_irq(info);
2585 info->tr_running = 0;
2586 DFLOW(DEBUG_LOG(info->line, "tx_int: stop2\n", 0));
2587 } else {
2588 /* We must enable since it is disabled in ser_interrupt */
2589 e100_enable_serial_tx_ready_irq(info);
2590 }
2591 local_irq_restore(flags);
2592
2593 if (CIRC_CNT(info->xmit.head,
2594 info->xmit.tail,
2595 SERIAL_XMIT_SIZE) < WAKEUP_CHARS)
2596 rs_sched_event(info, RS_EVENT_WRITE_WAKEUP);
2597
2598 } /* handle_ser_tx_interrupt */
2599
2600 /* result of time measurements:
2601 * RX duration 54-60 us when doing something, otherwise 6-9 us
2602 * ser_int duration: just sending: 8-15 us normally, up to 73 us
2603 */
2604 static irqreturn_t
2605 ser_interrupt(int irq, void *dev_id)
2606 {
2607 static volatile int tx_started = 0;
2608 struct e100_serial *info;
2609 int i;
2610 unsigned long flags;
2611 unsigned long irq_mask1_rd;
2612 unsigned long data_mask = (1 << (8+2*0)); /* ser0 data_avail */
2613 int handled = 0;
2614 static volatile unsigned long reentered_ready_mask = 0;
2615
2616 local_irq_save(flags);
2617 irq_mask1_rd = *R_IRQ_MASK1_RD;
2618 /* First handle all rx interrupts with ints disabled */
2619 info = rs_table;
2620 irq_mask1_rd &= e100_ser_int_mask;
2621 for (i = 0; i < NR_PORTS; i++) {
2622 /* Which line caused the data irq? */
2623 if (irq_mask1_rd & data_mask) {
2624 handled = 1;
2625 handle_ser_rx_interrupt(info);
2626 }
2627 info += 1;
2628 data_mask <<= 2;
2629 }
2630 /* Handle tx interrupts with interrupts enabled so we
2631 * can take care of new data interrupts while transmitting
2632 * We protect the tx part with the tx_started flag.
2633 * We disable the tr_ready interrupts we are about to handle and
2634 * unblock the serial interrupt so new serial interrupts may come.
2635 *
2636 * If we get a new interrupt:
2637 * - it migth be due to synchronous serial ports.
2638 * - serial irq will be blocked by general irq handler.
2639 * - async data will be handled above (sync will be ignored).
2640 * - tx_started flag will prevent us from trying to send again and
2641 * we will exit fast - no need to unblock serial irq.
2642 * - Next (sync) serial interrupt handler will be runned with
2643 * disabled interrupt due to restore_flags() at end of function,
2644 * so sync handler will not be preempted or reentered.
2645 */
2646 if (!tx_started) {
2647 unsigned long ready_mask;
2648 unsigned long
2649 tx_started = 1;
2650 /* Only the tr_ready interrupts left */
2651 irq_mask1_rd &= (IO_MASK(R_IRQ_MASK1_RD, ser0_ready) |
2652 IO_MASK(R_IRQ_MASK1_RD, ser1_ready) |
2653 IO_MASK(R_IRQ_MASK1_RD, ser2_ready) |
2654 IO_MASK(R_IRQ_MASK1_RD, ser3_ready));
2655 while (irq_mask1_rd) {
2656 /* Disable those we are about to handle */
2657 *R_IRQ_MASK1_CLR = irq_mask1_rd;
2658 /* Unblock the serial interrupt */
2659 *R_VECT_MASK_SET = IO_STATE(R_VECT_MASK_SET, serial, set);
2660
2661 local_irq_enable();
2662 ready_mask = (1 << (8+1+2*0)); /* ser0 tr_ready */
2663 info = rs_table;
2664 for (i = 0; i < NR_PORTS; i++) {
2665 /* Which line caused the ready irq? */
2666 if (irq_mask1_rd & ready_mask) {
2667 handled = 1;
2668 handle_ser_tx_interrupt(info);
2669 }
2670 info += 1;
2671 ready_mask <<= 2;
2672 }
2673 /* handle_ser_tx_interrupt enables tr_ready interrupts */
2674 local_irq_disable();
2675 /* Handle reentered TX interrupt */
2676 irq_mask1_rd = reentered_ready_mask;
2677 }
2678 local_irq_disable();
2679 tx_started = 0;
2680 } else {
2681 unsigned long ready_mask;
2682 ready_mask = irq_mask1_rd & (IO_MASK(R_IRQ_MASK1_RD, ser0_ready) |
2683 IO_MASK(R_IRQ_MASK1_RD, ser1_ready) |
2684 IO_MASK(R_IRQ_MASK1_RD, ser2_ready) |
2685 IO_MASK(R_IRQ_MASK1_RD, ser3_ready));
2686 if (ready_mask) {
2687 reentered_ready_mask |= ready_mask;
2688 /* Disable those we are about to handle */
2689 *R_IRQ_MASK1_CLR = ready_mask;
2690 DFLOW(DEBUG_LOG(SERIAL_DEBUG_LINE, "ser_int reentered with TX %X\n", ready_mask));
2691 }
2692 }
2693
2694 local_irq_restore(flags);
2695 return IRQ_RETVAL(handled);
2696 } /* ser_interrupt */
2697 #endif
2698
2699 /*
2700 * -------------------------------------------------------------------
2701 * Here ends the serial interrupt routines.
2702 * -------------------------------------------------------------------
2703 */
2704
2705 /*
2706 * This routine is used to handle the "bottom half" processing for the
2707 * serial driver, known also the "software interrupt" processing.
2708 * This processing is done at the kernel interrupt level, after the
2709 * rs_interrupt() has returned, BUT WITH INTERRUPTS TURNED ON. This
2710 * is where time-consuming activities which can not be done in the
2711 * interrupt driver proper are done; the interrupt driver schedules
2712 * them using rs_sched_event(), and they get done here.
2713 */
2714 static void
2715 do_softint(struct work_struct *work)
2716 {
2717 struct e100_serial *info;
2718 struct tty_struct *tty;
2719
2720 info = container_of(work, struct e100_serial, work);
2721
2722 tty = info->port.tty;
2723 if (!tty)
2724 return;
2725
2726 if (test_and_clear_bit(RS_EVENT_WRITE_WAKEUP, &info->event))
2727 tty_wakeup(tty);
2728 }
2729
2730 static int
2731 startup(struct e100_serial * info)
2732 {
2733 unsigned long flags;
2734 unsigned long xmit_page;
2735 int i;
2736
2737 xmit_page = get_zeroed_page(GFP_KERNEL);
2738 if (!xmit_page)
2739 return -ENOMEM;
2740
2741 local_irq_save(flags);
2742
2743 /* if it was already initialized, skip this */
2744
2745 if (info->flags & ASYNC_INITIALIZED) {
2746 local_irq_restore(flags);
2747 free_page(xmit_page);
2748 return 0;
2749 }
2750
2751 if (info->xmit.buf)
2752 free_page(xmit_page);
2753 else
2754 info->xmit.buf = (unsigned char *) xmit_page;
2755
2756 #ifdef SERIAL_DEBUG_OPEN
2757 printk("starting up ttyS%d (xmit_buf 0x%p)...\n", info->line, info->xmit.buf);
2758 #endif
2759
2760 #ifdef CONFIG_SVINTO_SIM
2761 /* Bits and pieces collected from below. Better to have them
2762 in one ifdef:ed clause than to mix in a lot of ifdefs,
2763 right? */
2764 if (info->port.tty)
2765 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
2766
2767 info->xmit.head = info->xmit.tail = 0;
2768 info->first_recv_buffer = info->last_recv_buffer = NULL;
2769 info->recv_cnt = info->max_recv_cnt = 0;
2770
2771 for (i = 0; i < SERIAL_RECV_DESCRIPTORS; i++)
2772 info->rec_descr[i].buf = NULL;
2773
2774 /* No real action in the simulator, but may set info important
2775 to ioctl. */
2776 change_speed(info);
2777 #else
2778
2779 /*
2780 * Clear the FIFO buffers and disable them
2781 * (they will be reenabled in change_speed())
2782 */
2783
2784 /*
2785 * Reset the DMA channels and make sure their interrupts are cleared
2786 */
2787
2788 if (info->dma_in_enabled) {
2789 info->uses_dma_in = 1;
2790 e100_enable_rxdma_channel(info);
2791
2792 *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, reset);
2793
2794 /* Wait until reset cycle is complete */
2795 while (IO_EXTRACT(R_DMA_CH6_CMD, cmd, *info->icmdadr) ==
2796 IO_STATE_VALUE(R_DMA_CH6_CMD, cmd, reset));
2797
2798 /* Make sure the irqs are cleared */
2799 *info->iclrintradr =
2800 IO_STATE(R_DMA_CH6_CLR_INTR, clr_descr, do) |
2801 IO_STATE(R_DMA_CH6_CLR_INTR, clr_eop, do);
2802 } else {
2803 e100_disable_rxdma_channel(info);
2804 }
2805
2806 if (info->dma_out_enabled) {
2807 info->uses_dma_out = 1;
2808 e100_enable_txdma_channel(info);
2809 *info->ocmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, reset);
2810
2811 while (IO_EXTRACT(R_DMA_CH6_CMD, cmd, *info->ocmdadr) ==
2812 IO_STATE_VALUE(R_DMA_CH6_CMD, cmd, reset));
2813
2814 /* Make sure the irqs are cleared */
2815 *info->oclrintradr =
2816 IO_STATE(R_DMA_CH6_CLR_INTR, clr_descr, do) |
2817 IO_STATE(R_DMA_CH6_CLR_INTR, clr_eop, do);
2818 } else {
2819 e100_disable_txdma_channel(info);
2820 }
2821
2822 if (info->port.tty)
2823 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
2824
2825 info->xmit.head = info->xmit.tail = 0;
2826 info->first_recv_buffer = info->last_recv_buffer = NULL;
2827 info->recv_cnt = info->max_recv_cnt = 0;
2828
2829 for (i = 0; i < SERIAL_RECV_DESCRIPTORS; i++)
2830 info->rec_descr[i].buf = 0;
2831
2832 /*
2833 * and set the speed and other flags of the serial port
2834 * this will start the rx/tx as well
2835 */
2836 #ifdef SERIAL_HANDLE_EARLY_ERRORS
2837 e100_enable_serial_data_irq(info);
2838 #endif
2839 change_speed(info);
2840
2841 /* dummy read to reset any serial errors */
2842
2843 (void)info->ioport[REG_DATA];
2844
2845 /* enable the interrupts */
2846 if (info->uses_dma_out)
2847 e100_enable_txdma_irq(info);
2848
2849 e100_enable_rx_irq(info);
2850
2851 info->tr_running = 0; /* to be sure we don't lock up the transmitter */
2852
2853 /* setup the dma input descriptor and start dma */
2854
2855 start_receive(info);
2856
2857 /* for safety, make sure the descriptors last result is 0 bytes written */
2858
2859 info->tr_descr.sw_len = 0;
2860 info->tr_descr.hw_len = 0;
2861 info->tr_descr.status = 0;
2862
2863 /* enable RTS/DTR last */
2864
2865 e100_rts(info, 1);
2866 e100_dtr(info, 1);
2867
2868 #endif /* CONFIG_SVINTO_SIM */
2869
2870 info->flags |= ASYNC_INITIALIZED;
2871
2872 local_irq_restore(flags);
2873 return 0;
2874 }
2875
2876 /*
2877 * This routine will shutdown a serial port; interrupts are disabled, and
2878 * DTR is dropped if the hangup on close termio flag is on.
2879 */
2880 static void
2881 shutdown(struct e100_serial * info)
2882 {
2883 unsigned long flags;
2884 struct etrax_dma_descr *descr = info->rec_descr;
2885 struct etrax_recv_buffer *buffer;
2886 int i;
2887
2888 #ifndef CONFIG_SVINTO_SIM
2889 /* shut down the transmitter and receiver */
2890 DFLOW(DEBUG_LOG(info->line, "shutdown %i\n", info->line));
2891 e100_disable_rx(info);
2892 info->ioport[REG_TR_CTRL] = (info->tx_ctrl &= ~0x40);
2893
2894 /* disable interrupts, reset dma channels */
2895 if (info->uses_dma_in) {
2896 e100_disable_rxdma_irq(info);
2897 *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, reset);
2898 info->uses_dma_in = 0;
2899 } else {
2900 e100_disable_serial_data_irq(info);
2901 }
2902
2903 if (info->uses_dma_out) {
2904 e100_disable_txdma_irq(info);
2905 info->tr_running = 0;
2906 *info->ocmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, reset);
2907 info->uses_dma_out = 0;
2908 } else {
2909 e100_disable_serial_tx_ready_irq(info);
2910 info->tr_running = 0;
2911 }
2912
2913 #endif /* CONFIG_SVINTO_SIM */
2914
2915 if (!(info->flags & ASYNC_INITIALIZED))
2916 return;
2917
2918 #ifdef SERIAL_DEBUG_OPEN
2919 printk("Shutting down serial port %d (irq %d)....\n", info->line,
2920 info->irq);
2921 #endif
2922
2923 local_irq_save(flags);
2924
2925 if (info->xmit.buf) {
2926 free_page((unsigned long)info->xmit.buf);
2927 info->xmit.buf = NULL;
2928 }
2929
2930 for (i = 0; i < SERIAL_RECV_DESCRIPTORS; i++)
2931 if (descr[i].buf) {
2932 buffer = phys_to_virt(descr[i].buf) - sizeof *buffer;
2933 kfree(buffer);
2934 descr[i].buf = 0;
2935 }
2936
2937 if (!info->port.tty || (info->port.tty->termios->c_cflag & HUPCL)) {
2938 /* hang up DTR and RTS if HUPCL is enabled */
2939 e100_dtr(info, 0);
2940 e100_rts(info, 0); /* could check CRTSCTS before doing this */
2941 }
2942
2943 if (info->port.tty)
2944 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
2945
2946 info->flags &= ~ASYNC_INITIALIZED;
2947 local_irq_restore(flags);
2948 }
2949
2950
2951 /* change baud rate and other assorted parameters */
2952
2953 static void
2954 change_speed(struct e100_serial *info)
2955 {
2956 unsigned int cflag;
2957 unsigned long xoff;
2958 unsigned long flags;
2959 /* first some safety checks */
2960
2961 if (!info->port.tty || !info->port.tty->termios)
2962 return;
2963 if (!info->ioport)
2964 return;
2965
2966 cflag = info->port.tty->termios->c_cflag;
2967
2968 /* possibly, the tx/rx should be disabled first to do this safely */
2969
2970 /* change baud-rate and write it to the hardware */
2971 if ((info->flags & ASYNC_SPD_MASK) == ASYNC_SPD_CUST) {
2972 /* Special baudrate */
2973 u32 mask = 0xFF << (info->line*8); /* Each port has 8 bits */
2974 unsigned long alt_source =
2975 IO_STATE(R_ALT_SER_BAUDRATE, ser0_rec, normal) |
2976 IO_STATE(R_ALT_SER_BAUDRATE, ser0_tr, normal);
2977 /* R_ALT_SER_BAUDRATE selects the source */
2978 DBAUD(printk("Custom baudrate: baud_base/divisor %lu/%i\n",
2979 (unsigned long)info->baud_base, info->custom_divisor));
2980 if (info->baud_base == SERIAL_PRESCALE_BASE) {
2981 /* 0, 2-65535 (0=65536) */
2982 u16 divisor = info->custom_divisor;
2983 /* R_SERIAL_PRESCALE (upper 16 bits of R_CLOCK_PRESCALE) */
2984 /* baudrate is 3.125MHz/custom_divisor */
2985 alt_source =
2986 IO_STATE(R_ALT_SER_BAUDRATE, ser0_rec, prescale) |
2987 IO_STATE(R_ALT_SER_BAUDRATE, ser0_tr, prescale);
2988 alt_source = 0x11;
2989 DBAUD(printk("Writing SERIAL_PRESCALE: divisor %i\n", divisor));
2990 *R_SERIAL_PRESCALE = divisor;
2991 info->baud = SERIAL_PRESCALE_BASE/divisor;
2992 }
2993 #ifdef CONFIG_ETRAX_EXTERN_PB6CLK_ENABLED
2994 else if ((info->baud_base==CONFIG_ETRAX_EXTERN_PB6CLK_FREQ/8 &&
2995 info->custom_divisor == 1) ||
2996 (info->baud_base==CONFIG_ETRAX_EXTERN_PB6CLK_FREQ &&
2997 info->custom_divisor == 8)) {
2998 /* ext_clk selected */
2999 alt_source =
3000 IO_STATE(R_ALT_SER_BAUDRATE, ser0_rec, extern) |
3001 IO_STATE(R_ALT_SER_BAUDRATE, ser0_tr, extern);
3002 DBAUD(printk("using external baudrate: %lu\n", CONFIG_ETRAX_EXTERN_PB6CLK_FREQ/8));
3003 info->baud = CONFIG_ETRAX_EXTERN_PB6CLK_FREQ/8;
3004 }
3005 #endif
3006 else
3007 {
3008 /* Bad baudbase, we don't support using timer0
3009 * for baudrate.
3010 */
3011 printk(KERN_WARNING "Bad baud_base/custom_divisor: %lu/%i\n",
3012 (unsigned long)info->baud_base, info->custom_divisor);
3013 }
3014 r_alt_ser_baudrate_shadow &= ~mask;
3015 r_alt_ser_baudrate_shadow |= (alt_source << (info->line*8));
3016 *R_ALT_SER_BAUDRATE = r_alt_ser_baudrate_shadow;
3017 } else {
3018 /* Normal baudrate */
3019 /* Make sure we use normal baudrate */
3020 u32 mask = 0xFF << (info->line*8); /* Each port has 8 bits */
3021 unsigned long alt_source =
3022 IO_STATE(R_ALT_SER_BAUDRATE, ser0_rec, normal) |
3023 IO_STATE(R_ALT_SER_BAUDRATE, ser0_tr, normal);
3024 r_alt_ser_baudrate_shadow &= ~mask;
3025 r_alt_ser_baudrate_shadow |= (alt_source << (info->line*8));
3026 #ifndef CONFIG_SVINTO_SIM
3027 *R_ALT_SER_BAUDRATE = r_alt_ser_baudrate_shadow;
3028 #endif /* CONFIG_SVINTO_SIM */
3029
3030 info->baud = cflag_to_baud(cflag);
3031 #ifndef CONFIG_SVINTO_SIM
3032 info->ioport[REG_BAUD] = cflag_to_etrax_baud(cflag);
3033 #endif /* CONFIG_SVINTO_SIM */
3034 }
3035
3036 #ifndef CONFIG_SVINTO_SIM
3037 /* start with default settings and then fill in changes */
3038 local_irq_save(flags);
3039 /* 8 bit, no/even parity */
3040 info->rx_ctrl &= ~(IO_MASK(R_SERIAL0_REC_CTRL, rec_bitnr) |
3041 IO_MASK(R_SERIAL0_REC_CTRL, rec_par_en) |
3042 IO_MASK(R_SERIAL0_REC_CTRL, rec_par));
3043
3044 /* 8 bit, no/even parity, 1 stop bit, no cts */
3045 info->tx_ctrl &= ~(IO_MASK(R_SERIAL0_TR_CTRL, tr_bitnr) |
3046 IO_MASK(R_SERIAL0_TR_CTRL, tr_par_en) |
3047 IO_MASK(R_SERIAL0_TR_CTRL, tr_par) |
3048 IO_MASK(R_SERIAL0_TR_CTRL, stop_bits) |
3049 IO_MASK(R_SERIAL0_TR_CTRL, auto_cts));
3050
3051 if ((cflag & CSIZE) == CS7) {
3052 /* set 7 bit mode */
3053 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_bitnr, tr_7bit);
3054 info->rx_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_bitnr, rec_7bit);
3055 }
3056
3057 if (cflag & CSTOPB) {
3058 /* set 2 stop bit mode */
3059 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, stop_bits, two_bits);
3060 }
3061
3062 if (cflag & PARENB) {
3063 /* enable parity */
3064 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_par_en, enable);
3065 info->rx_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_par_en, enable);
3066 }
3067
3068 if (cflag & CMSPAR) {
3069 /* enable stick parity, PARODD mean Mark which matches ETRAX */
3070 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_stick_par, stick);
3071 info->rx_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_stick_par, stick);
3072 }
3073 if (cflag & PARODD) {
3074 /* set odd parity (or Mark if CMSPAR) */
3075 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_par, odd);
3076 info->rx_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_par, odd);
3077 }
3078
3079 if (cflag & CRTSCTS) {
3080 /* enable automatic CTS handling */
3081 DFLOW(DEBUG_LOG(info->line, "FLOW auto_cts enabled\n", 0));
3082 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, auto_cts, active);
3083 }
3084
3085 /* make sure the tx and rx are enabled */
3086
3087 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_enable, enable);
3088 info->rx_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_enable, enable);
3089
3090 /* actually write the control regs to the hardware */
3091
3092 info->ioport[REG_TR_CTRL] = info->tx_ctrl;
3093 info->ioport[REG_REC_CTRL] = info->rx_ctrl;
3094 xoff = IO_FIELD(R_SERIAL0_XOFF, xoff_char, STOP_CHAR(info->port.tty));
3095 xoff |= IO_STATE(R_SERIAL0_XOFF, tx_stop, enable);
3096 if (info->port.tty->termios->c_iflag & IXON ) {
3097 DFLOW(DEBUG_LOG(info->line, "FLOW XOFF enabled 0x%02X\n",
3098 STOP_CHAR(info->port.tty)));
3099 xoff |= IO_STATE(R_SERIAL0_XOFF, auto_xoff, enable);
3100 }
3101
3102 *((unsigned long *)&info->ioport[REG_XOFF]) = xoff;
3103 local_irq_restore(flags);
3104 #endif /* !CONFIG_SVINTO_SIM */
3105
3106 update_char_time(info);
3107
3108 } /* change_speed */
3109
3110 /* start transmitting chars NOW */
3111
3112 static void
3113 rs_flush_chars(struct tty_struct *tty)
3114 {
3115 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3116 unsigned long flags;
3117
3118 if (info->tr_running ||
3119 info->xmit.head == info->xmit.tail ||
3120 tty->stopped ||
3121 tty->hw_stopped ||
3122 !info->xmit.buf)
3123 return;
3124
3125 #ifdef SERIAL_DEBUG_FLOW
3126 printk("rs_flush_chars\n");
3127 #endif
3128
3129 /* this protection might not exactly be necessary here */
3130
3131 local_irq_save(flags);
3132 start_transmit(info);
3133 local_irq_restore(flags);
3134 }
3135
3136 static int rs_raw_write(struct tty_struct *tty,
3137 const unsigned char *buf, int count)
3138 {
3139 int c, ret = 0;
3140 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3141 unsigned long flags;
3142
3143 /* first some sanity checks */
3144
3145 if (!tty || !info->xmit.buf || !tmp_buf)
3146 return 0;
3147
3148 #ifdef SERIAL_DEBUG_DATA
3149 if (info->line == SERIAL_DEBUG_LINE)
3150 printk("rs_raw_write (%d), status %d\n",
3151 count, info->ioport[REG_STATUS]);
3152 #endif
3153
3154 #ifdef CONFIG_SVINTO_SIM
3155 /* Really simple. The output is here and now. */
3156 SIMCOUT(buf, count);
3157 return count;
3158 #endif
3159 local_save_flags(flags);
3160 DFLOW(DEBUG_LOG(info->line, "write count %i ", count));
3161 DFLOW(DEBUG_LOG(info->line, "ldisc %i\n", tty->ldisc.chars_in_buffer(tty)));
3162
3163
3164 /* The local_irq_disable/restore_flags pairs below are needed
3165 * because the DMA interrupt handler moves the info->xmit values.
3166 * the memcpy needs to be in the critical region unfortunately,
3167 * because we need to read xmit values, memcpy, write xmit values
3168 * in one atomic operation... this could perhaps be avoided by
3169 * more clever design.
3170 */
3171 local_irq_disable();
3172 while (count) {
3173 c = CIRC_SPACE_TO_END(info->xmit.head,
3174 info->xmit.tail,
3175 SERIAL_XMIT_SIZE);
3176
3177 if (count < c)
3178 c = count;
3179 if (c <= 0)
3180 break;
3181
3182 memcpy(info->xmit.buf + info->xmit.head, buf, c);
3183 info->xmit.head = (info->xmit.head + c) &
3184 (SERIAL_XMIT_SIZE-1);
3185 buf += c;
3186 count -= c;
3187 ret += c;
3188 }
3189 local_irq_restore(flags);
3190
3191 /* enable transmitter if not running, unless the tty is stopped
3192 * this does not need IRQ protection since if tr_running == 0
3193 * the IRQ's are not running anyway for this port.
3194 */
3195 DFLOW(DEBUG_LOG(info->line, "write ret %i\n", ret));
3196
3197 if (info->xmit.head != info->xmit.tail &&
3198 !tty->stopped &&
3199 !tty->hw_stopped &&
3200 !info->tr_running) {
3201 start_transmit(info);
3202 }
3203
3204 return ret;
3205 } /* raw_raw_write() */
3206
3207 static int
3208 rs_write(struct tty_struct *tty,
3209 const unsigned char *buf, int count)
3210 {
3211 #if defined(CONFIG_ETRAX_RS485)
3212 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3213
3214 if (info->rs485.flags & SER_RS485_ENABLED)
3215 {
3216 /* If we are in RS-485 mode, we need to toggle RTS and disable
3217 * the receiver before initiating a DMA transfer
3218 */
3219 #ifdef CONFIG_ETRAX_FAST_TIMER
3220 /* Abort any started timer */
3221 fast_timers_rs485[info->line].function = NULL;
3222 del_fast_timer(&fast_timers_rs485[info->line]);
3223 #endif
3224 e100_rts(info, (info->rs485.flags & SER_RS485_RTS_ON_SEND));
3225 #if defined(CONFIG_ETRAX_RS485_DISABLE_RECEIVER)
3226 e100_disable_rx(info);
3227 e100_enable_rx_irq(info);
3228 #endif
3229
3230 if (info->rs485.delay_rts_before_send > 0)
3231 msleep(info->rs485.delay_rts_before_send);
3232 }
3233 #endif /* CONFIG_ETRAX_RS485 */
3234
3235 count = rs_raw_write(tty, buf, count);
3236
3237 #if defined(CONFIG_ETRAX_RS485)
3238 if (info->rs485.flags & SER_RS485_ENABLED)
3239 {
3240 unsigned int val;
3241 /* If we are in RS-485 mode the following has to be done:
3242 * wait until DMA is ready
3243 * wait on transmit shift register
3244 * toggle RTS
3245 * enable the receiver
3246 */
3247
3248 /* Sleep until all sent */
3249 tty_wait_until_sent(tty, 0);
3250 #ifdef CONFIG_ETRAX_FAST_TIMER
3251 /* Now sleep a little more so that shift register is empty */
3252 schedule_usleep(info->char_time_usec * 2);
3253 #endif
3254 /* wait on transmit shift register */
3255 do{
3256 get_lsr_info(info, &val);
3257 }while (!(val & TIOCSER_TEMT));
3258
3259 e100_rts(info, (info->rs485.flags & SER_RS485_RTS_AFTER_SEND));
3260
3261 #if defined(CONFIG_ETRAX_RS485_DISABLE_RECEIVER)
3262 e100_enable_rx(info);
3263 e100_enable_rxdma_irq(info);
3264 #endif
3265 }
3266 #endif /* CONFIG_ETRAX_RS485 */
3267
3268 return count;
3269 } /* rs_write */
3270
3271
3272 /* how much space is available in the xmit buffer? */
3273
3274 static int
3275 rs_write_room(struct tty_struct *tty)
3276 {
3277 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3278
3279 return CIRC_SPACE(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE);
3280 }
3281
3282 /* How many chars are in the xmit buffer?
3283 * This does not include any chars in the transmitter FIFO.
3284 * Use wait_until_sent for waiting for FIFO drain.
3285 */
3286
3287 static int
3288 rs_chars_in_buffer(struct tty_struct *tty)
3289 {
3290 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3291
3292 return CIRC_CNT(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE);
3293 }
3294
3295 /* discard everything in the xmit buffer */
3296
3297 static void
3298 rs_flush_buffer(struct tty_struct *tty)
3299 {
3300 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3301 unsigned long flags;
3302
3303 local_irq_save(flags);
3304 info->xmit.head = info->xmit.tail = 0;
3305 local_irq_restore(flags);
3306
3307 tty_wakeup(tty);
3308 }
3309
3310 /*
3311 * This function is used to send a high-priority XON/XOFF character to
3312 * the device
3313 *
3314 * Since we use DMA we don't check for info->x_char in transmit_chars_dma(),
3315 * but we do it in handle_ser_tx_interrupt().
3316 * We disable DMA channel and enable tx ready interrupt and write the
3317 * character when possible.
3318 */
3319 static void rs_send_xchar(struct tty_struct *tty, char ch)
3320 {
3321 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3322 unsigned long flags;
3323 local_irq_save(flags);
3324 if (info->uses_dma_out) {
3325 /* Put the DMA on hold and disable the channel */
3326 *info->ocmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, hold);
3327 while (IO_EXTRACT(R_DMA_CH6_CMD, cmd, *info->ocmdadr) !=
3328 IO_STATE_VALUE(R_DMA_CH6_CMD, cmd, hold));
3329 e100_disable_txdma_channel(info);
3330 }
3331
3332 /* Must make sure transmitter is not stopped before we can transmit */
3333 if (tty->stopped)
3334 rs_start(tty);
3335
3336 /* Enable manual transmit interrupt and send from there */
3337 DFLOW(DEBUG_LOG(info->line, "rs_send_xchar 0x%02X\n", ch));
3338 info->x_char = ch;
3339 e100_enable_serial_tx_ready_irq(info);
3340 local_irq_restore(flags);
3341 }
3342
3343 /*
3344 * ------------------------------------------------------------
3345 * rs_throttle()
3346 *
3347 * This routine is called by the upper-layer tty layer to signal that
3348 * incoming characters should be throttled.
3349 * ------------------------------------------------------------
3350 */
3351 static void
3352 rs_throttle(struct tty_struct * tty)
3353 {
3354 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3355 #ifdef SERIAL_DEBUG_THROTTLE
3356 char buf[64];
3357
3358 printk("throttle %s: %lu....\n", tty_name(tty, buf),
3359 (unsigned long)tty->ldisc.chars_in_buffer(tty));
3360 #endif
3361 DFLOW(DEBUG_LOG(info->line,"rs_throttle %lu\n", tty->ldisc.chars_in_buffer(tty)));
3362
3363 /* Do RTS before XOFF since XOFF might take some time */
3364 if (tty->termios->c_cflag & CRTSCTS) {
3365 /* Turn off RTS line */
3366 e100_rts(info, 0);
3367 }
3368 if (I_IXOFF(tty))
3369 rs_send_xchar(tty, STOP_CHAR(tty));
3370
3371 }
3372
3373 static void
3374 rs_unthrottle(struct tty_struct * tty)
3375 {
3376 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3377 #ifdef SERIAL_DEBUG_THROTTLE
3378 char buf[64];
3379
3380 printk("unthrottle %s: %lu....\n", tty_name(tty, buf),
3381 (unsigned long)tty->ldisc.chars_in_buffer(tty));
3382 #endif
3383 DFLOW(DEBUG_LOG(info->line,"rs_unthrottle ldisc %d\n", tty->ldisc.chars_in_buffer(tty)));
3384 DFLOW(DEBUG_LOG(info->line,"rs_unthrottle flip.count: %i\n", tty->flip.count));
3385 /* Do RTS before XOFF since XOFF might take some time */
3386 if (tty->termios->c_cflag & CRTSCTS) {
3387 /* Assert RTS line */
3388 e100_rts(info, 1);
3389 }
3390
3391 if (I_IXOFF(tty)) {
3392 if (info->x_char)
3393 info->x_char = 0;
3394 else
3395 rs_send_xchar(tty, START_CHAR(tty));
3396 }
3397
3398 }
3399
3400 /*
3401 * ------------------------------------------------------------
3402 * rs_ioctl() and friends
3403 * ------------------------------------------------------------
3404 */
3405
3406 static int
3407 get_serial_info(struct e100_serial * info,
3408 struct serial_struct * retinfo)
3409 {
3410 struct serial_struct tmp;
3411
3412 /* this is all probably wrong, there are a lot of fields
3413 * here that we don't have in e100_serial and maybe we
3414 * should set them to something else than 0.
3415 */
3416
3417 if (!retinfo)
3418 return -EFAULT;
3419 memset(&tmp, 0, sizeof(tmp));
3420 tmp.type = info->type;
3421 tmp.line = info->line;
3422 tmp.port = (int)info->ioport;
3423 tmp.irq = info->irq;
3424 tmp.flags = info->flags;
3425 tmp.baud_base = info->baud_base;
3426 tmp.close_delay = info->close_delay;
3427 tmp.closing_wait = info->closing_wait;
3428 tmp.custom_divisor = info->custom_divisor;
3429 if (copy_to_user(retinfo, &tmp, sizeof(*retinfo)))
3430 return -EFAULT;
3431 return 0;
3432 }
3433
3434 static int
3435 set_serial_info(struct e100_serial *info,
3436 struct serial_struct *new_info)
3437 {
3438 struct serial_struct new_serial;
3439 struct e100_serial old_info;
3440 int retval = 0;
3441
3442 if (copy_from_user(&new_serial, new_info, sizeof(new_serial)))
3443 return -EFAULT;
3444
3445 old_info = *info;
3446
3447 if (!capable(CAP_SYS_ADMIN)) {
3448 if ((new_serial.type != info->type) ||
3449 (new_serial.close_delay != info->close_delay) ||
3450 ((new_serial.flags & ~ASYNC_USR_MASK) !=
3451 (info->flags & ~ASYNC_USR_MASK)))
3452 return -EPERM;
3453 info->flags = ((info->flags & ~ASYNC_USR_MASK) |
3454 (new_serial.flags & ASYNC_USR_MASK));
3455 goto check_and_exit;
3456 }
3457
3458 if (info->count > 1)
3459 return -EBUSY;
3460
3461 /*
3462 * OK, past this point, all the error checking has been done.
3463 * At this point, we start making changes.....
3464 */
3465
3466 info->baud_base = new_serial.baud_base;
3467 info->flags = ((info->flags & ~ASYNC_FLAGS) |
3468 (new_serial.flags & ASYNC_FLAGS));
3469 info->custom_divisor = new_serial.custom_divisor;
3470 info->type = new_serial.type;
3471 info->close_delay = new_serial.close_delay;
3472 info->closing_wait = new_serial.closing_wait;
3473 info->port.tty->low_latency = (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
3474
3475 check_and_exit:
3476 if (info->flags & ASYNC_INITIALIZED) {
3477 change_speed(info);
3478 } else
3479 retval = startup(info);
3480 return retval;
3481 }
3482
3483 /*
3484 * get_lsr_info - get line status register info
3485 *
3486 * Purpose: Let user call ioctl() to get info when the UART physically
3487 * is emptied. On bus types like RS485, the transmitter must
3488 * release the bus after transmitting. This must be done when
3489 * the transmit shift register is empty, not be done when the
3490 * transmit holding register is empty. This functionality
3491 * allows an RS485 driver to be written in user space.
3492 */
3493 static int
3494 get_lsr_info(struct e100_serial * info, unsigned int *value)
3495 {
3496 unsigned int result = TIOCSER_TEMT;
3497 #ifndef CONFIG_SVINTO_SIM
3498 unsigned long curr_time = jiffies;
3499 unsigned long curr_time_usec = GET_JIFFIES_USEC();
3500 unsigned long elapsed_usec =
3501 (curr_time - info->last_tx_active) * 1000000/HZ +
3502 curr_time_usec - info->last_tx_active_usec;
3503
3504 if (info->xmit.head != info->xmit.tail ||
3505 elapsed_usec < 2*info->char_time_usec) {
3506 result = 0;
3507 }
3508 #endif
3509
3510 if (copy_to_user(value, &result, sizeof(int)))
3511 return -EFAULT;
3512 return 0;
3513 }
3514
3515 #ifdef SERIAL_DEBUG_IO
3516 struct state_str
3517 {
3518 int state;
3519 const char *str;
3520 };
3521
3522 const struct state_str control_state_str[] = {
3523 {TIOCM_DTR, "DTR" },
3524 {TIOCM_RTS, "RTS"},
3525 {TIOCM_ST, "ST?" },
3526 {TIOCM_SR, "SR?" },
3527 {TIOCM_CTS, "CTS" },
3528 {TIOCM_CD, "CD" },
3529 {TIOCM_RI, "RI" },
3530 {TIOCM_DSR, "DSR" },
3531 {0, NULL }
3532 };
3533
3534 char *get_control_state_str(int MLines, char *s)
3535 {
3536 int i = 0;
3537
3538 s[0]='\0';
3539 while (control_state_str[i].str != NULL) {
3540 if (MLines & control_state_str[i].state) {
3541 if (s[0] != '\0') {
3542 strcat(s, ", ");
3543 }
3544 strcat(s, control_state_str[i].str);
3545 }
3546 i++;
3547 }
3548 return s;
3549 }
3550 #endif
3551
3552 static int
3553 rs_break(struct tty_struct *tty, int break_state)
3554 {
3555 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3556 unsigned long flags;
3557
3558 if (!info->ioport)
3559 return -EIO;
3560
3561 local_irq_save(flags);
3562 if (break_state == -1) {
3563 /* Go to manual mode and set the txd pin to 0 */
3564 /* Clear bit 7 (txd) and 6 (tr_enable) */
3565 info->tx_ctrl &= 0x3F;
3566 } else {
3567 /* Set bit 7 (txd) and 6 (tr_enable) */
3568 info->tx_ctrl |= (0x80 | 0x40);
3569 }
3570 info->ioport[REG_TR_CTRL] = info->tx_ctrl;
3571 local_irq_restore(flags);
3572 return 0;
3573 }
3574
3575 static int
3576 rs_tiocmset(struct tty_struct *tty, struct file *file,
3577 unsigned int set, unsigned int clear)
3578 {
3579 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3580 unsigned long flags;
3581
3582 local_irq_save(flags);
3583
3584 if (clear & TIOCM_RTS)
3585 e100_rts(info, 0);
3586 if (clear & TIOCM_DTR)
3587 e100_dtr(info, 0);
3588 /* Handle FEMALE behaviour */
3589 if (clear & TIOCM_RI)
3590 e100_ri_out(info, 0);
3591 if (clear & TIOCM_CD)
3592 e100_cd_out(info, 0);
3593
3594 if (set & TIOCM_RTS)
3595 e100_rts(info, 1);
3596 if (set & TIOCM_DTR)
3597 e100_dtr(info, 1);
3598 /* Handle FEMALE behaviour */
3599 if (set & TIOCM_RI)
3600 e100_ri_out(info, 1);
3601 if (set & TIOCM_CD)
3602 e100_cd_out(info, 1);
3603
3604 local_irq_restore(flags);
3605 return 0;
3606 }
3607
3608 static int
3609 rs_tiocmget(struct tty_struct *tty, struct file *file)
3610 {
3611 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3612 unsigned int result;
3613 unsigned long flags;
3614
3615 local_irq_save(flags);
3616
3617 result =
3618 (!E100_RTS_GET(info) ? TIOCM_RTS : 0)
3619 | (!E100_DTR_GET(info) ? TIOCM_DTR : 0)
3620 | (!E100_RI_GET(info) ? TIOCM_RNG : 0)
3621 | (!E100_DSR_GET(info) ? TIOCM_DSR : 0)
3622 | (!E100_CD_GET(info) ? TIOCM_CAR : 0)
3623 | (!E100_CTS_GET(info) ? TIOCM_CTS : 0);
3624
3625 local_irq_restore(flags);
3626
3627 #ifdef SERIAL_DEBUG_IO
3628 printk(KERN_DEBUG "ser%i: modem state: %i 0x%08X\n",
3629 info->line, result, result);
3630 {
3631 char s[100];
3632
3633 get_control_state_str(result, s);
3634 printk(KERN_DEBUG "state: %s\n", s);
3635 }
3636 #endif
3637 return result;
3638
3639 }
3640
3641
3642 static int
3643 rs_ioctl(struct tty_struct *tty, struct file * file,
3644 unsigned int cmd, unsigned long arg)
3645 {
3646 struct e100_serial * info = (struct e100_serial *)tty->driver_data;
3647
3648 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
3649 (cmd != TIOCSERCONFIG) && (cmd != TIOCSERGWILD) &&
3650 (cmd != TIOCSERSWILD) && (cmd != TIOCSERGSTRUCT)) {
3651 if (tty->flags & (1 << TTY_IO_ERROR))
3652 return -EIO;
3653 }
3654
3655 switch (cmd) {
3656 case TIOCGSERIAL:
3657 return get_serial_info(info,
3658 (struct serial_struct *) arg);
3659 case TIOCSSERIAL:
3660 return set_serial_info(info,
3661 (struct serial_struct *) arg);
3662 case TIOCSERGETLSR: /* Get line status register */
3663 return get_lsr_info(info, (unsigned int *) arg);
3664
3665 case TIOCSERGSTRUCT:
3666 if (copy_to_user((struct e100_serial *) arg,
3667 info, sizeof(struct e100_serial)))
3668 return -EFAULT;
3669 return 0;
3670
3671 #if defined(CONFIG_ETRAX_RS485)
3672 case TIOCSERSETRS485:
3673 {
3674 /* In this ioctl we still use the old structure
3675 * rs485_control for backward compatibility
3676 * (if we use serial_rs485, then old user-level code
3677 * wouldn't work anymore...).
3678 * The use of this ioctl is deprecated: use TIOCSRS485
3679 * instead.*/
3680 struct rs485_control rs485ctrl;
3681 struct serial_rs485 rs485data;
3682 printk(KERN_DEBUG "The use of this ioctl is deprecated. Use TIOCSRS485 instead\n");
3683 if (copy_from_user(&rs485ctrl, (struct rs485_control *)arg,
3684 sizeof(rs485ctrl)))
3685 return -EFAULT;
3686
3687 rs485data.delay_rts_before_send = rs485ctrl.delay_rts_before_send;
3688 rs485data.flags = 0;
3689 if (rs485ctrl.enabled)
3690 rs485data.flags |= SER_RS485_ENABLED;
3691 else
3692 rs485data.flags &= ~(SER_RS485_ENABLED);
3693
3694 if (rs485ctrl.rts_on_send)
3695 rs485data.flags |= SER_RS485_RTS_ON_SEND;
3696 else
3697 rs485data.flags &= ~(SER_RS485_RTS_ON_SEND);
3698
3699 if (rs485ctrl.rts_after_sent)
3700 rs485data.flags |= SER_RS485_RTS_AFTER_SEND;
3701 else
3702 rs485data.flags &= ~(SER_RS485_RTS_AFTER_SEND);
3703
3704 return e100_enable_rs485(tty, &rs485data);
3705 }
3706
3707 case TIOCSRS485:
3708 {
3709 /* This is the new version of TIOCSRS485, with new
3710 * data structure serial_rs485 */
3711 struct serial_rs485 rs485data;
3712 if (copy_from_user(&rs485data, (struct rs485_control *)arg,
3713 sizeof(rs485data)))
3714 return -EFAULT;
3715
3716 return e100_enable_rs485(tty, &rs485data);
3717 }
3718
3719 case TIOCGRS485:
3720 {
3721 struct serial_rs485 *rs485data =
3722 &(((struct e100_serial *)tty->driver_data)->rs485);
3723 /* This is the ioctl to get RS485 data from user-space */
3724 if (copy_to_user((struct serial_rs485 *) arg,
3725 rs485data,
3726 sizeof(serial_rs485)))
3727 return -EFAULT;
3728 break;
3729 }
3730
3731 case TIOCSERWRRS485:
3732 {
3733 struct rs485_write rs485wr;
3734 if (copy_from_user(&rs485wr, (struct rs485_write *)arg,
3735 sizeof(rs485wr)))
3736 return -EFAULT;
3737
3738 return e100_write_rs485(tty, rs485wr.outc, rs485wr.outc_size);
3739 }
3740 #endif
3741
3742 default:
3743 return -ENOIOCTLCMD;
3744 }
3745 return 0;
3746 }
3747
3748 static void
3749 rs_set_termios(struct tty_struct *tty, struct ktermios *old_termios)
3750 {
3751 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3752
3753 change_speed(info);
3754
3755 /* Handle turning off CRTSCTS */
3756 if ((old_termios->c_cflag & CRTSCTS) &&
3757 !(tty->termios->c_cflag & CRTSCTS)) {
3758 tty->hw_stopped = 0;
3759 rs_start(tty);
3760 }
3761
3762 }
3763
3764 /*
3765 * ------------------------------------------------------------
3766 * rs_close()
3767 *
3768 * This routine is called when the serial port gets closed. First, we
3769 * wait for the last remaining data to be sent. Then, we unlink its
3770 * S structure from the interrupt chain if necessary, and we free
3771 * that IRQ if nothing is left in the chain.
3772 * ------------------------------------------------------------
3773 */
3774 static void
3775 rs_close(struct tty_struct *tty, struct file * filp)
3776 {
3777 struct e100_serial * info = (struct e100_serial *)tty->driver_data;
3778 unsigned long flags;
3779
3780 if (!info)
3781 return;
3782
3783 /* interrupts are disabled for this entire function */
3784
3785 local_irq_save(flags);
3786
3787 if (tty_hung_up_p(filp)) {
3788 local_irq_restore(flags);
3789 return;
3790 }
3791
3792 #ifdef SERIAL_DEBUG_OPEN
3793 printk("[%d] rs_close ttyS%d, count = %d\n", current->pid,
3794 info->line, info->count);
3795 #endif
3796 if ((tty->count == 1) && (info->count != 1)) {
3797 /*
3798 * Uh, oh. tty->count is 1, which means that the tty
3799 * structure will be freed. Info->count should always
3800 * be one in these conditions. If it's greater than
3801 * one, we've got real problems, since it means the
3802 * serial port won't be shutdown.
3803 */
3804 printk(KERN_CRIT
3805 "rs_close: bad serial port count; tty->count is 1, "
3806 "info->count is %d\n", info->count);
3807 info->count = 1;
3808 }
3809 if (--info->count < 0) {
3810 printk(KERN_CRIT "rs_close: bad serial port count for ttyS%d: %d\n",
3811 info->line, info->count);
3812 info->count = 0;
3813 }
3814 if (info->count) {
3815 local_irq_restore(flags);
3816 return;
3817 }
3818 info->flags |= ASYNC_CLOSING;
3819 /*
3820 * Save the termios structure, since this port may have
3821 * separate termios for callout and dialin.
3822 */
3823 if (info->flags & ASYNC_NORMAL_ACTIVE)
3824 info->normal_termios = *tty->termios;
3825 /*
3826 * Now we wait for the transmit buffer to clear; and we notify
3827 * the line discipline to only process XON/XOFF characters.
3828 */
3829 tty->closing = 1;
3830 if (info->closing_wait != ASYNC_CLOSING_WAIT_NONE)
3831 tty_wait_until_sent(tty, info->closing_wait);
3832 /*
3833 * At this point we stop accepting input. To do this, we
3834 * disable the serial receiver and the DMA receive interrupt.
3835 */
3836 #ifdef SERIAL_HANDLE_EARLY_ERRORS
3837 e100_disable_serial_data_irq(info);
3838 #endif
3839
3840 #ifndef CONFIG_SVINTO_SIM
3841 e100_disable_rx(info);
3842 e100_disable_rx_irq(info);
3843
3844 if (info->flags & ASYNC_INITIALIZED) {
3845 /*
3846 * Before we drop DTR, make sure the UART transmitter
3847 * has completely drained; this is especially
3848 * important as we have a transmit FIFO!
3849 */
3850 rs_wait_until_sent(tty, HZ);
3851 }
3852 #endif
3853
3854 shutdown(info);
3855 rs_flush_buffer(tty);
3856 tty_ldisc_flush(tty);
3857 tty->closing = 0;
3858 info->event = 0;
3859 info->port.tty = NULL;
3860 if (info->blocked_open) {
3861 if (info->close_delay)
3862 schedule_timeout_interruptible(info->close_delay);
3863 wake_up_interruptible(&info->open_wait);
3864 }
3865 info->flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CLOSING);
3866 wake_up_interruptible(&info->close_wait);
3867 local_irq_restore(flags);
3868
3869 /* port closed */
3870
3871 #if defined(CONFIG_ETRAX_RS485)
3872 if (info->rs485.flags & SER_RS485_ENABLED) {
3873 info->rs485.flags &= ~(SER_RS485_ENABLED);
3874 #if defined(CONFIG_ETRAX_RS485_ON_PA)
3875 *R_PORT_PA_DATA = port_pa_data_shadow &= ~(1 << rs485_pa_bit);
3876 #endif
3877 #if defined(CONFIG_ETRAX_RS485_ON_PORT_G)
3878 REG_SHADOW_SET(R_PORT_G_DATA, port_g_data_shadow,
3879 rs485_port_g_bit, 0);
3880 #endif
3881 #if defined(CONFIG_ETRAX_RS485_LTC1387)
3882 REG_SHADOW_SET(R_PORT_G_DATA, port_g_data_shadow,
3883 CONFIG_ETRAX_RS485_LTC1387_DXEN_PORT_G_BIT, 0);
3884 REG_SHADOW_SET(R_PORT_G_DATA, port_g_data_shadow,
3885 CONFIG_ETRAX_RS485_LTC1387_RXEN_PORT_G_BIT, 0);
3886 #endif
3887 }
3888 #endif
3889
3890 /*
3891 * Release any allocated DMA irq's.
3892 */
3893 if (info->dma_in_enabled) {
3894 free_irq(info->dma_in_irq_nbr, info);
3895 cris_free_dma(info->dma_in_nbr, info->dma_in_irq_description);
3896 info->uses_dma_in = 0;
3897 #ifdef SERIAL_DEBUG_OPEN
3898 printk(KERN_DEBUG "DMA irq '%s' freed\n",
3899 info->dma_in_irq_description);
3900 #endif
3901 }
3902 if (info->dma_out_enabled) {
3903 free_irq(info->dma_out_irq_nbr, info);
3904 cris_free_dma(info->dma_out_nbr, info->dma_out_irq_description);
3905 info->uses_dma_out = 0;
3906 #ifdef SERIAL_DEBUG_OPEN
3907 printk(KERN_DEBUG "DMA irq '%s' freed\n",
3908 info->dma_out_irq_description);
3909 #endif
3910 }
3911 }
3912
3913 /*
3914 * rs_wait_until_sent() --- wait until the transmitter is empty
3915 */
3916 static void rs_wait_until_sent(struct tty_struct *tty, int timeout)
3917 {
3918 unsigned long orig_jiffies;
3919 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3920 unsigned long curr_time = jiffies;
3921 unsigned long curr_time_usec = GET_JIFFIES_USEC();
3922 long elapsed_usec =
3923 (curr_time - info->last_tx_active) * (1000000/HZ) +
3924 curr_time_usec - info->last_tx_active_usec;
3925
3926 /*
3927 * Check R_DMA_CHx_STATUS bit 0-6=number of available bytes in FIFO
3928 * R_DMA_CHx_HWSW bit 31-16=nbr of bytes left in DMA buffer (0=64k)
3929 */
3930 orig_jiffies = jiffies;
3931 while (info->xmit.head != info->xmit.tail || /* More in send queue */
3932 (*info->ostatusadr & 0x007f) || /* more in FIFO */
3933 (elapsed_usec < 2*info->char_time_usec)) {
3934 schedule_timeout_interruptible(1);
3935 if (signal_pending(current))
3936 break;
3937 if (timeout && time_after(jiffies, orig_jiffies + timeout))
3938 break;
3939 curr_time = jiffies;
3940 curr_time_usec = GET_JIFFIES_USEC();
3941 elapsed_usec =
3942 (curr_time - info->last_tx_active) * (1000000/HZ) +
3943 curr_time_usec - info->last_tx_active_usec;
3944 }
3945 set_current_state(TASK_RUNNING);
3946 }
3947
3948 /*
3949 * rs_hangup() --- called by tty_hangup() when a hangup is signaled.
3950 */
3951 void
3952 rs_hangup(struct tty_struct *tty)
3953 {
3954 struct e100_serial * info = (struct e100_serial *)tty->driver_data;
3955
3956 rs_flush_buffer(tty);
3957 shutdown(info);
3958 info->event = 0;
3959 info->count = 0;
3960 info->flags &= ~ASYNC_NORMAL_ACTIVE;
3961 info->port.tty = NULL;
3962 wake_up_interruptible(&info->open_wait);
3963 }
3964
3965 /*
3966 * ------------------------------------------------------------
3967 * rs_open() and friends
3968 * ------------------------------------------------------------
3969 */
3970 static int
3971 block_til_ready(struct tty_struct *tty, struct file * filp,
3972 struct e100_serial *info)
3973 {
3974 DECLARE_WAITQUEUE(wait, current);
3975 unsigned long flags;
3976 int retval;
3977 int do_clocal = 0, extra_count = 0;
3978
3979 /*
3980 * If the device is in the middle of being closed, then block
3981 * until it's done, and then try again.
3982 */
3983 if (tty_hung_up_p(filp) ||
3984 (info->flags & ASYNC_CLOSING)) {
3985 wait_event_interruptible_tty(info->close_wait,
3986 !(info->flags & ASYNC_CLOSING));
3987 #ifdef SERIAL_DO_RESTART
3988 if (info->flags & ASYNC_HUP_NOTIFY)
3989 return -EAGAIN;
3990 else
3991 return -ERESTARTSYS;
3992 #else
3993 return -EAGAIN;
3994 #endif
3995 }
3996
3997 /*
3998 * If non-blocking mode is set, or the port is not enabled,
3999 * then make the check up front and then exit.
4000 */
4001 if ((filp->f_flags & O_NONBLOCK) ||
4002 (tty->flags & (1 << TTY_IO_ERROR))) {
4003 info->flags |= ASYNC_NORMAL_ACTIVE;
4004 return 0;
4005 }
4006
4007 if (tty->termios->c_cflag & CLOCAL) {
4008 do_clocal = 1;
4009 }
4010
4011 /*
4012 * Block waiting for the carrier detect and the line to become
4013 * free (i.e., not in use by the callout). While we are in
4014 * this loop, info->count is dropped by one, so that
4015 * rs_close() knows when to free things. We restore it upon
4016 * exit, either normal or abnormal.
4017 */
4018 retval = 0;
4019 add_wait_queue(&info->open_wait, &wait);
4020 #ifdef SERIAL_DEBUG_OPEN
4021 printk("block_til_ready before block: ttyS%d, count = %d\n",
4022 info->line, info->count);
4023 #endif
4024 local_irq_save(flags);
4025 if (!tty_hung_up_p(filp)) {
4026 extra_count++;
4027 info->count--;
4028 }
4029 local_irq_restore(flags);
4030 info->blocked_open++;
4031 while (1) {
4032 local_irq_save(flags);
4033 /* assert RTS and DTR */
4034 e100_rts(info, 1);
4035 e100_dtr(info, 1);
4036 local_irq_restore(flags);
4037 set_current_state(TASK_INTERRUPTIBLE);
4038 if (tty_hung_up_p(filp) ||
4039 !(info->flags & ASYNC_INITIALIZED)) {
4040 #ifdef SERIAL_DO_RESTART
4041 if (info->flags & ASYNC_HUP_NOTIFY)
4042 retval = -EAGAIN;
4043 else
4044 retval = -ERESTARTSYS;
4045 #else
4046 retval = -EAGAIN;
4047 #endif
4048 break;
4049 }
4050 if (!(info->flags & ASYNC_CLOSING) && do_clocal)
4051 /* && (do_clocal || DCD_IS_ASSERTED) */
4052 break;
4053 if (signal_pending(current)) {
4054 retval = -ERESTARTSYS;
4055 break;
4056 }
4057 #ifdef SERIAL_DEBUG_OPEN
4058 printk("block_til_ready blocking: ttyS%d, count = %d\n",
4059 info->line, info->count);
4060 #endif
4061 tty_unlock();
4062 schedule();
4063 tty_lock();
4064 }
4065 set_current_state(TASK_RUNNING);
4066 remove_wait_queue(&info->open_wait, &wait);
4067 if (extra_count)
4068 info->count++;
4069 info->blocked_open--;
4070 #ifdef SERIAL_DEBUG_OPEN
4071 printk("block_til_ready after blocking: ttyS%d, count = %d\n",
4072 info->line, info->count);
4073 #endif
4074 if (retval)
4075 return retval;
4076 info->flags |= ASYNC_NORMAL_ACTIVE;
4077 return 0;
4078 }
4079
4080 static void
4081 deinit_port(struct e100_serial *info)
4082 {
4083 if (info->dma_out_enabled) {
4084 cris_free_dma(info->dma_out_nbr, info->dma_out_irq_description);
4085 free_irq(info->dma_out_irq_nbr, info);
4086 }
4087 if (info->dma_in_enabled) {
4088 cris_free_dma(info->dma_in_nbr, info->dma_in_irq_description);
4089 free_irq(info->dma_in_irq_nbr, info);
4090 }
4091 }
4092
4093 /*
4094 * This routine is called whenever a serial port is opened.
4095 * It performs the serial-specific initialization for the tty structure.
4096 */
4097 static int
4098 rs_open(struct tty_struct *tty, struct file * filp)
4099 {
4100 struct e100_serial *info;
4101 int retval, line;
4102 unsigned long page;
4103 int allocated_resources = 0;
4104
4105 /* find which port we want to open */
4106 line = tty->index;
4107
4108 if (line < 0 || line >= NR_PORTS)
4109 return -ENODEV;
4110
4111 /* find the corresponding e100_serial struct in the table */
4112 info = rs_table + line;
4113
4114 /* don't allow the opening of ports that are not enabled in the HW config */
4115 if (!info->enabled)
4116 return -ENODEV;
4117
4118 #ifdef SERIAL_DEBUG_OPEN
4119 printk("[%d] rs_open %s, count = %d\n", current->pid, tty->name,
4120 info->count);
4121 #endif
4122
4123 info->count++;
4124 tty->driver_data = info;
4125 info->port.tty = tty;
4126
4127 info->port.tty->low_latency = (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
4128
4129 if (!tmp_buf) {
4130 page = get_zeroed_page(GFP_KERNEL);
4131 if (!page) {
4132 return -ENOMEM;
4133 }
4134 if (tmp_buf)
4135 free_page(page);
4136 else
4137 tmp_buf = (unsigned char *) page;
4138 }
4139
4140 /*
4141 * If the port is in the middle of closing, bail out now
4142 */
4143 if (tty_hung_up_p(filp) ||
4144 (info->flags & ASYNC_CLOSING)) {
4145 wait_event_interruptible_tty(info->close_wait,
4146 !(info->flags & ASYNC_CLOSING));
4147 #ifdef SERIAL_DO_RESTART
4148 return ((info->flags & ASYNC_HUP_NOTIFY) ?
4149 -EAGAIN : -ERESTARTSYS);
4150 #else
4151 return -EAGAIN;
4152 #endif
4153 }
4154
4155 /*
4156 * If DMA is enabled try to allocate the irq's.
4157 */
4158 if (info->count == 1) {
4159 allocated_resources = 1;
4160 if (info->dma_in_enabled) {
4161 if (request_irq(info->dma_in_irq_nbr,
4162 rec_interrupt,
4163 info->dma_in_irq_flags,
4164 info->dma_in_irq_description,
4165 info)) {
4166 printk(KERN_WARNING "DMA irq '%s' busy; "
4167 "falling back to non-DMA mode\n",
4168 info->dma_in_irq_description);
4169 /* Make sure we never try to use DMA in */
4170 /* for the port again. */
4171 info->dma_in_enabled = 0;
4172 } else if (cris_request_dma(info->dma_in_nbr,
4173 info->dma_in_irq_description,
4174 DMA_VERBOSE_ON_ERROR,
4175 info->dma_owner)) {
4176 free_irq(info->dma_in_irq_nbr, info);
4177 printk(KERN_WARNING "DMA '%s' busy; "
4178 "falling back to non-DMA mode\n",
4179 info->dma_in_irq_description);
4180 /* Make sure we never try to use DMA in */
4181 /* for the port again. */
4182 info->dma_in_enabled = 0;
4183 }
4184 #ifdef SERIAL_DEBUG_OPEN
4185 else
4186 printk(KERN_DEBUG "DMA irq '%s' allocated\n",
4187 info->dma_in_irq_description);
4188 #endif
4189 }
4190 if (info->dma_out_enabled) {
4191 if (request_irq(info->dma_out_irq_nbr,
4192 tr_interrupt,
4193 info->dma_out_irq_flags,
4194 info->dma_out_irq_description,
4195 info)) {
4196 printk(KERN_WARNING "DMA irq '%s' busy; "
4197 "falling back to non-DMA mode\n",
4198 info->dma_out_irq_description);
4199 /* Make sure we never try to use DMA out */
4200 /* for the port again. */
4201 info->dma_out_enabled = 0;
4202 } else if (cris_request_dma(info->dma_out_nbr,
4203 info->dma_out_irq_description,
4204 DMA_VERBOSE_ON_ERROR,
4205 info->dma_owner)) {
4206 free_irq(info->dma_out_irq_nbr, info);
4207 printk(KERN_WARNING "DMA '%s' busy; "
4208 "falling back to non-DMA mode\n",
4209 info->dma_out_irq_description);
4210 /* Make sure we never try to use DMA out */
4211 /* for the port again. */
4212 info->dma_out_enabled = 0;
4213 }
4214 #ifdef SERIAL_DEBUG_OPEN
4215 else
4216 printk(KERN_DEBUG "DMA irq '%s' allocated\n",
4217 info->dma_out_irq_description);
4218 #endif
4219 }
4220 }
4221
4222 /*
4223 * Start up the serial port
4224 */
4225
4226 retval = startup(info);
4227 if (retval) {
4228 if (allocated_resources)
4229 deinit_port(info);
4230
4231 return retval;
4232 }
4233
4234
4235 retval = block_til_ready(tty, filp, info);
4236 if (retval) {
4237 #ifdef SERIAL_DEBUG_OPEN
4238 printk("rs_open returning after block_til_ready with %d\n",
4239 retval);
4240 #endif
4241 if (allocated_resources)
4242 deinit_port(info);
4243
4244 return retval;
4245 }
4246
4247 if ((info->count == 1) && (info->flags & ASYNC_SPLIT_TERMIOS)) {
4248 *tty->termios = info->normal_termios;
4249 change_speed(info);
4250 }
4251
4252 #ifdef SERIAL_DEBUG_OPEN
4253 printk("rs_open ttyS%d successful...\n", info->line);
4254 #endif
4255 DLOG_INT_TRIG( log_int_pos = 0);
4256
4257 DFLIP( if (info->line == SERIAL_DEBUG_LINE) {
4258 info->icount.rx = 0;
4259 } );
4260
4261 return 0;
4262 }
4263
4264 #ifdef CONFIG_PROC_FS
4265 /*
4266 * /proc fs routines....
4267 */
4268
4269 static void seq_line_info(struct seq_file *m, struct e100_serial *info)
4270 {
4271 unsigned long tmp;
4272
4273 seq_printf(m, "%d: uart:E100 port:%lX irq:%d",
4274 info->line, (unsigned long)info->ioport, info->irq);
4275
4276 if (!info->ioport || (info->type == PORT_UNKNOWN)) {
4277 seq_printf(m, "\n");
4278 return;
4279 }
4280
4281 seq_printf(m, " baud:%d", info->baud);
4282 seq_printf(m, " tx:%lu rx:%lu",
4283 (unsigned long)info->icount.tx,
4284 (unsigned long)info->icount.rx);
4285 tmp = CIRC_CNT(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE);
4286 if (tmp)
4287 seq_printf(m, " tx_pend:%lu/%lu",
4288 (unsigned long)tmp,
4289 (unsigned long)SERIAL_XMIT_SIZE);
4290
4291 seq_printf(m, " rx_pend:%lu/%lu",
4292 (unsigned long)info->recv_cnt,
4293 (unsigned long)info->max_recv_cnt);
4294
4295 if (info->port.tty) {
4296 if (info->port.tty->stopped)
4297 seq_printf(m, " stopped:%i",
4298 (int)info->port.tty->stopped);
4299 if (info->port.tty->hw_stopped)
4300 seq_printf(m, " hw_stopped:%i",
4301 (int)info->port.tty->hw_stopped);
4302 }
4303
4304 {
4305 unsigned char rstat = info->ioport[REG_STATUS];
4306 if (rstat & IO_MASK(R_SERIAL0_STATUS, xoff_detect))
4307 seq_printf(m, " xoff_detect:1");
4308 }
4309
4310 if (info->icount.frame)
4311 seq_printf(m, " fe:%lu", (unsigned long)info->icount.frame);
4312
4313 if (info->icount.parity)
4314 seq_printf(m, " pe:%lu", (unsigned long)info->icount.parity);
4315
4316 if (info->icount.brk)
4317 seq_printf(m, " brk:%lu", (unsigned long)info->icount.brk);
4318
4319 if (info->icount.overrun)
4320 seq_printf(m, " oe:%lu", (unsigned long)info->icount.overrun);
4321
4322 /*
4323 * Last thing is the RS-232 status lines
4324 */
4325 if (!E100_RTS_GET(info))
4326 seq_puts(m, "|RTS");
4327 if (!E100_CTS_GET(info))
4328 seq_puts(m, "|CTS");
4329 if (!E100_DTR_GET(info))
4330 seq_puts(m, "|DTR");
4331 if (!E100_DSR_GET(info))
4332 seq_puts(m, "|DSR");
4333 if (!E100_CD_GET(info))
4334 seq_puts(m, "|CD");
4335 if (!E100_RI_GET(info))
4336 seq_puts(m, "|RI");
4337 seq_puts(m, "\n");
4338 }
4339
4340
4341 static int crisv10_proc_show(struct seq_file *m, void *v)
4342 {
4343 int i;
4344
4345 seq_printf(m, "serinfo:1.0 driver:%s\n", serial_version);
4346
4347 for (i = 0; i < NR_PORTS; i++) {
4348 if (!rs_table[i].enabled)
4349 continue;
4350 seq_line_info(m, &rs_table[i]);
4351 }
4352 #ifdef DEBUG_LOG_INCLUDED
4353 for (i = 0; i < debug_log_pos; i++) {
4354 seq_printf(m, "%-4i %lu.%lu ",
4355 i, debug_log[i].time,
4356 timer_data_to_ns(debug_log[i].timer_data));
4357 seq_printf(m, debug_log[i].string, debug_log[i].value);
4358 }
4359 seq_printf(m, "debug_log %i/%i\n", i, DEBUG_LOG_SIZE);
4360 debug_log_pos = 0;
4361 #endif
4362 return 0;
4363 }
4364
4365 static int crisv10_proc_open(struct inode *inode, struct file *file)
4366 {
4367 return single_open(file, crisv10_proc_show, NULL);
4368 }
4369
4370 static const struct file_operations crisv10_proc_fops = {
4371 .owner = THIS_MODULE,
4372 .open = crisv10_proc_open,
4373 .read = seq_read,
4374 .llseek = seq_lseek,
4375 .release = single_release,
4376 };
4377 #endif
4378
4379
4380 /* Finally, routines used to initialize the serial driver. */
4381
4382 static void show_serial_version(void)
4383 {
4384 printk(KERN_INFO
4385 "ETRAX 100LX serial-driver %s, "
4386 "(c) 2000-2004 Axis Communications AB\r\n",
4387 &serial_version[11]); /* "$Revision: x.yy" */
4388 }
4389
4390 /* rs_init inits the driver at boot (using the module_init chain) */
4391
4392 static const struct tty_operations rs_ops = {
4393 .open = rs_open,
4394 .close = rs_close,
4395 .write = rs_write,
4396 .flush_chars = rs_flush_chars,
4397 .write_room = rs_write_room,
4398 .chars_in_buffer = rs_chars_in_buffer,
4399 .flush_buffer = rs_flush_buffer,
4400 .ioctl = rs_ioctl,
4401 .throttle = rs_throttle,
4402 .unthrottle = rs_unthrottle,
4403 .set_termios = rs_set_termios,
4404 .stop = rs_stop,
4405 .start = rs_start,
4406 .hangup = rs_hangup,
4407 .break_ctl = rs_break,
4408 .send_xchar = rs_send_xchar,
4409 .wait_until_sent = rs_wait_until_sent,
4410 .tiocmget = rs_tiocmget,
4411 .tiocmset = rs_tiocmset,
4412 #ifdef CONFIG_PROC_FS
4413 .proc_fops = &crisv10_proc_fops,
4414 #endif
4415 };
4416
4417 static int __init rs_init(void)
4418 {
4419 int i;
4420 struct e100_serial *info;
4421 struct tty_driver *driver = alloc_tty_driver(NR_PORTS);
4422
4423 if (!driver)
4424 return -ENOMEM;
4425
4426 show_serial_version();
4427
4428 /* Setup the timed flush handler system */
4429
4430 #if !defined(CONFIG_ETRAX_SERIAL_FAST_TIMER)
4431 setup_timer(&flush_timer, timed_flush_handler, 0);
4432 mod_timer(&flush_timer, jiffies + 5);
4433 #endif
4434
4435 #if defined(CONFIG_ETRAX_RS485)
4436 #if defined(CONFIG_ETRAX_RS485_ON_PA)
4437 if (cris_io_interface_allocate_pins(if_ser0, 'a', rs485_pa_bit,
4438 rs485_pa_bit)) {
4439 printk(KERN_CRIT "ETRAX100LX serial: Could not allocate "
4440 "RS485 pin\n");
4441 put_tty_driver(driver);
4442 return -EBUSY;
4443 }
4444 #endif
4445 #if defined(CONFIG_ETRAX_RS485_ON_PORT_G)
4446 if (cris_io_interface_allocate_pins(if_ser0, 'g', rs485_pa_bit,
4447 rs485_port_g_bit)) {
4448 printk(KERN_CRIT "ETRAX100LX serial: Could not allocate "
4449 "RS485 pin\n");
4450 put_tty_driver(driver);
4451 return -EBUSY;
4452 }
4453 #endif
4454 #endif
4455
4456 /* Initialize the tty_driver structure */
4457
4458 driver->driver_name = "serial";
4459 driver->name = "ttyS";
4460 driver->major = TTY_MAJOR;
4461 driver->minor_start = 64;
4462 driver->type = TTY_DRIVER_TYPE_SERIAL;
4463 driver->subtype = SERIAL_TYPE_NORMAL;
4464 driver->init_termios = tty_std_termios;
4465 driver->init_termios.c_cflag =
4466 B115200 | CS8 | CREAD | HUPCL | CLOCAL; /* is normally B9600 default... */
4467 driver->init_termios.c_ispeed = 115200;
4468 driver->init_termios.c_ospeed = 115200;
4469 driver->flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV;
4470
4471 tty_set_operations(driver, &rs_ops);
4472 serial_driver = driver;
4473 if (tty_register_driver(driver))
4474 panic("Couldn't register serial driver\n");
4475 /* do some initializing for the separate ports */
4476
4477 for (i = 0, info = rs_table; i < NR_PORTS; i++,info++) {
4478 if (info->enabled) {
4479 if (cris_request_io_interface(info->io_if,
4480 info->io_if_description)) {
4481 printk(KERN_CRIT "ETRAX100LX async serial: "
4482 "Could not allocate IO pins for "
4483 "%s, port %d\n",
4484 info->io_if_description, i);
4485 info->enabled = 0;
4486 }
4487 }
4488 info->uses_dma_in = 0;
4489 info->uses_dma_out = 0;
4490 info->line = i;
4491 info->port.tty = NULL;
4492 info->type = PORT_ETRAX;
4493 info->tr_running = 0;
4494 info->forced_eop = 0;
4495 info->baud_base = DEF_BAUD_BASE;
4496 info->custom_divisor = 0;
4497 info->flags = 0;
4498 info->close_delay = 5*HZ/10;
4499 info->closing_wait = 30*HZ;
4500 info->x_char = 0;
4501 info->event = 0;
4502 info->count = 0;
4503 info->blocked_open = 0;
4504 info->normal_termios = driver->init_termios;
4505 init_waitqueue_head(&info->open_wait);
4506 init_waitqueue_head(&info->close_wait);
4507 info->xmit.buf = NULL;
4508 info->xmit.tail = info->xmit.head = 0;
4509 info->first_recv_buffer = info->last_recv_buffer = NULL;
4510 info->recv_cnt = info->max_recv_cnt = 0;
4511 info->last_tx_active_usec = 0;
4512 info->last_tx_active = 0;
4513
4514 #if defined(CONFIG_ETRAX_RS485)
4515 /* Set sane defaults */
4516 info->rs485.flags &= ~(SER_RS485_RTS_ON_SEND);
4517 info->rs485.flags |= SER_RS485_RTS_AFTER_SEND;
4518 info->rs485.delay_rts_before_send = 0;
4519 info->rs485.flags &= ~(SER_RS485_ENABLED);
4520 #endif
4521 INIT_WORK(&info->work, do_softint);
4522
4523 if (info->enabled) {
4524 printk(KERN_INFO "%s%d at %p is a builtin UART with DMA\n",
4525 serial_driver->name, info->line, info->ioport);
4526 }
4527 }
4528 #ifdef CONFIG_ETRAX_FAST_TIMER
4529 #ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER
4530 memset(fast_timers, 0, sizeof(fast_timers));
4531 #endif
4532 #ifdef CONFIG_ETRAX_RS485
4533 memset(fast_timers_rs485, 0, sizeof(fast_timers_rs485));
4534 #endif
4535 fast_timer_init();
4536 #endif
4537
4538 #ifndef CONFIG_SVINTO_SIM
4539 #ifndef CONFIG_ETRAX_KGDB
4540 /* Not needed in simulator. May only complicate stuff. */
4541 /* hook the irq's for DMA channel 6 and 7, serial output and input, and some more... */
4542
4543 if (request_irq(SERIAL_IRQ_NBR, ser_interrupt,
4544 IRQF_SHARED | IRQF_DISABLED, "serial ", driver))
4545 panic("%s: Failed to request irq8", __func__);
4546
4547 #endif
4548 #endif /* CONFIG_SVINTO_SIM */
4549
4550 return 0;
4551 }
4552
4553 /* this makes sure that rs_init is called during kernel boot */
4554
4555 module_init(rs_init);
Tomato firmware and modifications.