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GUI: Fix Tomato RAF theme for all builds. Compilation typo.
[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / drivers / scsi / mvsas / mv_94xx.c
blob25370b93463a9f2d1b92a7755eff27f29e755b53
1 /*
2 * Marvell 88SE94xx hardware specific
3 *
4 * Copyright 2007 Red Hat, Inc.
5 * Copyright 2008 Marvell. <kewei@marvell.com>
6 *
7 * This file is licensed under GPLv2.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; version 2 of the
12 * License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
22 * USA
23 */
24
25 #include "mv_sas.h"
26 #include "mv_94xx.h"
27 #include "mv_chips.h"
28
29 static void mvs_94xx_detect_porttype(struct mvs_info *mvi, int i)
30 {
31 u32 reg;
32 struct mvs_phy *phy = &mvi->phy[i];
33 u32 phy_status;
34
35 mvs_write_port_vsr_addr(mvi, i, VSR_PHY_MODE3);
36 reg = mvs_read_port_vsr_data(mvi, i);
37 phy_status = ((reg & 0x3f0000) >> 16) & 0xff;
38 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
39 switch (phy_status) {
40 case 0x10:
41 phy->phy_type |= PORT_TYPE_SAS;
42 break;
43 case 0x1d:
44 default:
45 phy->phy_type |= PORT_TYPE_SATA;
46 break;
47 }
48 }
49
50 static void __devinit mvs_94xx_enable_xmt(struct mvs_info *mvi, int phy_id)
51 {
52 void __iomem *regs = mvi->regs;
53 u32 tmp;
54
55 tmp = mr32(MVS_PCS);
56 tmp |= 1 << (phy_id + PCS_EN_PORT_XMT_SHIFT2);
57 mw32(MVS_PCS, tmp);
58 }
59
60 static void mvs_94xx_phy_reset(struct mvs_info *mvi, u32 phy_id, int hard)
61 {
62 u32 tmp;
63
64 tmp = mvs_read_port_irq_stat(mvi, phy_id);
65 tmp &= ~PHYEV_RDY_CH;
66 mvs_write_port_irq_stat(mvi, phy_id, tmp);
67 if (hard) {
68 tmp = mvs_read_phy_ctl(mvi, phy_id);
69 tmp |= PHY_RST_HARD;
70 mvs_write_phy_ctl(mvi, phy_id, tmp);
71 do {
72 tmp = mvs_read_phy_ctl(mvi, phy_id);
73 } while (tmp & PHY_RST_HARD);
74 } else {
75 mvs_write_port_vsr_addr(mvi, phy_id, VSR_PHY_STAT);
76 tmp = mvs_read_port_vsr_data(mvi, phy_id);
77 tmp |= PHY_RST;
78 mvs_write_port_vsr_data(mvi, phy_id, tmp);
79 }
80 }
81
82 static void mvs_94xx_phy_disable(struct mvs_info *mvi, u32 phy_id)
83 {
84 u32 tmp;
85 mvs_write_port_vsr_addr(mvi, phy_id, VSR_PHY_MODE2);
86 tmp = mvs_read_port_vsr_data(mvi, phy_id);
87 mvs_write_port_vsr_data(mvi, phy_id, tmp | 0x00800000);
88 }
89
90 static void mvs_94xx_phy_enable(struct mvs_info *mvi, u32 phy_id)
91 {
92 mvs_write_port_vsr_addr(mvi, phy_id, 0x1B4);
93 mvs_write_port_vsr_data(mvi, phy_id, 0x8300ffc1);
94 mvs_write_port_vsr_addr(mvi, phy_id, 0x104);
95 mvs_write_port_vsr_data(mvi, phy_id, 0x00018080);
96 mvs_write_port_vsr_addr(mvi, phy_id, VSR_PHY_MODE2);
97 mvs_write_port_vsr_data(mvi, phy_id, 0x00207fff);
98 }
99
100 static int __devinit mvs_94xx_init(struct mvs_info *mvi)
101 {
102 void __iomem *regs = mvi->regs;
103 int i;
104 u32 tmp, cctl;
105
106 mvs_show_pcie_usage(mvi);
107 if (mvi->flags & MVF_FLAG_SOC) {
108 tmp = mr32(MVS_PHY_CTL);
109 tmp &= ~PCTL_PWR_OFF;
110 tmp |= PCTL_PHY_DSBL;
111 mw32(MVS_PHY_CTL, tmp);
112 }
113
114 /* Init Chip */
115 /* make sure RST is set; HBA_RST /should/ have done that for us */
116 cctl = mr32(MVS_CTL) & 0xFFFF;
117 if (cctl & CCTL_RST)
118 cctl &= ~CCTL_RST;
119 else
120 mw32_f(MVS_CTL, cctl | CCTL_RST);
121
122 if (mvi->flags & MVF_FLAG_SOC) {
123 tmp = mr32(MVS_PHY_CTL);
124 tmp &= ~PCTL_PWR_OFF;
125 tmp |= PCTL_COM_ON;
126 tmp &= ~PCTL_PHY_DSBL;
127 tmp |= PCTL_LINK_RST;
128 mw32(MVS_PHY_CTL, tmp);
129 msleep(100);
130 tmp &= ~PCTL_LINK_RST;
131 mw32(MVS_PHY_CTL, tmp);
132 msleep(100);
133 }
134
135 /* reset control */
136 mw32(MVS_PCS, 0); /* MVS_PCS */
137 mw32(MVS_STP_REG_SET_0, 0);
138 mw32(MVS_STP_REG_SET_1, 0);
139
140 /* init phys */
141 mvs_phy_hacks(mvi);
142
143 /* disable Multiplexing, enable phy implemented */
144 mw32(MVS_PORTS_IMP, 0xFF);
145
146
147 mw32(MVS_PA_VSR_ADDR, 0x00000104);
148 mw32(MVS_PA_VSR_PORT, 0x00018080);
149 mw32(MVS_PA_VSR_ADDR, VSR_PHY_MODE8);
150 mw32(MVS_PA_VSR_PORT, 0x0084ffff);
151
152 /* set LED blink when IO*/
153 mw32(MVS_PA_VSR_ADDR, 0x00000030);
154 tmp = mr32(MVS_PA_VSR_PORT);
155 tmp &= 0xFFFF00FF;
156 tmp |= 0x00003300;
157 mw32(MVS_PA_VSR_PORT, tmp);
158
159 mw32(MVS_CMD_LIST_LO, mvi->slot_dma);
160 mw32(MVS_CMD_LIST_HI, (mvi->slot_dma >> 16) >> 16);
161
162 mw32(MVS_RX_FIS_LO, mvi->rx_fis_dma);
163 mw32(MVS_RX_FIS_HI, (mvi->rx_fis_dma >> 16) >> 16);
164
165 mw32(MVS_TX_CFG, MVS_CHIP_SLOT_SZ);
166 mw32(MVS_TX_LO, mvi->tx_dma);
167 mw32(MVS_TX_HI, (mvi->tx_dma >> 16) >> 16);
168
169 mw32(MVS_RX_CFG, MVS_RX_RING_SZ);
170 mw32(MVS_RX_LO, mvi->rx_dma);
171 mw32(MVS_RX_HI, (mvi->rx_dma >> 16) >> 16);
172
173 for (i = 0; i < mvi->chip->n_phy; i++) {
174 mvs_94xx_phy_disable(mvi, i);
175 /* set phy local SAS address */
176 mvs_set_sas_addr(mvi, i, CONFIG_ID_FRAME3, CONFIG_ID_FRAME4,
177 (mvi->phy[i].dev_sas_addr));
178
179 mvs_94xx_enable_xmt(mvi, i);
180 mvs_94xx_phy_enable(mvi, i);
181
182 mvs_94xx_phy_reset(mvi, i, 1);
183 msleep(500);
184 mvs_94xx_detect_porttype(mvi, i);
185 }
186
187 if (mvi->flags & MVF_FLAG_SOC) {
188 /* set select registers */
189 writel(0x0E008000, regs + 0x000);
190 writel(0x59000008, regs + 0x004);
191 writel(0x20, regs + 0x008);
192 writel(0x20, regs + 0x00c);
193 writel(0x20, regs + 0x010);
194 writel(0x20, regs + 0x014);
195 writel(0x20, regs + 0x018);
196 writel(0x20, regs + 0x01c);
197 }
198 for (i = 0; i < mvi->chip->n_phy; i++) {
199 /* clear phy int status */
200 tmp = mvs_read_port_irq_stat(mvi, i);
201 tmp &= ~PHYEV_SIG_FIS;
202 mvs_write_port_irq_stat(mvi, i, tmp);
203
204 /* set phy int mask */
205 tmp = PHYEV_RDY_CH | PHYEV_BROAD_CH |
206 PHYEV_ID_DONE | PHYEV_DCDR_ERR | PHYEV_CRC_ERR ;
207 mvs_write_port_irq_mask(mvi, i, tmp);
208
209 msleep(100);
210 mvs_update_phyinfo(mvi, i, 1);
211 }
212
213
214 /* little endian for open address and command table, etc. */
215 /*
216 * it seems that ( from the spec ) turning on big-endian won't
217 * do us any good on big-endian machines, need further confirmation
218 */
219 cctl = mr32(MVS_CTL);
220 cctl |= CCTL_ENDIAN_CMD;
221 cctl |= CCTL_ENDIAN_DATA;
222 cctl &= ~CCTL_ENDIAN_OPEN;
223 cctl |= CCTL_ENDIAN_RSP;
224 mw32_f(MVS_CTL, cctl);
225
226 /* reset CMD queue */
227 tmp = mr32(MVS_PCS);
228 tmp |= PCS_CMD_RST;
229 mw32(MVS_PCS, tmp);
230 /* interrupt coalescing may cause missing HW interrput in some case,
231 * and the max count is 0x1ff, while our max slot is 0x200,
232 * it will make count 0.
233 */
234 tmp = 0;
235 mw32(MVS_INT_COAL, tmp);
236
237 tmp = 0x100;
238 mw32(MVS_INT_COAL_TMOUT, tmp);
239
240 /* ladies and gentlemen, start your engines */
241 mw32(MVS_TX_CFG, 0);
242 mw32(MVS_TX_CFG, MVS_CHIP_SLOT_SZ | TX_EN);
243 mw32(MVS_RX_CFG, MVS_RX_RING_SZ | RX_EN);
244 /* enable CMD/CMPL_Q/RESP mode */
245 mw32(MVS_PCS, PCS_SATA_RETRY_2 | PCS_FIS_RX_EN |
246 PCS_CMD_EN | PCS_CMD_STOP_ERR);
247
248 /* enable completion queue interrupt */
249 tmp = (CINT_PORT_MASK | CINT_DONE | CINT_MEM | CINT_SRS | CINT_CI_STOP |
250 CINT_DMA_PCIE);
251 tmp |= CINT_PHY_MASK;
252 mw32(MVS_INT_MASK, tmp);
253
254 /* Enable SRS interrupt */
255 mw32(MVS_INT_MASK_SRS_0, 0xFFFF);
256
257 return 0;
258 }
259
260 static int mvs_94xx_ioremap(struct mvs_info *mvi)
261 {
262 if (!mvs_ioremap(mvi, 2, -1)) {
263 mvi->regs_ex = mvi->regs + 0x10200;
264 mvi->regs += 0x20000;
265 if (mvi->id == 1)
266 mvi->regs += 0x4000;
267 return 0;
268 }
269 return -1;
270 }
271
272 static void mvs_94xx_iounmap(struct mvs_info *mvi)
273 {
274 if (mvi->regs) {
275 mvi->regs -= 0x20000;
276 if (mvi->id == 1)
277 mvi->regs -= 0x4000;
278 mvs_iounmap(mvi->regs);
279 }
280 }
281
282 static void mvs_94xx_interrupt_enable(struct mvs_info *mvi)
283 {
284 void __iomem *regs = mvi->regs_ex;
285 u32 tmp;
286
287 tmp = mr32(MVS_GBL_CTL);
288 tmp |= (IRQ_SAS_A | IRQ_SAS_B);
289 mw32(MVS_GBL_INT_STAT, tmp);
290 writel(tmp, regs + 0x0C);
291 writel(tmp, regs + 0x10);
292 writel(tmp, regs + 0x14);
293 writel(tmp, regs + 0x18);
294 mw32(MVS_GBL_CTL, tmp);
295 }
296
297 static void mvs_94xx_interrupt_disable(struct mvs_info *mvi)
298 {
299 void __iomem *regs = mvi->regs_ex;
300 u32 tmp;
301
302 tmp = mr32(MVS_GBL_CTL);
303
304 tmp &= ~(IRQ_SAS_A | IRQ_SAS_B);
305 mw32(MVS_GBL_INT_STAT, tmp);
306 writel(tmp, regs + 0x0C);
307 writel(tmp, regs + 0x10);
308 writel(tmp, regs + 0x14);
309 writel(tmp, regs + 0x18);
310 mw32(MVS_GBL_CTL, tmp);
311 }
312
313 static u32 mvs_94xx_isr_status(struct mvs_info *mvi, int irq)
314 {
315 void __iomem *regs = mvi->regs_ex;
316 u32 stat = 0;
317 if (!(mvi->flags & MVF_FLAG_SOC)) {
318 stat = mr32(MVS_GBL_INT_STAT);
319
320 if (!(stat & (IRQ_SAS_A | IRQ_SAS_B)))
321 return 0;
322 }
323 return stat;
324 }
325
326 static irqreturn_t mvs_94xx_isr(struct mvs_info *mvi, int irq, u32 stat)
327 {
328 void __iomem *regs = mvi->regs;
329
330 if (((stat & IRQ_SAS_A) && mvi->id == 0) ||
331 ((stat & IRQ_SAS_B) && mvi->id == 1)) {
332 mw32_f(MVS_INT_STAT, CINT_DONE);
333 #ifndef MVS_USE_TASKLET
334 spin_lock(&mvi->lock);
335 #endif
336 mvs_int_full(mvi);
337 #ifndef MVS_USE_TASKLET
338 spin_unlock(&mvi->lock);
339 #endif
340 }
341 return IRQ_HANDLED;
342 }
343
344 static void mvs_94xx_command_active(struct mvs_info *mvi, u32 slot_idx)
345 {
346 u32 tmp;
347 mvs_cw32(mvi, 0x300 + (slot_idx >> 3), 1 << (slot_idx % 32));
348 do {
349 tmp = mvs_cr32(mvi, 0x300 + (slot_idx >> 3));
350 } while (tmp & 1 << (slot_idx % 32));
351 }
352
353 static void mvs_94xx_issue_stop(struct mvs_info *mvi, enum mvs_port_type type,
354 u32 tfs)
355 {
356 void __iomem *regs = mvi->regs;
357 u32 tmp;
358
359 if (type == PORT_TYPE_SATA) {
360 tmp = mr32(MVS_INT_STAT_SRS_0) | (1U << tfs);
361 mw32(MVS_INT_STAT_SRS_0, tmp);
362 }
363 mw32(MVS_INT_STAT, CINT_CI_STOP);
364 tmp = mr32(MVS_PCS) | 0xFF00;
365 mw32(MVS_PCS, tmp);
366 }
367
368 static void mvs_94xx_free_reg_set(struct mvs_info *mvi, u8 *tfs)
369 {
370 void __iomem *regs = mvi->regs;
371 u32 tmp;
372 u8 reg_set = *tfs;
373
374 if (*tfs == MVS_ID_NOT_MAPPED)
375 return;
376
377 mvi->sata_reg_set &= ~bit(reg_set);
378 if (reg_set < 32) {
379 w_reg_set_enable(reg_set, (u32)mvi->sata_reg_set);
380 tmp = mr32(MVS_INT_STAT_SRS_0) & (u32)mvi->sata_reg_set;
381 if (tmp)
382 mw32(MVS_INT_STAT_SRS_0, tmp);
383 } else {
384 w_reg_set_enable(reg_set, mvi->sata_reg_set);
385 tmp = mr32(MVS_INT_STAT_SRS_1) & mvi->sata_reg_set;
386 if (tmp)
387 mw32(MVS_INT_STAT_SRS_1, tmp);
388 }
389
390 *tfs = MVS_ID_NOT_MAPPED;
391
392 return;
393 }
394
395 static u8 mvs_94xx_assign_reg_set(struct mvs_info *mvi, u8 *tfs)
396 {
397 int i;
398 void __iomem *regs = mvi->regs;
399
400 if (*tfs != MVS_ID_NOT_MAPPED)
401 return 0;
402
403 i = mv_ffc64(mvi->sata_reg_set);
404 if (i > 32) {
405 mvi->sata_reg_set |= bit(i);
406 w_reg_set_enable(i, (u32)(mvi->sata_reg_set >> 32));
407 *tfs = i;
408 return 0;
409 } else if (i >= 0) {
410 mvi->sata_reg_set |= bit(i);
411 w_reg_set_enable(i, (u32)mvi->sata_reg_set);
412 *tfs = i;
413 return 0;
414 }
415 return MVS_ID_NOT_MAPPED;
416 }
417
418 static void mvs_94xx_make_prd(struct scatterlist *scatter, int nr, void *prd)
419 {
420 int i;
421 struct scatterlist *sg;
422 struct mvs_prd *buf_prd = prd;
423 for_each_sg(scatter, sg, nr, i) {
424 buf_prd->addr = cpu_to_le64(sg_dma_address(sg));
425 buf_prd->im_len.len = cpu_to_le32(sg_dma_len(sg));
426 buf_prd++;
427 }
428 }
429
430 static int mvs_94xx_oob_done(struct mvs_info *mvi, int i)
431 {
432 u32 phy_st;
433 phy_st = mvs_read_phy_ctl(mvi, i);
434 if (phy_st & PHY_READY_MASK) /* phy ready */
435 return 1;
436 return 0;
437 }
438
439 static void mvs_94xx_get_dev_identify_frame(struct mvs_info *mvi, int port_id,
440 struct sas_identify_frame *id)
441 {
442 int i;
443 u32 id_frame[7];
444
445 for (i = 0; i < 7; i++) {
446 mvs_write_port_cfg_addr(mvi, port_id,
447 CONFIG_ID_FRAME0 + i * 4);
448 id_frame[i] = mvs_read_port_cfg_data(mvi, port_id);
449 }
450 memcpy(id, id_frame, 28);
451 }
452
453 static void mvs_94xx_get_att_identify_frame(struct mvs_info *mvi, int port_id,
454 struct sas_identify_frame *id)
455 {
456 int i;
457 u32 id_frame[7];
458
459 /* mvs_hexdump(28, (u8 *)id_frame, 0); */
460 for (i = 0; i < 7; i++) {
461 mvs_write_port_cfg_addr(mvi, port_id,
462 CONFIG_ATT_ID_FRAME0 + i * 4);
463 id_frame[i] = mvs_read_port_cfg_data(mvi, port_id);
464 mv_dprintk("94xx phy %d atta frame %d %x.\n",
465 port_id + mvi->id * mvi->chip->n_phy, i, id_frame[i]);
466 }
467 /* mvs_hexdump(28, (u8 *)id_frame, 0); */
468 memcpy(id, id_frame, 28);
469 }
470
471 static u32 mvs_94xx_make_dev_info(struct sas_identify_frame *id)
472 {
473 u32 att_dev_info = 0;
474
475 att_dev_info |= id->dev_type;
476 if (id->stp_iport)
477 att_dev_info |= PORT_DEV_STP_INIT;
478 if (id->smp_iport)
479 att_dev_info |= PORT_DEV_SMP_INIT;
480 if (id->ssp_iport)
481 att_dev_info |= PORT_DEV_SSP_INIT;
482 if (id->stp_tport)
483 att_dev_info |= PORT_DEV_STP_TRGT;
484 if (id->smp_tport)
485 att_dev_info |= PORT_DEV_SMP_TRGT;
486 if (id->ssp_tport)
487 att_dev_info |= PORT_DEV_SSP_TRGT;
488
489 att_dev_info |= (u32)id->phy_id<<24;
490 return att_dev_info;
491 }
492
493 static u32 mvs_94xx_make_att_info(struct sas_identify_frame *id)
494 {
495 return mvs_94xx_make_dev_info(id);
496 }
497
498 static void mvs_94xx_fix_phy_info(struct mvs_info *mvi, int i,
499 struct sas_identify_frame *id)
500 {
501 struct mvs_phy *phy = &mvi->phy[i];
502 struct asd_sas_phy *sas_phy = &phy->sas_phy;
503 mv_dprintk("get all reg link rate is 0x%x\n", phy->phy_status);
504 sas_phy->linkrate =
505 (phy->phy_status & PHY_NEG_SPP_PHYS_LINK_RATE_MASK) >>
506 PHY_NEG_SPP_PHYS_LINK_RATE_MASK_OFFSET;
507 sas_phy->linkrate += 0x8;
508 mv_dprintk("get link rate is %d\n", sas_phy->linkrate);
509 phy->minimum_linkrate = SAS_LINK_RATE_1_5_GBPS;
510 phy->maximum_linkrate = SAS_LINK_RATE_6_0_GBPS;
511 mvs_94xx_get_dev_identify_frame(mvi, i, id);
512 phy->dev_info = mvs_94xx_make_dev_info(id);
513
514 if (phy->phy_type & PORT_TYPE_SAS) {
515 mvs_94xx_get_att_identify_frame(mvi, i, id);
516 phy->att_dev_info = mvs_94xx_make_att_info(id);
517 phy->att_dev_sas_addr = *(u64 *)id->sas_addr;
518 } else {
519 phy->att_dev_info = PORT_DEV_STP_TRGT | 1;
520 }
521
522 }
523
524 void mvs_94xx_phy_set_link_rate(struct mvs_info *mvi, u32 phy_id,
525 struct sas_phy_linkrates *rates)
526 {
527 /* TODO */
528 }
529
530 static void mvs_94xx_clear_active_cmds(struct mvs_info *mvi)
531 {
532 u32 tmp;
533 void __iomem *regs = mvi->regs;
534 tmp = mr32(MVS_STP_REG_SET_0);
535 mw32(MVS_STP_REG_SET_0, 0);
536 mw32(MVS_STP_REG_SET_0, tmp);
537 tmp = mr32(MVS_STP_REG_SET_1);
538 mw32(MVS_STP_REG_SET_1, 0);
539 mw32(MVS_STP_REG_SET_1, tmp);
540 }
541
542
543 u32 mvs_94xx_spi_read_data(struct mvs_info *mvi)
544 {
545 void __iomem *regs = mvi->regs_ex - 0x10200;
546 return mr32(SPI_RD_DATA_REG_94XX);
547 }
548
549 void mvs_94xx_spi_write_data(struct mvs_info *mvi, u32 data)
550 {
551 void __iomem *regs = mvi->regs_ex - 0x10200;
552 mw32(SPI_RD_DATA_REG_94XX, data);
553 }
554
555
556 int mvs_94xx_spi_buildcmd(struct mvs_info *mvi,
557 u32 *dwCmd,
558 u8 cmd,
559 u8 read,
560 u8 length,
561 u32 addr
562 )
563 {
564 void __iomem *regs = mvi->regs_ex - 0x10200;
565 u32 dwTmp;
566
567 dwTmp = ((u32)cmd << 8) | ((u32)length << 4);
568 if (read)
569 dwTmp |= SPI_CTRL_READ_94XX;
570
571 if (addr != MV_MAX_U32) {
572 mw32(SPI_ADDR_REG_94XX, (addr & 0x0003FFFFL));
573 dwTmp |= SPI_ADDR_VLD_94XX;
574 }
575
576 *dwCmd = dwTmp;
577 return 0;
578 }
579
580
581 int mvs_94xx_spi_issuecmd(struct mvs_info *mvi, u32 cmd)
582 {
583 void __iomem *regs = mvi->regs_ex - 0x10200;
584 mw32(SPI_CTRL_REG_94XX, cmd | SPI_CTRL_SpiStart_94XX);
585
586 return 0;
587 }
588
589 int mvs_94xx_spi_waitdataready(struct mvs_info *mvi, u32 timeout)
590 {
591 void __iomem *regs = mvi->regs_ex - 0x10200;
592 u32 i, dwTmp;
593
594 for (i = 0; i < timeout; i++) {
595 dwTmp = mr32(SPI_CTRL_REG_94XX);
596 if (!(dwTmp & SPI_CTRL_SpiStart_94XX))
597 return 0;
598 msleep(10);
599 }
600
601 return -1;
602 }
603
604 #ifndef DISABLE_HOTPLUG_DMA_FIX
605 void mvs_94xx_fix_dma(dma_addr_t buf_dma, int buf_len, int from, void *prd)
606 {
607 int i;
608 struct mvs_prd *buf_prd = prd;
609 buf_prd += from;
610 for (i = 0; i < MAX_SG_ENTRY - from; i++) {
611 buf_prd->addr = cpu_to_le64(buf_dma);
612 buf_prd->im_len.len = cpu_to_le32(buf_len);
613 ++buf_prd;
614 }
615 }
616 #endif
617
618 static void mvs_94xx_clear_srs_irq(struct mvs_info *mvi, u8 reg_set,
619 u8 clear_all)
620 {
621 }
622
623 const struct mvs_dispatch mvs_94xx_dispatch = {
624 "mv94xx",
625 mvs_94xx_init,
626 NULL,
627 mvs_94xx_ioremap,
628 mvs_94xx_iounmap,
629 mvs_94xx_isr,
630 mvs_94xx_isr_status,
631 mvs_94xx_interrupt_enable,
632 mvs_94xx_interrupt_disable,
633 mvs_read_phy_ctl,
634 mvs_write_phy_ctl,
635 mvs_read_port_cfg_data,
636 mvs_write_port_cfg_data,
637 mvs_write_port_cfg_addr,
638 mvs_read_port_vsr_data,
639 mvs_write_port_vsr_data,
640 mvs_write_port_vsr_addr,
641 mvs_read_port_irq_stat,
642 mvs_write_port_irq_stat,
643 mvs_read_port_irq_mask,
644 mvs_write_port_irq_mask,
645 mvs_get_sas_addr,
646 mvs_94xx_command_active,
647 mvs_94xx_clear_srs_irq,
648 mvs_94xx_issue_stop,
649 mvs_start_delivery,
650 mvs_rx_update,
651 mvs_int_full,
652 mvs_94xx_assign_reg_set,
653 mvs_94xx_free_reg_set,
654 mvs_get_prd_size,
655 mvs_get_prd_count,
656 mvs_94xx_make_prd,
657 mvs_94xx_detect_porttype,
658 mvs_94xx_oob_done,
659 mvs_94xx_fix_phy_info,
660 NULL,
661 mvs_94xx_phy_set_link_rate,
662 mvs_hw_max_link_rate,
663 mvs_94xx_phy_disable,
664 mvs_94xx_phy_enable,
665 mvs_94xx_phy_reset,
666 NULL,
667 mvs_94xx_clear_active_cmds,
668 mvs_94xx_spi_read_data,
669 mvs_94xx_spi_write_data,
670 mvs_94xx_spi_buildcmd,
671 mvs_94xx_spi_issuecmd,
672 mvs_94xx_spi_waitdataready,
673 #ifndef DISABLE_HOTPLUG_DMA_FIX
674 mvs_94xx_fix_dma,
675 #endif
676 };
Tomato firmware and modifications.