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GUI: Fix Tomato RAF theme for all builds. Compilation typo.
[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / drivers / scsi / mesh.c
blob3de11c1e3efd9559ec7161068fb4374ab4b3b410
1 /*
2 * SCSI low-level driver for the MESH (Macintosh Enhanced SCSI Hardware)
3 * bus adaptor found on Power Macintosh computers.
4 * We assume the MESH is connected to a DBDMA (descriptor-based DMA)
5 * controller.
6 *
7 * Paul Mackerras, August 1996.
8 * Copyright (C) 1996 Paul Mackerras.
9 *
10 * Apr. 21 2002 - BenH Rework bus reset code for new error handler
11 * Add delay after initial bus reset
12 * Add module parameters
13 *
14 * Sep. 27 2003 - BenH Move to new driver model, fix some write posting
15 * issues
16 * To do:
17 * - handle aborts correctly
18 * - retry arbitration if lost (unless higher levels do this for us)
19 * - power down the chip when no device is detected
20 */
21 #include <linux/module.h>
22 #include <linux/kernel.h>
23 #include <linux/delay.h>
24 #include <linux/types.h>
25 #include <linux/string.h>
26 #include <linux/blkdev.h>
27 #include <linux/proc_fs.h>
28 #include <linux/stat.h>
29 #include <linux/interrupt.h>
30 #include <linux/reboot.h>
31 #include <linux/spinlock.h>
32 #include <asm/dbdma.h>
33 #include <asm/io.h>
34 #include <asm/pgtable.h>
35 #include <asm/prom.h>
36 #include <asm/system.h>
37 #include <asm/irq.h>
38 #include <asm/hydra.h>
39 #include <asm/processor.h>
40 #include <asm/machdep.h>
41 #include <asm/pmac_feature.h>
42 #include <asm/pci-bridge.h>
43 #include <asm/macio.h>
44
45 #include <scsi/scsi.h>
46 #include <scsi/scsi_cmnd.h>
47 #include <scsi/scsi_device.h>
48 #include <scsi/scsi_host.h>
49
50 #include "mesh.h"
51
52 #undef KERN_DEBUG
53 #define KERN_DEBUG KERN_WARNING
54
55 MODULE_AUTHOR("Paul Mackerras (paulus@samba.org)");
56 MODULE_DESCRIPTION("PowerMac MESH SCSI driver");
57 MODULE_LICENSE("GPL");
58
59 static int sync_rate = CONFIG_SCSI_MESH_SYNC_RATE;
60 static int sync_targets = 0xff;
61 static int resel_targets = 0xff;
62 static int debug_targets = 0; /* print debug for these targets */
63 static int init_reset_delay = CONFIG_SCSI_MESH_RESET_DELAY_MS;
64
65 module_param(sync_rate, int, 0);
66 MODULE_PARM_DESC(sync_rate, "Synchronous rate (0..10, 0=async)");
67 module_param(sync_targets, int, 0);
68 MODULE_PARM_DESC(sync_targets, "Bitmask of targets allowed to set synchronous");
69 module_param(resel_targets, int, 0);
70 MODULE_PARM_DESC(resel_targets, "Bitmask of targets allowed to set disconnect");
71 module_param(debug_targets, int, 0644);
72 MODULE_PARM_DESC(debug_targets, "Bitmask of debugged targets");
73 module_param(init_reset_delay, int, 0);
74 MODULE_PARM_DESC(init_reset_delay, "Initial bus reset delay (0=no reset)");
75
76 static int mesh_sync_period = 100;
77 static int mesh_sync_offset = 0;
78 static unsigned char use_active_neg = 0; /* bit mask for SEQ_ACTIVE_NEG if used */
79
80 #define ALLOW_SYNC(tgt) ((sync_targets >> (tgt)) & 1)
81 #define ALLOW_RESEL(tgt) ((resel_targets >> (tgt)) & 1)
82 #define ALLOW_DEBUG(tgt) ((debug_targets >> (tgt)) & 1)
83 #define DEBUG_TARGET(cmd) ((cmd) && ALLOW_DEBUG((cmd)->device->id))
84
85 #undef MESH_DBG
86 #define N_DBG_LOG 50
87 #define N_DBG_SLOG 20
88 #define NUM_DBG_EVENTS 13
89 #undef DBG_USE_TB /* bombs on 601 */
90
91 struct dbglog {
92 char *fmt;
93 u32 tb;
94 u8 phase;
95 u8 bs0;
96 u8 bs1;
97 u8 tgt;
98 int d;
99 };
100
101 enum mesh_phase {
102 idle,
103 arbitrating,
104 selecting,
105 commanding,
106 dataing,
107 statusing,
108 busfreeing,
109 disconnecting,
110 reselecting,
111 sleeping
112 };
113
114 enum msg_phase {
115 msg_none,
116 msg_out,
117 msg_out_xxx,
118 msg_out_last,
119 msg_in,
120 msg_in_bad,
121 };
122
123 enum sdtr_phase {
124 do_sdtr,
125 sdtr_sent,
126 sdtr_done
127 };
128
129 struct mesh_target {
130 enum sdtr_phase sdtr_state;
131 int sync_params;
132 int data_goes_out; /* guess as to data direction */
133 struct scsi_cmnd *current_req;
134 u32 saved_ptr;
135 #ifdef MESH_DBG
136 int log_ix;
137 int n_log;
138 struct dbglog log[N_DBG_LOG];
139 #endif
140 };
141
142 struct mesh_state {
143 volatile struct mesh_regs __iomem *mesh;
144 int meshintr;
145 volatile struct dbdma_regs __iomem *dma;
146 int dmaintr;
147 struct Scsi_Host *host;
148 struct mesh_state *next;
149 struct scsi_cmnd *request_q;
150 struct scsi_cmnd *request_qtail;
151 enum mesh_phase phase; /* what we're currently trying to do */
152 enum msg_phase msgphase;
153 int conn_tgt; /* target we're connected to */
154 struct scsi_cmnd *current_req; /* req we're currently working on */
155 int data_ptr;
156 int dma_started;
157 int dma_count;
158 int stat;
159 int aborting;
160 int expect_reply;
161 int n_msgin;
162 u8 msgin[16];
163 int n_msgout;
164 int last_n_msgout;
165 u8 msgout[16];
166 struct dbdma_cmd *dma_cmds; /* space for dbdma commands, aligned */
167 dma_addr_t dma_cmd_bus;
168 void *dma_cmd_space;
169 int dma_cmd_size;
170 int clk_freq;
171 struct mesh_target tgts[8];
172 struct macio_dev *mdev;
173 struct pci_dev* pdev;
174 #ifdef MESH_DBG
175 int log_ix;
176 int n_log;
177 struct dbglog log[N_DBG_SLOG];
178 #endif
179 };
180
181 /*
182 * Driver is too messy, we need a few prototypes...
183 */
184 static void mesh_done(struct mesh_state *ms, int start_next);
185 static void mesh_interrupt(struct mesh_state *ms);
186 static void cmd_complete(struct mesh_state *ms);
187 static void set_dma_cmds(struct mesh_state *ms, struct scsi_cmnd *cmd);
188 static void halt_dma(struct mesh_state *ms);
189 static void phase_mismatch(struct mesh_state *ms);
190
191
192 /*
193 * Some debugging & logging routines
194 */
195
196 #ifdef MESH_DBG
197
198 static inline u32 readtb(void)
199 {
200 u32 tb;
201
202 #ifdef DBG_USE_TB
203 /* Beware: if you enable this, it will crash on 601s. */
204 asm ("mftb %0" : "=r" (tb) : );
205 #else
206 tb = 0;
207 #endif
208 return tb;
209 }
210
211 static void dlog(struct mesh_state *ms, char *fmt, int a)
212 {
213 struct mesh_target *tp = &ms->tgts[ms->conn_tgt];
214 struct dbglog *tlp, *slp;
215
216 tlp = &tp->log[tp->log_ix];
217 slp = &ms->log[ms->log_ix];
218 tlp->fmt = fmt;
219 tlp->tb = readtb();
220 tlp->phase = (ms->msgphase << 4) + ms->phase;
221 tlp->bs0 = ms->mesh->bus_status0;
222 tlp->bs1 = ms->mesh->bus_status1;
223 tlp->tgt = ms->conn_tgt;
224 tlp->d = a;
225 *slp = *tlp;
226 if (++tp->log_ix >= N_DBG_LOG)
227 tp->log_ix = 0;
228 if (tp->n_log < N_DBG_LOG)
229 ++tp->n_log;
230 if (++ms->log_ix >= N_DBG_SLOG)
231 ms->log_ix = 0;
232 if (ms->n_log < N_DBG_SLOG)
233 ++ms->n_log;
234 }
235
236 static void dumplog(struct mesh_state *ms, int t)
237 {
238 struct mesh_target *tp = &ms->tgts[t];
239 struct dbglog *lp;
240 int i;
241
242 if (tp->n_log == 0)
243 return;
244 i = tp->log_ix - tp->n_log;
245 if (i < 0)
246 i += N_DBG_LOG;
247 tp->n_log = 0;
248 do {
249 lp = &tp->log[i];
250 printk(KERN_DEBUG "mesh log %d: bs=%.2x%.2x ph=%.2x ",
251 t, lp->bs1, lp->bs0, lp->phase);
252 #ifdef DBG_USE_TB
253 printk("tb=%10u ", lp->tb);
254 #endif
255 printk(lp->fmt, lp->d);
256 printk("\n");
257 if (++i >= N_DBG_LOG)
258 i = 0;
259 } while (i != tp->log_ix);
260 }
261
262 static void dumpslog(struct mesh_state *ms)
263 {
264 struct dbglog *lp;
265 int i;
266
267 if (ms->n_log == 0)
268 return;
269 i = ms->log_ix - ms->n_log;
270 if (i < 0)
271 i += N_DBG_SLOG;
272 ms->n_log = 0;
273 do {
274 lp = &ms->log[i];
275 printk(KERN_DEBUG "mesh log: bs=%.2x%.2x ph=%.2x t%d ",
276 lp->bs1, lp->bs0, lp->phase, lp->tgt);
277 #ifdef DBG_USE_TB
278 printk("tb=%10u ", lp->tb);
279 #endif
280 printk(lp->fmt, lp->d);
281 printk("\n");
282 if (++i >= N_DBG_SLOG)
283 i = 0;
284 } while (i != ms->log_ix);
285 }
286
287 #else
288
289 static inline void dlog(struct mesh_state *ms, char *fmt, int a)
290 {}
291 static inline void dumplog(struct mesh_state *ms, int tgt)
292 {}
293 static inline void dumpslog(struct mesh_state *ms)
294 {}
295
296 #endif /* MESH_DBG */
297
298 #define MKWORD(a, b, c, d) (((a) << 24) + ((b) << 16) + ((c) << 8) + (d))
299
300 static void
301 mesh_dump_regs(struct mesh_state *ms)
302 {
303 volatile struct mesh_regs __iomem *mr = ms->mesh;
304 volatile struct dbdma_regs __iomem *md = ms->dma;
305 int t;
306 struct mesh_target *tp;
307
308 printk(KERN_DEBUG "mesh: state at %p, regs at %p, dma at %p\n",
309 ms, mr, md);
310 printk(KERN_DEBUG " ct=%4x seq=%2x bs=%4x fc=%2x "
311 "exc=%2x err=%2x im=%2x int=%2x sp=%2x\n",
312 (mr->count_hi << 8) + mr->count_lo, mr->sequence,
313 (mr->bus_status1 << 8) + mr->bus_status0, mr->fifo_count,
314 mr->exception, mr->error, mr->intr_mask, mr->interrupt,
315 mr->sync_params);
316 while(in_8(&mr->fifo_count))
317 printk(KERN_DEBUG " fifo data=%.2x\n",in_8(&mr->fifo));
318 printk(KERN_DEBUG " dma stat=%x cmdptr=%x\n",
319 in_le32(&md->status), in_le32(&md->cmdptr));
320 printk(KERN_DEBUG " phase=%d msgphase=%d conn_tgt=%d data_ptr=%d\n",
321 ms->phase, ms->msgphase, ms->conn_tgt, ms->data_ptr);
322 printk(KERN_DEBUG " dma_st=%d dma_ct=%d n_msgout=%d\n",
323 ms->dma_started, ms->dma_count, ms->n_msgout);
324 for (t = 0; t < 8; ++t) {
325 tp = &ms->tgts[t];
326 if (tp->current_req == NULL)
327 continue;
328 printk(KERN_DEBUG " target %d: req=%p goes_out=%d saved_ptr=%d\n",
329 t, tp->current_req, tp->data_goes_out, tp->saved_ptr);
330 }
331 }
332
333
334 /*
335 * Flush write buffers on the bus path to the mesh
336 */
337 static inline void mesh_flush_io(volatile struct mesh_regs __iomem *mr)
338 {
339 (void)in_8(&mr->mesh_id);
340 }
341
342
343 /*
344 * Complete a SCSI command
345 */
346 static void mesh_completed(struct mesh_state *ms, struct scsi_cmnd *cmd)
347 {
348 (*cmd->scsi_done)(cmd);
349 }
350
351
352 /* Called with meshinterrupt disabled, initialize the chipset
353 * and eventually do the initial bus reset. The lock must not be
354 * held since we can schedule.
355 */
356 static void mesh_init(struct mesh_state *ms)
357 {
358 volatile struct mesh_regs __iomem *mr = ms->mesh;
359 volatile struct dbdma_regs __iomem *md = ms->dma;
360
361 mesh_flush_io(mr);
362 udelay(100);
363
364 /* Reset controller */
365 out_le32(&md->control, (RUN|PAUSE|FLUSH|WAKE) << 16); /* stop dma */
366 out_8(&mr->exception, 0xff); /* clear all exception bits */
367 out_8(&mr->error, 0xff); /* clear all error bits */
368 out_8(&mr->sequence, SEQ_RESETMESH);
369 mesh_flush_io(mr);
370 udelay(10);
371 out_8(&mr->intr_mask, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
372 out_8(&mr->source_id, ms->host->this_id);
373 out_8(&mr->sel_timeout, 25); /* 250ms */
374 out_8(&mr->sync_params, ASYNC_PARAMS);
375
376 if (init_reset_delay) {
377 printk(KERN_INFO "mesh: performing initial bus reset...\n");
378
379 /* Reset bus */
380 out_8(&mr->bus_status1, BS1_RST); /* assert RST */
381 mesh_flush_io(mr);
382 udelay(30); /* leave it on for >= 25us */
383 out_8(&mr->bus_status1, 0); /* negate RST */
384 mesh_flush_io(mr);
385
386 /* Wait for bus to come back */
387 msleep(init_reset_delay);
388 }
389
390 /* Reconfigure controller */
391 out_8(&mr->interrupt, 0xff); /* clear all interrupt bits */
392 out_8(&mr->sequence, SEQ_FLUSHFIFO);
393 mesh_flush_io(mr);
394 udelay(1);
395 out_8(&mr->sync_params, ASYNC_PARAMS);
396 out_8(&mr->sequence, SEQ_ENBRESEL);
397
398 ms->phase = idle;
399 ms->msgphase = msg_none;
400 }
401
402
403 static void mesh_start_cmd(struct mesh_state *ms, struct scsi_cmnd *cmd)
404 {
405 volatile struct mesh_regs __iomem *mr = ms->mesh;
406 int t, id;
407
408 id = cmd->device->id;
409 ms->current_req = cmd;
410 ms->tgts[id].data_goes_out = cmd->sc_data_direction == DMA_TO_DEVICE;
411 ms->tgts[id].current_req = cmd;
412
413 if (DEBUG_TARGET(cmd)) {
414 int i;
415 printk(KERN_DEBUG "mesh_start: %p ser=%lu tgt=%d cmd=",
416 cmd, cmd->serial_number, id);
417 for (i = 0; i < cmd->cmd_len; ++i)
418 printk(" %x", cmd->cmnd[i]);
419 printk(" use_sg=%d buffer=%p bufflen=%u\n",
420 scsi_sg_count(cmd), scsi_sglist(cmd), scsi_bufflen(cmd));
421 }
422 if (ms->dma_started)
423 panic("mesh: double DMA start !\n");
424
425 ms->phase = arbitrating;
426 ms->msgphase = msg_none;
427 ms->data_ptr = 0;
428 ms->dma_started = 0;
429 ms->n_msgout = 0;
430 ms->last_n_msgout = 0;
431 ms->expect_reply = 0;
432 ms->conn_tgt = id;
433 ms->tgts[id].saved_ptr = 0;
434 ms->stat = DID_OK;
435 ms->aborting = 0;
436 #ifdef MESH_DBG
437 ms->tgts[id].n_log = 0;
438 dlog(ms, "start cmd=%x", (int) cmd);
439 #endif
440
441 /* Off we go */
442 dlog(ms, "about to arb, intr/exc/err/fc=%.8x",
443 MKWORD(mr->interrupt, mr->exception, mr->error, mr->fifo_count));
444 out_8(&mr->interrupt, INT_CMDDONE);
445 out_8(&mr->sequence, SEQ_ENBRESEL);
446 mesh_flush_io(mr);
447 udelay(1);
448
449 if (in_8(&mr->bus_status1) & (BS1_BSY | BS1_SEL)) {
450 /*
451 * Some other device has the bus or is arbitrating for it -
452 * probably a target which is about to reselect us.
453 */
454 dlog(ms, "busy b4 arb, intr/exc/err/fc=%.8x",
455 MKWORD(mr->interrupt, mr->exception,
456 mr->error, mr->fifo_count));
457 for (t = 100; t > 0; --t) {
458 if ((in_8(&mr->bus_status1) & (BS1_BSY | BS1_SEL)) == 0)
459 break;
460 if (in_8(&mr->interrupt) != 0) {
461 dlog(ms, "intr b4 arb, intr/exc/err/fc=%.8x",
462 MKWORD(mr->interrupt, mr->exception,
463 mr->error, mr->fifo_count));
464 mesh_interrupt(ms);
465 if (ms->phase != arbitrating)
466 return;
467 }
468 udelay(1);
469 }
470 if (in_8(&mr->bus_status1) & (BS1_BSY | BS1_SEL)) {
471 ms->stat = DID_BUS_BUSY;
472 ms->phase = idle;
473 mesh_done(ms, 0);
474 return;
475 }
476 }
477
478 /*
479 * Apparently the mesh has a bug where it will assert both its
480 * own bit and the target's bit on the bus during arbitration.
481 */
482 out_8(&mr->dest_id, mr->source_id);
483
484 /*
485 * There appears to be a race with reselection sometimes,
486 * where a target reselects us just as we issue the
487 * arbitrate command. It seems that then the arbitrate
488 * command just hangs waiting for the bus to be free
489 * without giving us a reselection exception.
490 * The only way I have found to get it to respond correctly
491 * is this: disable reselection before issuing the arbitrate
492 * command, then after issuing it, if it looks like a target
493 * is trying to reselect us, reset the mesh and then enable
494 * reselection.
495 */
496 out_8(&mr->sequence, SEQ_DISRESEL);
497 if (in_8(&mr->interrupt) != 0) {
498 dlog(ms, "intr after disresel, intr/exc/err/fc=%.8x",
499 MKWORD(mr->interrupt, mr->exception,
500 mr->error, mr->fifo_count));
501 mesh_interrupt(ms);
502 if (ms->phase != arbitrating)
503 return;
504 dlog(ms, "after intr after disresel, intr/exc/err/fc=%.8x",
505 MKWORD(mr->interrupt, mr->exception,
506 mr->error, mr->fifo_count));
507 }
508
509 out_8(&mr->sequence, SEQ_ARBITRATE);
510
511 for (t = 230; t > 0; --t) {
512 if (in_8(&mr->interrupt) != 0)
513 break;
514 udelay(1);
515 }
516 dlog(ms, "after arb, intr/exc/err/fc=%.8x",
517 MKWORD(mr->interrupt, mr->exception, mr->error, mr->fifo_count));
518 if (in_8(&mr->interrupt) == 0 && (in_8(&mr->bus_status1) & BS1_SEL)
519 && (in_8(&mr->bus_status0) & BS0_IO)) {
520 /* looks like a reselection - try resetting the mesh */
521 dlog(ms, "resel? after arb, intr/exc/err/fc=%.8x",
522 MKWORD(mr->interrupt, mr->exception, mr->error, mr->fifo_count));
523 out_8(&mr->sequence, SEQ_RESETMESH);
524 mesh_flush_io(mr);
525 udelay(10);
526 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
527 out_8(&mr->intr_mask, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
528 out_8(&mr->sequence, SEQ_ENBRESEL);
529 mesh_flush_io(mr);
530 for (t = 10; t > 0 && in_8(&mr->interrupt) == 0; --t)
531 udelay(1);
532 dlog(ms, "tried reset after arb, intr/exc/err/fc=%.8x",
533 MKWORD(mr->interrupt, mr->exception, mr->error, mr->fifo_count));
534 #ifndef MESH_MULTIPLE_HOSTS
535 if (in_8(&mr->interrupt) == 0 && (in_8(&mr->bus_status1) & BS1_SEL)
536 && (in_8(&mr->bus_status0) & BS0_IO)) {
537 printk(KERN_ERR "mesh: controller not responding"
538 " to reselection!\n");
539 /*
540 * If this is a target reselecting us, and the
541 * mesh isn't responding, the higher levels of
542 * the scsi code will eventually time out and
543 * reset the bus.
544 */
545 }
546 #endif
547 }
548 }
549
550 /*
551 * Start the next command for a MESH.
552 * Should be called with interrupts disabled.
553 */
554 static void mesh_start(struct mesh_state *ms)
555 {
556 struct scsi_cmnd *cmd, *prev, *next;
557
558 if (ms->phase != idle || ms->current_req != NULL) {
559 printk(KERN_ERR "inappropriate mesh_start (phase=%d, ms=%p)",
560 ms->phase, ms);
561 return;
562 }
563
564 while (ms->phase == idle) {
565 prev = NULL;
566 for (cmd = ms->request_q; ; cmd = (struct scsi_cmnd *) cmd->host_scribble) {
567 if (cmd == NULL)
568 return;
569 if (ms->tgts[cmd->device->id].current_req == NULL)
570 break;
571 prev = cmd;
572 }
573 next = (struct scsi_cmnd *) cmd->host_scribble;
574 if (prev == NULL)
575 ms->request_q = next;
576 else
577 prev->host_scribble = (void *) next;
578 if (next == NULL)
579 ms->request_qtail = prev;
580
581 mesh_start_cmd(ms, cmd);
582 }
583 }
584
585 static void mesh_done(struct mesh_state *ms, int start_next)
586 {
587 struct scsi_cmnd *cmd;
588 struct mesh_target *tp = &ms->tgts[ms->conn_tgt];
589
590 cmd = ms->current_req;
591 ms->current_req = NULL;
592 tp->current_req = NULL;
593 if (cmd) {
594 cmd->result = (ms->stat << 16) + cmd->SCp.Status;
595 if (ms->stat == DID_OK)
596 cmd->result += (cmd->SCp.Message << 8);
597 if (DEBUG_TARGET(cmd)) {
598 printk(KERN_DEBUG "mesh_done: result = %x, data_ptr=%d, buflen=%d\n",
599 cmd->result, ms->data_ptr, scsi_bufflen(cmd));
600 }
601 cmd->SCp.this_residual -= ms->data_ptr;
602 mesh_completed(ms, cmd);
603 }
604 if (start_next) {
605 out_8(&ms->mesh->sequence, SEQ_ENBRESEL);
606 mesh_flush_io(ms->mesh);
607 udelay(1);
608 ms->phase = idle;
609 mesh_start(ms);
610 }
611 }
612
613 static inline void add_sdtr_msg(struct mesh_state *ms)
614 {
615 int i = ms->n_msgout;
616
617 ms->msgout[i] = EXTENDED_MESSAGE;
618 ms->msgout[i+1] = 3;
619 ms->msgout[i+2] = EXTENDED_SDTR;
620 ms->msgout[i+3] = mesh_sync_period/4;
621 ms->msgout[i+4] = (ALLOW_SYNC(ms->conn_tgt)? mesh_sync_offset: 0);
622 ms->n_msgout = i + 5;
623 }
624
625 static void set_sdtr(struct mesh_state *ms, int period, int offset)
626 {
627 struct mesh_target *tp = &ms->tgts[ms->conn_tgt];
628 volatile struct mesh_regs __iomem *mr = ms->mesh;
629 int v, tr;
630
631 tp->sdtr_state = sdtr_done;
632 if (offset == 0) {
633 /* asynchronous */
634 if (SYNC_OFF(tp->sync_params))
635 printk(KERN_INFO "mesh: target %d now asynchronous\n",
636 ms->conn_tgt);
637 tp->sync_params = ASYNC_PARAMS;
638 out_8(&mr->sync_params, ASYNC_PARAMS);
639 return;
640 }
641 /*
642 * We need to compute ceil(clk_freq * period / 500e6) - 2
643 * without incurring overflow.
644 */
645 v = (ms->clk_freq / 5000) * period;
646 if (v <= 250000) {
647 /* special case: sync_period == 5 * clk_period */
648 v = 0;
649 /* units of tr are 100kB/s */
650 tr = (ms->clk_freq + 250000) / 500000;
651 } else {
652 /* sync_period == (v + 2) * 2 * clk_period */
653 v = (v + 99999) / 100000 - 2;
654 if (v > 15)
655 v = 15; /* oops */
656 tr = ((ms->clk_freq / (v + 2)) + 199999) / 200000;
657 }
658 if (offset > 15)
659 offset = 15; /* can't happen */
660 tp->sync_params = SYNC_PARAMS(offset, v);
661 out_8(&mr->sync_params, tp->sync_params);
662 printk(KERN_INFO "mesh: target %d synchronous at %d.%d MB/s\n",
663 ms->conn_tgt, tr/10, tr%10);
664 }
665
666 static void start_phase(struct mesh_state *ms)
667 {
668 int i, seq, nb;
669 volatile struct mesh_regs __iomem *mr = ms->mesh;
670 volatile struct dbdma_regs __iomem *md = ms->dma;
671 struct scsi_cmnd *cmd = ms->current_req;
672 struct mesh_target *tp = &ms->tgts[ms->conn_tgt];
673
674 dlog(ms, "start_phase nmo/exc/fc/seq = %.8x",
675 MKWORD(ms->n_msgout, mr->exception, mr->fifo_count, mr->sequence));
676 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
677 seq = use_active_neg + (ms->n_msgout? SEQ_ATN: 0);
678 switch (ms->msgphase) {
679 case msg_none:
680 break;
681
682 case msg_in:
683 out_8(&mr->count_hi, 0);
684 out_8(&mr->count_lo, 1);
685 out_8(&mr->sequence, SEQ_MSGIN + seq);
686 ms->n_msgin = 0;
687 return;
688
689 case msg_out:
690 /*
691 * To make sure ATN drops before we assert ACK for
692 * the last byte of the message, we have to do the
693 * last byte specially.
694 */
695 if (ms->n_msgout <= 0) {
696 printk(KERN_ERR "mesh: msg_out but n_msgout=%d\n",
697 ms->n_msgout);
698 mesh_dump_regs(ms);
699 ms->msgphase = msg_none;
700 break;
701 }
702 if (ALLOW_DEBUG(ms->conn_tgt)) {
703 printk(KERN_DEBUG "mesh: sending %d msg bytes:",
704 ms->n_msgout);
705 for (i = 0; i < ms->n_msgout; ++i)
706 printk(" %x", ms->msgout[i]);
707 printk("\n");
708 }
709 dlog(ms, "msgout msg=%.8x", MKWORD(ms->n_msgout, ms->msgout[0],
710 ms->msgout[1], ms->msgout[2]));
711 out_8(&mr->count_hi, 0);
712 out_8(&mr->sequence, SEQ_FLUSHFIFO);
713 mesh_flush_io(mr);
714 udelay(1);
715 /*
716 * If ATN is not already asserted, we assert it, then
717 * issue a SEQ_MSGOUT to get the mesh to drop ACK.
718 */
719 if ((in_8(&mr->bus_status0) & BS0_ATN) == 0) {
720 dlog(ms, "bus0 was %.2x explicitly asserting ATN", mr->bus_status0);
721 out_8(&mr->bus_status0, BS0_ATN); /* explicit ATN */
722 mesh_flush_io(mr);
723 udelay(1);
724 out_8(&mr->count_lo, 1);
725 out_8(&mr->sequence, SEQ_MSGOUT + seq);
726 out_8(&mr->bus_status0, 0); /* release explicit ATN */
727 dlog(ms,"hace: after explicit ATN bus0=%.2x",mr->bus_status0);
728 }
729 if (ms->n_msgout == 1) {
730 /*
731 * We can't issue the SEQ_MSGOUT without ATN
732 * until the target has asserted REQ. The logic
733 * in cmd_complete handles both situations:
734 * REQ already asserted or not.
735 */
736 cmd_complete(ms);
737 } else {
738 out_8(&mr->count_lo, ms->n_msgout - 1);
739 out_8(&mr->sequence, SEQ_MSGOUT + seq);
740 for (i = 0; i < ms->n_msgout - 1; ++i)
741 out_8(&mr->fifo, ms->msgout[i]);
742 }
743 return;
744
745 default:
746 printk(KERN_ERR "mesh bug: start_phase msgphase=%d\n",
747 ms->msgphase);
748 }
749
750 switch (ms->phase) {
751 case selecting:
752 out_8(&mr->dest_id, ms->conn_tgt);
753 out_8(&mr->sequence, SEQ_SELECT + SEQ_ATN);
754 break;
755 case commanding:
756 out_8(&mr->sync_params, tp->sync_params);
757 out_8(&mr->count_hi, 0);
758 if (cmd) {
759 out_8(&mr->count_lo, cmd->cmd_len);
760 out_8(&mr->sequence, SEQ_COMMAND + seq);
761 for (i = 0; i < cmd->cmd_len; ++i)
762 out_8(&mr->fifo, cmd->cmnd[i]);
763 } else {
764 out_8(&mr->count_lo, 6);
765 out_8(&mr->sequence, SEQ_COMMAND + seq);
766 for (i = 0; i < 6; ++i)
767 out_8(&mr->fifo, 0);
768 }
769 break;
770 case dataing:
771 /* transfer data, if any */
772 if (!ms->dma_started) {
773 set_dma_cmds(ms, cmd);
774 out_le32(&md->cmdptr, virt_to_phys(ms->dma_cmds));
775 out_le32(&md->control, (RUN << 16) | RUN);
776 ms->dma_started = 1;
777 }
778 nb = ms->dma_count;
779 if (nb > 0xfff0)
780 nb = 0xfff0;
781 ms->dma_count -= nb;
782 ms->data_ptr += nb;
783 out_8(&mr->count_lo, nb);
784 out_8(&mr->count_hi, nb >> 8);
785 out_8(&mr->sequence, (tp->data_goes_out?
786 SEQ_DATAOUT: SEQ_DATAIN) + SEQ_DMA_MODE + seq);
787 break;
788 case statusing:
789 out_8(&mr->count_hi, 0);
790 out_8(&mr->count_lo, 1);
791 out_8(&mr->sequence, SEQ_STATUS + seq);
792 break;
793 case busfreeing:
794 case disconnecting:
795 out_8(&mr->sequence, SEQ_ENBRESEL);
796 mesh_flush_io(mr);
797 udelay(1);
798 dlog(ms, "enbresel intr/exc/err/fc=%.8x",
799 MKWORD(mr->interrupt, mr->exception, mr->error,
800 mr->fifo_count));
801 out_8(&mr->sequence, SEQ_BUSFREE);
802 break;
803 default:
804 printk(KERN_ERR "mesh: start_phase called with phase=%d\n",
805 ms->phase);
806 dumpslog(ms);
807 }
808
809 }
810
811 static inline void get_msgin(struct mesh_state *ms)
812 {
813 volatile struct mesh_regs __iomem *mr = ms->mesh;
814 int i, n;
815
816 n = mr->fifo_count;
817 if (n != 0) {
818 i = ms->n_msgin;
819 ms->n_msgin = i + n;
820 for (; n > 0; --n)
821 ms->msgin[i++] = in_8(&mr->fifo);
822 }
823 }
824
825 static inline int msgin_length(struct mesh_state *ms)
826 {
827 int b, n;
828
829 n = 1;
830 if (ms->n_msgin > 0) {
831 b = ms->msgin[0];
832 if (b == 1) {
833 /* extended message */
834 n = ms->n_msgin < 2? 2: ms->msgin[1] + 2;
835 } else if (0x20 <= b && b <= 0x2f) {
836 /* 2-byte message */
837 n = 2;
838 }
839 }
840 return n;
841 }
842
843 static void reselected(struct mesh_state *ms)
844 {
845 volatile struct mesh_regs __iomem *mr = ms->mesh;
846 struct scsi_cmnd *cmd;
847 struct mesh_target *tp;
848 int b, t, prev;
849
850 switch (ms->phase) {
851 case idle:
852 break;
853 case arbitrating:
854 if ((cmd = ms->current_req) != NULL) {
855 /* put the command back on the queue */
856 cmd->host_scribble = (void *) ms->request_q;
857 if (ms->request_q == NULL)
858 ms->request_qtail = cmd;
859 ms->request_q = cmd;
860 tp = &ms->tgts[cmd->device->id];
861 tp->current_req = NULL;
862 }
863 break;
864 case busfreeing:
865 ms->phase = reselecting;
866 mesh_done(ms, 0);
867 break;
868 case disconnecting:
869 break;
870 default:
871 printk(KERN_ERR "mesh: reselected in phase %d/%d tgt %d\n",
872 ms->msgphase, ms->phase, ms->conn_tgt);
873 dumplog(ms, ms->conn_tgt);
874 dumpslog(ms);
875 }
876
877 if (ms->dma_started) {
878 printk(KERN_ERR "mesh: reselected with DMA started !\n");
879 halt_dma(ms);
880 }
881 ms->current_req = NULL;
882 ms->phase = dataing;
883 ms->msgphase = msg_in;
884 ms->n_msgout = 0;
885 ms->last_n_msgout = 0;
886 prev = ms->conn_tgt;
887
888 /*
889 * We seem to get abortive reselections sometimes.
890 */
891 while ((in_8(&mr->bus_status1) & BS1_BSY) == 0) {
892 static int mesh_aborted_resels;
893 mesh_aborted_resels++;
894 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
895 mesh_flush_io(mr);
896 udelay(1);
897 out_8(&mr->sequence, SEQ_ENBRESEL);
898 mesh_flush_io(mr);
899 udelay(5);
900 dlog(ms, "extra resel err/exc/fc = %.6x",
901 MKWORD(0, mr->error, mr->exception, mr->fifo_count));
902 }
903 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
904 mesh_flush_io(mr);
905 udelay(1);
906 out_8(&mr->sequence, SEQ_ENBRESEL);
907 mesh_flush_io(mr);
908 udelay(1);
909 out_8(&mr->sync_params, ASYNC_PARAMS);
910
911 /*
912 * Find out who reselected us.
913 */
914 if (in_8(&mr->fifo_count) == 0) {
915 printk(KERN_ERR "mesh: reselection but nothing in fifo?\n");
916 ms->conn_tgt = ms->host->this_id;
917 goto bogus;
918 }
919 /* get the last byte in the fifo */
920 do {
921 b = in_8(&mr->fifo);
922 dlog(ms, "reseldata %x", b);
923 } while (in_8(&mr->fifo_count));
924 for (t = 0; t < 8; ++t)
925 if ((b & (1 << t)) != 0 && t != ms->host->this_id)
926 break;
927 if (b != (1 << t) + (1 << ms->host->this_id)) {
928 printk(KERN_ERR "mesh: bad reselection data %x\n", b);
929 ms->conn_tgt = ms->host->this_id;
930 goto bogus;
931 }
932
933
934 /*
935 * Set up to continue with that target's transfer.
936 */
937 ms->conn_tgt = t;
938 tp = &ms->tgts[t];
939 out_8(&mr->sync_params, tp->sync_params);
940 if (ALLOW_DEBUG(t)) {
941 printk(KERN_DEBUG "mesh: reselected by target %d\n", t);
942 printk(KERN_DEBUG "mesh: saved_ptr=%x goes_out=%d cmd=%p\n",
943 tp->saved_ptr, tp->data_goes_out, tp->current_req);
944 }
945 ms->current_req = tp->current_req;
946 if (tp->current_req == NULL) {
947 printk(KERN_ERR "mesh: reselected by tgt %d but no cmd!\n", t);
948 goto bogus;
949 }
950 ms->data_ptr = tp->saved_ptr;
951 dlog(ms, "resel prev tgt=%d", prev);
952 dlog(ms, "resel err/exc=%.4x", MKWORD(0, 0, mr->error, mr->exception));
953 start_phase(ms);
954 return;
955
956 bogus:
957 dumplog(ms, ms->conn_tgt);
958 dumpslog(ms);
959 ms->data_ptr = 0;
960 ms->aborting = 1;
961 start_phase(ms);
962 }
963
964 static void do_abort(struct mesh_state *ms)
965 {
966 ms->msgout[0] = ABORT;
967 ms->n_msgout = 1;
968 ms->aborting = 1;
969 ms->stat = DID_ABORT;
970 dlog(ms, "abort", 0);
971 }
972
973 static void handle_reset(struct mesh_state *ms)
974 {
975 int tgt;
976 struct mesh_target *tp;
977 struct scsi_cmnd *cmd;
978 volatile struct mesh_regs __iomem *mr = ms->mesh;
979
980 for (tgt = 0; tgt < 8; ++tgt) {
981 tp = &ms->tgts[tgt];
982 if ((cmd = tp->current_req) != NULL) {
983 cmd->result = DID_RESET << 16;
984 tp->current_req = NULL;
985 mesh_completed(ms, cmd);
986 }
987 ms->tgts[tgt].sdtr_state = do_sdtr;
988 ms->tgts[tgt].sync_params = ASYNC_PARAMS;
989 }
990 ms->current_req = NULL;
991 while ((cmd = ms->request_q) != NULL) {
992 ms->request_q = (struct scsi_cmnd *) cmd->host_scribble;
993 cmd->result = DID_RESET << 16;
994 mesh_completed(ms, cmd);
995 }
996 ms->phase = idle;
997 ms->msgphase = msg_none;
998 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
999 out_8(&mr->sequence, SEQ_FLUSHFIFO);
1000 mesh_flush_io(mr);
1001 udelay(1);
1002 out_8(&mr->sync_params, ASYNC_PARAMS);
1003 out_8(&mr->sequence, SEQ_ENBRESEL);
1004 }
1005
1006 static irqreturn_t do_mesh_interrupt(int irq, void *dev_id)
1007 {
1008 unsigned long flags;
1009 struct mesh_state *ms = dev_id;
1010 struct Scsi_Host *dev = ms->host;
1011
1012 spin_lock_irqsave(dev->host_lock, flags);
1013 mesh_interrupt(ms);
1014 spin_unlock_irqrestore(dev->host_lock, flags);
1015 return IRQ_HANDLED;
1016 }
1017
1018 static void handle_error(struct mesh_state *ms)
1019 {
1020 int err, exc, count;
1021 volatile struct mesh_regs __iomem *mr = ms->mesh;
1022
1023 err = in_8(&mr->error);
1024 exc = in_8(&mr->exception);
1025 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
1026 dlog(ms, "error err/exc/fc/cl=%.8x",
1027 MKWORD(err, exc, mr->fifo_count, mr->count_lo));
1028 if (err & ERR_SCSIRESET) {
1029 /* SCSI bus was reset */
1030 printk(KERN_INFO "mesh: SCSI bus reset detected: "
1031 "waiting for end...");
1032 while ((in_8(&mr->bus_status1) & BS1_RST) != 0)
1033 udelay(1);
1034 printk("done\n");
1035 handle_reset(ms);
1036 /* request_q is empty, no point in mesh_start() */
1037 return;
1038 }
1039 if (err & ERR_UNEXPDISC) {
1040 /* Unexpected disconnect */
1041 if (exc & EXC_RESELECTED) {
1042 reselected(ms);
1043 return;
1044 }
1045 if (!ms->aborting) {
1046 printk(KERN_WARNING "mesh: target %d aborted\n",
1047 ms->conn_tgt);
1048 dumplog(ms, ms->conn_tgt);
1049 dumpslog(ms);
1050 }
1051 out_8(&mr->interrupt, INT_CMDDONE);
1052 ms->stat = DID_ABORT;
1053 mesh_done(ms, 1);
1054 return;
1055 }
1056 if (err & ERR_PARITY) {
1057 if (ms->msgphase == msg_in) {
1058 printk(KERN_ERR "mesh: msg parity error, target %d\n",
1059 ms->conn_tgt);
1060 ms->msgout[0] = MSG_PARITY_ERROR;
1061 ms->n_msgout = 1;
1062 ms->msgphase = msg_in_bad;
1063 cmd_complete(ms);
1064 return;
1065 }
1066 if (ms->stat == DID_OK) {
1067 printk(KERN_ERR "mesh: parity error, target %d\n",
1068 ms->conn_tgt);
1069 ms->stat = DID_PARITY;
1070 }
1071 count = (mr->count_hi << 8) + mr->count_lo;
1072 if (count == 0) {
1073 cmd_complete(ms);
1074 } else {
1075 /* reissue the data transfer command */
1076 out_8(&mr->sequence, mr->sequence);
1077 }
1078 return;
1079 }
1080 if (err & ERR_SEQERR) {
1081 if (exc & EXC_RESELECTED) {
1082 /* This can happen if we issue a command to
1083 get the bus just after the target reselects us. */
1084 static int mesh_resel_seqerr;
1085 mesh_resel_seqerr++;
1086 reselected(ms);
1087 return;
1088 }
1089 if (exc == EXC_PHASEMM) {
1090 static int mesh_phasemm_seqerr;
1091 mesh_phasemm_seqerr++;
1092 phase_mismatch(ms);
1093 return;
1094 }
1095 printk(KERN_ERR "mesh: sequence error (err=%x exc=%x)\n",
1096 err, exc);
1097 } else {
1098 printk(KERN_ERR "mesh: unknown error %x (exc=%x)\n", err, exc);
1099 }
1100 mesh_dump_regs(ms);
1101 dumplog(ms, ms->conn_tgt);
1102 if (ms->phase > selecting && (in_8(&mr->bus_status1) & BS1_BSY)) {
1103 /* try to do what the target wants */
1104 do_abort(ms);
1105 phase_mismatch(ms);
1106 return;
1107 }
1108 ms->stat = DID_ERROR;
1109 mesh_done(ms, 1);
1110 }
1111
1112 static void handle_exception(struct mesh_state *ms)
1113 {
1114 int exc;
1115 volatile struct mesh_regs __iomem *mr = ms->mesh;
1116
1117 exc = in_8(&mr->exception);
1118 out_8(&mr->interrupt, INT_EXCEPTION | INT_CMDDONE);
1119 if (exc & EXC_RESELECTED) {
1120 static int mesh_resel_exc;
1121 mesh_resel_exc++;
1122 reselected(ms);
1123 } else if (exc == EXC_ARBLOST) {
1124 printk(KERN_DEBUG "mesh: lost arbitration\n");
1125 ms->stat = DID_BUS_BUSY;
1126 mesh_done(ms, 1);
1127 } else if (exc == EXC_SELTO) {
1128 /* selection timed out */
1129 ms->stat = DID_BAD_TARGET;
1130 mesh_done(ms, 1);
1131 } else if (exc == EXC_PHASEMM) {
1132 /* target wants to do something different:
1133 find out what it wants and do it. */
1134 phase_mismatch(ms);
1135 } else {
1136 printk(KERN_ERR "mesh: can't cope with exception %x\n", exc);
1137 mesh_dump_regs(ms);
1138 dumplog(ms, ms->conn_tgt);
1139 do_abort(ms);
1140 phase_mismatch(ms);
1141 }
1142 }
1143
1144 static void handle_msgin(struct mesh_state *ms)
1145 {
1146 int i, code;
1147 struct scsi_cmnd *cmd = ms->current_req;
1148 struct mesh_target *tp = &ms->tgts[ms->conn_tgt];
1149
1150 if (ms->n_msgin == 0)
1151 return;
1152 code = ms->msgin[0];
1153 if (ALLOW_DEBUG(ms->conn_tgt)) {
1154 printk(KERN_DEBUG "got %d message bytes:", ms->n_msgin);
1155 for (i = 0; i < ms->n_msgin; ++i)
1156 printk(" %x", ms->msgin[i]);
1157 printk("\n");
1158 }
1159 dlog(ms, "msgin msg=%.8x",
1160 MKWORD(ms->n_msgin, code, ms->msgin[1], ms->msgin[2]));
1161
1162 ms->expect_reply = 0;
1163 ms->n_msgout = 0;
1164 if (ms->n_msgin < msgin_length(ms))
1165 goto reject;
1166 if (cmd)
1167 cmd->SCp.Message = code;
1168 switch (code) {
1169 case COMMAND_COMPLETE:
1170 break;
1171 case EXTENDED_MESSAGE:
1172 switch (ms->msgin[2]) {
1173 case EXTENDED_MODIFY_DATA_POINTER:
1174 ms->data_ptr += (ms->msgin[3] << 24) + ms->msgin[6]
1175 + (ms->msgin[4] << 16) + (ms->msgin[5] << 8);
1176 break;
1177 case EXTENDED_SDTR:
1178 if (tp->sdtr_state != sdtr_sent) {
1179 /* reply with an SDTR */
1180 add_sdtr_msg(ms);
1181 /* limit period to at least his value,
1182 offset to no more than his */
1183 if (ms->msgout[3] < ms->msgin[3])
1184 ms->msgout[3] = ms->msgin[3];
1185 if (ms->msgout[4] > ms->msgin[4])
1186 ms->msgout[4] = ms->msgin[4];
1187 set_sdtr(ms, ms->msgout[3], ms->msgout[4]);
1188 ms->msgphase = msg_out;
1189 } else {
1190 set_sdtr(ms, ms->msgin[3], ms->msgin[4]);
1191 }
1192 break;
1193 default:
1194 goto reject;
1195 }
1196 break;
1197 case SAVE_POINTERS:
1198 tp->saved_ptr = ms->data_ptr;
1199 break;
1200 case RESTORE_POINTERS:
1201 ms->data_ptr = tp->saved_ptr;
1202 break;
1203 case DISCONNECT:
1204 ms->phase = disconnecting;
1205 break;
1206 case ABORT:
1207 break;
1208 case MESSAGE_REJECT:
1209 if (tp->sdtr_state == sdtr_sent)
1210 set_sdtr(ms, 0, 0);
1211 break;
1212 case NOP:
1213 break;
1214 default:
1215 if (IDENTIFY_BASE <= code && code <= IDENTIFY_BASE + 7) {
1216 if (cmd == NULL) {
1217 do_abort(ms);
1218 ms->msgphase = msg_out;
1219 } else if (code != cmd->device->lun + IDENTIFY_BASE) {
1220 printk(KERN_WARNING "mesh: lun mismatch "
1221 "(%d != %d) on reselection from "
1222 "target %d\n", code - IDENTIFY_BASE,
1223 cmd->device->lun, ms->conn_tgt);
1224 }
1225 break;
1226 }
1227 goto reject;
1228 }
1229 return;
1230
1231 reject:
1232 printk(KERN_WARNING "mesh: rejecting message from target %d:",
1233 ms->conn_tgt);
1234 for (i = 0; i < ms->n_msgin; ++i)
1235 printk(" %x", ms->msgin[i]);
1236 printk("\n");
1237 ms->msgout[0] = MESSAGE_REJECT;
1238 ms->n_msgout = 1;
1239 ms->msgphase = msg_out;
1240 }
1241
1242 /*
1243 * Set up DMA commands for transferring data.
1244 */
1245 static void set_dma_cmds(struct mesh_state *ms, struct scsi_cmnd *cmd)
1246 {
1247 int i, dma_cmd, total, off, dtot;
1248 struct scatterlist *scl;
1249 struct dbdma_cmd *dcmds;
1250
1251 dma_cmd = ms->tgts[ms->conn_tgt].data_goes_out?
1252 OUTPUT_MORE: INPUT_MORE;
1253 dcmds = ms->dma_cmds;
1254 dtot = 0;
1255 if (cmd) {
1256 int nseg;
1257
1258 cmd->SCp.this_residual = scsi_bufflen(cmd);
1259
1260 nseg = scsi_dma_map(cmd);
1261 BUG_ON(nseg < 0);
1262
1263 if (nseg) {
1264 total = 0;
1265 off = ms->data_ptr;
1266
1267 scsi_for_each_sg(cmd, scl, nseg, i) {
1268 u32 dma_addr = sg_dma_address(scl);
1269 u32 dma_len = sg_dma_len(scl);
1270
1271 total += scl->length;
1272 if (off >= dma_len) {
1273 off -= dma_len;
1274 continue;
1275 }
1276 if (dma_len > 0xffff)
1277 panic("mesh: scatterlist element >= 64k");
1278 st_le16(&dcmds->req_count, dma_len - off);
1279 st_le16(&dcmds->command, dma_cmd);
1280 st_le32(&dcmds->phy_addr, dma_addr + off);
1281 dcmds->xfer_status = 0;
1282 ++dcmds;
1283 dtot += dma_len - off;
1284 off = 0;
1285 }
1286 }
1287 }
1288 if (dtot == 0) {
1289 /* Either the target has overrun our buffer,
1290 or the caller didn't provide a buffer. */
1291 static char mesh_extra_buf[64];
1292
1293 dtot = sizeof(mesh_extra_buf);
1294 st_le16(&dcmds->req_count, dtot);
1295 st_le32(&dcmds->phy_addr, virt_to_phys(mesh_extra_buf));
1296 dcmds->xfer_status = 0;
1297 ++dcmds;
1298 }
1299 dma_cmd += OUTPUT_LAST - OUTPUT_MORE;
1300 st_le16(&dcmds[-1].command, dma_cmd);
1301 memset(dcmds, 0, sizeof(*dcmds));
1302 st_le16(&dcmds->command, DBDMA_STOP);
1303 ms->dma_count = dtot;
1304 }
1305
1306 static void halt_dma(struct mesh_state *ms)
1307 {
1308 volatile struct dbdma_regs __iomem *md = ms->dma;
1309 volatile struct mesh_regs __iomem *mr = ms->mesh;
1310 struct scsi_cmnd *cmd = ms->current_req;
1311 int t, nb;
1312
1313 if (!ms->tgts[ms->conn_tgt].data_goes_out) {
1314 /* wait a little while until the fifo drains */
1315 t = 50;
1316 while (t > 0 && in_8(&mr->fifo_count) != 0
1317 && (in_le32(&md->status) & ACTIVE) != 0) {
1318 --t;
1319 udelay(1);
1320 }
1321 }
1322 out_le32(&md->control, RUN << 16); /* turn off RUN bit */
1323 nb = (mr->count_hi << 8) + mr->count_lo;
1324 dlog(ms, "halt_dma fc/count=%.6x",
1325 MKWORD(0, mr->fifo_count, 0, nb));
1326 if (ms->tgts[ms->conn_tgt].data_goes_out)
1327 nb += mr->fifo_count;
1328 /* nb is the number of bytes not yet transferred
1329 to/from the target. */
1330 ms->data_ptr -= nb;
1331 dlog(ms, "data_ptr %x", ms->data_ptr);
1332 if (ms->data_ptr < 0) {
1333 printk(KERN_ERR "mesh: halt_dma: data_ptr=%d (nb=%d, ms=%p)\n",
1334 ms->data_ptr, nb, ms);
1335 ms->data_ptr = 0;
1336 #ifdef MESH_DBG
1337 dumplog(ms, ms->conn_tgt);
1338 dumpslog(ms);
1339 #endif /* MESH_DBG */
1340 } else if (cmd && scsi_bufflen(cmd) &&
1341 ms->data_ptr > scsi_bufflen(cmd)) {
1342 printk(KERN_DEBUG "mesh: target %d overrun, "
1343 "data_ptr=%x total=%x goes_out=%d\n",
1344 ms->conn_tgt, ms->data_ptr, scsi_bufflen(cmd),
1345 ms->tgts[ms->conn_tgt].data_goes_out);
1346 }
1347 scsi_dma_unmap(cmd);
1348 ms->dma_started = 0;
1349 }
1350
1351 static void phase_mismatch(struct mesh_state *ms)
1352 {
1353 volatile struct mesh_regs __iomem *mr = ms->mesh;
1354 int phase;
1355
1356 dlog(ms, "phasemm ch/cl/seq/fc=%.8x",
1357 MKWORD(mr->count_hi, mr->count_lo, mr->sequence, mr->fifo_count));
1358 phase = in_8(&mr->bus_status0) & BS0_PHASE;
1359 if (ms->msgphase == msg_out_xxx && phase == BP_MSGOUT) {
1360 /* output the last byte of the message, without ATN */
1361 out_8(&mr->count_lo, 1);
1362 out_8(&mr->sequence, SEQ_MSGOUT + use_active_neg);
1363 mesh_flush_io(mr);
1364 udelay(1);
1365 out_8(&mr->fifo, ms->msgout[ms->n_msgout-1]);
1366 ms->msgphase = msg_out_last;
1367 return;
1368 }
1369
1370 if (ms->msgphase == msg_in) {
1371 get_msgin(ms);
1372 if (ms->n_msgin)
1373 handle_msgin(ms);
1374 }
1375
1376 if (ms->dma_started)
1377 halt_dma(ms);
1378 if (mr->fifo_count) {
1379 out_8(&mr->sequence, SEQ_FLUSHFIFO);
1380 mesh_flush_io(mr);
1381 udelay(1);
1382 }
1383
1384 ms->msgphase = msg_none;
1385 switch (phase) {
1386 case BP_DATAIN:
1387 ms->tgts[ms->conn_tgt].data_goes_out = 0;
1388 ms->phase = dataing;
1389 break;
1390 case BP_DATAOUT:
1391 ms->tgts[ms->conn_tgt].data_goes_out = 1;
1392 ms->phase = dataing;
1393 break;
1394 case BP_COMMAND:
1395 ms->phase = commanding;
1396 break;
1397 case BP_STATUS:
1398 ms->phase = statusing;
1399 break;
1400 case BP_MSGIN:
1401 ms->msgphase = msg_in;
1402 ms->n_msgin = 0;
1403 break;
1404 case BP_MSGOUT:
1405 ms->msgphase = msg_out;
1406 if (ms->n_msgout == 0) {
1407 if (ms->aborting) {
1408 do_abort(ms);
1409 } else {
1410 if (ms->last_n_msgout == 0) {
1411 printk(KERN_DEBUG
1412 "mesh: no msg to repeat\n");
1413 ms->msgout[0] = NOP;
1414 ms->last_n_msgout = 1;
1415 }
1416 ms->n_msgout = ms->last_n_msgout;
1417 }
1418 }
1419 break;
1420 default:
1421 printk(KERN_DEBUG "mesh: unknown scsi phase %x\n", phase);
1422 ms->stat = DID_ERROR;
1423 mesh_done(ms, 1);
1424 return;
1425 }
1426
1427 start_phase(ms);
1428 }
1429
1430 static void cmd_complete(struct mesh_state *ms)
1431 {
1432 volatile struct mesh_regs __iomem *mr = ms->mesh;
1433 struct scsi_cmnd *cmd = ms->current_req;
1434 struct mesh_target *tp = &ms->tgts[ms->conn_tgt];
1435 int seq, n, t;
1436
1437 dlog(ms, "cmd_complete fc=%x", mr->fifo_count);
1438 seq = use_active_neg + (ms->n_msgout? SEQ_ATN: 0);
1439 switch (ms->msgphase) {
1440 case msg_out_xxx:
1441 /* huh? we expected a phase mismatch */
1442 ms->n_msgin = 0;
1443 ms->msgphase = msg_in;
1444 /* fall through */
1445
1446 case msg_in:
1447 /* should have some message bytes in fifo */
1448 get_msgin(ms);
1449 n = msgin_length(ms);
1450 if (ms->n_msgin < n) {
1451 out_8(&mr->count_lo, n - ms->n_msgin);
1452 out_8(&mr->sequence, SEQ_MSGIN + seq);
1453 } else {
1454 ms->msgphase = msg_none;
1455 handle_msgin(ms);
1456 start_phase(ms);
1457 }
1458 break;
1459
1460 case msg_in_bad:
1461 out_8(&mr->sequence, SEQ_FLUSHFIFO);
1462 mesh_flush_io(mr);
1463 udelay(1);
1464 out_8(&mr->count_lo, 1);
1465 out_8(&mr->sequence, SEQ_MSGIN + SEQ_ATN + use_active_neg);
1466 break;
1467
1468 case msg_out:
1469 /*
1470 * To get the right timing on ATN wrt ACK, we have
1471 * to get the MESH to drop ACK, wait until REQ gets
1472 * asserted, then drop ATN. To do this we first
1473 * issue a SEQ_MSGOUT with ATN and wait for REQ,
1474 * then change the command to a SEQ_MSGOUT w/o ATN.
1475 * If we don't see REQ in a reasonable time, we
1476 * change the command to SEQ_MSGIN with ATN,
1477 * wait for the phase mismatch interrupt, then
1478 * issue the SEQ_MSGOUT without ATN.
1479 */
1480 out_8(&mr->count_lo, 1);
1481 out_8(&mr->sequence, SEQ_MSGOUT + use_active_neg + SEQ_ATN);
1482 t = 30; /* wait up to 30us */
1483 while ((in_8(&mr->bus_status0) & BS0_REQ) == 0 && --t >= 0)
1484 udelay(1);
1485 dlog(ms, "last_mbyte err/exc/fc/cl=%.8x",
1486 MKWORD(mr->error, mr->exception,
1487 mr->fifo_count, mr->count_lo));
1488 if (in_8(&mr->interrupt) & (INT_ERROR | INT_EXCEPTION)) {
1489 /* whoops, target didn't do what we expected */
1490 ms->last_n_msgout = ms->n_msgout;
1491 ms->n_msgout = 0;
1492 if (in_8(&mr->interrupt) & INT_ERROR) {
1493 printk(KERN_ERR "mesh: error %x in msg_out\n",
1494 in_8(&mr->error));
1495 handle_error(ms);
1496 return;
1497 }
1498 if (in_8(&mr->exception) != EXC_PHASEMM)
1499 printk(KERN_ERR "mesh: exc %x in msg_out\n",
1500 in_8(&mr->exception));
1501 else
1502 printk(KERN_DEBUG "mesh: bs0=%x in msg_out\n",
1503 in_8(&mr->bus_status0));
1504 handle_exception(ms);
1505 return;
1506 }
1507 if (in_8(&mr->bus_status0) & BS0_REQ) {
1508 out_8(&mr->sequence, SEQ_MSGOUT + use_active_neg);
1509 mesh_flush_io(mr);
1510 udelay(1);
1511 out_8(&mr->fifo, ms->msgout[ms->n_msgout-1]);
1512 ms->msgphase = msg_out_last;
1513 } else {
1514 out_8(&mr->sequence, SEQ_MSGIN + use_active_neg + SEQ_ATN);
1515 ms->msgphase = msg_out_xxx;
1516 }
1517 break;
1518
1519 case msg_out_last:
1520 ms->last_n_msgout = ms->n_msgout;
1521 ms->n_msgout = 0;
1522 ms->msgphase = ms->expect_reply? msg_in: msg_none;
1523 start_phase(ms);
1524 break;
1525
1526 case msg_none:
1527 switch (ms->phase) {
1528 case idle:
1529 printk(KERN_ERR "mesh: interrupt in idle phase?\n");
1530 dumpslog(ms);
1531 return;
1532 case selecting:
1533 dlog(ms, "Selecting phase at command completion",0);
1534 ms->msgout[0] = IDENTIFY(ALLOW_RESEL(ms->conn_tgt),
1535 (cmd? cmd->device->lun: 0));
1536 ms->n_msgout = 1;
1537 ms->expect_reply = 0;
1538 if (ms->aborting) {
1539 ms->msgout[0] = ABORT;
1540 ms->n_msgout++;
1541 } else if (tp->sdtr_state == do_sdtr) {
1542 /* add SDTR message */
1543 add_sdtr_msg(ms);
1544 ms->expect_reply = 1;
1545 tp->sdtr_state = sdtr_sent;
1546 }
1547 ms->msgphase = msg_out;
1548 /*
1549 * We need to wait for REQ before dropping ATN.
1550 * We wait for at most 30us, then fall back to
1551 * a scheme where we issue a SEQ_COMMAND with ATN,
1552 * which will give us a phase mismatch interrupt
1553 * when REQ does come, and then we send the message.
1554 */
1555 t = 230; /* wait up to 230us */
1556 while ((in_8(&mr->bus_status0) & BS0_REQ) == 0) {
1557 if (--t < 0) {
1558 dlog(ms, "impatient for req", ms->n_msgout);
1559 ms->msgphase = msg_none;
1560 break;
1561 }
1562 udelay(1);
1563 }
1564 break;
1565 case dataing:
1566 if (ms->dma_count != 0) {
1567 start_phase(ms);
1568 return;
1569 }
1570 /*
1571 * We can get a phase mismatch here if the target
1572 * changes to the status phase, even though we have
1573 * had a command complete interrupt. Then, if we
1574 * issue the SEQ_STATUS command, we'll get a sequence
1575 * error interrupt. Which isn't so bad except that
1576 * occasionally the mesh actually executes the
1577 * SEQ_STATUS *as well as* giving us the sequence
1578 * error and phase mismatch exception.
1579 */
1580 out_8(&mr->sequence, 0);
1581 out_8(&mr->interrupt,
1582 INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
1583 halt_dma(ms);
1584 break;
1585 case statusing:
1586 if (cmd) {
1587 cmd->SCp.Status = mr->fifo;
1588 if (DEBUG_TARGET(cmd))
1589 printk(KERN_DEBUG "mesh: status is %x\n",
1590 cmd->SCp.Status);
1591 }
1592 ms->msgphase = msg_in;
1593 break;
1594 case busfreeing:
1595 mesh_done(ms, 1);
1596 return;
1597 case disconnecting:
1598 ms->current_req = NULL;
1599 ms->phase = idle;
1600 mesh_start(ms);
1601 return;
1602 default:
1603 break;
1604 }
1605 ++ms->phase;
1606 start_phase(ms);
1607 break;
1608 }
1609 }
1610
1611
1612 /*
1613 * Called by midlayer with host locked to queue a new
1614 * request
1615 */
1616 static int mesh_queue(struct scsi_cmnd *cmd, void (*done)(struct scsi_cmnd *))
1617 {
1618 struct mesh_state *ms;
1619
1620 cmd->scsi_done = done;
1621 cmd->host_scribble = NULL;
1622
1623 ms = (struct mesh_state *) cmd->device->host->hostdata;
1624
1625 if (ms->request_q == NULL)
1626 ms->request_q = cmd;
1627 else
1628 ms->request_qtail->host_scribble = (void *) cmd;
1629 ms->request_qtail = cmd;
1630
1631 if (ms->phase == idle)
1632 mesh_start(ms);
1633
1634 return 0;
1635 }
1636
1637 /*
1638 * Called to handle interrupts, either call by the interrupt
1639 * handler (do_mesh_interrupt) or by other functions in
1640 * exceptional circumstances
1641 */
1642 static void mesh_interrupt(struct mesh_state *ms)
1643 {
1644 volatile struct mesh_regs __iomem *mr = ms->mesh;
1645 int intr;
1646
1647 while ((intr = in_8(&mr->interrupt)) != 0) {
1648 dlog(ms, "interrupt intr/err/exc/seq=%.8x",
1649 MKWORD(intr, mr->error, mr->exception, mr->sequence));
1650 if (intr & INT_ERROR) {
1651 handle_error(ms);
1652 } else if (intr & INT_EXCEPTION) {
1653 handle_exception(ms);
1654 } else if (intr & INT_CMDDONE) {
1655 out_8(&mr->interrupt, INT_CMDDONE);
1656 cmd_complete(ms);
1657 }
1658 }
1659 }
1660
1661 /* Todo: here we can at least try to remove the command from the
1662 * queue if it isn't connected yet, and for pending command, assert
1663 * ATN until the bus gets freed.
1664 */
1665 static int mesh_abort(struct scsi_cmnd *cmd)
1666 {
1667 struct mesh_state *ms = (struct mesh_state *) cmd->device->host->hostdata;
1668
1669 printk(KERN_DEBUG "mesh_abort(%p)\n", cmd);
1670 mesh_dump_regs(ms);
1671 dumplog(ms, cmd->device->id);
1672 dumpslog(ms);
1673 return FAILED;
1674 }
1675
1676 /*
1677 * Called by the midlayer with the lock held to reset the
1678 * SCSI host and bus.
1679 * The midlayer will wait for devices to come back, we don't need
1680 * to do that ourselves
1681 */
1682 static int mesh_host_reset(struct scsi_cmnd *cmd)
1683 {
1684 struct mesh_state *ms = (struct mesh_state *) cmd->device->host->hostdata;
1685 volatile struct mesh_regs __iomem *mr = ms->mesh;
1686 volatile struct dbdma_regs __iomem *md = ms->dma;
1687 unsigned long flags;
1688
1689 printk(KERN_DEBUG "mesh_host_reset\n");
1690
1691 spin_lock_irqsave(ms->host->host_lock, flags);
1692
1693 /* Reset the controller & dbdma channel */
1694 out_le32(&md->control, (RUN|PAUSE|FLUSH|WAKE) << 16); /* stop dma */
1695 out_8(&mr->exception, 0xff); /* clear all exception bits */
1696 out_8(&mr->error, 0xff); /* clear all error bits */
1697 out_8(&mr->sequence, SEQ_RESETMESH);
1698 mesh_flush_io(mr);
1699 udelay(1);
1700 out_8(&mr->intr_mask, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
1701 out_8(&mr->source_id, ms->host->this_id);
1702 out_8(&mr->sel_timeout, 25); /* 250ms */
1703 out_8(&mr->sync_params, ASYNC_PARAMS);
1704
1705 /* Reset the bus */
1706 out_8(&mr->bus_status1, BS1_RST); /* assert RST */
1707 mesh_flush_io(mr);
1708 udelay(30); /* leave it on for >= 25us */
1709 out_8(&mr->bus_status1, 0); /* negate RST */
1710
1711 /* Complete pending commands */
1712 handle_reset(ms);
1713
1714 spin_unlock_irqrestore(ms->host->host_lock, flags);
1715 return SUCCESS;
1716 }
1717
1718 static void set_mesh_power(struct mesh_state *ms, int state)
1719 {
1720 if (!machine_is(powermac))
1721 return;
1722 if (state) {
1723 pmac_call_feature(PMAC_FTR_MESH_ENABLE, macio_get_of_node(ms->mdev), 0, 1);
1724 msleep(200);
1725 } else {
1726 pmac_call_feature(PMAC_FTR_MESH_ENABLE, macio_get_of_node(ms->mdev), 0, 0);
1727 msleep(10);
1728 }
1729 }
1730
1731
1732 #ifdef CONFIG_PM
1733 static int mesh_suspend(struct macio_dev *mdev, pm_message_t mesg)
1734 {
1735 struct mesh_state *ms = (struct mesh_state *)macio_get_drvdata(mdev);
1736 unsigned long flags;
1737
1738 switch (mesg.event) {
1739 case PM_EVENT_SUSPEND:
1740 case PM_EVENT_HIBERNATE:
1741 case PM_EVENT_FREEZE:
1742 break;
1743 default:
1744 return 0;
1745 }
1746 if (ms->phase == sleeping)
1747 return 0;
1748
1749 scsi_block_requests(ms->host);
1750 spin_lock_irqsave(ms->host->host_lock, flags);
1751 while(ms->phase != idle) {
1752 spin_unlock_irqrestore(ms->host->host_lock, flags);
1753 msleep(10);
1754 spin_lock_irqsave(ms->host->host_lock, flags);
1755 }
1756 ms->phase = sleeping;
1757 spin_unlock_irqrestore(ms->host->host_lock, flags);
1758 disable_irq(ms->meshintr);
1759 set_mesh_power(ms, 0);
1760
1761 return 0;
1762 }
1763
1764 static int mesh_resume(struct macio_dev *mdev)
1765 {
1766 struct mesh_state *ms = (struct mesh_state *)macio_get_drvdata(mdev);
1767 unsigned long flags;
1768
1769 if (ms->phase != sleeping)
1770 return 0;
1771
1772 set_mesh_power(ms, 1);
1773 mesh_init(ms);
1774 spin_lock_irqsave(ms->host->host_lock, flags);
1775 mesh_start(ms);
1776 spin_unlock_irqrestore(ms->host->host_lock, flags);
1777 enable_irq(ms->meshintr);
1778 scsi_unblock_requests(ms->host);
1779
1780 return 0;
1781 }
1782
1783 #endif /* CONFIG_PM */
1784
1785 /*
1786 * If we leave drives set for synchronous transfers (especially
1787 * CDROMs), and reboot to MacOS, it gets confused, poor thing.
1788 * So, on reboot we reset the SCSI bus.
1789 */
1790 static int mesh_shutdown(struct macio_dev *mdev)
1791 {
1792 struct mesh_state *ms = (struct mesh_state *)macio_get_drvdata(mdev);
1793 volatile struct mesh_regs __iomem *mr;
1794 unsigned long flags;
1795
1796 printk(KERN_INFO "resetting MESH scsi bus(es)\n");
1797 spin_lock_irqsave(ms->host->host_lock, flags);
1798 mr = ms->mesh;
1799 out_8(&mr->intr_mask, 0);
1800 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
1801 out_8(&mr->bus_status1, BS1_RST);
1802 mesh_flush_io(mr);
1803 udelay(30);
1804 out_8(&mr->bus_status1, 0);
1805 spin_unlock_irqrestore(ms->host->host_lock, flags);
1806
1807 return 0;
1808 }
1809
1810 static struct scsi_host_template mesh_template = {
1811 .proc_name = "mesh",
1812 .name = "MESH",
1813 .queuecommand = mesh_queue,
1814 .eh_abort_handler = mesh_abort,
1815 .eh_host_reset_handler = mesh_host_reset,
1816 .can_queue = 20,
1817 .this_id = 7,
1818 .sg_tablesize = SG_ALL,
1819 .cmd_per_lun = 2,
1820 .use_clustering = DISABLE_CLUSTERING,
1821 };
1822
1823 static int mesh_probe(struct macio_dev *mdev, const struct of_device_id *match)
1824 {
1825 struct device_node *mesh = macio_get_of_node(mdev);
1826 struct pci_dev* pdev = macio_get_pci_dev(mdev);
1827 int tgt, minper;
1828 const int *cfp;
1829 struct mesh_state *ms;
1830 struct Scsi_Host *mesh_host;
1831 void *dma_cmd_space;
1832 dma_addr_t dma_cmd_bus;
1833
1834 switch (mdev->bus->chip->type) {
1835 case macio_heathrow:
1836 case macio_gatwick:
1837 case macio_paddington:
1838 use_active_neg = 0;
1839 break;
1840 default:
1841 use_active_neg = SEQ_ACTIVE_NEG;
1842 }
1843
1844 if (macio_resource_count(mdev) != 2 || macio_irq_count(mdev) != 2) {
1845 printk(KERN_ERR "mesh: expected 2 addrs and 2 intrs"
1846 " (got %d,%d)\n", macio_resource_count(mdev),
1847 macio_irq_count(mdev));
1848 return -ENODEV;
1849 }
1850
1851 if (macio_request_resources(mdev, "mesh") != 0) {
1852 printk(KERN_ERR "mesh: unable to request memory resources");
1853 return -EBUSY;
1854 }
1855 mesh_host = scsi_host_alloc(&mesh_template, sizeof(struct mesh_state));
1856 if (mesh_host == NULL) {
1857 printk(KERN_ERR "mesh: couldn't register host");
1858 goto out_release;
1859 }
1860
1861 /* Old junk for root discovery, that will die ultimately */
1862 #if !defined(MODULE)
1863 note_scsi_host(mesh, mesh_host);
1864 #endif
1865
1866 mesh_host->base = macio_resource_start(mdev, 0);
1867 mesh_host->irq = macio_irq(mdev, 0);
1868 ms = (struct mesh_state *) mesh_host->hostdata;
1869 macio_set_drvdata(mdev, ms);
1870 ms->host = mesh_host;
1871 ms->mdev = mdev;
1872 ms->pdev = pdev;
1873
1874 ms->mesh = ioremap(macio_resource_start(mdev, 0), 0x1000);
1875 if (ms->mesh == NULL) {
1876 printk(KERN_ERR "mesh: can't map registers\n");
1877 goto out_free;
1878 }
1879 ms->dma = ioremap(macio_resource_start(mdev, 1), 0x1000);
1880 if (ms->dma == NULL) {
1881 printk(KERN_ERR "mesh: can't map registers\n");
1882 iounmap(ms->mesh);
1883 goto out_free;
1884 }
1885
1886 ms->meshintr = macio_irq(mdev, 0);
1887 ms->dmaintr = macio_irq(mdev, 1);
1888
1889 /* Space for dma command list: +1 for stop command,
1890 * +1 to allow for aligning.
1891 */
1892 ms->dma_cmd_size = (mesh_host->sg_tablesize + 2) * sizeof(struct dbdma_cmd);
1893
1894 /* We use the PCI APIs for now until the generic one gets fixed
1895 * enough or until we get some macio-specific versions
1896 */
1897 dma_cmd_space = pci_alloc_consistent(macio_get_pci_dev(mdev),
1898 ms->dma_cmd_size,
1899 &dma_cmd_bus);
1900 if (dma_cmd_space == NULL) {
1901 printk(KERN_ERR "mesh: can't allocate DMA table\n");
1902 goto out_unmap;
1903 }
1904 memset(dma_cmd_space, 0, ms->dma_cmd_size);
1905
1906 ms->dma_cmds = (struct dbdma_cmd *) DBDMA_ALIGN(dma_cmd_space);
1907 ms->dma_cmd_space = dma_cmd_space;
1908 ms->dma_cmd_bus = dma_cmd_bus + ((unsigned long)ms->dma_cmds)
1909 - (unsigned long)dma_cmd_space;
1910 ms->current_req = NULL;
1911 for (tgt = 0; tgt < 8; ++tgt) {
1912 ms->tgts[tgt].sdtr_state = do_sdtr;
1913 ms->tgts[tgt].sync_params = ASYNC_PARAMS;
1914 ms->tgts[tgt].current_req = NULL;
1915 }
1916
1917 if ((cfp = of_get_property(mesh, "clock-frequency", NULL)))
1918 ms->clk_freq = *cfp;
1919 else {
1920 printk(KERN_INFO "mesh: assuming 50MHz clock frequency\n");
1921 ms->clk_freq = 50000000;
1922 }
1923
1924 /* The maximum sync rate is clock / 5; increase
1925 * mesh_sync_period if necessary.
1926 */
1927 minper = 1000000000 / (ms->clk_freq / 5); /* ns */
1928 if (mesh_sync_period < minper)
1929 mesh_sync_period = minper;
1930
1931 /* Power up the chip */
1932 set_mesh_power(ms, 1);
1933
1934 /* Set it up */
1935 mesh_init(ms);
1936
1937 /* Request interrupt */
1938 if (request_irq(ms->meshintr, do_mesh_interrupt, 0, "MESH", ms)) {
1939 printk(KERN_ERR "MESH: can't get irq %d\n", ms->meshintr);
1940 goto out_shutdown;
1941 }
1942
1943 /* Add scsi host & scan */
1944 if (scsi_add_host(mesh_host, &mdev->ofdev.dev))
1945 goto out_release_irq;
1946 scsi_scan_host(mesh_host);
1947
1948 return 0;
1949
1950 out_release_irq:
1951 free_irq(ms->meshintr, ms);
1952 out_shutdown:
1953 /* shutdown & reset bus in case of error or macos can be confused
1954 * at reboot if the bus was set to synchronous mode already
1955 */
1956 mesh_shutdown(mdev);
1957 set_mesh_power(ms, 0);
1958 pci_free_consistent(macio_get_pci_dev(mdev), ms->dma_cmd_size,
1959 ms->dma_cmd_space, ms->dma_cmd_bus);
1960 out_unmap:
1961 iounmap(ms->dma);
1962 iounmap(ms->mesh);
1963 out_free:
1964 scsi_host_put(mesh_host);
1965 out_release:
1966 macio_release_resources(mdev);
1967
1968 return -ENODEV;
1969 }
1970
1971 static int mesh_remove(struct macio_dev *mdev)
1972 {
1973 struct mesh_state *ms = (struct mesh_state *)macio_get_drvdata(mdev);
1974 struct Scsi_Host *mesh_host = ms->host;
1975
1976 scsi_remove_host(mesh_host);
1977
1978 free_irq(ms->meshintr, ms);
1979
1980 /* Reset scsi bus */
1981 mesh_shutdown(mdev);
1982
1983 /* Shut down chip & termination */
1984 set_mesh_power(ms, 0);
1985
1986 /* Unmap registers & dma controller */
1987 iounmap(ms->mesh);
1988 iounmap(ms->dma);
1989
1990 /* Free DMA commands memory */
1991 pci_free_consistent(macio_get_pci_dev(mdev), ms->dma_cmd_size,
1992 ms->dma_cmd_space, ms->dma_cmd_bus);
1993
1994 /* Release memory resources */
1995 macio_release_resources(mdev);
1996
1997 scsi_host_put(mesh_host);
1998
1999 return 0;
2000 }
2001
2002
2003 static struct of_device_id mesh_match[] =
2004 {
2005 {
2006 .name = "mesh",
2007 },
2008 {
2009 .type = "scsi",
2010 .compatible = "chrp,mesh0"
2011 },
2012 {},
2013 };
2014 MODULE_DEVICE_TABLE (of, mesh_match);
2015
2016 static struct macio_driver mesh_driver =
2017 {
2018 .driver = {
2019 .name = "mesh",
2020 .owner = THIS_MODULE,
2021 .of_match_table = mesh_match,
2022 },
2023 .probe = mesh_probe,
2024 .remove = mesh_remove,
2025 .shutdown = mesh_shutdown,
2026 #ifdef CONFIG_PM
2027 .suspend = mesh_suspend,
2028 .resume = mesh_resume,
2029 #endif
2030 };
2031
2032
2033 static int __init init_mesh(void)
2034 {
2035
2036 /* Calculate sync rate from module parameters */
2037 if (sync_rate > 10)
2038 sync_rate = 10;
2039 if (sync_rate > 0) {
2040 printk(KERN_INFO "mesh: configured for synchronous %d MB/s\n", sync_rate);
2041 mesh_sync_period = 1000 / sync_rate; /* ns */
2042 mesh_sync_offset = 15;
2043 } else
2044 printk(KERN_INFO "mesh: configured for asynchronous\n");
2045
2046 return macio_register_driver(&mesh_driver);
2047 }
2048
2049 static void __exit exit_mesh(void)
2050 {
2051 return macio_unregister_driver(&mesh_driver);
2052 }
2053
2054 module_init(init_mesh);
2055 module_exit(exit_mesh);
Tomato firmware and modifications.