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GUI: Fix Tomato RAF theme for all builds. Compilation typo.
[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / drivers / pci / hotplug / cpqphp_pci.c
blobb567fc5214f2e026aebfd268c4f4484dbde8a3bd
1 /*
2 * Compaq Hot Plug Controller Driver
3 *
4 * Copyright (C) 1995,2001 Compaq Computer Corporation
5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
6 * Copyright (C) 2001 IBM Corp.
7 *
8 * All rights reserved.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or (at
13 * your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
18 * NON INFRINGEMENT. See the GNU General Public License for more
19 * details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 * Send feedback to <greg@kroah.com>
26 *
27 */
28
29 #include <linux/module.h>
30 #include <linux/kernel.h>
31 #include <linux/types.h>
32 #include <linux/slab.h>
33 #include <linux/workqueue.h>
34 #include <linux/proc_fs.h>
35 #include <linux/pci.h>
36 #include <linux/pci_hotplug.h>
37 #include "../pci.h"
38 #include "cpqphp.h"
39 #include "cpqphp_nvram.h"
40
41
42 u8 cpqhp_nic_irq;
43 u8 cpqhp_disk_irq;
44
45 static u16 unused_IRQ;
46
47 /*
48 * detect_HRT_floating_pointer
49 *
50 * find the Hot Plug Resource Table in the specified region of memory.
51 *
52 */
53 static void __iomem *detect_HRT_floating_pointer(void __iomem *begin, void __iomem *end)
54 {
55 void __iomem *fp;
56 void __iomem *endp;
57 u8 temp1, temp2, temp3, temp4;
58 int status = 0;
59
60 endp = (end - sizeof(struct hrt) + 1);
61
62 for (fp = begin; fp <= endp; fp += 16) {
63 temp1 = readb(fp + SIG0);
64 temp2 = readb(fp + SIG1);
65 temp3 = readb(fp + SIG2);
66 temp4 = readb(fp + SIG3);
67 if (temp1 == '$' &&
68 temp2 == 'H' &&
69 temp3 == 'R' &&
70 temp4 == 'T') {
71 status = 1;
72 break;
73 }
74 }
75
76 if (!status)
77 fp = NULL;
78
79 dbg("Discovered Hotplug Resource Table at %p\n", fp);
80 return fp;
81 }
82
83
84 int cpqhp_configure_device (struct controller* ctrl, struct pci_func* func)
85 {
86 unsigned char bus;
87 struct pci_bus *child;
88 int num;
89
90 if (func->pci_dev == NULL)
91 func->pci_dev = pci_get_bus_and_slot(func->bus,PCI_DEVFN(func->device, func->function));
92
93 /* No pci device, we need to create it then */
94 if (func->pci_dev == NULL) {
95 dbg("INFO: pci_dev still null\n");
96
97 num = pci_scan_slot(ctrl->pci_dev->bus, PCI_DEVFN(func->device, func->function));
98 if (num)
99 pci_bus_add_devices(ctrl->pci_dev->bus);
100
101 func->pci_dev = pci_get_bus_and_slot(func->bus, PCI_DEVFN(func->device, func->function));
102 if (func->pci_dev == NULL) {
103 dbg("ERROR: pci_dev still null\n");
104 return 0;
105 }
106 }
107
108 if (func->pci_dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
109 pci_read_config_byte(func->pci_dev, PCI_SECONDARY_BUS, &bus);
110 child = (struct pci_bus*) pci_add_new_bus(func->pci_dev->bus, (func->pci_dev), bus);
111 pci_do_scan_bus(child);
112 }
113
114 pci_dev_put(func->pci_dev);
115
116 return 0;
117 }
118
119
120 int cpqhp_unconfigure_device(struct pci_func* func)
121 {
122 int j;
123
124 dbg("%s: bus/dev/func = %x/%x/%x\n", __func__, func->bus, func->device, func->function);
125
126 for (j=0; j<8 ; j++) {
127 struct pci_dev* temp = pci_get_bus_and_slot(func->bus, PCI_DEVFN(func->device, j));
128 if (temp) {
129 pci_dev_put(temp);
130 pci_remove_bus_device(temp);
131 }
132 }
133 return 0;
134 }
135
136 static int PCI_RefinedAccessConfig(struct pci_bus *bus, unsigned int devfn, u8 offset, u32 *value)
137 {
138 u32 vendID = 0;
139
140 if (pci_bus_read_config_dword (bus, devfn, PCI_VENDOR_ID, &vendID) == -1)
141 return -1;
142 if (vendID == 0xffffffff)
143 return -1;
144 return pci_bus_read_config_dword (bus, devfn, offset, value);
145 }
146
147
148 /*
149 * cpqhp_set_irq
150 *
151 * @bus_num: bus number of PCI device
152 * @dev_num: device number of PCI device
153 * @slot: pointer to u8 where slot number will be returned
154 */
155 int cpqhp_set_irq (u8 bus_num, u8 dev_num, u8 int_pin, u8 irq_num)
156 {
157 int rc = 0;
158
159 if (cpqhp_legacy_mode) {
160 struct pci_dev *fakedev;
161 struct pci_bus *fakebus;
162 u16 temp_word;
163
164 fakedev = kmalloc(sizeof(*fakedev), GFP_KERNEL);
165 fakebus = kmalloc(sizeof(*fakebus), GFP_KERNEL);
166 if (!fakedev || !fakebus) {
167 kfree(fakedev);
168 kfree(fakebus);
169 return -ENOMEM;
170 }
171
172 fakedev->devfn = dev_num << 3;
173 fakedev->bus = fakebus;
174 fakebus->number = bus_num;
175 dbg("%s: dev %d, bus %d, pin %d, num %d\n",
176 __func__, dev_num, bus_num, int_pin, irq_num);
177 rc = pcibios_set_irq_routing(fakedev, int_pin - 1, irq_num);
178 kfree(fakedev);
179 kfree(fakebus);
180 dbg("%s: rc %d\n", __func__, rc);
181 if (!rc)
182 return !rc;
183
184 /* set the Edge Level Control Register (ELCR) */
185 temp_word = inb(0x4d0);
186 temp_word |= inb(0x4d1) << 8;
187
188 temp_word |= 0x01 << irq_num;
189
190 /* This should only be for x86 as it sets the Edge Level
191 * Control Register
192 */
193 outb((u8) (temp_word & 0xFF), 0x4d0); outb((u8) ((temp_word &
194 0xFF00) >> 8), 0x4d1); rc = 0; }
195
196 return rc;
197 }
198
199
200 static int PCI_ScanBusForNonBridge(struct controller *ctrl, u8 bus_num, u8 * dev_num)
201 {
202 u16 tdevice;
203 u32 work;
204 u8 tbus;
205
206 ctrl->pci_bus->number = bus_num;
207
208 for (tdevice = 0; tdevice < 0xFF; tdevice++) {
209 /* Scan for access first */
210 if (PCI_RefinedAccessConfig(ctrl->pci_bus, tdevice, 0x08, &work) == -1)
211 continue;
212 dbg("Looking for nonbridge bus_num %d dev_num %d\n", bus_num, tdevice);
213 /* Yep we got one. Not a bridge ? */
214 if ((work >> 8) != PCI_TO_PCI_BRIDGE_CLASS) {
215 *dev_num = tdevice;
216 dbg("found it !\n");
217 return 0;
218 }
219 }
220 for (tdevice = 0; tdevice < 0xFF; tdevice++) {
221 /* Scan for access first */
222 if (PCI_RefinedAccessConfig(ctrl->pci_bus, tdevice, 0x08, &work) == -1)
223 continue;
224 dbg("Looking for bridge bus_num %d dev_num %d\n", bus_num, tdevice);
225 /* Yep we got one. bridge ? */
226 if ((work >> 8) == PCI_TO_PCI_BRIDGE_CLASS) {
227 pci_bus_read_config_byte (ctrl->pci_bus, PCI_DEVFN(tdevice, 0), PCI_SECONDARY_BUS, &tbus);
228 dbg("Recurse on bus_num %d tdevice %d\n", tbus, tdevice);
229 return 0;
230 }
231 }
232
233 return -1;
234 }
235
236
237 static int PCI_GetBusDevHelper(struct controller *ctrl, u8 *bus_num, u8 *dev_num, u8 slot, u8 nobridge)
238 {
239 int loop, len;
240 u32 work;
241 u8 tbus, tdevice, tslot;
242
243 len = cpqhp_routing_table_length();
244 for (loop = 0; loop < len; ++loop) {
245 tbus = cpqhp_routing_table->slots[loop].bus;
246 tdevice = cpqhp_routing_table->slots[loop].devfn;
247 tslot = cpqhp_routing_table->slots[loop].slot;
248
249 if (tslot == slot) {
250 *bus_num = tbus;
251 *dev_num = tdevice;
252 ctrl->pci_bus->number = tbus;
253 pci_bus_read_config_dword (ctrl->pci_bus, *dev_num, PCI_VENDOR_ID, &work);
254 if (!nobridge || (work == 0xffffffff))
255 return 0;
256
257 dbg("bus_num %d devfn %d\n", *bus_num, *dev_num);
258 pci_bus_read_config_dword (ctrl->pci_bus, *dev_num, PCI_CLASS_REVISION, &work);
259 dbg("work >> 8 (%x) = BRIDGE (%x)\n", work >> 8, PCI_TO_PCI_BRIDGE_CLASS);
260
261 if ((work >> 8) == PCI_TO_PCI_BRIDGE_CLASS) {
262 pci_bus_read_config_byte (ctrl->pci_bus, *dev_num, PCI_SECONDARY_BUS, &tbus);
263 dbg("Scan bus for Non Bridge: bus %d\n", tbus);
264 if (PCI_ScanBusForNonBridge(ctrl, tbus, dev_num) == 0) {
265 *bus_num = tbus;
266 return 0;
267 }
268 } else
269 return 0;
270 }
271 }
272 return -1;
273 }
274
275
276 int cpqhp_get_bus_dev (struct controller *ctrl, u8 * bus_num, u8 * dev_num, u8 slot)
277 {
278 /* plain (bridges allowed) */
279 return PCI_GetBusDevHelper(ctrl, bus_num, dev_num, slot, 0);
280 }
281
282
283 /* More PCI configuration routines; this time centered around hotplug
284 * controller
285 */
286
287
288 /*
289 * cpqhp_save_config
290 *
291 * Reads configuration for all slots in a PCI bus and saves info.
292 *
293 * Note: For non-hot plug busses, the slot # saved is the device #
294 *
295 * returns 0 if success
296 */
297 int cpqhp_save_config(struct controller *ctrl, int busnumber, int is_hot_plug)
298 {
299 long rc;
300 u8 class_code;
301 u8 header_type;
302 u32 ID;
303 u8 secondary_bus;
304 struct pci_func *new_slot;
305 int sub_bus;
306 int FirstSupported;
307 int LastSupported;
308 int max_functions;
309 int function;
310 u8 DevError;
311 int device = 0;
312 int cloop = 0;
313 int stop_it;
314 int index;
315
316 /* Decide which slots are supported */
317
318 if (is_hot_plug) {
319 /*
320 * is_hot_plug is the slot mask
321 */
322 FirstSupported = is_hot_plug >> 4;
323 LastSupported = FirstSupported + (is_hot_plug & 0x0F) - 1;
324 } else {
325 FirstSupported = 0;
326 LastSupported = 0x1F;
327 }
328
329 /* Save PCI configuration space for all devices in supported slots */
330 ctrl->pci_bus->number = busnumber;
331 for (device = FirstSupported; device <= LastSupported; device++) {
332 ID = 0xFFFFFFFF;
333 rc = pci_bus_read_config_dword(ctrl->pci_bus, PCI_DEVFN(device, 0), PCI_VENDOR_ID, &ID);
334
335 if (ID == 0xFFFFFFFF) {
336 if (is_hot_plug) {
337 /* Setup slot structure with entry for empty
338 * slot
339 */
340 new_slot = cpqhp_slot_create(busnumber);
341 if (new_slot == NULL)
342 return 1;
343
344 new_slot->bus = (u8) busnumber;
345 new_slot->device = (u8) device;
346 new_slot->function = 0;
347 new_slot->is_a_board = 0;
348 new_slot->presence_save = 0;
349 new_slot->switch_save = 0;
350 }
351 continue;
352 }
353
354 rc = pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(device, 0), 0x0B, &class_code);
355 if (rc)
356 return rc;
357
358 rc = pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(device, 0), PCI_HEADER_TYPE, &header_type);
359 if (rc)
360 return rc;
361
362 /* If multi-function device, set max_functions to 8 */
363 if (header_type & 0x80)
364 max_functions = 8;
365 else
366 max_functions = 1;
367
368 function = 0;
369
370 do {
371 DevError = 0;
372 if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) {
373 /* Recurse the subordinate bus
374 * get the subordinate bus number
375 */
376 rc = pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(device, function), PCI_SECONDARY_BUS, &secondary_bus);
377 if (rc) {
378 return rc;
379 } else {
380 sub_bus = (int) secondary_bus;
381
382 /* Save secondary bus cfg spc
383 * with this recursive call.
384 */
385 rc = cpqhp_save_config(ctrl, sub_bus, 0);
386 if (rc)
387 return rc;
388 ctrl->pci_bus->number = busnumber;
389 }
390 }
391
392 index = 0;
393 new_slot = cpqhp_slot_find(busnumber, device, index++);
394 while (new_slot &&
395 (new_slot->function != (u8) function))
396 new_slot = cpqhp_slot_find(busnumber, device, index++);
397
398 if (!new_slot) {
399 /* Setup slot structure. */
400 new_slot = cpqhp_slot_create(busnumber);
401 if (new_slot == NULL)
402 return 1;
403 }
404
405 new_slot->bus = (u8) busnumber;
406 new_slot->device = (u8) device;
407 new_slot->function = (u8) function;
408 new_slot->is_a_board = 1;
409 new_slot->switch_save = 0x10;
410 /* In case of unsupported board */
411 new_slot->status = DevError;
412 new_slot->pci_dev = pci_get_bus_and_slot(new_slot->bus, (new_slot->device << 3) | new_slot->function);
413
414 for (cloop = 0; cloop < 0x20; cloop++) {
415 rc = pci_bus_read_config_dword(ctrl->pci_bus, PCI_DEVFN(device, function), cloop << 2, (u32 *) & (new_slot-> config_space [cloop]));
416 if (rc)
417 return rc;
418 }
419
420 pci_dev_put(new_slot->pci_dev);
421
422 function++;
423
424 stop_it = 0;
425
426 /* this loop skips to the next present function
427 * reading in Class Code and Header type.
428 */
429 while ((function < max_functions) && (!stop_it)) {
430 rc = pci_bus_read_config_dword(ctrl->pci_bus, PCI_DEVFN(device, function), PCI_VENDOR_ID, &ID);
431 if (ID == 0xFFFFFFFF) {
432 function++;
433 continue;
434 }
435 rc = pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(device, function), 0x0B, &class_code);
436 if (rc)
437 return rc;
438
439 rc = pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(device, function), PCI_HEADER_TYPE, &header_type);
440 if (rc)
441 return rc;
442
443 stop_it++;
444 }
445
446 } while (function < max_functions);
447 } /* End of FOR loop */
448
449 return 0;
450 }
451
452
453 /*
454 * cpqhp_save_slot_config
455 *
456 * Saves configuration info for all PCI devices in a given slot
457 * including subordinate busses.
458 *
459 * returns 0 if success
460 */
461 int cpqhp_save_slot_config (struct controller *ctrl, struct pci_func * new_slot)
462 {
463 long rc;
464 u8 class_code;
465 u8 header_type;
466 u32 ID;
467 u8 secondary_bus;
468 int sub_bus;
469 int max_functions;
470 int function = 0;
471 int cloop = 0;
472 int stop_it;
473
474 ID = 0xFFFFFFFF;
475
476 ctrl->pci_bus->number = new_slot->bus;
477 pci_bus_read_config_dword (ctrl->pci_bus, PCI_DEVFN(new_slot->device, 0), PCI_VENDOR_ID, &ID);
478
479 if (ID == 0xFFFFFFFF)
480 return 2;
481
482 pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(new_slot->device, 0), 0x0B, &class_code);
483 pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(new_slot->device, 0), PCI_HEADER_TYPE, &header_type);
484
485 if (header_type & 0x80) /* Multi-function device */
486 max_functions = 8;
487 else
488 max_functions = 1;
489
490 while (function < max_functions) {
491 if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) {
492 /* Recurse the subordinate bus */
493 pci_bus_read_config_byte (ctrl->pci_bus, PCI_DEVFN(new_slot->device, function), PCI_SECONDARY_BUS, &secondary_bus);
494
495 sub_bus = (int) secondary_bus;
496
497 /* Save the config headers for the secondary
498 * bus.
499 */
500 rc = cpqhp_save_config(ctrl, sub_bus, 0);
501 if (rc)
502 return(rc);
503 ctrl->pci_bus->number = new_slot->bus;
504
505 }
506
507 new_slot->status = 0;
508
509 for (cloop = 0; cloop < 0x20; cloop++)
510 pci_bus_read_config_dword(ctrl->pci_bus, PCI_DEVFN(new_slot->device, function), cloop << 2, (u32 *) & (new_slot-> config_space [cloop]));
511
512 function++;
513
514 stop_it = 0;
515
516 /* this loop skips to the next present function
517 * reading in the Class Code and the Header type.
518 */
519 while ((function < max_functions) && (!stop_it)) {
520 pci_bus_read_config_dword(ctrl->pci_bus, PCI_DEVFN(new_slot->device, function), PCI_VENDOR_ID, &ID);
521
522 if (ID == 0xFFFFFFFF)
523 function++;
524 else {
525 pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(new_slot->device, function), 0x0B, &class_code);
526 pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(new_slot->device, function), PCI_HEADER_TYPE, &header_type);
527 stop_it++;
528 }
529 }
530
531 }
532
533 return 0;
534 }
535
536
537 /*
538 * cpqhp_save_base_addr_length
539 *
540 * Saves the length of all base address registers for the
541 * specified slot. this is for hot plug REPLACE
542 *
543 * returns 0 if success
544 */
545 int cpqhp_save_base_addr_length(struct controller *ctrl, struct pci_func * func)
546 {
547 u8 cloop;
548 u8 header_type;
549 u8 secondary_bus;
550 u8 type;
551 int sub_bus;
552 u32 temp_register;
553 u32 base;
554 u32 rc;
555 struct pci_func *next;
556 int index = 0;
557 struct pci_bus *pci_bus = ctrl->pci_bus;
558 unsigned int devfn;
559
560 func = cpqhp_slot_find(func->bus, func->device, index++);
561
562 while (func != NULL) {
563 pci_bus->number = func->bus;
564 devfn = PCI_DEVFN(func->device, func->function);
565
566 /* Check for Bridge */
567 pci_bus_read_config_byte (pci_bus, devfn, PCI_HEADER_TYPE, &header_type);
568
569 if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) {
570 pci_bus_read_config_byte (pci_bus, devfn, PCI_SECONDARY_BUS, &secondary_bus);
571
572 sub_bus = (int) secondary_bus;
573
574 next = cpqhp_slot_list[sub_bus];
575
576 while (next != NULL) {
577 rc = cpqhp_save_base_addr_length(ctrl, next);
578 if (rc)
579 return rc;
580
581 next = next->next;
582 }
583 pci_bus->number = func->bus;
584
585 for (cloop = 0x10; cloop <= 0x14; cloop += 4) {
586 temp_register = 0xFFFFFFFF;
587 pci_bus_write_config_dword (pci_bus, devfn, cloop, temp_register);
588 pci_bus_read_config_dword (pci_bus, devfn, cloop, &base);
589 /* If this register is implemented */
590 if (base) {
591 if (base & 0x01L) {
592 /* IO base
593 * set base = amount of IO space
594 * requested
595 */
596 base = base & 0xFFFFFFFE;
597 base = (~base) + 1;
598
599 type = 1;
600 } else {
601 /* memory base */
602 base = base & 0xFFFFFFF0;
603 base = (~base) + 1;
604
605 type = 0;
606 }
607 } else {
608 base = 0x0L;
609 type = 0;
610 }
611
612 /* Save information in slot structure */
613 func->base_length[(cloop - 0x10) >> 2] =
614 base;
615 func->base_type[(cloop - 0x10) >> 2] = type;
616
617 } /* End of base register loop */
618
619 } else if ((header_type & 0x7F) == 0x00) {
620 /* Figure out IO and memory base lengths */
621 for (cloop = 0x10; cloop <= 0x24; cloop += 4) {
622 temp_register = 0xFFFFFFFF;
623 pci_bus_write_config_dword (pci_bus, devfn, cloop, temp_register);
624 pci_bus_read_config_dword (pci_bus, devfn, cloop, &base);
625
626 /* If this register is implemented */
627 if (base) {
628 if (base & 0x01L) {
629 /* IO base
630 * base = amount of IO space
631 * requested
632 */
633 base = base & 0xFFFFFFFE;
634 base = (~base) + 1;
635
636 type = 1;
637 } else {
638 /* memory base
639 * base = amount of memory
640 * space requested
641 */
642 base = base & 0xFFFFFFF0;
643 base = (~base) + 1;
644
645 type = 0;
646 }
647 } else {
648 base = 0x0L;
649 type = 0;
650 }
651
652 /* Save information in slot structure */
653 func->base_length[(cloop - 0x10) >> 2] = base;
654 func->base_type[(cloop - 0x10) >> 2] = type;
655
656 } /* End of base register loop */
657
658 } else { /* Some other unknown header type */
659 }
660
661 /* find the next device in this slot */
662 func = cpqhp_slot_find(func->bus, func->device, index++);
663 }
664
665 return(0);
666 }
667
668
669 /*
670 * cpqhp_save_used_resources
671 *
672 * Stores used resource information for existing boards. this is
673 * for boards that were in the system when this driver was loaded.
674 * this function is for hot plug ADD
675 *
676 * returns 0 if success
677 */
678 int cpqhp_save_used_resources (struct controller *ctrl, struct pci_func * func)
679 {
680 u8 cloop;
681 u8 header_type;
682 u8 secondary_bus;
683 u8 temp_byte;
684 u8 b_base;
685 u8 b_length;
686 u16 command;
687 u16 save_command;
688 u16 w_base;
689 u16 w_length;
690 u32 temp_register;
691 u32 save_base;
692 u32 base;
693 int index = 0;
694 struct pci_resource *mem_node;
695 struct pci_resource *p_mem_node;
696 struct pci_resource *io_node;
697 struct pci_resource *bus_node;
698 struct pci_bus *pci_bus = ctrl->pci_bus;
699 unsigned int devfn;
700
701 func = cpqhp_slot_find(func->bus, func->device, index++);
702
703 while ((func != NULL) && func->is_a_board) {
704 pci_bus->number = func->bus;
705 devfn = PCI_DEVFN(func->device, func->function);
706
707 /* Save the command register */
708 pci_bus_read_config_word(pci_bus, devfn, PCI_COMMAND, &save_command);
709
710 /* disable card */
711 command = 0x00;
712 pci_bus_write_config_word(pci_bus, devfn, PCI_COMMAND, command);
713
714 /* Check for Bridge */
715 pci_bus_read_config_byte(pci_bus, devfn, PCI_HEADER_TYPE, &header_type);
716
717 if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) {
718 /* Clear Bridge Control Register */
719 command = 0x00;
720 pci_bus_write_config_word(pci_bus, devfn, PCI_BRIDGE_CONTROL, command);
721 pci_bus_read_config_byte(pci_bus, devfn, PCI_SECONDARY_BUS, &secondary_bus);
722 pci_bus_read_config_byte(pci_bus, devfn, PCI_SUBORDINATE_BUS, &temp_byte);
723
724 bus_node = kmalloc(sizeof(*bus_node), GFP_KERNEL);
725 if (!bus_node)
726 return -ENOMEM;
727
728 bus_node->base = secondary_bus;
729 bus_node->length = temp_byte - secondary_bus + 1;
730
731 bus_node->next = func->bus_head;
732 func->bus_head = bus_node;
733
734 /* Save IO base and Limit registers */
735 pci_bus_read_config_byte(pci_bus, devfn, PCI_IO_BASE, &b_base);
736 pci_bus_read_config_byte(pci_bus, devfn, PCI_IO_LIMIT, &b_length);
737
738 if ((b_base <= b_length) && (save_command & 0x01)) {
739 io_node = kmalloc(sizeof(*io_node), GFP_KERNEL);
740 if (!io_node)
741 return -ENOMEM;
742
743 io_node->base = (b_base & 0xF0) << 8;
744 io_node->length = (b_length - b_base + 0x10) << 8;
745
746 io_node->next = func->io_head;
747 func->io_head = io_node;
748 }
749
750 /* Save memory base and Limit registers */
751 pci_bus_read_config_word(pci_bus, devfn, PCI_MEMORY_BASE, &w_base);
752 pci_bus_read_config_word(pci_bus, devfn, PCI_MEMORY_LIMIT, &w_length);
753
754 if ((w_base <= w_length) && (save_command & 0x02)) {
755 mem_node = kmalloc(sizeof(*mem_node), GFP_KERNEL);
756 if (!mem_node)
757 return -ENOMEM;
758
759 mem_node->base = w_base << 16;
760 mem_node->length = (w_length - w_base + 0x10) << 16;
761
762 mem_node->next = func->mem_head;
763 func->mem_head = mem_node;
764 }
765
766 /* Save prefetchable memory base and Limit registers */
767 pci_bus_read_config_word(pci_bus, devfn, PCI_PREF_MEMORY_BASE, &w_base);
768 pci_bus_read_config_word(pci_bus, devfn, PCI_PREF_MEMORY_LIMIT, &w_length);
769
770 if ((w_base <= w_length) && (save_command & 0x02)) {
771 p_mem_node = kmalloc(sizeof(*p_mem_node), GFP_KERNEL);
772 if (!p_mem_node)
773 return -ENOMEM;
774
775 p_mem_node->base = w_base << 16;
776 p_mem_node->length = (w_length - w_base + 0x10) << 16;
777
778 p_mem_node->next = func->p_mem_head;
779 func->p_mem_head = p_mem_node;
780 }
781 /* Figure out IO and memory base lengths */
782 for (cloop = 0x10; cloop <= 0x14; cloop += 4) {
783 pci_bus_read_config_dword (pci_bus, devfn, cloop, &save_base);
784
785 temp_register = 0xFFFFFFFF;
786 pci_bus_write_config_dword(pci_bus, devfn, cloop, temp_register);
787 pci_bus_read_config_dword(pci_bus, devfn, cloop, &base);
788
789 temp_register = base;
790
791 /* If this register is implemented */
792 if (base) {
793 if (((base & 0x03L) == 0x01)
794 && (save_command & 0x01)) {
795 /* IO base
796 * set temp_register = amount
797 * of IO space requested
798 */
799 temp_register = base & 0xFFFFFFFE;
800 temp_register = (~temp_register) + 1;
801
802 io_node = kmalloc(sizeof(*io_node),
803 GFP_KERNEL);
804 if (!io_node)
805 return -ENOMEM;
806
807 io_node->base =
808 save_base & (~0x03L);
809 io_node->length = temp_register;
810
811 io_node->next = func->io_head;
812 func->io_head = io_node;
813 } else
814 if (((base & 0x0BL) == 0x08)
815 && (save_command & 0x02)) {
816 /* prefetchable memory base */
817 temp_register = base & 0xFFFFFFF0;
818 temp_register = (~temp_register) + 1;
819
820 p_mem_node = kmalloc(sizeof(*p_mem_node),
821 GFP_KERNEL);
822 if (!p_mem_node)
823 return -ENOMEM;
824
825 p_mem_node->base = save_base & (~0x0FL);
826 p_mem_node->length = temp_register;
827
828 p_mem_node->next = func->p_mem_head;
829 func->p_mem_head = p_mem_node;
830 } else
831 if (((base & 0x0BL) == 0x00)
832 && (save_command & 0x02)) {
833 /* prefetchable memory base */
834 temp_register = base & 0xFFFFFFF0;
835 temp_register = (~temp_register) + 1;
836
837 mem_node = kmalloc(sizeof(*mem_node),
838 GFP_KERNEL);
839 if (!mem_node)
840 return -ENOMEM;
841
842 mem_node->base = save_base & (~0x0FL);
843 mem_node->length = temp_register;
844
845 mem_node->next = func->mem_head;
846 func->mem_head = mem_node;
847 } else
848 return(1);
849 }
850 } /* End of base register loop */
851 /* Standard header */
852 } else if ((header_type & 0x7F) == 0x00) {
853 /* Figure out IO and memory base lengths */
854 for (cloop = 0x10; cloop <= 0x24; cloop += 4) {
855 pci_bus_read_config_dword(pci_bus, devfn, cloop, &save_base);
856
857 temp_register = 0xFFFFFFFF;
858 pci_bus_write_config_dword(pci_bus, devfn, cloop, temp_register);
859 pci_bus_read_config_dword(pci_bus, devfn, cloop, &base);
860
861 temp_register = base;
862
863 /* If this register is implemented */
864 if (base) {
865 if (((base & 0x03L) == 0x01)
866 && (save_command & 0x01)) {
867 /* IO base
868 * set temp_register = amount
869 * of IO space requested
870 */
871 temp_register = base & 0xFFFFFFFE;
872 temp_register = (~temp_register) + 1;
873
874 io_node = kmalloc(sizeof(*io_node),
875 GFP_KERNEL);
876 if (!io_node)
877 return -ENOMEM;
878
879 io_node->base = save_base & (~0x01L);
880 io_node->length = temp_register;
881
882 io_node->next = func->io_head;
883 func->io_head = io_node;
884 } else
885 if (((base & 0x0BL) == 0x08)
886 && (save_command & 0x02)) {
887 /* prefetchable memory base */
888 temp_register = base & 0xFFFFFFF0;
889 temp_register = (~temp_register) + 1;
890
891 p_mem_node = kmalloc(sizeof(*p_mem_node),
892 GFP_KERNEL);
893 if (!p_mem_node)
894 return -ENOMEM;
895
896 p_mem_node->base = save_base & (~0x0FL);
897 p_mem_node->length = temp_register;
898
899 p_mem_node->next = func->p_mem_head;
900 func->p_mem_head = p_mem_node;
901 } else
902 if (((base & 0x0BL) == 0x00)
903 && (save_command & 0x02)) {
904 /* prefetchable memory base */
905 temp_register = base & 0xFFFFFFF0;
906 temp_register = (~temp_register) + 1;
907
908 mem_node = kmalloc(sizeof(*mem_node),
909 GFP_KERNEL);
910 if (!mem_node)
911 return -ENOMEM;
912
913 mem_node->base = save_base & (~0x0FL);
914 mem_node->length = temp_register;
915
916 mem_node->next = func->mem_head;
917 func->mem_head = mem_node;
918 } else
919 return(1);
920 }
921 } /* End of base register loop */
922 }
923
924 /* find the next device in this slot */
925 func = cpqhp_slot_find(func->bus, func->device, index++);
926 }
927
928 return 0;
929 }
930
931
932 /*
933 * cpqhp_configure_board
934 *
935 * Copies saved configuration information to one slot.
936 * this is called recursively for bridge devices.
937 * this is for hot plug REPLACE!
938 *
939 * returns 0 if success
940 */
941 int cpqhp_configure_board(struct controller *ctrl, struct pci_func * func)
942 {
943 int cloop;
944 u8 header_type;
945 u8 secondary_bus;
946 int sub_bus;
947 struct pci_func *next;
948 u32 temp;
949 u32 rc;
950 int index = 0;
951 struct pci_bus *pci_bus = ctrl->pci_bus;
952 unsigned int devfn;
953
954 func = cpqhp_slot_find(func->bus, func->device, index++);
955
956 while (func != NULL) {
957 pci_bus->number = func->bus;
958 devfn = PCI_DEVFN(func->device, func->function);
959
960 /* Start at the top of config space so that the control
961 * registers are programmed last
962 */
963 for (cloop = 0x3C; cloop > 0; cloop -= 4)
964 pci_bus_write_config_dword (pci_bus, devfn, cloop, func->config_space[cloop >> 2]);
965
966 pci_bus_read_config_byte (pci_bus, devfn, PCI_HEADER_TYPE, &header_type);
967
968 /* If this is a bridge device, restore subordinate devices */
969 if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) {
970 pci_bus_read_config_byte (pci_bus, devfn, PCI_SECONDARY_BUS, &secondary_bus);
971
972 sub_bus = (int) secondary_bus;
973
974 next = cpqhp_slot_list[sub_bus];
975
976 while (next != NULL) {
977 rc = cpqhp_configure_board(ctrl, next);
978 if (rc)
979 return rc;
980
981 next = next->next;
982 }
983 } else {
984
985 /* Check all the base Address Registers to make sure
986 * they are the same. If not, the board is different.
987 */
988
989 for (cloop = 16; cloop < 40; cloop += 4) {
990 pci_bus_read_config_dword (pci_bus, devfn, cloop, &temp);
991
992 if (temp != func->config_space[cloop >> 2]) {
993 dbg("Config space compare failure!!! offset = %x\n", cloop);
994 dbg("bus = %x, device = %x, function = %x\n", func->bus, func->device, func->function);
995 dbg("temp = %x, config space = %x\n\n", temp, func->config_space[cloop >> 2]);
996 return 1;
997 }
998 }
999 }
1000
1001 func->configured = 1;
1002
1003 func = cpqhp_slot_find(func->bus, func->device, index++);
1004 }
1005
1006 return 0;
1007 }
1008
1009
1010 /*
1011 * cpqhp_valid_replace
1012 *
1013 * this function checks to see if a board is the same as the
1014 * one it is replacing. this check will detect if the device's
1015 * vendor or device id's are the same
1016 *
1017 * returns 0 if the board is the same nonzero otherwise
1018 */
1019 int cpqhp_valid_replace(struct controller *ctrl, struct pci_func * func)
1020 {
1021 u8 cloop;
1022 u8 header_type;
1023 u8 secondary_bus;
1024 u8 type;
1025 u32 temp_register = 0;
1026 u32 base;
1027 u32 rc;
1028 struct pci_func *next;
1029 int index = 0;
1030 struct pci_bus *pci_bus = ctrl->pci_bus;
1031 unsigned int devfn;
1032
1033 if (!func->is_a_board)
1034 return(ADD_NOT_SUPPORTED);
1035
1036 func = cpqhp_slot_find(func->bus, func->device, index++);
1037
1038 while (func != NULL) {
1039 pci_bus->number = func->bus;
1040 devfn = PCI_DEVFN(func->device, func->function);
1041
1042 pci_bus_read_config_dword (pci_bus, devfn, PCI_VENDOR_ID, &temp_register);
1043
1044 /* No adapter present */
1045 if (temp_register == 0xFFFFFFFF)
1046 return(NO_ADAPTER_PRESENT);
1047
1048 if (temp_register != func->config_space[0])
1049 return(ADAPTER_NOT_SAME);
1050
1051 /* Check for same revision number and class code */
1052 pci_bus_read_config_dword (pci_bus, devfn, PCI_CLASS_REVISION, &temp_register);
1053
1054 /* Adapter not the same */
1055 if (temp_register != func->config_space[0x08 >> 2])
1056 return(ADAPTER_NOT_SAME);
1057
1058 /* Check for Bridge */
1059 pci_bus_read_config_byte (pci_bus, devfn, PCI_HEADER_TYPE, &header_type);
1060
1061 if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) {
1062 /* In order to continue checking, we must program the
1063 * bus registers in the bridge to respond to accesses
1064 * for its subordinate bus(es)
1065 */
1066
1067 temp_register = func->config_space[0x18 >> 2];
1068 pci_bus_write_config_dword (pci_bus, devfn, PCI_PRIMARY_BUS, temp_register);
1069
1070 secondary_bus = (temp_register >> 8) & 0xFF;
1071
1072 next = cpqhp_slot_list[secondary_bus];
1073
1074 while (next != NULL) {
1075 rc = cpqhp_valid_replace(ctrl, next);
1076 if (rc)
1077 return rc;
1078
1079 next = next->next;
1080 }
1081
1082 }
1083 /* Check to see if it is a standard config header */
1084 else if ((header_type & 0x7F) == PCI_HEADER_TYPE_NORMAL) {
1085 /* Check subsystem vendor and ID */
1086 pci_bus_read_config_dword (pci_bus, devfn, PCI_SUBSYSTEM_VENDOR_ID, &temp_register);
1087
1088 if (temp_register != func->config_space[0x2C >> 2]) {
1089 /* If it's a SMART-2 and the register isn't
1090 * filled in, ignore the difference because
1091 * they just have an old rev of the firmware
1092 */
1093 if (!((func->config_space[0] == 0xAE100E11)
1094 && (temp_register == 0x00L)))
1095 return(ADAPTER_NOT_SAME);
1096 }
1097 /* Figure out IO and memory base lengths */
1098 for (cloop = 0x10; cloop <= 0x24; cloop += 4) {
1099 temp_register = 0xFFFFFFFF;
1100 pci_bus_write_config_dword (pci_bus, devfn, cloop, temp_register);
1101 pci_bus_read_config_dword (pci_bus, devfn, cloop, &base);
1102
1103 /* If this register is implemented */
1104 if (base) {
1105 if (base & 0x01L) {
1106 /* IO base
1107 * set base = amount of IO
1108 * space requested
1109 */
1110 base = base & 0xFFFFFFFE;
1111 base = (~base) + 1;
1112
1113 type = 1;
1114 } else {
1115 /* memory base */
1116 base = base & 0xFFFFFFF0;
1117 base = (~base) + 1;
1118
1119 type = 0;
1120 }
1121 } else {
1122 base = 0x0L;
1123 type = 0;
1124 }
1125
1126 /* Check information in slot structure */
1127 if (func->base_length[(cloop - 0x10) >> 2] != base)
1128 return(ADAPTER_NOT_SAME);
1129
1130 if (func->base_type[(cloop - 0x10) >> 2] != type)
1131 return(ADAPTER_NOT_SAME);
1132
1133 } /* End of base register loop */
1134
1135 } /* End of (type 0 config space) else */
1136 else {
1137 /* this is not a type 0 or 1 config space header so
1138 * we don't know how to do it
1139 */
1140 return(DEVICE_TYPE_NOT_SUPPORTED);
1141 }
1142
1143 /* Get the next function */
1144 func = cpqhp_slot_find(func->bus, func->device, index++);
1145 }
1146
1147
1148 return 0;
1149 }
1150
1151
1152 /*
1153 * cpqhp_find_available_resources
1154 *
1155 * Finds available memory, IO, and IRQ resources for programming
1156 * devices which may be added to the system
1157 * this function is for hot plug ADD!
1158 *
1159 * returns 0 if success
1160 */
1161 int cpqhp_find_available_resources(struct controller *ctrl, void __iomem *rom_start)
1162 {
1163 u8 temp;
1164 u8 populated_slot;
1165 u8 bridged_slot;
1166 void __iomem *one_slot;
1167 void __iomem *rom_resource_table;
1168 struct pci_func *func = NULL;
1169 int i = 10, index;
1170 u32 temp_dword, rc;
1171 struct pci_resource *mem_node;
1172 struct pci_resource *p_mem_node;
1173 struct pci_resource *io_node;
1174 struct pci_resource *bus_node;
1175
1176 rom_resource_table = detect_HRT_floating_pointer(rom_start, rom_start+0xffff);
1177 dbg("rom_resource_table = %p\n", rom_resource_table);
1178
1179 if (rom_resource_table == NULL)
1180 return -ENODEV;
1181
1182 /* Sum all resources and setup resource maps */
1183 unused_IRQ = readl(rom_resource_table + UNUSED_IRQ);
1184 dbg("unused_IRQ = %x\n", unused_IRQ);
1185
1186 temp = 0;
1187 while (unused_IRQ) {
1188 if (unused_IRQ & 1) {
1189 cpqhp_disk_irq = temp;
1190 break;
1191 }
1192 unused_IRQ = unused_IRQ >> 1;
1193 temp++;
1194 }
1195
1196 dbg("cpqhp_disk_irq= %d\n", cpqhp_disk_irq);
1197 unused_IRQ = unused_IRQ >> 1;
1198 temp++;
1199
1200 while (unused_IRQ) {
1201 if (unused_IRQ & 1) {
1202 cpqhp_nic_irq = temp;
1203 break;
1204 }
1205 unused_IRQ = unused_IRQ >> 1;
1206 temp++;
1207 }
1208
1209 dbg("cpqhp_nic_irq= %d\n", cpqhp_nic_irq);
1210 unused_IRQ = readl(rom_resource_table + PCIIRQ);
1211
1212 temp = 0;
1213
1214 if (!cpqhp_nic_irq)
1215 cpqhp_nic_irq = ctrl->cfgspc_irq;
1216
1217 if (!cpqhp_disk_irq)
1218 cpqhp_disk_irq = ctrl->cfgspc_irq;
1219
1220 dbg("cpqhp_disk_irq, cpqhp_nic_irq= %d, %d\n", cpqhp_disk_irq, cpqhp_nic_irq);
1221
1222 rc = compaq_nvram_load(rom_start, ctrl);
1223 if (rc)
1224 return rc;
1225
1226 one_slot = rom_resource_table + sizeof (struct hrt);
1227
1228 i = readb(rom_resource_table + NUMBER_OF_ENTRIES);
1229 dbg("number_of_entries = %d\n", i);
1230
1231 if (!readb(one_slot + SECONDARY_BUS))
1232 return 1;
1233
1234 dbg("dev|IO base|length|Mem base|length|Pre base|length|PB SB MB\n");
1235
1236 while (i && readb(one_slot + SECONDARY_BUS)) {
1237 u8 dev_func = readb(one_slot + DEV_FUNC);
1238 u8 primary_bus = readb(one_slot + PRIMARY_BUS);
1239 u8 secondary_bus = readb(one_slot + SECONDARY_BUS);
1240 u8 max_bus = readb(one_slot + MAX_BUS);
1241 u16 io_base = readw(one_slot + IO_BASE);
1242 u16 io_length = readw(one_slot + IO_LENGTH);
1243 u16 mem_base = readw(one_slot + MEM_BASE);
1244 u16 mem_length = readw(one_slot + MEM_LENGTH);
1245 u16 pre_mem_base = readw(one_slot + PRE_MEM_BASE);
1246 u16 pre_mem_length = readw(one_slot + PRE_MEM_LENGTH);
1247
1248 dbg("%2.2x | %4.4x | %4.4x | %4.4x | %4.4x | %4.4x | %4.4x |%2.2x %2.2x %2.2x\n",
1249 dev_func, io_base, io_length, mem_base, mem_length, pre_mem_base, pre_mem_length,
1250 primary_bus, secondary_bus, max_bus);
1251
1252 /* If this entry isn't for our controller's bus, ignore it */
1253 if (primary_bus != ctrl->bus) {
1254 i--;
1255 one_slot += sizeof (struct slot_rt);
1256 continue;
1257 }
1258 /* find out if this entry is for an occupied slot */
1259 ctrl->pci_bus->number = primary_bus;
1260 pci_bus_read_config_dword (ctrl->pci_bus, dev_func, PCI_VENDOR_ID, &temp_dword);
1261 dbg("temp_D_word = %x\n", temp_dword);
1262
1263 if (temp_dword != 0xFFFFFFFF) {
1264 index = 0;
1265 func = cpqhp_slot_find(primary_bus, dev_func >> 3, 0);
1266
1267 while (func && (func->function != (dev_func & 0x07))) {
1268 dbg("func = %p (bus, dev, fun) = (%d, %d, %d)\n", func, primary_bus, dev_func >> 3, index);
1269 func = cpqhp_slot_find(primary_bus, dev_func >> 3, index++);
1270 }
1271
1272 /* If we can't find a match, skip this table entry */
1273 if (!func) {
1274 i--;
1275 one_slot += sizeof (struct slot_rt);
1276 continue;
1277 }
1278 /* this may not work and shouldn't be used */
1279 if (secondary_bus != primary_bus)
1280 bridged_slot = 1;
1281 else
1282 bridged_slot = 0;
1283
1284 populated_slot = 1;
1285 } else {
1286 populated_slot = 0;
1287 bridged_slot = 0;
1288 }
1289
1290
1291 /* If we've got a valid IO base, use it */
1292
1293 temp_dword = io_base + io_length;
1294
1295 if ((io_base) && (temp_dword < 0x10000)) {
1296 io_node = kmalloc(sizeof(*io_node), GFP_KERNEL);
1297 if (!io_node)
1298 return -ENOMEM;
1299
1300 io_node->base = io_base;
1301 io_node->length = io_length;
1302
1303 dbg("found io_node(base, length) = %x, %x\n",
1304 io_node->base, io_node->length);
1305 dbg("populated slot =%d \n", populated_slot);
1306 if (!populated_slot) {
1307 io_node->next = ctrl->io_head;
1308 ctrl->io_head = io_node;
1309 } else {
1310 io_node->next = func->io_head;
1311 func->io_head = io_node;
1312 }
1313 }
1314
1315 /* If we've got a valid memory base, use it */
1316 temp_dword = mem_base + mem_length;
1317 if ((mem_base) && (temp_dword < 0x10000)) {
1318 mem_node = kmalloc(sizeof(*mem_node), GFP_KERNEL);
1319 if (!mem_node)
1320 return -ENOMEM;
1321
1322 mem_node->base = mem_base << 16;
1323
1324 mem_node->length = mem_length << 16;
1325
1326 dbg("found mem_node(base, length) = %x, %x\n",
1327 mem_node->base, mem_node->length);
1328 dbg("populated slot =%d \n", populated_slot);
1329 if (!populated_slot) {
1330 mem_node->next = ctrl->mem_head;
1331 ctrl->mem_head = mem_node;
1332 } else {
1333 mem_node->next = func->mem_head;
1334 func->mem_head = mem_node;
1335 }
1336 }
1337
1338 /* If we've got a valid prefetchable memory base, and
1339 * the base + length isn't greater than 0xFFFF
1340 */
1341 temp_dword = pre_mem_base + pre_mem_length;
1342 if ((pre_mem_base) && (temp_dword < 0x10000)) {
1343 p_mem_node = kmalloc(sizeof(*p_mem_node), GFP_KERNEL);
1344 if (!p_mem_node)
1345 return -ENOMEM;
1346
1347 p_mem_node->base = pre_mem_base << 16;
1348
1349 p_mem_node->length = pre_mem_length << 16;
1350 dbg("found p_mem_node(base, length) = %x, %x\n",
1351 p_mem_node->base, p_mem_node->length);
1352 dbg("populated slot =%d \n", populated_slot);
1353
1354 if (!populated_slot) {
1355 p_mem_node->next = ctrl->p_mem_head;
1356 ctrl->p_mem_head = p_mem_node;
1357 } else {
1358 p_mem_node->next = func->p_mem_head;
1359 func->p_mem_head = p_mem_node;
1360 }
1361 }
1362
1363 /* If we've got a valid bus number, use it
1364 * The second condition is to ignore bus numbers on
1365 * populated slots that don't have PCI-PCI bridges
1366 */
1367 if (secondary_bus && (secondary_bus != primary_bus)) {
1368 bus_node = kmalloc(sizeof(*bus_node), GFP_KERNEL);
1369 if (!bus_node)
1370 return -ENOMEM;
1371
1372 bus_node->base = secondary_bus;
1373 bus_node->length = max_bus - secondary_bus + 1;
1374 dbg("found bus_node(base, length) = %x, %x\n",
1375 bus_node->base, bus_node->length);
1376 dbg("populated slot =%d \n", populated_slot);
1377 if (!populated_slot) {
1378 bus_node->next = ctrl->bus_head;
1379 ctrl->bus_head = bus_node;
1380 } else {
1381 bus_node->next = func->bus_head;
1382 func->bus_head = bus_node;
1383 }
1384 }
1385
1386 i--;
1387 one_slot += sizeof (struct slot_rt);
1388 }
1389
1390 /* If all of the following fail, we don't have any resources for
1391 * hot plug add
1392 */
1393 rc = 1;
1394 rc &= cpqhp_resource_sort_and_combine(&(ctrl->mem_head));
1395 rc &= cpqhp_resource_sort_and_combine(&(ctrl->p_mem_head));
1396 rc &= cpqhp_resource_sort_and_combine(&(ctrl->io_head));
1397 rc &= cpqhp_resource_sort_and_combine(&(ctrl->bus_head));
1398
1399 return rc;
1400 }
1401
1402
1403 /*
1404 * cpqhp_return_board_resources
1405 *
1406 * this routine returns all resources allocated to a board to
1407 * the available pool.
1408 *
1409 * returns 0 if success
1410 */
1411 int cpqhp_return_board_resources(struct pci_func * func, struct resource_lists * resources)
1412 {
1413 int rc = 0;
1414 struct pci_resource *node;
1415 struct pci_resource *t_node;
1416 dbg("%s\n", __func__);
1417
1418 if (!func)
1419 return 1;
1420
1421 node = func->io_head;
1422 func->io_head = NULL;
1423 while (node) {
1424 t_node = node->next;
1425 return_resource(&(resources->io_head), node);
1426 node = t_node;
1427 }
1428
1429 node = func->mem_head;
1430 func->mem_head = NULL;
1431 while (node) {
1432 t_node = node->next;
1433 return_resource(&(resources->mem_head), node);
1434 node = t_node;
1435 }
1436
1437 node = func->p_mem_head;
1438 func->p_mem_head = NULL;
1439 while (node) {
1440 t_node = node->next;
1441 return_resource(&(resources->p_mem_head), node);
1442 node = t_node;
1443 }
1444
1445 node = func->bus_head;
1446 func->bus_head = NULL;
1447 while (node) {
1448 t_node = node->next;
1449 return_resource(&(resources->bus_head), node);
1450 node = t_node;
1451 }
1452
1453 rc |= cpqhp_resource_sort_and_combine(&(resources->mem_head));
1454 rc |= cpqhp_resource_sort_and_combine(&(resources->p_mem_head));
1455 rc |= cpqhp_resource_sort_and_combine(&(resources->io_head));
1456 rc |= cpqhp_resource_sort_and_combine(&(resources->bus_head));
1457
1458 return rc;
1459 }
1460
1461
1462 /*
1463 * cpqhp_destroy_resource_list
1464 *
1465 * Puts node back in the resource list pointed to by head
1466 */
1467 void cpqhp_destroy_resource_list (struct resource_lists * resources)
1468 {
1469 struct pci_resource *res, *tres;
1470
1471 res = resources->io_head;
1472 resources->io_head = NULL;
1473
1474 while (res) {
1475 tres = res;
1476 res = res->next;
1477 kfree(tres);
1478 }
1479
1480 res = resources->mem_head;
1481 resources->mem_head = NULL;
1482
1483 while (res) {
1484 tres = res;
1485 res = res->next;
1486 kfree(tres);
1487 }
1488
1489 res = resources->p_mem_head;
1490 resources->p_mem_head = NULL;
1491
1492 while (res) {
1493 tres = res;
1494 res = res->next;
1495 kfree(tres);
1496 }
1497
1498 res = resources->bus_head;
1499 resources->bus_head = NULL;
1500
1501 while (res) {
1502 tres = res;
1503 res = res->next;
1504 kfree(tres);
1505 }
1506 }
1507
1508
1509 /*
1510 * cpqhp_destroy_board_resources
1511 *
1512 * Puts node back in the resource list pointed to by head
1513 */
1514 void cpqhp_destroy_board_resources (struct pci_func * func)
1515 {
1516 struct pci_resource *res, *tres;
1517
1518 res = func->io_head;
1519 func->io_head = NULL;
1520
1521 while (res) {
1522 tres = res;
1523 res = res->next;
1524 kfree(tres);
1525 }
1526
1527 res = func->mem_head;
1528 func->mem_head = NULL;
1529
1530 while (res) {
1531 tres = res;
1532 res = res->next;
1533 kfree(tres);
1534 }
1535
1536 res = func->p_mem_head;
1537 func->p_mem_head = NULL;
1538
1539 while (res) {
1540 tres = res;
1541 res = res->next;
1542 kfree(tres);
1543 }
1544
1545 res = func->bus_head;
1546 func->bus_head = NULL;
1547
1548 while (res) {
1549 tres = res;
1550 res = res->next;
1551 kfree(tres);
1552 }
1553 }
Tomato firmware and modifications.