release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/net/wireless/b43/phy_a.c

   1 /*
   2
   3   Broadcom B43 wireless driver
   4   IEEE 802.11a PHY driver
   5
   6   Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
   7   Copyright (c) 2005-2007 Stefano Brivio <stefano.brivio@polimi.it>
   8   Copyright (c) 2005-2008 Michael Buesch <mb@bu3sch.de>
   9   Copyright (c) 2005, 2006 Danny van Dyk <kugelfang@gentoo.org>
  10   Copyright (c) 2005, 2006 Andreas Jaggi <andreas.jaggi@waterwave.ch>
  11
  12   This program is free software; you can redistribute it and/or modify
  13   it under the terms of the GNU General Public License as published by
  14   the Free Software Foundation; either version 2 of the License, or
  15   (at your option) any later version.
  16
  17   This program is distributed in the hope that it will be useful,
  18   but WITHOUT ANY WARRANTY; without even the implied warranty of
  19   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20   GNU General Public License for more details.
  21
  22   You should have received a copy of the GNU General Public License
  23   along with this program; see the file COPYING.  If not, write to
  24   the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  25   Boston, MA 02110-1301, USA.
  26
  27 */
  28
  29 #include <linux/slab.h>
  30
  31 #include "b43.h"
  32 #include "phy_a.h"
  33 #include "phy_common.h"
  34 #include "wa.h"
  35 #include "tables.h"
  36 #include "main.h"
  37
  38
  39 /* Get the freq, as it has to be written to the device. */
  40 static inline u16 channel2freq_a(u8 channel)
  41 {
  42         B43_WARN_ON(channel > 200);
  43
  44         return (5000 + 5 * channel);
  45 }
  46
  47 static inline u16 freq_r3A_value(u16 frequency)
  48 {
  49         u16 value;
  50
  51         if (frequency < 5091)
  52                 value = 0x0040;
  53         else if (frequency < 5321)
  54                 value = 0x0000;
  55         else if (frequency < 5806)
  56                 value = 0x0080;
  57         else
  58                 value = 0x0040;
  59
  60         return value;
  61 }
  62
  63
  64 static void b43_radio_set_tx_iq(struct b43_wldev *dev)
  65 {
  66         static const u8 data_high[5] = { 0x00, 0x40, 0x80, 0x90, 0xD0 };
  67         static const u8 data_low[5] = { 0x00, 0x01, 0x05, 0x06, 0x0A };
  68         u16 tmp = b43_radio_read16(dev, 0x001E);
  69         int i, j;
  70
  71         for (i = 0; i < 5; i++) {
  72                 for (j = 0; j < 5; j++) {
  73                         if (tmp == (data_high[i] << 4 | data_low[j])) {
  74                                 b43_phy_write(dev, 0x0069,
  75                                               (i - j) << 8 | 0x00C0);
  76                                 return;
  77                         }
  78                 }
  79         }
  80 }
  81
  82 static void aphy_channel_switch(struct b43_wldev *dev, unsigned int channel)
  83 {
  84         u16 freq, r8, tmp;
  85
  86         freq = channel2freq_a(channel);
  87
  88         r8 = b43_radio_read16(dev, 0x0008);
  89         b43_write16(dev, 0x03F0, freq);
  90         b43_radio_write16(dev, 0x0008, r8);
  91
  92         //TODO: write max channel TX power? to Radio 0x2D
  93         tmp = b43_radio_read16(dev, 0x002E);
  94         tmp &= 0x0080;
  95         //TODO: OR tmp with the Power out estimation for this channel?
  96         b43_radio_write16(dev, 0x002E, tmp);
  97
  98         if (freq >= 4920 && freq <= 5500) {
  99                 /*
 100                  * r8 = (((freq * 15 * 0xE1FC780F) >> 32) / 29) & 0x0F;
 101                  *    = (freq * 0.025862069
 102                  */
 103                 r8 = 3 * freq / 116;    /* is equal to r8 = freq * 0.025862 */
 104         }
 105         b43_radio_write16(dev, 0x0007, (r8 << 4) | r8);
 106         b43_radio_write16(dev, 0x0020, (r8 << 4) | r8);
 107         b43_radio_write16(dev, 0x0021, (r8 << 4) | r8);
 108         b43_radio_maskset(dev, 0x0022, 0x000F, (r8 << 4));
 109         b43_radio_write16(dev, 0x002A, (r8 << 4));
 110         b43_radio_write16(dev, 0x002B, (r8 << 4));
 111         b43_radio_maskset(dev, 0x0008, 0x00F0, (r8 << 4));
 112         b43_radio_maskset(dev, 0x0029, 0xFF0F, 0x00B0);
 113         b43_radio_write16(dev, 0x0035, 0x00AA);
 114         b43_radio_write16(dev, 0x0036, 0x0085);
 115         b43_radio_maskset(dev, 0x003A, 0xFF20, freq_r3A_value(freq));
 116         b43_radio_mask(dev, 0x003D, 0x00FF);
 117         b43_radio_maskset(dev, 0x0081, 0xFF7F, 0x0080);
 118         b43_radio_mask(dev, 0x0035, 0xFFEF);
 119         b43_radio_maskset(dev, 0x0035, 0xFFEF, 0x0010);
 120         b43_radio_set_tx_iq(dev);
 121 }
 122
 123 static void b43_radio_init2060(struct b43_wldev *dev)
 124 {
 125         b43_radio_write16(dev, 0x0004, 0x00C0);
 126         b43_radio_write16(dev, 0x0005, 0x0008);
 127         b43_radio_write16(dev, 0x0009, 0x0040);
 128         b43_radio_write16(dev, 0x0005, 0x00AA);
 129         b43_radio_write16(dev, 0x0032, 0x008F);
 130         b43_radio_write16(dev, 0x0006, 0x008F);
 131         b43_radio_write16(dev, 0x0034, 0x008F);
 132         b43_radio_write16(dev, 0x002C, 0x0007);
 133         b43_radio_write16(dev, 0x0082, 0x0080);
 134         b43_radio_write16(dev, 0x0080, 0x0000);
 135         b43_radio_write16(dev, 0x003F, 0x00DA);
 136         b43_radio_mask(dev, 0x0005, ~0x0008);
 137         b43_radio_mask(dev, 0x0081, ~0x0010);
 138         b43_radio_mask(dev, 0x0081, ~0x0020);
 139         b43_radio_mask(dev, 0x0081, ~0x0020);
 140         msleep(1);              /* delay 400usec */
 141
 142         b43_radio_maskset(dev, 0x0081, ~0x0020, 0x0010);
 143         msleep(1);              /* delay 400usec */
 144
 145         b43_radio_maskset(dev, 0x0005, ~0x0008, 0x0008);
 146         b43_radio_mask(dev, 0x0085, ~0x0010);
 147         b43_radio_mask(dev, 0x0005, ~0x0008);
 148         b43_radio_mask(dev, 0x0081, ~0x0040);
 149         b43_radio_maskset(dev, 0x0081, ~0x0040, 0x0040);
 150         b43_radio_write16(dev, 0x0005,
 151                           (b43_radio_read16(dev, 0x0081) & ~0x0008) | 0x0008);
 152         b43_phy_write(dev, 0x0063, 0xDDC6);
 153         b43_phy_write(dev, 0x0069, 0x07BE);
 154         b43_phy_write(dev, 0x006A, 0x0000);
 155
 156         aphy_channel_switch(dev, dev->phy.ops->get_default_chan(dev));
 157
 158         msleep(1);
 159 }
 160
 161 static void b43_phy_rssiagc(struct b43_wldev *dev, u8 enable)
 162 {
 163         int i;
 164
 165         if (dev->phy.rev < 3) {
 166                 if (enable)
 167                         for (i = 0; i < B43_TAB_RSSIAGC1_SIZE; i++) {
 168                                 b43_ofdmtab_write16(dev,
 169                                         B43_OFDMTAB_LNAHPFGAIN1, i, 0xFFF8);
 170                                 b43_ofdmtab_write16(dev,
 171                                         B43_OFDMTAB_WRSSI, i, 0xFFF8);
 172                         }
 173                 else
 174                         for (i = 0; i < B43_TAB_RSSIAGC1_SIZE; i++) {
 175                                 b43_ofdmtab_write16(dev,
 176                                         B43_OFDMTAB_LNAHPFGAIN1, i, b43_tab_rssiagc1[i]);
 177                                 b43_ofdmtab_write16(dev,
 178                                         B43_OFDMTAB_WRSSI, i, b43_tab_rssiagc1[i]);
 179                         }
 180         } else {
 181                 if (enable)
 182                         for (i = 0; i < B43_TAB_RSSIAGC1_SIZE; i++)
 183                                 b43_ofdmtab_write16(dev,
 184                                         B43_OFDMTAB_WRSSI, i, 0x0820);
 185                 else
 186                         for (i = 0; i < B43_TAB_RSSIAGC2_SIZE; i++)
 187                                 b43_ofdmtab_write16(dev,
 188                                         B43_OFDMTAB_WRSSI, i, b43_tab_rssiagc2[i]);
 189         }
 190 }
 191
 192 static void b43_phy_ww(struct b43_wldev *dev)
 193 {
 194         u16 b, curr_s, best_s = 0xFFFF;
 195         int i;
 196
 197         b43_phy_mask(dev, B43_PHY_CRS0, ~B43_PHY_CRS0_EN);
 198         b43_phy_set(dev, B43_PHY_OFDM(0x1B), 0x1000);
 199         b43_phy_maskset(dev, B43_PHY_OFDM(0x82), 0xF0FF, 0x0300);
 200         b43_radio_set(dev, 0x0009, 0x0080);
 201         b43_radio_maskset(dev, 0x0012, 0xFFFC, 0x0002);
 202         b43_wa_initgains(dev);
 203         b43_phy_write(dev, B43_PHY_OFDM(0xBA), 0x3ED5);
 204         b = b43_phy_read(dev, B43_PHY_PWRDOWN);
 205         b43_phy_write(dev, B43_PHY_PWRDOWN, (b & 0xFFF8) | 0x0005);
 206         b43_radio_set(dev, 0x0004, 0x0004);
 207         for (i = 0x10; i <= 0x20; i++) {
 208                 b43_radio_write16(dev, 0x0013, i);
 209                 curr_s = b43_phy_read(dev, B43_PHY_OTABLEQ) & 0x00FF;
 210                 if (!curr_s) {
 211                         best_s = 0x0000;
 212                         break;
 213                 } else if (curr_s >= 0x0080)
 214                         curr_s = 0x0100 - curr_s;
 215                 if (curr_s < best_s)
 216                         best_s = curr_s;
 217         }
 218         b43_phy_write(dev, B43_PHY_PWRDOWN, b);
 219         b43_radio_mask(dev, 0x0004, 0xFFFB);
 220         b43_radio_write16(dev, 0x0013, best_s);
 221         b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1_R1, 0, 0xFFEC);
 222         b43_phy_write(dev, B43_PHY_OFDM(0xB7), 0x1E80);
 223         b43_phy_write(dev, B43_PHY_OFDM(0xB6), 0x1C00);
 224         b43_phy_write(dev, B43_PHY_OFDM(0xB5), 0x0EC0);
 225         b43_phy_write(dev, B43_PHY_OFDM(0xB2), 0x00C0);
 226         b43_phy_write(dev, B43_PHY_OFDM(0xB9), 0x1FFF);
 227         b43_phy_maskset(dev, B43_PHY_OFDM(0xBB), 0xF000, 0x0053);
 228         b43_phy_maskset(dev, B43_PHY_OFDM61, 0xFE1F, 0x0120);
 229         b43_phy_maskset(dev, B43_PHY_OFDM(0x13), 0x0FFF, 0x3000);
 230         b43_phy_maskset(dev, B43_PHY_OFDM(0x14), 0x0FFF, 0x3000);
 231         b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 6, 0x0017);
 232         for (i = 0; i < 6; i++)
 233                 b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, i, 0x000F);
 234         b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 0x0D, 0x000E);
 235         b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 0x0E, 0x0011);
 236         b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 0x0F, 0x0013);
 237         b43_phy_write(dev, B43_PHY_OFDM(0x33), 0x5030);
 238         b43_phy_set(dev, B43_PHY_CRS0, B43_PHY_CRS0_EN);
 239 }
 240
 241 static void hardware_pctl_init_aphy(struct b43_wldev *dev)
 242 {
 243         //TODO
 244 }
 245
 246 void b43_phy_inita(struct b43_wldev *dev)
 247 {
 248         struct ssb_bus *bus = dev->dev->bus;
 249         struct b43_phy *phy = &dev->phy;
 250
 251         /* This lowlevel A-PHY init is also called from G-PHY init.
 252          * So we must not access phy->a, if called from G-PHY code.
 253          */
 254         B43_WARN_ON((phy->type != B43_PHYTYPE_A) &&
 255                     (phy->type != B43_PHYTYPE_G));
 256
 257         might_sleep();
 258
 259         if (phy->rev >= 6) {
 260                 if (phy->type == B43_PHYTYPE_A)
 261                         b43_phy_mask(dev, B43_PHY_OFDM(0x1B), ~0x1000);
 262                 if (b43_phy_read(dev, B43_PHY_ENCORE) & B43_PHY_ENCORE_EN)
 263                         b43_phy_set(dev, B43_PHY_ENCORE, 0x0010);
 264                 else
 265                         b43_phy_mask(dev, B43_PHY_ENCORE, ~0x1010);
 266         }
 267
 268         b43_wa_all(dev);
 269
 270         if (phy->type == B43_PHYTYPE_A) {
 271                 if (phy->gmode && (phy->rev < 3))
 272                         b43_phy_set(dev, 0x0034, 0x0001);
 273                 b43_phy_rssiagc(dev, 0);
 274
 275                 b43_phy_set(dev, B43_PHY_CRS0, B43_PHY_CRS0_EN);
 276
 277                 b43_radio_init2060(dev);
 278
 279                 if ((bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM) &&
 280                     ((bus->boardinfo.type == SSB_BOARD_BU4306) ||
 281                      (bus->boardinfo.type == SSB_BOARD_BU4309))) {
 282                         ; //TODO: A PHY LO
 283                 }
 284
 285                 if (phy->rev >= 3)
 286                         b43_phy_ww(dev);
 287
 288                 hardware_pctl_init_aphy(dev);
 289
 290                 //TODO: radar detection
 291         }
 292
 293         if ((phy->type == B43_PHYTYPE_G) &&
 294             (dev->dev->bus->sprom.boardflags_lo & B43_BFL_PACTRL)) {
 295                 b43_phy_maskset(dev, B43_PHY_OFDM(0x6E), 0xE000, 0x3CF);
 296         }
 297 }
 298
 299 /* Initialise the TSSI->dBm lookup table */
 300 static int b43_aphy_init_tssi2dbm_table(struct b43_wldev *dev)
 301 {
 302         struct b43_phy *phy = &dev->phy;
 303         struct b43_phy_a *aphy = phy->a;
 304         s16 pab0, pab1, pab2;
 305
 306         pab0 = (s16) (dev->dev->bus->sprom.pa1b0);
 307         pab1 = (s16) (dev->dev->bus->sprom.pa1b1);
 308         pab2 = (s16) (dev->dev->bus->sprom.pa1b2);
 309
 310         if (pab0 != 0 && pab1 != 0 && pab2 != 0 &&
 311             pab0 != -1 && pab1 != -1 && pab2 != -1) {
 312                 /* The pabX values are set in SPROM. Use them. */
 313                 if ((s8) dev->dev->bus->sprom.itssi_a != 0 &&
 314                     (s8) dev->dev->bus->sprom.itssi_a != -1)
 315                         aphy->tgt_idle_tssi =
 316                             (s8) (dev->dev->bus->sprom.itssi_a);
 317                 else
 318                         aphy->tgt_idle_tssi = 62;
 319                 aphy->tssi2dbm = b43_generate_dyn_tssi2dbm_tab(dev, pab0,
 320                                                                pab1, pab2);
 321                 if (!aphy->tssi2dbm)
 322                         return -ENOMEM;
 323         } else {
 324                 /* pabX values not set in SPROM,
 325                  * but APHY needs a generated table. */
 326                 aphy->tssi2dbm = NULL;
 327                 b43err(dev->wl, "Could not generate tssi2dBm "
 328                        "table (wrong SPROM info)!\n");
 329                 return -ENODEV;
 330         }
 331
 332         return 0;
 333 }
 334
 335 static int b43_aphy_op_allocate(struct b43_wldev *dev)
 336 {
 337         struct b43_phy_a *aphy;
 338         int err;
 339
 340         aphy = kzalloc(sizeof(*aphy), GFP_KERNEL);
 341         if (!aphy)
 342                 return -ENOMEM;
 343         dev->phy.a = aphy;
 344
 345         err = b43_aphy_init_tssi2dbm_table(dev);
 346         if (err)
 347                 goto err_free_aphy;
 348
 349         return 0;
 350
 351 err_free_aphy:
 352         kfree(aphy);
 353         dev->phy.a = NULL;
 354
 355         return err;
 356 }
 357
 358 static void b43_aphy_op_prepare_structs(struct b43_wldev *dev)
 359 {
 360         struct b43_phy *phy = &dev->phy;
 361         struct b43_phy_a *aphy = phy->a;
 362         const void *tssi2dbm;
 363         int tgt_idle_tssi;
 364
 365         /* tssi2dbm table is constant, so it is initialized at alloc time.
 366          * Save a copy of the pointer. */
 367         tssi2dbm = aphy->tssi2dbm;
 368         tgt_idle_tssi = aphy->tgt_idle_tssi;
 369
 370         /* Zero out the whole PHY structure. */
 371         memset(aphy, 0, sizeof(*aphy));
 372
 373         aphy->tssi2dbm = tssi2dbm;
 374         aphy->tgt_idle_tssi = tgt_idle_tssi;
 375
 376         //TODO init struct b43_phy_a
 377
 378 }
 379
 380 static void b43_aphy_op_free(struct b43_wldev *dev)
 381 {
 382         struct b43_phy *phy = &dev->phy;
 383         struct b43_phy_a *aphy = phy->a;
 384
 385         kfree(aphy->tssi2dbm);
 386         aphy->tssi2dbm = NULL;
 387
 388         kfree(aphy);
 389         dev->phy.a = NULL;
 390 }
 391
 392 static int b43_aphy_op_init(struct b43_wldev *dev)
 393 {
 394         b43_phy_inita(dev);
 395
 396         return 0;
 397 }
 398
 399 static inline u16 adjust_phyreg(struct b43_wldev *dev, u16 offset)
 400 {
 401         /* OFDM registers are base-registers for the A-PHY. */
 402         if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
 403                 offset &= ~B43_PHYROUTE;
 404                 offset |= B43_PHYROUTE_BASE;
 405         }
 406
 407 #if B43_DEBUG
 408         if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
 409                 /* Ext-G registers are only available on G-PHYs */
 410                 b43err(dev->wl, "Invalid EXT-G PHY access at "
 411                        "0x%04X on A-PHY\n", offset);
 412                 dump_stack();
 413         }
 414         if ((offset & B43_PHYROUTE) == B43_PHYROUTE_N_BMODE) {
 415                 /* N-BMODE registers are only available on N-PHYs */
 416                 b43err(dev->wl, "Invalid N-BMODE PHY access at "
 417                        "0x%04X on A-PHY\n", offset);
 418                 dump_stack();
 419         }
 420 #endif /* B43_DEBUG */
 421
 422         return offset;
 423 }
 424
 425 static u16 b43_aphy_op_read(struct b43_wldev *dev, u16 reg)
 426 {
 427         reg = adjust_phyreg(dev, reg);
 428         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
 429         return b43_read16(dev, B43_MMIO_PHY_DATA);
 430 }
 431
 432 static void b43_aphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
 433 {
 434         reg = adjust_phyreg(dev, reg);
 435         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
 436         b43_write16(dev, B43_MMIO_PHY_DATA, value);
 437 }
 438
 439 static u16 b43_aphy_op_radio_read(struct b43_wldev *dev, u16 reg)
 440 {
 441         /* Register 1 is a 32-bit register. */
 442         B43_WARN_ON(reg == 1);
 443         /* A-PHY needs 0x40 for read access */
 444         reg |= 0x40;
 445
 446         b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
 447         return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
 448 }
 449
 450 static void b43_aphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
 451 {
 452         /* Register 1 is a 32-bit register. */
 453         B43_WARN_ON(reg == 1);
 454
 455         b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
 456         b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
 457 }
 458
 459 static bool b43_aphy_op_supports_hwpctl(struct b43_wldev *dev)
 460 {
 461         return (dev->phy.rev >= 5);
 462 }
 463
 464 static void b43_aphy_op_software_rfkill(struct b43_wldev *dev,
 465                                         bool blocked)
 466 {
 467         struct b43_phy *phy = &dev->phy;
 468
 469         if (!blocked) {
 470                 if (phy->radio_on)
 471                         return;
 472                 b43_radio_write16(dev, 0x0004, 0x00C0);
 473                 b43_radio_write16(dev, 0x0005, 0x0008);
 474                 b43_phy_mask(dev, 0x0010, 0xFFF7);
 475                 b43_phy_mask(dev, 0x0011, 0xFFF7);
 476                 b43_radio_init2060(dev);
 477         } else {
 478                 b43_radio_write16(dev, 0x0004, 0x00FF);
 479                 b43_radio_write16(dev, 0x0005, 0x00FB);
 480                 b43_phy_set(dev, 0x0010, 0x0008);
 481                 b43_phy_set(dev, 0x0011, 0x0008);
 482         }
 483 }
 484
 485 static int b43_aphy_op_switch_channel(struct b43_wldev *dev,
 486                                       unsigned int new_channel)
 487 {
 488         if (new_channel > 200)
 489                 return -EINVAL;
 490         aphy_channel_switch(dev, new_channel);
 491
 492         return 0;
 493 }
 494
 495 static unsigned int b43_aphy_op_get_default_chan(struct b43_wldev *dev)
 496 {
 497         return 36; /* Default to channel 36 */
 498 }
 499
 500 static void b43_aphy_op_set_rx_antenna(struct b43_wldev *dev, int antenna)
 501 {//TODO
 502         struct b43_phy *phy = &dev->phy;
 503         u16 tmp;
 504         int autodiv = 0;
 505
 506         if (antenna == B43_ANTENNA_AUTO0 || antenna == B43_ANTENNA_AUTO1)
 507                 autodiv = 1;
 508
 509         b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_ANTDIVHELP);
 510
 511         b43_phy_maskset(dev, B43_PHY_BBANDCFG, ~B43_PHY_BBANDCFG_RXANT,
 512                         (autodiv ? B43_ANTENNA_AUTO1 : antenna) <<
 513                         B43_PHY_BBANDCFG_RXANT_SHIFT);
 514
 515         if (autodiv) {
 516                 tmp = b43_phy_read(dev, B43_PHY_ANTDWELL);
 517                 if (antenna == B43_ANTENNA_AUTO1)
 518                         tmp &= ~B43_PHY_ANTDWELL_AUTODIV1;
 519                 else
 520                         tmp |= B43_PHY_ANTDWELL_AUTODIV1;
 521                 b43_phy_write(dev, B43_PHY_ANTDWELL, tmp);
 522         }
 523         if (phy->rev < 3)
 524                 b43_phy_maskset(dev, B43_PHY_ANTDWELL, 0xFF00, 0x24);
 525         else {
 526                 b43_phy_set(dev, B43_PHY_OFDM61, 0x10);
 527                 if (phy->rev == 3) {
 528                         b43_phy_write(dev, B43_PHY_CLIPPWRDOWNT, 0x1D);
 529                         b43_phy_write(dev, B43_PHY_ADIVRELATED, 8);
 530                 } else {
 531                         b43_phy_write(dev, B43_PHY_CLIPPWRDOWNT, 0x3A);
 532                         b43_phy_maskset(dev, B43_PHY_ADIVRELATED, 0xFF00, 8);
 533                 }
 534         }
 535
 536         b43_hf_write(dev, b43_hf_read(dev) | B43_HF_ANTDIVHELP);
 537 }
 538
 539 static void b43_aphy_op_adjust_txpower(struct b43_wldev *dev)
 540 {//TODO
 541 }
 542
 543 static enum b43_txpwr_result b43_aphy_op_recalc_txpower(struct b43_wldev *dev,
 544                                                         bool ignore_tssi)
 545 {//TODO
 546         return B43_TXPWR_RES_DONE;
 547 }
 548
 549 static void b43_aphy_op_pwork_15sec(struct b43_wldev *dev)
 550 {//TODO
 551 }
 552
 553 static void b43_aphy_op_pwork_60sec(struct b43_wldev *dev)
 554 {//TODO
 555 }
 556
 557 const struct b43_phy_operations b43_phyops_a = {
 558         .allocate               = b43_aphy_op_allocate,
 559         .free                   = b43_aphy_op_free,
 560         .prepare_structs        = b43_aphy_op_prepare_structs,
 561         .init                   = b43_aphy_op_init,
 562         .phy_read               = b43_aphy_op_read,
 563         .phy_write              = b43_aphy_op_write,
 564         .radio_read             = b43_aphy_op_radio_read,
 565         .radio_write            = b43_aphy_op_radio_write,
 566         .supports_hwpctl        = b43_aphy_op_supports_hwpctl,
 567         .software_rfkill        = b43_aphy_op_software_rfkill,
 568         .switch_analog          = b43_phyop_switch_analog_generic,
 569         .switch_channel         = b43_aphy_op_switch_channel,
 570         .get_default_chan       = b43_aphy_op_get_default_chan,
 571         .set_rx_antenna         = b43_aphy_op_set_rx_antenna,
 572         .recalc_txpower         = b43_aphy_op_recalc_txpower,
 573         .adjust_txpower         = b43_aphy_op_adjust_txpower,
 574         .pwork_15sec            = b43_aphy_op_pwork_15sec,
 575         .pwork_60sec            = b43_aphy_op_pwork_60sec,
 576 };