?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
GUI: Fix Tomato RAF theme for all builds. Compilation typo.
[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / drivers / net / wireless / ath / ath9k / init.c
blob58b2ae50fa1f1c5c4a4316ee3d34f1935726e75f
1 /*
2 * Copyright (c) 2008-2009 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/slab.h>
18
19 #include "ath9k.h"
20
21 static char *dev_info = "ath9k";
22
23 MODULE_AUTHOR("Atheros Communications");
24 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
25 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
26 MODULE_LICENSE("Dual BSD/GPL");
27
28 static unsigned int ath9k_debug = ATH_DBG_DEFAULT;
29 module_param_named(debug, ath9k_debug, uint, 0);
30 MODULE_PARM_DESC(debug, "Debugging mask");
31
32 int modparam_nohwcrypt;
33 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
34 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
35
36 int led_blink = 1;
37 module_param_named(blink, led_blink, int, 0444);
38 MODULE_PARM_DESC(blink, "Enable LED blink on activity");
39
40 /* We use the hw_value as an index into our private channel structure */
41
42 #define CHAN2G(_freq, _idx) { \
43 .center_freq = (_freq), \
44 .hw_value = (_idx), \
45 .max_power = 20, \
46 }
47
48 #define CHAN5G(_freq, _idx) { \
49 .band = IEEE80211_BAND_5GHZ, \
50 .center_freq = (_freq), \
51 .hw_value = (_idx), \
52 .max_power = 20, \
53 }
54
55 /* Some 2 GHz radios are actually tunable on 2312-2732
56 * on 5 MHz steps, we support the channels which we know
57 * we have calibration data for all cards though to make
58 * this static */
59 static const struct ieee80211_channel ath9k_2ghz_chantable[] = {
60 CHAN2G(2412, 0), /* Channel 1 */
61 CHAN2G(2417, 1), /* Channel 2 */
62 CHAN2G(2422, 2), /* Channel 3 */
63 CHAN2G(2427, 3), /* Channel 4 */
64 CHAN2G(2432, 4), /* Channel 5 */
65 CHAN2G(2437, 5), /* Channel 6 */
66 CHAN2G(2442, 6), /* Channel 7 */
67 CHAN2G(2447, 7), /* Channel 8 */
68 CHAN2G(2452, 8), /* Channel 9 */
69 CHAN2G(2457, 9), /* Channel 10 */
70 CHAN2G(2462, 10), /* Channel 11 */
71 CHAN2G(2467, 11), /* Channel 12 */
72 CHAN2G(2472, 12), /* Channel 13 */
73 CHAN2G(2484, 13), /* Channel 14 */
74 };
75
76 static const struct ieee80211_channel ath9k_5ghz_chantable[] = {
77 /* _We_ call this UNII 1 */
78 CHAN5G(5180, 14), /* Channel 36 */
79 CHAN5G(5200, 15), /* Channel 40 */
80 CHAN5G(5220, 16), /* Channel 44 */
81 CHAN5G(5240, 17), /* Channel 48 */
82 /* _We_ call this UNII 2 */
83 CHAN5G(5260, 18), /* Channel 52 */
84 CHAN5G(5280, 19), /* Channel 56 */
85 CHAN5G(5300, 20), /* Channel 60 */
86 CHAN5G(5320, 21), /* Channel 64 */
87 /* _We_ call this "Middle band" */
88 CHAN5G(5500, 22), /* Channel 100 */
89 CHAN5G(5520, 23), /* Channel 104 */
90 CHAN5G(5540, 24), /* Channel 108 */
91 CHAN5G(5560, 25), /* Channel 112 */
92 CHAN5G(5580, 26), /* Channel 116 */
93 CHAN5G(5600, 27), /* Channel 120 */
94 CHAN5G(5620, 28), /* Channel 124 */
95 CHAN5G(5640, 29), /* Channel 128 */
96 CHAN5G(5660, 30), /* Channel 132 */
97 CHAN5G(5680, 31), /* Channel 136 */
98 CHAN5G(5700, 32), /* Channel 140 */
99 /* _We_ call this UNII 3 */
100 CHAN5G(5745, 33), /* Channel 149 */
101 CHAN5G(5765, 34), /* Channel 153 */
102 CHAN5G(5785, 35), /* Channel 157 */
103 CHAN5G(5805, 36), /* Channel 161 */
104 CHAN5G(5825, 37), /* Channel 165 */
105 };
106
107 /* Atheros hardware rate code addition for short premble */
108 #define SHPCHECK(__hw_rate, __flags) \
109 ((__flags & IEEE80211_RATE_SHORT_PREAMBLE) ? (__hw_rate | 0x04 ) : 0)
110
111 #define RATE(_bitrate, _hw_rate, _flags) { \
112 .bitrate = (_bitrate), \
113 .flags = (_flags), \
114 .hw_value = (_hw_rate), \
115 .hw_value_short = (SHPCHECK(_hw_rate, _flags)) \
116 }
117
118 static struct ieee80211_rate ath9k_legacy_rates[] = {
119 RATE(10, 0x1b, 0),
120 RATE(20, 0x1a, IEEE80211_RATE_SHORT_PREAMBLE),
121 RATE(55, 0x19, IEEE80211_RATE_SHORT_PREAMBLE),
122 RATE(110, 0x18, IEEE80211_RATE_SHORT_PREAMBLE),
123 RATE(60, 0x0b, 0),
124 RATE(90, 0x0f, 0),
125 RATE(120, 0x0a, 0),
126 RATE(180, 0x0e, 0),
127 RATE(240, 0x09, 0),
128 RATE(360, 0x0d, 0),
129 RATE(480, 0x08, 0),
130 RATE(540, 0x0c, 0),
131 };
132
133 static void ath9k_deinit_softc(struct ath_softc *sc);
134
135 /*
136 * Read and write, they both share the same lock. We do this to serialize
137 * reads and writes on Atheros 802.11n PCI devices only. This is required
138 * as the FIFO on these devices can only accept sanely 2 requests.
139 */
140
141 static void ath9k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
142 {
143 struct ath_hw *ah = (struct ath_hw *) hw_priv;
144 struct ath_common *common = ath9k_hw_common(ah);
145 struct ath_softc *sc = (struct ath_softc *) common->priv;
146
147 if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
148 unsigned long flags;
149 spin_lock_irqsave(&sc->sc_serial_rw, flags);
150 iowrite32(val, sc->mem + reg_offset);
151 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
152 } else
153 iowrite32(val, sc->mem + reg_offset);
154 }
155
156 static unsigned int ath9k_ioread32(void *hw_priv, u32 reg_offset)
157 {
158 struct ath_hw *ah = (struct ath_hw *) hw_priv;
159 struct ath_common *common = ath9k_hw_common(ah);
160 struct ath_softc *sc = (struct ath_softc *) common->priv;
161 u32 val;
162
163 if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
164 unsigned long flags;
165 spin_lock_irqsave(&sc->sc_serial_rw, flags);
166 val = ioread32(sc->mem + reg_offset);
167 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
168 } else
169 val = ioread32(sc->mem + reg_offset);
170 return val;
171 }
172
173 static const struct ath_ops ath9k_common_ops = {
174 .read = ath9k_ioread32,
175 .write = ath9k_iowrite32,
176 };
177
178 /**************************/
179 /* Initialization */
180 /**************************/
181
182 static void setup_ht_cap(struct ath_softc *sc,
183 struct ieee80211_sta_ht_cap *ht_info)
184 {
185 struct ath_hw *ah = sc->sc_ah;
186 struct ath_common *common = ath9k_hw_common(ah);
187 u8 tx_streams, rx_streams;
188 int i, max_streams;
189
190 ht_info->ht_supported = true;
191 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
192 IEEE80211_HT_CAP_SM_PS |
193 IEEE80211_HT_CAP_SGI_40 |
194 IEEE80211_HT_CAP_DSSSCCK40;
195
196 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_LDPC)
197 ht_info->cap |= IEEE80211_HT_CAP_LDPC_CODING;
198
199 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_SGI_20)
200 ht_info->cap |= IEEE80211_HT_CAP_SGI_20;
201
202 ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
203 ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8;
204
205 if (AR_SREV_9300_20_OR_LATER(ah))
206 max_streams = 3;
207 else
208 max_streams = 2;
209
210 if (AR_SREV_9280_10_OR_LATER(ah)) {
211 if (max_streams >= 2)
212 ht_info->cap |= IEEE80211_HT_CAP_TX_STBC;
213 ht_info->cap |= (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT);
214 }
215
216 /* set up supported mcs set */
217 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
218 tx_streams = ath9k_cmn_count_streams(common->tx_chainmask, max_streams);
219 rx_streams = ath9k_cmn_count_streams(common->rx_chainmask, max_streams);
220
221 ath_print(common, ATH_DBG_CONFIG,
222 "TX streams %d, RX streams: %d\n",
223 tx_streams, rx_streams);
224
225 if (tx_streams != rx_streams) {
226 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
227 ht_info->mcs.tx_params |= ((tx_streams - 1) <<
228 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
229 }
230
231 for (i = 0; i < rx_streams; i++)
232 ht_info->mcs.rx_mask[i] = 0xff;
233
234 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED;
235 }
236
237 static int ath9k_reg_notifier(struct wiphy *wiphy,
238 struct regulatory_request *request)
239 {
240 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
241 struct ath_wiphy *aphy = hw->priv;
242 struct ath_softc *sc = aphy->sc;
243 struct ath_regulatory *reg = ath9k_hw_regulatory(sc->sc_ah);
244
245 return ath_reg_notifier_apply(wiphy, request, reg);
246 }
247
248 /*
249 * This function will allocate both the DMA descriptor structure, and the
250 * buffers it contains. These are used to contain the descriptors used
251 * by the system.
252 */
253 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
254 struct list_head *head, const char *name,
255 int nbuf, int ndesc, bool is_tx)
256 {
257 #define DS2PHYS(_dd, _ds) \
258 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
259 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
260 #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
261 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
262 u8 *ds;
263 struct ath_buf *bf;
264 int i, bsize, error, desc_len;
265
266 ath_print(common, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
267 name, nbuf, ndesc);
268
269 INIT_LIST_HEAD(head);
270
271 if (is_tx)
272 desc_len = sc->sc_ah->caps.tx_desc_len;
273 else
274 desc_len = sizeof(struct ath_desc);
275
276 /* ath_desc must be a multiple of DWORDs */
277 if ((desc_len % 4) != 0) {
278 ath_print(common, ATH_DBG_FATAL,
279 "ath_desc not DWORD aligned\n");
280 BUG_ON((desc_len % 4) != 0);
281 error = -ENOMEM;
282 goto fail;
283 }
284
285 dd->dd_desc_len = desc_len * nbuf * ndesc;
286
287 /*
288 * Need additional DMA memory because we can't use
289 * descriptors that cross the 4K page boundary. Assume
290 * one skipped descriptor per 4K page.
291 */
292 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
293 u32 ndesc_skipped =
294 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
295 u32 dma_len;
296
297 while (ndesc_skipped) {
298 dma_len = ndesc_skipped * desc_len;
299 dd->dd_desc_len += dma_len;
300
301 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
302 }
303 }
304
305 /* allocate descriptors */
306 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
307 &dd->dd_desc_paddr, GFP_KERNEL);
308 if (dd->dd_desc == NULL) {
309 error = -ENOMEM;
310 goto fail;
311 }
312 ds = (u8 *) dd->dd_desc;
313 ath_print(common, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
314 name, ds, (u32) dd->dd_desc_len,
315 ito64(dd->dd_desc_paddr),(u32) dd->dd_desc_len);
316
317 /* allocate buffers */
318 bsize = sizeof(struct ath_buf) * nbuf;
319 bf = kzalloc(bsize, GFP_KERNEL);
320 if (bf == NULL) {
321 error = -ENOMEM;
322 goto fail2;
323 }
324 dd->dd_bufptr = bf;
325
326 for (i = 0; i < nbuf; i++, bf++, ds += (desc_len * ndesc)) {
327 bf->bf_desc = ds;
328 bf->bf_daddr = DS2PHYS(dd, ds);
329
330 if (!(sc->sc_ah->caps.hw_caps &
331 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
332 /*
333 * Skip descriptor addresses which can cause 4KB
334 * boundary crossing (addr + length) with a 32 dword
335 * descriptor fetch.
336 */
337 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
338 BUG_ON((caddr_t) bf->bf_desc >=
339 ((caddr_t) dd->dd_desc +
340 dd->dd_desc_len));
341
342 ds += (desc_len * ndesc);
343 bf->bf_desc = ds;
344 bf->bf_daddr = DS2PHYS(dd, ds);
345 }
346 }
347 list_add_tail(&bf->list, head);
348 }
349 return 0;
350 fail2:
351 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
352 dd->dd_desc_paddr);
353 fail:
354 memset(dd, 0, sizeof(*dd));
355 return error;
356 #undef ATH_DESC_4KB_BOUND_CHECK
357 #undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
358 #undef DS2PHYS
359 }
360
361 static void ath9k_init_crypto(struct ath_softc *sc)
362 {
363 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
364 int i = 0;
365
366 /* Get the hardware key cache size. */
367 common->keymax = sc->sc_ah->caps.keycache_size;
368 if (common->keymax > ATH_KEYMAX) {
369 ath_print(common, ATH_DBG_ANY,
370 "Warning, using only %u entries in %u key cache\n",
371 ATH_KEYMAX, common->keymax);
372 common->keymax = ATH_KEYMAX;
373 }
374
375 /*
376 * Reset the key cache since some parts do not
377 * reset the contents on initial power up.
378 */
379 for (i = 0; i < common->keymax; i++)
380 ath9k_hw_keyreset(sc->sc_ah, (u16) i);
381
382 /*
383 * Check whether the separate key cache entries
384 * are required to handle both tx+rx MIC keys.
385 * With split mic keys the number of stations is limited
386 * to 27 otherwise 59.
387 */
388 if (!(sc->sc_ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA))
389 common->splitmic = 1;
390 }
391
392 static int ath9k_init_btcoex(struct ath_softc *sc)
393 {
394 int r, qnum;
395
396 switch (sc->sc_ah->btcoex_hw.scheme) {
397 case ATH_BTCOEX_CFG_NONE:
398 break;
399 case ATH_BTCOEX_CFG_2WIRE:
400 ath9k_hw_btcoex_init_2wire(sc->sc_ah);
401 break;
402 case ATH_BTCOEX_CFG_3WIRE:
403 ath9k_hw_btcoex_init_3wire(sc->sc_ah);
404 r = ath_init_btcoex_timer(sc);
405 if (r)
406 return -1;
407 qnum = sc->tx.hwq_map[WME_AC_BE];
408 ath9k_hw_init_btcoex_hw(sc->sc_ah, qnum);
409 sc->btcoex.bt_stomp_type = ATH_BTCOEX_STOMP_LOW;
410 break;
411 default:
412 WARN_ON(1);
413 break;
414 }
415
416 return 0;
417 }
418
419 static int ath9k_init_queues(struct ath_softc *sc)
420 {
421 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
422 int i = 0;
423
424 for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
425 sc->tx.hwq_map[i] = -1;
426
427 sc->beacon.beaconq = ath9k_hw_beaconq_setup(sc->sc_ah);
428 if (sc->beacon.beaconq == -1) {
429 ath_print(common, ATH_DBG_FATAL,
430 "Unable to setup a beacon xmit queue\n");
431 goto err;
432 }
433
434 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
435 if (sc->beacon.cabq == NULL) {
436 ath_print(common, ATH_DBG_FATAL,
437 "Unable to setup CAB xmit queue\n");
438 goto err;
439 }
440
441 sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
442 ath_cabq_update(sc);
443
444 if (!ath_tx_setup(sc, WME_AC_BK)) {
445 ath_print(common, ATH_DBG_FATAL,
446 "Unable to setup xmit queue for BK traffic\n");
447 goto err;
448 }
449
450 if (!ath_tx_setup(sc, WME_AC_BE)) {
451 ath_print(common, ATH_DBG_FATAL,
452 "Unable to setup xmit queue for BE traffic\n");
453 goto err;
454 }
455 if (!ath_tx_setup(sc, WME_AC_VI)) {
456 ath_print(common, ATH_DBG_FATAL,
457 "Unable to setup xmit queue for VI traffic\n");
458 goto err;
459 }
460 if (!ath_tx_setup(sc, WME_AC_VO)) {
461 ath_print(common, ATH_DBG_FATAL,
462 "Unable to setup xmit queue for VO traffic\n");
463 goto err;
464 }
465
466 return 0;
467
468 err:
469 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
470 if (ATH_TXQ_SETUP(sc, i))
471 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
472
473 return -EIO;
474 }
475
476 static int ath9k_init_channels_rates(struct ath_softc *sc)
477 {
478 void *channels;
479
480 if (test_bit(ATH9K_MODE_11G, sc->sc_ah->caps.wireless_modes)) {
481 channels = kmemdup(ath9k_2ghz_chantable,
482 sizeof(ath9k_2ghz_chantable), GFP_KERNEL);
483 if (!channels)
484 return -ENOMEM;
485
486 sc->sbands[IEEE80211_BAND_2GHZ].channels = channels;
487 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
488 sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
489 ARRAY_SIZE(ath9k_2ghz_chantable);
490 sc->sbands[IEEE80211_BAND_2GHZ].bitrates = ath9k_legacy_rates;
491 sc->sbands[IEEE80211_BAND_2GHZ].n_bitrates =
492 ARRAY_SIZE(ath9k_legacy_rates);
493 }
494
495 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) {
496 channels = kmemdup(ath9k_5ghz_chantable,
497 sizeof(ath9k_5ghz_chantable), GFP_KERNEL);
498 if (!channels) {
499 if (sc->sbands[IEEE80211_BAND_2GHZ].channels)
500 kfree(sc->sbands[IEEE80211_BAND_2GHZ].channels);
501 return -ENOMEM;
502 }
503
504 sc->sbands[IEEE80211_BAND_5GHZ].channels = channels;
505 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
506 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
507 ARRAY_SIZE(ath9k_5ghz_chantable);
508 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
509 ath9k_legacy_rates + 4;
510 sc->sbands[IEEE80211_BAND_5GHZ].n_bitrates =
511 ARRAY_SIZE(ath9k_legacy_rates) - 4;
512 }
513 return 0;
514 }
515
516 static void ath9k_init_misc(struct ath_softc *sc)
517 {
518 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
519 int i = 0;
520
521 common->ani.noise_floor = ATH_DEFAULT_NOISE_FLOOR;
522 setup_timer(&common->ani.timer, ath_ani_calibrate, (unsigned long)sc);
523
524 sc->config.txpowlimit = ATH_TXPOWER_MAX;
525
526 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
527 sc->sc_flags |= SC_OP_TXAGGR;
528 sc->sc_flags |= SC_OP_RXAGGR;
529 }
530
531 common->tx_chainmask = sc->sc_ah->caps.tx_chainmask;
532 common->rx_chainmask = sc->sc_ah->caps.rx_chainmask;
533
534 ath9k_hw_set_diversity(sc->sc_ah, true);
535 sc->rx.defant = ath9k_hw_getdefantenna(sc->sc_ah);
536
537 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
538 memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN);
539
540 sc->beacon.slottime = ATH9K_SLOT_TIME_9;
541
542 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
543 sc->beacon.bslot[i] = NULL;
544 sc->beacon.bslot_aphy[i] = NULL;
545 }
546 }
547
548 static int ath9k_init_softc(u16 devid, struct ath_softc *sc, u16 subsysid,
549 const struct ath_bus_ops *bus_ops)
550 {
551 struct ath_hw *ah = NULL;
552 struct ath_common *common;
553 int ret = 0, i;
554 int csz = 0;
555
556 ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL);
557 if (!ah)
558 return -ENOMEM;
559
560 ah->hw_version.devid = devid;
561 ah->hw_version.subsysid = subsysid;
562 sc->sc_ah = ah;
563
564 common = ath9k_hw_common(ah);
565 common->ops = &ath9k_common_ops;
566 common->bus_ops = bus_ops;
567 common->ah = ah;
568 common->hw = sc->hw;
569 common->priv = sc;
570 common->debug_mask = ath9k_debug;
571
572 spin_lock_init(&sc->wiphy_lock);
573 spin_lock_init(&sc->sc_serial_rw);
574 spin_lock_init(&sc->sc_pm_lock);
575 mutex_init(&sc->mutex);
576 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
577 tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet,
578 (unsigned long)sc);
579
580 /*
581 * Cache line size is used to size and align various
582 * structures used to communicate with the hardware.
583 */
584 ath_read_cachesize(common, &csz);
585 common->cachelsz = csz << 2; /* convert to bytes */
586
587 /* Initializes the hardware for all supported chipsets */
588 ret = ath9k_hw_init(ah);
589 if (ret)
590 goto err_hw;
591
592 ret = ath9k_init_debug(ah);
593 if (ret) {
594 ath_print(common, ATH_DBG_FATAL,
595 "Unable to create debugfs files\n");
596 goto err_debug;
597 }
598
599 ret = ath9k_init_queues(sc);
600 if (ret)
601 goto err_queues;
602
603 ret = ath9k_init_btcoex(sc);
604 if (ret)
605 goto err_btcoex;
606
607 ret = ath9k_init_channels_rates(sc);
608 if (ret)
609 goto err_btcoex;
610
611 ath9k_init_crypto(sc);
612 ath9k_init_misc(sc);
613
614 return 0;
615
616 err_btcoex:
617 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
618 if (ATH_TXQ_SETUP(sc, i))
619 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
620 err_queues:
621 ath9k_exit_debug(ah);
622 err_debug:
623 ath9k_hw_deinit(ah);
624 err_hw:
625 tasklet_kill(&sc->intr_tq);
626 tasklet_kill(&sc->bcon_tasklet);
627
628 kfree(ah);
629 sc->sc_ah = NULL;
630
631 return ret;
632 }
633
634 void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
635 {
636 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
637
638 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
639 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
640 IEEE80211_HW_SIGNAL_DBM |
641 IEEE80211_HW_SUPPORTS_PS |
642 IEEE80211_HW_PS_NULLFUNC_STACK |
643 IEEE80211_HW_SPECTRUM_MGMT |
644 IEEE80211_HW_REPORTS_TX_ACK_STATUS;
645
646 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
647 hw->flags |= IEEE80211_HW_AMPDU_AGGREGATION;
648
649 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || modparam_nohwcrypt)
650 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
651
652 hw->wiphy->interface_modes =
653 BIT(NL80211_IFTYPE_AP) |
654 BIT(NL80211_IFTYPE_STATION) |
655 BIT(NL80211_IFTYPE_ADHOC) |
656 BIT(NL80211_IFTYPE_MESH_POINT);
657
658 if (AR_SREV_5416(sc->sc_ah))
659 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
660
661 hw->queues = 4;
662 hw->max_rates = 4;
663 hw->channel_change_time = 5000;
664 hw->max_listen_interval = 10;
665 hw->max_rate_tries = 10;
666 hw->sta_data_size = sizeof(struct ath_node);
667 hw->vif_data_size = sizeof(struct ath_vif);
668
669 hw->rate_control_algorithm = "ath9k_rate_control";
670
671 if (test_bit(ATH9K_MODE_11G, sc->sc_ah->caps.wireless_modes))
672 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
673 &sc->sbands[IEEE80211_BAND_2GHZ];
674 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
675 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
676 &sc->sbands[IEEE80211_BAND_5GHZ];
677
678 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
679 if (test_bit(ATH9K_MODE_11G, sc->sc_ah->caps.wireless_modes))
680 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
681 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
682 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
683 }
684
685 SET_IEEE80211_PERM_ADDR(hw, common->macaddr);
686 }
687
688 int ath9k_init_device(u16 devid, struct ath_softc *sc, u16 subsysid,
689 const struct ath_bus_ops *bus_ops)
690 {
691 struct ieee80211_hw *hw = sc->hw;
692 struct ath_common *common;
693 struct ath_hw *ah;
694 int error = 0;
695 struct ath_regulatory *reg;
696
697 /* Bring up device */
698 error = ath9k_init_softc(devid, sc, subsysid, bus_ops);
699 if (error != 0)
700 goto error_init;
701
702 ah = sc->sc_ah;
703 common = ath9k_hw_common(ah);
704 ath9k_set_hw_capab(sc, hw);
705
706 /* Initialize regulatory */
707 error = ath_regd_init(&common->regulatory, sc->hw->wiphy,
708 ath9k_reg_notifier);
709 if (error)
710 goto error_regd;
711
712 reg = &common->regulatory;
713
714 /* Setup TX DMA */
715 error = ath_tx_init(sc, ATH_TXBUF);
716 if (error != 0)
717 goto error_tx;
718
719 /* Setup RX DMA */
720 error = ath_rx_init(sc, ATH_RXBUF);
721 if (error != 0)
722 goto error_rx;
723
724 /* Register with mac80211 */
725 error = ieee80211_register_hw(hw);
726 if (error)
727 goto error_register;
728
729 /* Handle world regulatory */
730 if (!ath_is_world_regd(reg)) {
731 error = regulatory_hint(hw->wiphy, reg->alpha2);
732 if (error)
733 goto error_world;
734 }
735
736 INIT_WORK(&sc->hw_check_work, ath_hw_check);
737 INIT_WORK(&sc->paprd_work, ath_paprd_calibrate);
738 INIT_WORK(&sc->chan_work, ath9k_wiphy_chan_work);
739 INIT_DELAYED_WORK(&sc->wiphy_work, ath9k_wiphy_work);
740 sc->wiphy_scheduler_int = msecs_to_jiffies(500);
741
742 ath_init_leds(sc);
743 ath_start_rfkill_poll(sc);
744
745 return 0;
746
747 error_world:
748 ieee80211_unregister_hw(hw);
749 error_register:
750 ath_rx_cleanup(sc);
751 error_rx:
752 ath_tx_cleanup(sc);
753 error_tx:
754 /* Nothing */
755 error_regd:
756 ath9k_deinit_softc(sc);
757 error_init:
758 return error;
759 }
760
761 /*****************************/
762 /* De-Initialization */
763 /*****************************/
764
765 static void ath9k_deinit_softc(struct ath_softc *sc)
766 {
767 int i = 0;
768
769 if (sc->sbands[IEEE80211_BAND_2GHZ].channels)
770 kfree(sc->sbands[IEEE80211_BAND_2GHZ].channels);
771
772 if (sc->sbands[IEEE80211_BAND_5GHZ].channels)
773 kfree(sc->sbands[IEEE80211_BAND_5GHZ].channels);
774
775 if ((sc->btcoex.no_stomp_timer) &&
776 sc->sc_ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
777 ath_gen_timer_free(sc->sc_ah, sc->btcoex.no_stomp_timer);
778
779 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
780 if (ATH_TXQ_SETUP(sc, i))
781 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
782
783 ath9k_exit_debug(sc->sc_ah);
784 ath9k_hw_deinit(sc->sc_ah);
785
786 tasklet_kill(&sc->intr_tq);
787 tasklet_kill(&sc->bcon_tasklet);
788
789 kfree(sc->sc_ah);
790 sc->sc_ah = NULL;
791 }
792
793 void ath9k_deinit_device(struct ath_softc *sc)
794 {
795 struct ieee80211_hw *hw = sc->hw;
796 int i = 0;
797
798 ath9k_ps_wakeup(sc);
799
800 wiphy_rfkill_stop_polling(sc->hw->wiphy);
801 ath_deinit_leds(sc);
802
803 for (i = 0; i < sc->num_sec_wiphy; i++) {
804 struct ath_wiphy *aphy = sc->sec_wiphy[i];
805 if (aphy == NULL)
806 continue;
807 sc->sec_wiphy[i] = NULL;
808 ieee80211_unregister_hw(aphy->hw);
809 ieee80211_free_hw(aphy->hw);
810 }
811
812 ieee80211_unregister_hw(hw);
813 ath_rx_cleanup(sc);
814 ath_tx_cleanup(sc);
815 ath9k_deinit_softc(sc);
816 kfree(sc->sec_wiphy);
817 }
818
819 void ath_descdma_cleanup(struct ath_softc *sc,
820 struct ath_descdma *dd,
821 struct list_head *head)
822 {
823 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
824 dd->dd_desc_paddr);
825
826 INIT_LIST_HEAD(head);
827 kfree(dd->dd_bufptr);
828 memset(dd, 0, sizeof(*dd));
829 }
830
831 /************************/
832 /* Module Hooks */
833 /************************/
834
835 static int __init ath9k_init(void)
836 {
837 int error;
838
839 /* Register rate control algorithm */
840 error = ath_rate_control_register();
841 if (error != 0) {
842 printk(KERN_ERR
843 "ath9k: Unable to register rate control "
844 "algorithm: %d\n",
845 error);
846 goto err_out;
847 }
848
849 error = ath9k_debug_create_root();
850 if (error) {
851 printk(KERN_ERR
852 "ath9k: Unable to create debugfs root: %d\n",
853 error);
854 goto err_rate_unregister;
855 }
856
857 error = ath_pci_init();
858 if (error < 0) {
859 printk(KERN_ERR
860 "ath9k: No PCI devices found, driver not installed.\n");
861 error = -ENODEV;
862 goto err_remove_root;
863 }
864
865 error = ath_ahb_init();
866 if (error < 0) {
867 error = -ENODEV;
868 goto err_pci_exit;
869 }
870
871 return 0;
872
873 err_pci_exit:
874 ath_pci_exit();
875
876 err_remove_root:
877 ath9k_debug_remove_root();
878 err_rate_unregister:
879 ath_rate_control_unregister();
880 err_out:
881 return error;
882 }
883 module_init(ath9k_init);
884
885 static void __exit ath9k_exit(void)
886 {
887 ath_ahb_exit();
888 ath_pci_exit();
889 ath9k_debug_remove_root();
890 ath_rate_control_unregister();
891 printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
892 }
893 module_exit(ath9k_exit);
Tomato firmware and modifications.