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GUI: Fix Tomato RAF theme for all builds. Compilation typo.
[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / drivers / net / wireless / ath / ar9170 / phy.c
bloba50f82c3fe2fe34327801429245caa8445b52680
1 /*
2 * Atheros AR9170 driver
3 *
4 * PHY and RF code
5 *
6 * Copyright 2008, Johannes Berg <johannes@sipsolutions.net>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; see the file COPYING. If not, see
20 * http://www.gnu.org/licenses/.
21 *
22 * This file incorporates work covered by the following copyright and
23 * permission notice:
24 * Copyright (c) 2007-2008 Atheros Communications, Inc.
25 *
26 * Permission to use, copy, modify, and/or distribute this software for any
27 * purpose with or without fee is hereby granted, provided that the above
28 * copyright notice and this permission notice appear in all copies.
29 *
30 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
31 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
32 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
33 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
34 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
35 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
36 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
37 */
38
39 #include <linux/bitrev.h>
40 #include "ar9170.h"
41 #include "cmd.h"
42
43 static int ar9170_init_power_cal(struct ar9170 *ar)
44 {
45 ar9170_regwrite_begin(ar);
46
47 ar9170_regwrite(0x1bc000 + 0x993c, 0x7f);
48 ar9170_regwrite(0x1bc000 + 0x9934, 0x3f3f3f3f);
49 ar9170_regwrite(0x1bc000 + 0x9938, 0x3f3f3f3f);
50 ar9170_regwrite(0x1bc000 + 0xa234, 0x3f3f3f3f);
51 ar9170_regwrite(0x1bc000 + 0xa238, 0x3f3f3f3f);
52 ar9170_regwrite(0x1bc000 + 0xa38c, 0x3f3f3f3f);
53 ar9170_regwrite(0x1bc000 + 0xa390, 0x3f3f3f3f);
54 ar9170_regwrite(0x1bc000 + 0xa3cc, 0x3f3f3f3f);
55 ar9170_regwrite(0x1bc000 + 0xa3d0, 0x3f3f3f3f);
56 ar9170_regwrite(0x1bc000 + 0xa3d4, 0x3f3f3f3f);
57
58 ar9170_regwrite_finish();
59 return ar9170_regwrite_result();
60 }
61
62 struct ar9170_phy_init {
63 u32 reg, _5ghz_20, _5ghz_40, _2ghz_40, _2ghz_20;
64 };
65
66 static struct ar9170_phy_init ar5416_phy_init[] = {
67 { 0x1c5800, 0x00000007, 0x00000007, 0x00000007, 0x00000007, },
68 { 0x1c5804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, },
69 { 0x1c5808, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
70 { 0x1c580c, 0xad848e19, 0xad848e19, 0xad848e19, 0xad848e19, },
71 { 0x1c5810, 0x7d14e000, 0x7d14e000, 0x7d14e000, 0x7d14e000, },
72 { 0x1c5814, 0x9c0a9f6b, 0x9c0a9f6b, 0x9c0a9f6b, 0x9c0a9f6b, },
73 { 0x1c5818, 0x00000090, 0x00000090, 0x00000090, 0x00000090, },
74 { 0x1c581c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
75 { 0x1c5820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, },
76 { 0x1c5824, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, },
77 { 0x1c5828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, },
78 { 0x1c582c, 0x0000a000, 0x0000a000, 0x0000a000, 0x0000a000, },
79 { 0x1c5830, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
80 { 0x1c5834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, },
81 { 0x1c5838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, },
82 { 0x1c583c, 0x00200400, 0x00200400, 0x00200400, 0x00200400, },
83 { 0x1c5840, 0x206a002e, 0x206a002e, 0x206a002e, 0x206a002e, },
84 { 0x1c5844, 0x1372161e, 0x13721c1e, 0x13721c24, 0x137216a4, },
85 { 0x1c5848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, },
86 { 0x1c584c, 0x1284233c, 0x1284233c, 0x1284233c, 0x1284233c, },
87 { 0x1c5850, 0x6c48b4e4, 0x6c48b4e4, 0x6c48b0e4, 0x6c48b0e4, },
88 { 0x1c5854, 0x00000859, 0x00000859, 0x00000859, 0x00000859, },
89 { 0x1c5858, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e, },
90 { 0x1c585c, 0x31395c5e, 0x31395c5e, 0x31395c5e, 0x31395c5e, },
91 { 0x1c5860, 0x0004dd10, 0x0004dd10, 0x0004dd20, 0x0004dd20, },
92 { 0x1c5868, 0x409a4190, 0x409a4190, 0x409a4190, 0x409a4190, },
93 { 0x1c586c, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, },
94 { 0x1c5900, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
95 { 0x1c5904, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
96 { 0x1c5908, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
97 { 0x1c590c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
98 { 0x1c5914, 0x000007d0, 0x000007d0, 0x00000898, 0x00000898, },
99 { 0x1c5918, 0x00000118, 0x00000230, 0x00000268, 0x00000134, },
100 { 0x1c591c, 0x10000fff, 0x10000fff, 0x10000fff, 0x10000fff, },
101 { 0x1c5920, 0x0510081c, 0x0510081c, 0x0510001c, 0x0510001c, },
102 { 0x1c5924, 0xd0058a15, 0xd0058a15, 0xd0058a15, 0xd0058a15, },
103 { 0x1c5928, 0x00000001, 0x00000001, 0x00000001, 0x00000001, },
104 { 0x1c592c, 0x00000004, 0x00000004, 0x00000004, 0x00000004, },
105 { 0x1c5934, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, },
106 { 0x1c5938, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, },
107 { 0x1c593c, 0x0000007f, 0x0000007f, 0x0000007f, 0x0000007f, },
108 { 0x1c5944, 0xdfb81020, 0xdfb81020, 0xdfb81020, 0xdfb81020, },
109 { 0x1c5948, 0x9280b212, 0x9280b212, 0x9280b212, 0x9280b212, },
110 { 0x1c594c, 0x00020028, 0x00020028, 0x00020028, 0x00020028, },
111 { 0x1c5954, 0x5d50e188, 0x5d50e188, 0x5d50e188, 0x5d50e188, },
112 { 0x1c5958, 0x00081fff, 0x00081fff, 0x00081fff, 0x00081fff, },
113 { 0x1c5960, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40, },
114 { 0x1c5964, 0x00001120, 0x00001120, 0x00001120, 0x00001120, },
115 { 0x1c5970, 0x190fb515, 0x190fb515, 0x190fb515, 0x190fb515, },
116 { 0x1c5974, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
117 { 0x1c5978, 0x00000001, 0x00000001, 0x00000001, 0x00000001, },
118 { 0x1c597c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
119 { 0x1c5980, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
120 { 0x1c5984, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
121 { 0x1c5988, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
122 { 0x1c598c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
123 { 0x1c5990, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
124 { 0x1c5994, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
125 { 0x1c5998, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
126 { 0x1c599c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
127 { 0x1c59a0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
128 { 0x1c59a4, 0x00000007, 0x00000007, 0x00000007, 0x00000007, },
129 { 0x1c59a8, 0x001fff00, 0x001fff00, 0x001fff00, 0x001fff00, },
130 { 0x1c59ac, 0x006f00c4, 0x006f00c4, 0x006f00c4, 0x006f00c4, },
131 { 0x1c59b0, 0x03051000, 0x03051000, 0x03051000, 0x03051000, },
132 { 0x1c59b4, 0x00000820, 0x00000820, 0x00000820, 0x00000820, },
133 { 0x1c59c0, 0x038919be, 0x038919be, 0x038919be, 0x038919be, },
134 { 0x1c59c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, },
135 { 0x1c59c8, 0x60f6532c, 0x60f6532c, 0x60f6532c, 0x60f6532c, },
136 { 0x1c59cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, },
137 { 0x1c59d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, },
138 { 0x1c59d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
139 { 0x1c59d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
140 { 0x1c59dc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
141 { 0x1c59e0, 0x00000200, 0x00000200, 0x00000200, 0x00000200, },
142 { 0x1c59e4, 0x64646464, 0x64646464, 0x64646464, 0x64646464, },
143 { 0x1c59e8, 0x3c787878, 0x3c787878, 0x3c787878, 0x3c787878, },
144 { 0x1c59ec, 0x000000aa, 0x000000aa, 0x000000aa, 0x000000aa, },
145 { 0x1c59f0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
146 { 0x1c59fc, 0x00001042, 0x00001042, 0x00001042, 0x00001042, },
147 { 0x1c5a00, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
148 { 0x1c5a04, 0x00000040, 0x00000040, 0x00000040, 0x00000040, },
149 { 0x1c5a08, 0x00000080, 0x00000080, 0x00000080, 0x00000080, },
150 { 0x1c5a0c, 0x000001a1, 0x000001a1, 0x00000141, 0x00000141, },
151 { 0x1c5a10, 0x000001e1, 0x000001e1, 0x00000181, 0x00000181, },
152 { 0x1c5a14, 0x00000021, 0x00000021, 0x000001c1, 0x000001c1, },
153 { 0x1c5a18, 0x00000061, 0x00000061, 0x00000001, 0x00000001, },
154 { 0x1c5a1c, 0x00000168, 0x00000168, 0x00000041, 0x00000041, },
155 { 0x1c5a20, 0x000001a8, 0x000001a8, 0x000001a8, 0x000001a8, },
156 { 0x1c5a24, 0x000001e8, 0x000001e8, 0x000001e8, 0x000001e8, },
157 { 0x1c5a28, 0x00000028, 0x00000028, 0x00000028, 0x00000028, },
158 { 0x1c5a2c, 0x00000068, 0x00000068, 0x00000068, 0x00000068, },
159 { 0x1c5a30, 0x00000189, 0x00000189, 0x000000a8, 0x000000a8, },
160 { 0x1c5a34, 0x000001c9, 0x000001c9, 0x00000169, 0x00000169, },
161 { 0x1c5a38, 0x00000009, 0x00000009, 0x000001a9, 0x000001a9, },
162 { 0x1c5a3c, 0x00000049, 0x00000049, 0x000001e9, 0x000001e9, },
163 { 0x1c5a40, 0x00000089, 0x00000089, 0x00000029, 0x00000029, },
164 { 0x1c5a44, 0x00000170, 0x00000170, 0x00000069, 0x00000069, },
165 { 0x1c5a48, 0x000001b0, 0x000001b0, 0x00000190, 0x00000190, },
166 { 0x1c5a4c, 0x000001f0, 0x000001f0, 0x000001d0, 0x000001d0, },
167 { 0x1c5a50, 0x00000030, 0x00000030, 0x00000010, 0x00000010, },
168 { 0x1c5a54, 0x00000070, 0x00000070, 0x00000050, 0x00000050, },
169 { 0x1c5a58, 0x00000191, 0x00000191, 0x00000090, 0x00000090, },
170 { 0x1c5a5c, 0x000001d1, 0x000001d1, 0x00000151, 0x00000151, },
171 { 0x1c5a60, 0x00000011, 0x00000011, 0x00000191, 0x00000191, },
172 { 0x1c5a64, 0x00000051, 0x00000051, 0x000001d1, 0x000001d1, },
173 { 0x1c5a68, 0x00000091, 0x00000091, 0x00000011, 0x00000011, },
174 { 0x1c5a6c, 0x000001b8, 0x000001b8, 0x00000051, 0x00000051, },
175 { 0x1c5a70, 0x000001f8, 0x000001f8, 0x00000198, 0x00000198, },
176 { 0x1c5a74, 0x00000038, 0x00000038, 0x000001d8, 0x000001d8, },
177 { 0x1c5a78, 0x00000078, 0x00000078, 0x00000018, 0x00000018, },
178 { 0x1c5a7c, 0x00000199, 0x00000199, 0x00000058, 0x00000058, },
179 { 0x1c5a80, 0x000001d9, 0x000001d9, 0x00000098, 0x00000098, },
180 { 0x1c5a84, 0x00000019, 0x00000019, 0x00000159, 0x00000159, },
181 { 0x1c5a88, 0x00000059, 0x00000059, 0x00000199, 0x00000199, },
182 { 0x1c5a8c, 0x00000099, 0x00000099, 0x000001d9, 0x000001d9, },
183 { 0x1c5a90, 0x000000d9, 0x000000d9, 0x00000019, 0x00000019, },
184 { 0x1c5a94, 0x000000f9, 0x000000f9, 0x00000059, 0x00000059, },
185 { 0x1c5a98, 0x000000f9, 0x000000f9, 0x00000099, 0x00000099, },
186 { 0x1c5a9c, 0x000000f9, 0x000000f9, 0x000000d9, 0x000000d9, },
187 { 0x1c5aa0, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, },
188 { 0x1c5aa4, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, },
189 { 0x1c5aa8, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, },
190 { 0x1c5aac, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, },
191 { 0x1c5ab0, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, },
192 { 0x1c5ab4, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, },
193 { 0x1c5ab8, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, },
194 { 0x1c5abc, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, },
195 { 0x1c5ac0, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, },
196 { 0x1c5ac4, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, },
197 { 0x1c5ac8, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, },
198 { 0x1c5acc, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, },
199 { 0x1c5ad0, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, },
200 { 0x1c5ad4, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, },
201 { 0x1c5ad8, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, },
202 { 0x1c5adc, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, },
203 { 0x1c5ae0, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, },
204 { 0x1c5ae4, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, },
205 { 0x1c5ae8, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, },
206 { 0x1c5aec, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, },
207 { 0x1c5af0, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, },
208 { 0x1c5af4, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, },
209 { 0x1c5af8, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, },
210 { 0x1c5afc, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, },
211 { 0x1c5b00, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
212 { 0x1c5b04, 0x00000001, 0x00000001, 0x00000001, 0x00000001, },
213 { 0x1c5b08, 0x00000002, 0x00000002, 0x00000002, 0x00000002, },
214 { 0x1c5b0c, 0x00000003, 0x00000003, 0x00000003, 0x00000003, },
215 { 0x1c5b10, 0x00000004, 0x00000004, 0x00000004, 0x00000004, },
216 { 0x1c5b14, 0x00000005, 0x00000005, 0x00000005, 0x00000005, },
217 { 0x1c5b18, 0x00000008, 0x00000008, 0x00000008, 0x00000008, },
218 { 0x1c5b1c, 0x00000009, 0x00000009, 0x00000009, 0x00000009, },
219 { 0x1c5b20, 0x0000000a, 0x0000000a, 0x0000000a, 0x0000000a, },
220 { 0x1c5b24, 0x0000000b, 0x0000000b, 0x0000000b, 0x0000000b, },
221 { 0x1c5b28, 0x0000000c, 0x0000000c, 0x0000000c, 0x0000000c, },
222 { 0x1c5b2c, 0x0000000d, 0x0000000d, 0x0000000d, 0x0000000d, },
223 { 0x1c5b30, 0x00000010, 0x00000010, 0x00000010, 0x00000010, },
224 { 0x1c5b34, 0x00000011, 0x00000011, 0x00000011, 0x00000011, },
225 { 0x1c5b38, 0x00000012, 0x00000012, 0x00000012, 0x00000012, },
226 { 0x1c5b3c, 0x00000013, 0x00000013, 0x00000013, 0x00000013, },
227 { 0x1c5b40, 0x00000014, 0x00000014, 0x00000014, 0x00000014, },
228 { 0x1c5b44, 0x00000015, 0x00000015, 0x00000015, 0x00000015, },
229 { 0x1c5b48, 0x00000018, 0x00000018, 0x00000018, 0x00000018, },
230 { 0x1c5b4c, 0x00000019, 0x00000019, 0x00000019, 0x00000019, },
231 { 0x1c5b50, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a, },
232 { 0x1c5b54, 0x0000001b, 0x0000001b, 0x0000001b, 0x0000001b, },
233 { 0x1c5b58, 0x0000001c, 0x0000001c, 0x0000001c, 0x0000001c, },
234 { 0x1c5b5c, 0x0000001d, 0x0000001d, 0x0000001d, 0x0000001d, },
235 { 0x1c5b60, 0x00000020, 0x00000020, 0x00000020, 0x00000020, },
236 { 0x1c5b64, 0x00000021, 0x00000021, 0x00000021, 0x00000021, },
237 { 0x1c5b68, 0x00000022, 0x00000022, 0x00000022, 0x00000022, },
238 { 0x1c5b6c, 0x00000023, 0x00000023, 0x00000023, 0x00000023, },
239 { 0x1c5b70, 0x00000024, 0x00000024, 0x00000024, 0x00000024, },
240 { 0x1c5b74, 0x00000025, 0x00000025, 0x00000025, 0x00000025, },
241 { 0x1c5b78, 0x00000028, 0x00000028, 0x00000028, 0x00000028, },
242 { 0x1c5b7c, 0x00000029, 0x00000029, 0x00000029, 0x00000029, },
243 { 0x1c5b80, 0x0000002a, 0x0000002a, 0x0000002a, 0x0000002a, },
244 { 0x1c5b84, 0x0000002b, 0x0000002b, 0x0000002b, 0x0000002b, },
245 { 0x1c5b88, 0x0000002c, 0x0000002c, 0x0000002c, 0x0000002c, },
246 { 0x1c5b8c, 0x0000002d, 0x0000002d, 0x0000002d, 0x0000002d, },
247 { 0x1c5b90, 0x00000030, 0x00000030, 0x00000030, 0x00000030, },
248 { 0x1c5b94, 0x00000031, 0x00000031, 0x00000031, 0x00000031, },
249 { 0x1c5b98, 0x00000032, 0x00000032, 0x00000032, 0x00000032, },
250 { 0x1c5b9c, 0x00000033, 0x00000033, 0x00000033, 0x00000033, },
251 { 0x1c5ba0, 0x00000034, 0x00000034, 0x00000034, 0x00000034, },
252 { 0x1c5ba4, 0x00000035, 0x00000035, 0x00000035, 0x00000035, },
253 { 0x1c5ba8, 0x00000035, 0x00000035, 0x00000035, 0x00000035, },
254 { 0x1c5bac, 0x00000035, 0x00000035, 0x00000035, 0x00000035, },
255 { 0x1c5bb0, 0x00000035, 0x00000035, 0x00000035, 0x00000035, },
256 { 0x1c5bb4, 0x00000035, 0x00000035, 0x00000035, 0x00000035, },
257 { 0x1c5bb8, 0x00000035, 0x00000035, 0x00000035, 0x00000035, },
258 { 0x1c5bbc, 0x00000035, 0x00000035, 0x00000035, 0x00000035, },
259 { 0x1c5bc0, 0x00000035, 0x00000035, 0x00000035, 0x00000035, },
260 { 0x1c5bc4, 0x00000035, 0x00000035, 0x00000035, 0x00000035, },
261 { 0x1c5bc8, 0x00000035, 0x00000035, 0x00000035, 0x00000035, },
262 { 0x1c5bcc, 0x00000035, 0x00000035, 0x00000035, 0x00000035, },
263 { 0x1c5bd0, 0x00000035, 0x00000035, 0x00000035, 0x00000035, },
264 { 0x1c5bd4, 0x00000035, 0x00000035, 0x00000035, 0x00000035, },
265 { 0x1c5bd8, 0x00000035, 0x00000035, 0x00000035, 0x00000035, },
266 { 0x1c5bdc, 0x00000035, 0x00000035, 0x00000035, 0x00000035, },
267 { 0x1c5be0, 0x00000035, 0x00000035, 0x00000035, 0x00000035, },
268 { 0x1c5be4, 0x00000035, 0x00000035, 0x00000035, 0x00000035, },
269 { 0x1c5be8, 0x00000035, 0x00000035, 0x00000035, 0x00000035, },
270 { 0x1c5bec, 0x00000035, 0x00000035, 0x00000035, 0x00000035, },
271 { 0x1c5bf0, 0x00000035, 0x00000035, 0x00000035, 0x00000035, },
272 { 0x1c5bf4, 0x00000035, 0x00000035, 0x00000035, 0x00000035, },
273 { 0x1c5bf8, 0x00000010, 0x00000010, 0x00000010, 0x00000010, },
274 { 0x1c5bfc, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a, },
275 { 0x1c5c00, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
276 { 0x1c5c0c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
277 { 0x1c5c10, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
278 { 0x1c5c14, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
279 { 0x1c5c18, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
280 { 0x1c5c1c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
281 { 0x1c5c20, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
282 { 0x1c5c24, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
283 { 0x1c5c28, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
284 { 0x1c5c2c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
285 { 0x1c5c30, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
286 { 0x1c5c34, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
287 { 0x1c5c38, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
288 { 0x1c5c3c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
289 { 0x1c5cf0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
290 { 0x1c5cf4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
291 { 0x1c5cf8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
292 { 0x1c5cfc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
293 { 0x1c6200, 0x00000008, 0x00000008, 0x0000000e, 0x0000000e, },
294 { 0x1c6204, 0x00000440, 0x00000440, 0x00000440, 0x00000440, },
295 { 0x1c6208, 0xd6be4788, 0xd6be4788, 0xd03e4788, 0xd03e4788, },
296 { 0x1c620c, 0x012e8160, 0x012e8160, 0x012a8160, 0x012a8160, },
297 { 0x1c6210, 0x40806333, 0x40806333, 0x40806333, 0x40806333, },
298 { 0x1c6214, 0x00106c10, 0x00106c10, 0x00106c10, 0x00106c10, },
299 { 0x1c6218, 0x009c4060, 0x009c4060, 0x009c4060, 0x009c4060, },
300 { 0x1c621c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a, },
301 { 0x1c6220, 0x018830c6, 0x018830c6, 0x018830c6, 0x018830c6, },
302 { 0x1c6224, 0x00000400, 0x00000400, 0x00000400, 0x00000400, },
303 { 0x1c6228, 0x000009b5, 0x000009b5, 0x000009b5, 0x000009b5, },
304 { 0x1c622c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
305 { 0x1c6230, 0x00000108, 0x00000210, 0x00000210, 0x00000108, },
306 { 0x1c6234, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, },
307 { 0x1c6238, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, },
308 { 0x1c623c, 0x13c889af, 0x13c889af, 0x13c889af, 0x13c889af, },
309 { 0x1c6240, 0x38490a20, 0x38490a20, 0x38490a20, 0x38490a20, },
310 { 0x1c6244, 0x00007bb6, 0x00007bb6, 0x00007bb6, 0x00007bb6, },
311 { 0x1c6248, 0x0fff3ffc, 0x0fff3ffc, 0x0fff3ffc, 0x0fff3ffc, },
312 { 0x1c624c, 0x00000001, 0x00000001, 0x00000001, 0x00000001, },
313 { 0x1c6250, 0x0000a000, 0x0000a000, 0x0000a000, 0x0000a000, },
314 { 0x1c6254, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
315 { 0x1c6258, 0x0cc75380, 0x0cc75380, 0x0cc75380, 0x0cc75380, },
316 { 0x1c625c, 0x0f0f0f01, 0x0f0f0f01, 0x0f0f0f01, 0x0f0f0f01, },
317 { 0x1c6260, 0xdfa91f01, 0xdfa91f01, 0xdfa91f01, 0xdfa91f01, },
318 { 0x1c6264, 0x00418a11, 0x00418a11, 0x00418a11, 0x00418a11, },
319 { 0x1c6268, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
320 { 0x1c626c, 0x09249126, 0x09249126, 0x09249126, 0x09249126, },
321 { 0x1c6274, 0x0a1a9caa, 0x0a1a9caa, 0x0a1a7caa, 0x0a1a7caa, },
322 { 0x1c6278, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce, },
323 { 0x1c627c, 0x051701ce, 0x051701ce, 0x051701ce, 0x051701ce, },
324 { 0x1c6300, 0x18010000, 0x18010000, 0x18010000, 0x18010000, },
325 { 0x1c6304, 0x30032602, 0x30032602, 0x2e032402, 0x2e032402, },
326 { 0x1c6308, 0x48073e06, 0x48073e06, 0x4a0a3c06, 0x4a0a3c06, },
327 { 0x1c630c, 0x560b4c0a, 0x560b4c0a, 0x621a540b, 0x621a540b, },
328 { 0x1c6310, 0x641a600f, 0x641a600f, 0x764f6c1b, 0x764f6c1b, },
329 { 0x1c6314, 0x7a4f6e1b, 0x7a4f6e1b, 0x845b7a5a, 0x845b7a5a, },
330 { 0x1c6318, 0x8c5b7e5a, 0x8c5b7e5a, 0x950f8ccf, 0x950f8ccf, },
331 { 0x1c631c, 0x9d0f96cf, 0x9d0f96cf, 0xa5cf9b4f, 0xa5cf9b4f, },
332 { 0x1c6320, 0xb51fa69f, 0xb51fa69f, 0xbddfaf1f, 0xbddfaf1f, },
333 { 0x1c6324, 0xcb3fbd07, 0xcb3fbcbf, 0xd1ffc93f, 0xd1ffc93f, },
334 { 0x1c6328, 0x0000d7bf, 0x0000d7bf, 0x00000000, 0x00000000, },
335 { 0x1c632c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
336 { 0x1c6330, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
337 { 0x1c6334, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
338 { 0x1c6338, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
339 { 0x1c633c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
340 { 0x1c6340, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
341 { 0x1c6344, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
342 { 0x1c6348, 0x3fffffff, 0x3fffffff, 0x3fffffff, 0x3fffffff, },
343 { 0x1c634c, 0x3fffffff, 0x3fffffff, 0x3fffffff, 0x3fffffff, },
344 { 0x1c6350, 0x3fffffff, 0x3fffffff, 0x3fffffff, 0x3fffffff, },
345 { 0x1c6354, 0x0003ffff, 0x0003ffff, 0x0003ffff, 0x0003ffff, },
346 { 0x1c6358, 0x79a8aa1f, 0x79a8aa1f, 0x79a8aa1f, 0x79a8aa1f, },
347 { 0x1c6388, 0x08000000, 0x08000000, 0x08000000, 0x08000000, },
348 { 0x1c638c, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, },
349 { 0x1c6390, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, },
350 { 0x1c6394, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce, },
351 { 0x1c6398, 0x000001ce, 0x000001ce, 0x000001ce, 0x000001ce, },
352 { 0x1c639c, 0x00000007, 0x00000007, 0x00000007, 0x00000007, },
353 { 0x1c63a0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
354 { 0x1c63a4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
355 { 0x1c63a8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
356 { 0x1c63ac, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
357 { 0x1c63b0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
358 { 0x1c63b4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
359 { 0x1c63b8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
360 { 0x1c63bc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
361 { 0x1c63c0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
362 { 0x1c63c4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
363 { 0x1c63c8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
364 { 0x1c63cc, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, },
365 { 0x1c63d0, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, },
366 { 0x1c63d4, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, },
367 { 0x1c63d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
368 { 0x1c63dc, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce, },
369 { 0x1c63e0, 0x000000c0, 0x000000c0, 0x000000c0, 0x000000c0, },
370 { 0x1c6848, 0x00180a65, 0x00180a65, 0x00180a68, 0x00180a68, },
371 { 0x1c6920, 0x0510001c, 0x0510001c, 0x0510001c, 0x0510001c, },
372 { 0x1c6960, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40, },
373 { 0x1c720c, 0x012e8160, 0x012e8160, 0x012a8160, 0x012a8160, },
374 { 0x1c726c, 0x09249126, 0x09249126, 0x09249126, 0x09249126, },
375 { 0x1c7848, 0x00180a65, 0x00180a65, 0x00180a68, 0x00180a68, },
376 { 0x1c7920, 0x0510001c, 0x0510001c, 0x0510001c, 0x0510001c, },
377 { 0x1c7960, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40, },
378 { 0x1c820c, 0x012e8160, 0x012e8160, 0x012a8160, 0x012a8160, },
379 { 0x1c826c, 0x09249126, 0x09249126, 0x09249126, 0x09249126, },
380 /* { 0x1c8864, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00, }, */
381 { 0x1c8864, 0x0001c600, 0x0001c600, 0x0001c600, 0x0001c600, },
382 { 0x1c895c, 0x004b6a8e, 0x004b6a8e, 0x004b6a8e, 0x004b6a8e, },
383 { 0x1c8968, 0x000003ce, 0x000003ce, 0x000003ce, 0x000003ce, },
384 { 0x1c89bc, 0x00181400, 0x00181400, 0x00181400, 0x00181400, },
385 { 0x1c9270, 0x00820820, 0x00820820, 0x00820820, 0x00820820, },
386 { 0x1c935c, 0x066c420f, 0x066c420f, 0x066c420f, 0x066c420f, },
387 { 0x1c9360, 0x0f282207, 0x0f282207, 0x0f282207, 0x0f282207, },
388 { 0x1c9364, 0x17601685, 0x17601685, 0x17601685, 0x17601685, },
389 { 0x1c9368, 0x1f801104, 0x1f801104, 0x1f801104, 0x1f801104, },
390 { 0x1c936c, 0x37a00c03, 0x37a00c03, 0x37a00c03, 0x37a00c03, },
391 { 0x1c9370, 0x3fc40883, 0x3fc40883, 0x3fc40883, 0x3fc40883, },
392 { 0x1c9374, 0x57c00803, 0x57c00803, 0x57c00803, 0x57c00803, },
393 { 0x1c9378, 0x5fd80682, 0x5fd80682, 0x5fd80682, 0x5fd80682, },
394 { 0x1c937c, 0x7fe00482, 0x7fe00482, 0x7fe00482, 0x7fe00482, },
395 { 0x1c9380, 0x7f3c7bba, 0x7f3c7bba, 0x7f3c7bba, 0x7f3c7bba, },
396 { 0x1c9384, 0xf3307ff0, 0xf3307ff0, 0xf3307ff0, 0xf3307ff0, }
397 };
398
399 /*
400 * look up a certain register in ar5416_phy_init[] and return the init. value
401 * for the band and bandwidth given. Return 0 if register address not found.
402 */
403 static u32 ar9170_get_default_phy_reg_val(u32 reg, bool is_2ghz, bool is_40mhz)
404 {
405 unsigned int i;
406 for (i = 0; i < ARRAY_SIZE(ar5416_phy_init); i++) {
407 if (ar5416_phy_init[i].reg != reg)
408 continue;
409
410 if (is_2ghz) {
411 if (is_40mhz)
412 return ar5416_phy_init[i]._2ghz_40;
413 else
414 return ar5416_phy_init[i]._2ghz_20;
415 } else {
416 if (is_40mhz)
417 return ar5416_phy_init[i]._5ghz_40;
418 else
419 return ar5416_phy_init[i]._5ghz_20;
420 }
421 }
422 return 0;
423 }
424
425 /*
426 * initialize some phy regs from eeprom values in modal_header[]
427 * acc. to band and bandwith
428 */
429 static int ar9170_init_phy_from_eeprom(struct ar9170 *ar,
430 bool is_2ghz, bool is_40mhz)
431 {
432 static const u8 xpd2pd[16] = {
433 0x2, 0x2, 0x2, 0x1, 0x2, 0x2, 0x6, 0x2,
434 0x2, 0x3, 0x7, 0x2, 0xB, 0x2, 0x2, 0x2
435 };
436 u32 defval, newval;
437 /* pointer to the modal_header acc. to band */
438 struct ar9170_eeprom_modal *m = &ar->eeprom.modal_header[is_2ghz];
439
440 ar9170_regwrite_begin(ar);
441
442 /* ant common control (index 0) */
443 newval = le32_to_cpu(m->antCtrlCommon);
444 ar9170_regwrite(0x1c5964, newval);
445
446 /* ant control chain 0 (index 1) */
447 newval = le32_to_cpu(m->antCtrlChain[0]);
448 ar9170_regwrite(0x1c5960, newval);
449
450 /* ant control chain 2 (index 2) */
451 newval = le32_to_cpu(m->antCtrlChain[1]);
452 ar9170_regwrite(0x1c7960, newval);
453
454 /* SwSettle (index 3) */
455 if (!is_40mhz) {
456 defval = ar9170_get_default_phy_reg_val(0x1c5844,
457 is_2ghz, is_40mhz);
458 newval = (defval & ~0x3f80) |
459 ((m->switchSettling & 0x7f) << 7);
460 ar9170_regwrite(0x1c5844, newval);
461 }
462
463 /* adcDesired, pdaDesired (index 4) */
464 defval = ar9170_get_default_phy_reg_val(0x1c5850, is_2ghz, is_40mhz);
465 newval = (defval & ~0xffff) | ((u8)m->pgaDesiredSize << 8) |
466 ((u8)m->adcDesiredSize);
467 ar9170_regwrite(0x1c5850, newval);
468
469 /* TxEndToXpaOff, TxFrameToXpaOn (index 5) */
470 defval = ar9170_get_default_phy_reg_val(0x1c5834, is_2ghz, is_40mhz);
471 newval = (m->txEndToXpaOff << 24) | (m->txEndToXpaOff << 16) |
472 (m->txFrameToXpaOn << 8) | m->txFrameToXpaOn;
473 ar9170_regwrite(0x1c5834, newval);
474
475 /* TxEndToRxOn (index 6) */
476 defval = ar9170_get_default_phy_reg_val(0x1c5828, is_2ghz, is_40mhz);
477 newval = (defval & ~0xff0000) | (m->txEndToRxOn << 16);
478 ar9170_regwrite(0x1c5828, newval);
479
480 /* thresh62 (index 7) */
481 defval = ar9170_get_default_phy_reg_val(0x1c8864, is_2ghz, is_40mhz);
482 newval = (defval & ~0x7f000) | (m->thresh62 << 12);
483 ar9170_regwrite(0x1c8864, newval);
484
485 /* tx/rx attenuation chain 0 (index 8) */
486 defval = ar9170_get_default_phy_reg_val(0x1c5848, is_2ghz, is_40mhz);
487 newval = (defval & ~0x3f000) | ((m->txRxAttenCh[0] & 0x3f) << 12);
488 ar9170_regwrite(0x1c5848, newval);
489
490 /* tx/rx attenuation chain 2 (index 9) */
491 defval = ar9170_get_default_phy_reg_val(0x1c7848, is_2ghz, is_40mhz);
492 newval = (defval & ~0x3f000) | ((m->txRxAttenCh[1] & 0x3f) << 12);
493 ar9170_regwrite(0x1c7848, newval);
494
495 /* tx/rx margin chain 0 (index 10) */
496 defval = ar9170_get_default_phy_reg_val(0x1c620c, is_2ghz, is_40mhz);
497 newval = (defval & ~0xfc0000) | ((m->rxTxMarginCh[0] & 0x3f) << 18);
498 /* bsw margin chain 0 for 5GHz only */
499 if (!is_2ghz)
500 newval = (newval & ~0x3c00) | ((m->bswMargin[0] & 0xf) << 10);
501 ar9170_regwrite(0x1c620c, newval);
502
503 /* tx/rx margin chain 2 (index 11) */
504 defval = ar9170_get_default_phy_reg_val(0x1c820c, is_2ghz, is_40mhz);
505 newval = (defval & ~0xfc0000) | ((m->rxTxMarginCh[1] & 0x3f) << 18);
506 ar9170_regwrite(0x1c820c, newval);
507
508 /* iqCall, iqCallq chain 0 (index 12) */
509 defval = ar9170_get_default_phy_reg_val(0x1c5920, is_2ghz, is_40mhz);
510 newval = (defval & ~0x7ff) | (((u8)m->iqCalICh[0] & 0x3f) << 5) |
511 ((u8)m->iqCalQCh[0] & 0x1f);
512 ar9170_regwrite(0x1c5920, newval);
513
514 /* iqCall, iqCallq chain 2 (index 13) */
515 defval = ar9170_get_default_phy_reg_val(0x1c7920, is_2ghz, is_40mhz);
516 newval = (defval & ~0x7ff) | (((u8)m->iqCalICh[1] & 0x3f) << 5) |
517 ((u8)m->iqCalQCh[1] & 0x1f);
518 ar9170_regwrite(0x1c7920, newval);
519
520 /* xpd gain mask (index 14) */
521 defval = ar9170_get_default_phy_reg_val(0x1c6258, is_2ghz, is_40mhz);
522 newval = (defval & ~0xf0000) | (xpd2pd[m->xpdGain & 0xf] << 16);
523 ar9170_regwrite(0x1c6258, newval);
524 ar9170_regwrite_finish();
525
526 return ar9170_regwrite_result();
527 }
528
529 int ar9170_init_phy(struct ar9170 *ar, enum ieee80211_band band)
530 {
531 int i, err;
532 u32 val;
533 bool is_2ghz = band == IEEE80211_BAND_2GHZ;
534 bool is_40mhz = conf_is_ht40(&ar->hw->conf);
535
536 ar9170_regwrite_begin(ar);
537
538 for (i = 0; i < ARRAY_SIZE(ar5416_phy_init); i++) {
539 if (is_40mhz) {
540 if (is_2ghz)
541 val = ar5416_phy_init[i]._2ghz_40;
542 else
543 val = ar5416_phy_init[i]._5ghz_40;
544 } else {
545 if (is_2ghz)
546 val = ar5416_phy_init[i]._2ghz_20;
547 else
548 val = ar5416_phy_init[i]._5ghz_20;
549 }
550
551 ar9170_regwrite(ar5416_phy_init[i].reg, val);
552 }
553
554 ar9170_regwrite_finish();
555 err = ar9170_regwrite_result();
556 if (err)
557 return err;
558
559 err = ar9170_init_phy_from_eeprom(ar, is_2ghz, is_40mhz);
560 if (err)
561 return err;
562
563 err = ar9170_init_power_cal(ar);
564 if (err)
565 return err;
566
567 if (is_2ghz)
568 err = ar9170_write_reg(ar, 0x1d4014, 0x5163);
569 else
570 err = ar9170_write_reg(ar, 0x1d4014, 0x5143);
571
572 return err;
573 }
574
575 struct ar9170_rf_init {
576 u32 reg, _5ghz, _2ghz;
577 };
578
579 static struct ar9170_rf_init ar9170_rf_init[] = {
580 /* bank 0 */
581 { 0x1c58b0, 0x1e5795e5, 0x1e5795e5},
582 { 0x1c58e0, 0x02008020, 0x02008020},
583 /* bank 1 */
584 { 0x1c58b0, 0x02108421, 0x02108421},
585 { 0x1c58ec, 0x00000008, 0x00000008},
586 /* bank 2 */
587 { 0x1c58b0, 0x0e73ff17, 0x0e73ff17},
588 { 0x1c58e0, 0x00000420, 0x00000420},
589 /* bank 3 */
590 { 0x1c58f0, 0x01400018, 0x01c00018},
591 /* bank 4 */
592 { 0x1c58b0, 0x000001a1, 0x000001a1},
593 { 0x1c58e8, 0x00000001, 0x00000001},
594 /* bank 5 */
595 { 0x1c58b0, 0x00000013, 0x00000013},
596 { 0x1c58e4, 0x00000002, 0x00000002},
597 /* bank 6 */
598 { 0x1c58b0, 0x00000000, 0x00000000},
599 { 0x1c58b0, 0x00000000, 0x00000000},
600 { 0x1c58b0, 0x00000000, 0x00000000},
601 { 0x1c58b0, 0x00000000, 0x00000000},
602 { 0x1c58b0, 0x00000000, 0x00000000},
603 { 0x1c58b0, 0x00004000, 0x00004000},
604 { 0x1c58b0, 0x00006c00, 0x00006c00},
605 { 0x1c58b0, 0x00002c00, 0x00002c00},
606 { 0x1c58b0, 0x00004800, 0x00004800},
607 { 0x1c58b0, 0x00004000, 0x00004000},
608 { 0x1c58b0, 0x00006000, 0x00006000},
609 { 0x1c58b0, 0x00001000, 0x00001000},
610 { 0x1c58b0, 0x00004000, 0x00004000},
611 { 0x1c58b0, 0x00007c00, 0x00007c00},
612 { 0x1c58b0, 0x00007c00, 0x00007c00},
613 { 0x1c58b0, 0x00007c00, 0x00007c00},
614 { 0x1c58b0, 0x00007c00, 0x00007c00},
615 { 0x1c58b0, 0x00007c00, 0x00007c00},
616 { 0x1c58b0, 0x00087c00, 0x00087c00},
617 { 0x1c58b0, 0x00007c00, 0x00007c00},
618 { 0x1c58b0, 0x00005400, 0x00005400},
619 { 0x1c58b0, 0x00000c00, 0x00000c00},
620 { 0x1c58b0, 0x00001800, 0x00001800},
621 { 0x1c58b0, 0x00007c00, 0x00007c00},
622 { 0x1c58b0, 0x00006c00, 0x00006c00},
623 { 0x1c58b0, 0x00006c00, 0x00006c00},
624 { 0x1c58b0, 0x00007c00, 0x00007c00},
625 { 0x1c58b0, 0x00002c00, 0x00002c00},
626 { 0x1c58b0, 0x00003c00, 0x00003c00},
627 { 0x1c58b0, 0x00003800, 0x00003800},
628 { 0x1c58b0, 0x00001c00, 0x00001c00},
629 { 0x1c58b0, 0x00000800, 0x00000800},
630 { 0x1c58b0, 0x00000408, 0x00000408},
631 { 0x1c58b0, 0x00004c15, 0x00004c15},
632 { 0x1c58b0, 0x00004188, 0x00004188},
633 { 0x1c58b0, 0x0000201e, 0x0000201e},
634 { 0x1c58b0, 0x00010408, 0x00010408},
635 { 0x1c58b0, 0x00000801, 0x00000801},
636 { 0x1c58b0, 0x00000c08, 0x00000c08},
637 { 0x1c58b0, 0x0000181e, 0x0000181e},
638 { 0x1c58b0, 0x00001016, 0x00001016},
639 { 0x1c58b0, 0x00002800, 0x00002800},
640 { 0x1c58b0, 0x00004010, 0x00004010},
641 { 0x1c58b0, 0x0000081c, 0x0000081c},
642 { 0x1c58b0, 0x00000115, 0x00000115},
643 { 0x1c58b0, 0x00000015, 0x00000015},
644 { 0x1c58b0, 0x00000066, 0x00000066},
645 { 0x1c58b0, 0x0000001c, 0x0000001c},
646 { 0x1c58b0, 0x00000000, 0x00000000},
647 { 0x1c58b0, 0x00000004, 0x00000004},
648 { 0x1c58b0, 0x00000015, 0x00000015},
649 { 0x1c58b0, 0x0000001f, 0x0000001f},
650 { 0x1c58e0, 0x00000000, 0x00000400},
651 /* bank 7 */
652 { 0x1c58b0, 0x000000a0, 0x000000a0},
653 { 0x1c58b0, 0x00000000, 0x00000000},
654 { 0x1c58b0, 0x00000040, 0x00000040},
655 { 0x1c58f0, 0x0000001c, 0x0000001c},
656 };
657
658 static int ar9170_init_rf_banks_0_7(struct ar9170 *ar, bool band5ghz)
659 {
660 int err, i;
661
662 ar9170_regwrite_begin(ar);
663
664 for (i = 0; i < ARRAY_SIZE(ar9170_rf_init); i++)
665 ar9170_regwrite(ar9170_rf_init[i].reg,
666 band5ghz ? ar9170_rf_init[i]._5ghz
667 : ar9170_rf_init[i]._2ghz);
668
669 ar9170_regwrite_finish();
670 err = ar9170_regwrite_result();
671 if (err)
672 wiphy_err(ar->hw->wiphy, "rf init failed\n");
673 return err;
674 }
675
676 static int ar9170_init_rf_bank4_pwr(struct ar9170 *ar, bool band5ghz,
677 u32 freq, enum ar9170_bw bw)
678 {
679 int err;
680 u32 d0, d1, td0, td1, fd0, fd1;
681 u8 chansel;
682 u8 refsel0 = 1, refsel1 = 0;
683 u8 lf_synth = 0;
684
685 switch (bw) {
686 case AR9170_BW_40_ABOVE:
687 freq += 10;
688 break;
689 case AR9170_BW_40_BELOW:
690 freq -= 10;
691 break;
692 case AR9170_BW_20:
693 break;
694 case __AR9170_NUM_BW:
695 BUG();
696 }
697
698 if (band5ghz) {
699 if (freq % 10) {
700 chansel = (freq - 4800) / 5;
701 } else {
702 chansel = ((freq - 4800) / 10) * 2;
703 refsel0 = 0;
704 refsel1 = 1;
705 }
706 chansel = byte_rev_table[chansel];
707 } else {
708 if (freq == 2484) {
709 chansel = 10 + (freq - 2274) / 5;
710 lf_synth = 1;
711 } else
712 chansel = 16 + (freq - 2272) / 5;
713 chansel *= 4;
714 chansel = byte_rev_table[chansel];
715 }
716
717 d1 = chansel;
718 d0 = 0x21 |
719 refsel0 << 3 |
720 refsel1 << 2 |
721 lf_synth << 1;
722 td0 = d0 & 0x1f;
723 td1 = d1 & 0x1f;
724 fd0 = td1 << 5 | td0;
725
726 td0 = (d0 >> 5) & 0x7;
727 td1 = (d1 >> 5) & 0x7;
728 fd1 = td1 << 5 | td0;
729
730 ar9170_regwrite_begin(ar);
731
732 ar9170_regwrite(0x1c58b0, fd0);
733 ar9170_regwrite(0x1c58e8, fd1);
734
735 ar9170_regwrite_finish();
736 err = ar9170_regwrite_result();
737 if (err)
738 return err;
739
740 msleep(10);
741
742 return 0;
743 }
744
745 struct ar9170_phy_freq_params {
746 u8 coeff_exp;
747 u16 coeff_man;
748 u8 coeff_exp_shgi;
749 u16 coeff_man_shgi;
750 };
751
752 struct ar9170_phy_freq_entry {
753 u16 freq;
754 struct ar9170_phy_freq_params params[__AR9170_NUM_BW];
755 };
756
757 /* NB: must be in sync with channel tables in main! */
758 static const struct ar9170_phy_freq_entry ar9170_phy_freq_params[] = {
759 /*
760 * freq,
761 * 20MHz,
762 * 40MHz (below),
763 * 40Mhz (above),
764 */
765 { 2412, {
766 { 3, 21737, 3, 19563, },
767 { 3, 21827, 3, 19644, },
768 { 3, 21647, 3, 19482, },
769 } },
770 { 2417, {
771 { 3, 21692, 3, 19523, },
772 { 3, 21782, 3, 19604, },
773 { 3, 21602, 3, 19442, },
774 } },
775 { 2422, {
776 { 3, 21647, 3, 19482, },
777 { 3, 21737, 3, 19563, },
778 { 3, 21558, 3, 19402, },
779 } },
780 { 2427, {
781 { 3, 21602, 3, 19442, },
782 { 3, 21692, 3, 19523, },
783 { 3, 21514, 3, 19362, },
784 } },
785 { 2432, {
786 { 3, 21558, 3, 19402, },
787 { 3, 21647, 3, 19482, },
788 { 3, 21470, 3, 19323, },
789 } },
790 { 2437, {
791 { 3, 21514, 3, 19362, },
792 { 3, 21602, 3, 19442, },
793 { 3, 21426, 3, 19283, },
794 } },
795 { 2442, {
796 { 3, 21470, 3, 19323, },
797 { 3, 21558, 3, 19402, },
798 { 3, 21382, 3, 19244, },
799 } },
800 { 2447, {
801 { 3, 21426, 3, 19283, },
802 { 3, 21514, 3, 19362, },
803 { 3, 21339, 3, 19205, },
804 } },
805 { 2452, {
806 { 3, 21382, 3, 19244, },
807 { 3, 21470, 3, 19323, },
808 { 3, 21295, 3, 19166, },
809 } },
810 { 2457, {
811 { 3, 21339, 3, 19205, },
812 { 3, 21426, 3, 19283, },
813 { 3, 21252, 3, 19127, },
814 } },
815 { 2462, {
816 { 3, 21295, 3, 19166, },
817 { 3, 21382, 3, 19244, },
818 { 3, 21209, 3, 19088, },
819 } },
820 { 2467, {
821 { 3, 21252, 3, 19127, },
822 { 3, 21339, 3, 19205, },
823 { 3, 21166, 3, 19050, },
824 } },
825 { 2472, {
826 { 3, 21209, 3, 19088, },
827 { 3, 21295, 3, 19166, },
828 { 3, 21124, 3, 19011, },
829 } },
830 { 2484, {
831 { 3, 21107, 3, 18996, },
832 { 3, 21192, 3, 19073, },
833 { 3, 21022, 3, 18920, },
834 } },
835 { 4920, {
836 { 4, 21313, 4, 19181, },
837 { 4, 21356, 4, 19220, },
838 { 4, 21269, 4, 19142, },
839 } },
840 { 4940, {
841 { 4, 21226, 4, 19104, },
842 { 4, 21269, 4, 19142, },
843 { 4, 21183, 4, 19065, },
844 } },
845 { 4960, {
846 { 4, 21141, 4, 19027, },
847 { 4, 21183, 4, 19065, },
848 { 4, 21098, 4, 18988, },
849 } },
850 { 4980, {
851 { 4, 21056, 4, 18950, },
852 { 4, 21098, 4, 18988, },
853 { 4, 21014, 4, 18912, },
854 } },
855 { 5040, {
856 { 4, 20805, 4, 18725, },
857 { 4, 20846, 4, 18762, },
858 { 4, 20764, 4, 18687, },
859 } },
860 { 5060, {
861 { 4, 20723, 4, 18651, },
862 { 4, 20764, 4, 18687, },
863 { 4, 20682, 4, 18614, },
864 } },
865 { 5080, {
866 { 4, 20641, 4, 18577, },
867 { 4, 20682, 4, 18614, },
868 { 4, 20601, 4, 18541, },
869 } },
870 { 5180, {
871 { 4, 20243, 4, 18219, },
872 { 4, 20282, 4, 18254, },
873 { 4, 20204, 4, 18183, },
874 } },
875 { 5200, {
876 { 4, 20165, 4, 18148, },
877 { 4, 20204, 4, 18183, },
878 { 4, 20126, 4, 18114, },
879 } },
880 { 5220, {
881 { 4, 20088, 4, 18079, },
882 { 4, 20126, 4, 18114, },
883 { 4, 20049, 4, 18044, },
884 } },
885 { 5240, {
886 { 4, 20011, 4, 18010, },
887 { 4, 20049, 4, 18044, },
888 { 4, 19973, 4, 17976, },
889 } },
890 { 5260, {
891 { 4, 19935, 4, 17941, },
892 { 4, 19973, 4, 17976, },
893 { 4, 19897, 4, 17907, },
894 } },
895 { 5280, {
896 { 4, 19859, 4, 17873, },
897 { 4, 19897, 4, 17907, },
898 { 4, 19822, 4, 17840, },
899 } },
900 { 5300, {
901 { 4, 19784, 4, 17806, },
902 { 4, 19822, 4, 17840, },
903 { 4, 19747, 4, 17772, },
904 } },
905 { 5320, {
906 { 4, 19710, 4, 17739, },
907 { 4, 19747, 4, 17772, },
908 { 4, 19673, 4, 17706, },
909 } },
910 { 5500, {
911 { 4, 19065, 4, 17159, },
912 { 4, 19100, 4, 17190, },
913 { 4, 19030, 4, 17127, },
914 } },
915 { 5520, {
916 { 4, 18996, 4, 17096, },
917 { 4, 19030, 4, 17127, },
918 { 4, 18962, 4, 17065, },
919 } },
920 { 5540, {
921 { 4, 18927, 4, 17035, },
922 { 4, 18962, 4, 17065, },
923 { 4, 18893, 4, 17004, },
924 } },
925 { 5560, {
926 { 4, 18859, 4, 16973, },
927 { 4, 18893, 4, 17004, },
928 { 4, 18825, 4, 16943, },
929 } },
930 { 5580, {
931 { 4, 18792, 4, 16913, },
932 { 4, 18825, 4, 16943, },
933 { 4, 18758, 4, 16882, },
934 } },
935 { 5600, {
936 { 4, 18725, 4, 16852, },
937 { 4, 18758, 4, 16882, },
938 { 4, 18691, 4, 16822, },
939 } },
940 { 5620, {
941 { 4, 18658, 4, 16792, },
942 { 4, 18691, 4, 16822, },
943 { 4, 18625, 4, 16762, },
944 } },
945 { 5640, {
946 { 4, 18592, 4, 16733, },
947 { 4, 18625, 4, 16762, },
948 { 4, 18559, 4, 16703, },
949 } },
950 { 5660, {
951 { 4, 18526, 4, 16673, },
952 { 4, 18559, 4, 16703, },
953 { 4, 18493, 4, 16644, },
954 } },
955 { 5680, {
956 { 4, 18461, 4, 16615, },
957 { 4, 18493, 4, 16644, },
958 { 4, 18428, 4, 16586, },
959 } },
960 { 5700, {
961 { 4, 18396, 4, 16556, },
962 { 4, 18428, 4, 16586, },
963 { 4, 18364, 4, 16527, },
964 } },
965 { 5745, {
966 { 4, 18252, 4, 16427, },
967 { 4, 18284, 4, 16455, },
968 { 4, 18220, 4, 16398, },
969 } },
970 { 5765, {
971 { 4, 18189, 5, 32740, },
972 { 4, 18220, 4, 16398, },
973 { 4, 18157, 5, 32683, },
974 } },
975 { 5785, {
976 { 4, 18126, 5, 32626, },
977 { 4, 18157, 5, 32683, },
978 { 4, 18094, 5, 32570, },
979 } },
980 { 5805, {
981 { 4, 18063, 5, 32514, },
982 { 4, 18094, 5, 32570, },
983 { 4, 18032, 5, 32458, },
984 } },
985 { 5825, {
986 { 4, 18001, 5, 32402, },
987 { 4, 18032, 5, 32458, },
988 { 4, 17970, 5, 32347, },
989 } },
990 { 5170, {
991 { 4, 20282, 4, 18254, },
992 { 4, 20321, 4, 18289, },
993 { 4, 20243, 4, 18219, },
994 } },
995 { 5190, {
996 { 4, 20204, 4, 18183, },
997 { 4, 20243, 4, 18219, },
998 { 4, 20165, 4, 18148, },
999 } },
1000 { 5210, {
1001 { 4, 20126, 4, 18114, },
1002 { 4, 20165, 4, 18148, },
1003 { 4, 20088, 4, 18079, },
1004 } },
1005 { 5230, {
1006 { 4, 20049, 4, 18044, },
1007 { 4, 20088, 4, 18079, },
1008 { 4, 20011, 4, 18010, },
1009 } },
1010 };
1011
1012 static const struct ar9170_phy_freq_params *
1013 ar9170_get_hw_dyn_params(struct ieee80211_channel *channel,
1014 enum ar9170_bw bw)
1015 {
1016 unsigned int chanidx = 0;
1017 u16 freq = 2412;
1018
1019 if (channel) {
1020 chanidx = channel->hw_value;
1021 freq = channel->center_freq;
1022 }
1023
1024 BUG_ON(chanidx >= ARRAY_SIZE(ar9170_phy_freq_params));
1025
1026 BUILD_BUG_ON(__AR9170_NUM_BW != 3);
1027
1028 WARN_ON(ar9170_phy_freq_params[chanidx].freq != freq);
1029
1030 return &ar9170_phy_freq_params[chanidx].params[bw];
1031 }
1032
1033
1034 int ar9170_init_rf(struct ar9170 *ar)
1035 {
1036 const struct ar9170_phy_freq_params *freqpar;
1037 __le32 cmd[7];
1038 int err;
1039
1040 err = ar9170_init_rf_banks_0_7(ar, false);
1041 if (err)
1042 return err;
1043
1044 err = ar9170_init_rf_bank4_pwr(ar, false, 2412, AR9170_BW_20);
1045 if (err)
1046 return err;
1047
1048 freqpar = ar9170_get_hw_dyn_params(NULL, AR9170_BW_20);
1049
1050 cmd[0] = cpu_to_le32(2412 * 1000);
1051 cmd[1] = cpu_to_le32(0);
1052 cmd[2] = cpu_to_le32(1);
1053 cmd[3] = cpu_to_le32(freqpar->coeff_exp);
1054 cmd[4] = cpu_to_le32(freqpar->coeff_man);
1055 cmd[5] = cpu_to_le32(freqpar->coeff_exp_shgi);
1056 cmd[6] = cpu_to_le32(freqpar->coeff_man_shgi);
1057
1058 /* RF_INIT echoes the command back to us */
1059 err = ar->exec_cmd(ar, AR9170_CMD_RF_INIT,
1060 sizeof(cmd), (u8 *)cmd,
1061 sizeof(cmd), (u8 *)cmd);
1062 if (err)
1063 return err;
1064
1065 msleep(1000);
1066
1067 return ar9170_echo_test(ar, 0xaabbccdd);
1068 }
1069
1070 static int ar9170_find_freq_idx(int nfreqs, u8 *freqs, u8 f)
1071 {
1072 int idx = nfreqs - 2;
1073
1074 while (idx >= 0) {
1075 if (f >= freqs[idx])
1076 return idx;
1077 idx--;
1078 }
1079
1080 return 0;
1081 }
1082
1083 static s32 ar9170_interpolate_s32(s32 x, s32 x1, s32 y1, s32 x2, s32 y2)
1084 {
1085 /* nothing to interpolate, it's horizontal */
1086 if (y2 == y1)
1087 return y1;
1088
1089 /* check if we hit one of the edges */
1090 if (x == x1)
1091 return y1;
1092 if (x == x2)
1093 return y2;
1094
1095 /* x1 == x2 is bad, hopefully == x */
1096 if (x2 == x1)
1097 return y1;
1098
1099 return y1 + (((y2 - y1) * (x - x1)) / (x2 - x1));
1100 }
1101
1102 static u8 ar9170_interpolate_u8(u8 x, u8 x1, u8 y1, u8 x2, u8 y2)
1103 {
1104 #define SHIFT 8
1105 s32 y;
1106
1107 y = ar9170_interpolate_s32(x << SHIFT,
1108 x1 << SHIFT, y1 << SHIFT,
1109 x2 << SHIFT, y2 << SHIFT);
1110
1111 return (y >> SHIFT) + ((y & (1<<(SHIFT-1))) >> (SHIFT - 1));
1112 #undef SHIFT
1113 }
1114
1115 static u8 ar9170_interpolate_val(u8 x, u8 *x_array, u8 *y_array)
1116 {
1117 int i;
1118
1119 for (i = 0; i < 3; i++)
1120 if (x <= x_array[i + 1])
1121 break;
1122
1123 return ar9170_interpolate_u8(x,
1124 x_array[i],
1125 y_array[i],
1126 x_array[i + 1],
1127 y_array[i + 1]);
1128 }
1129
1130 static int ar9170_set_freq_cal_data(struct ar9170 *ar,
1131 struct ieee80211_channel *channel)
1132 {
1133 u8 *cal_freq_pier;
1134 u8 vpds[2][AR5416_PD_GAIN_ICEPTS];
1135 u8 pwrs[2][AR5416_PD_GAIN_ICEPTS];
1136 int chain, idx, i;
1137 u32 phy_data = 0;
1138 u8 f, tmp;
1139
1140 switch (channel->band) {
1141 case IEEE80211_BAND_2GHZ:
1142 f = channel->center_freq - 2300;
1143 cal_freq_pier = ar->eeprom.cal_freq_pier_2G;
1144 i = AR5416_NUM_2G_CAL_PIERS - 1;
1145 break;
1146
1147 case IEEE80211_BAND_5GHZ:
1148 f = (channel->center_freq - 4800) / 5;
1149 cal_freq_pier = ar->eeprom.cal_freq_pier_5G;
1150 i = AR5416_NUM_5G_CAL_PIERS - 1;
1151 break;
1152
1153 default:
1154 return -EINVAL;
1155 break;
1156 }
1157
1158 for (; i >= 0; i--) {
1159 if (cal_freq_pier[i] != 0xff)
1160 break;
1161 }
1162 if (i < 0)
1163 return -EINVAL;
1164
1165 idx = ar9170_find_freq_idx(i, cal_freq_pier, f);
1166
1167 ar9170_regwrite_begin(ar);
1168
1169 for (chain = 0; chain < AR5416_MAX_CHAINS; chain++) {
1170 for (i = 0; i < AR5416_PD_GAIN_ICEPTS; i++) {
1171 struct ar9170_calibration_data_per_freq *cal_pier_data;
1172 int j;
1173
1174 switch (channel->band) {
1175 case IEEE80211_BAND_2GHZ:
1176 cal_pier_data = &ar->eeprom.
1177 cal_pier_data_2G[chain][idx];
1178 break;
1179
1180 case IEEE80211_BAND_5GHZ:
1181 cal_pier_data = &ar->eeprom.
1182 cal_pier_data_5G[chain][idx];
1183 break;
1184
1185 default:
1186 return -EINVAL;
1187 }
1188
1189 for (j = 0; j < 2; j++) {
1190 vpds[j][i] = ar9170_interpolate_u8(f,
1191 cal_freq_pier[idx],
1192 cal_pier_data->vpd_pdg[j][i],
1193 cal_freq_pier[idx + 1],
1194 cal_pier_data[1].vpd_pdg[j][i]);
1195
1196 pwrs[j][i] = ar9170_interpolate_u8(f,
1197 cal_freq_pier[idx],
1198 cal_pier_data->pwr_pdg[j][i],
1199 cal_freq_pier[idx + 1],
1200 cal_pier_data[1].pwr_pdg[j][i]) / 2;
1201 }
1202 }
1203
1204 for (i = 0; i < 76; i++) {
1205 if (i < 25) {
1206 tmp = ar9170_interpolate_val(i, &pwrs[0][0],
1207 &vpds[0][0]);
1208 } else {
1209 tmp = ar9170_interpolate_val(i - 12,
1210 &pwrs[1][0],
1211 &vpds[1][0]);
1212 }
1213
1214 phy_data |= tmp << ((i & 3) << 3);
1215 if ((i & 3) == 3) {
1216 ar9170_regwrite(0x1c6280 + chain * 0x1000 +
1217 (i & ~3), phy_data);
1218 phy_data = 0;
1219 }
1220 }
1221
1222 for (i = 19; i < 32; i++)
1223 ar9170_regwrite(0x1c6280 + chain * 0x1000 + (i << 2),
1224 0x0);
1225 }
1226
1227 ar9170_regwrite_finish();
1228 return ar9170_regwrite_result();
1229 }
1230
1231 static u8 ar9170_get_max_edge_power(struct ar9170 *ar,
1232 struct ar9170_calctl_edges edges[],
1233 u32 freq)
1234 {
1235 int i;
1236 u8 rc = AR5416_MAX_RATE_POWER;
1237 u8 f;
1238 if (freq < 3000)
1239 f = freq - 2300;
1240 else
1241 f = (freq - 4800) / 5;
1242
1243 for (i = 0; i < AR5416_NUM_BAND_EDGES; i++) {
1244 if (edges[i].channel == 0xff)
1245 break;
1246 if (f == edges[i].channel) {
1247 /* exact freq match */
1248 rc = edges[i].power_flags & ~AR9170_CALCTL_EDGE_FLAGS;
1249 break;
1250 }
1251 if (i > 0 && f < edges[i].channel) {
1252 if (f > edges[i - 1].channel &&
1253 edges[i - 1].power_flags &
1254 AR9170_CALCTL_EDGE_FLAGS) {
1255 /* lower channel has the inband flag set */
1256 rc = edges[i - 1].power_flags &
1257 ~AR9170_CALCTL_EDGE_FLAGS;
1258 }
1259 break;
1260 }
1261 }
1262
1263 if (i == AR5416_NUM_BAND_EDGES) {
1264 if (f > edges[i - 1].channel &&
1265 edges[i - 1].power_flags & AR9170_CALCTL_EDGE_FLAGS) {
1266 /* lower channel has the inband flag set */
1267 rc = edges[i - 1].power_flags &
1268 ~AR9170_CALCTL_EDGE_FLAGS;
1269 }
1270 }
1271 return rc;
1272 }
1273
1274 static u8 ar9170_get_heavy_clip(struct ar9170 *ar,
1275 struct ar9170_calctl_edges edges[],
1276 u32 freq, enum ar9170_bw bw)
1277 {
1278 u8 f;
1279 int i;
1280 u8 rc = 0;
1281
1282 if (freq < 3000)
1283 f = freq - 2300;
1284 else
1285 f = (freq - 4800) / 5;
1286
1287 if (bw == AR9170_BW_40_BELOW || bw == AR9170_BW_40_ABOVE)
1288 rc |= 0xf0;
1289
1290 for (i = 0; i < AR5416_NUM_BAND_EDGES; i++) {
1291 if (edges[i].channel == 0xff)
1292 break;
1293 if (f == edges[i].channel) {
1294 if (!(edges[i].power_flags & AR9170_CALCTL_EDGE_FLAGS))
1295 rc |= 0x0f;
1296 break;
1297 }
1298 }
1299
1300 return rc;
1301 }
1302
1303 /*
1304 * calculate the conformance test limits and the heavy clip parameter
1305 * and apply them to ar->power* (derived from otus hal/hpmain.c, line 3706)
1306 */
1307 static void ar9170_calc_ctl(struct ar9170 *ar, u32 freq, enum ar9170_bw bw)
1308 {
1309 u8 ctl_grp; /* CTL group */
1310 u8 ctl_idx; /* CTL index */
1311 int i, j;
1312 struct ctl_modes {
1313 u8 ctl_mode;
1314 u8 max_power;
1315 u8 *pwr_cal_data;
1316 int pwr_cal_len;
1317 } *modes;
1318
1319 /*
1320 * order is relevant in the mode_list_*: we fall back to the
1321 * lower indices if any mode is missed in the EEPROM.
1322 */
1323 struct ctl_modes mode_list_2ghz[] = {
1324 { CTL_11B, 0, ar->power_2G_cck, 4 },
1325 { CTL_11G, 0, ar->power_2G_ofdm, 4 },
1326 { CTL_2GHT20, 0, ar->power_2G_ht20, 8 },
1327 { CTL_2GHT40, 0, ar->power_2G_ht40, 8 },
1328 };
1329 struct ctl_modes mode_list_5ghz[] = {
1330 { CTL_11A, 0, ar->power_5G_leg, 4 },
1331 { CTL_5GHT20, 0, ar->power_5G_ht20, 8 },
1332 { CTL_5GHT40, 0, ar->power_5G_ht40, 8 },
1333 };
1334 int nr_modes;
1335
1336 #define EDGES(c, n) (ar->eeprom.ctl_data[c].control_edges[n])
1337
1338 ar->phy_heavy_clip = 0;
1339
1340 /*
1341 * TODO: investigate the differences between OTUS'
1342 * hpreg.c::zfHpGetRegulatoryDomain() and
1343 * ath/regd.c::ath_regd_get_band_ctl() -
1344 * e.g. for FCC3_WORLD the OTUS procedure
1345 * always returns CTL_FCC, while the one in ath/ delivers
1346 * CTL_ETSI for 2GHz and CTL_FCC for 5GHz.
1347 */
1348 ctl_grp = ath_regd_get_band_ctl(&ar->common.regulatory,
1349 ar->hw->conf.channel->band);
1350
1351 /* ctl group not found - either invalid band (NO_CTL) or ww roaming */
1352 if (ctl_grp == NO_CTL || ctl_grp == SD_NO_CTL)
1353 ctl_grp = CTL_FCC;
1354
1355 if (ctl_grp != CTL_FCC)
1356 /* skip CTL and heavy clip for CTL_MKK and CTL_ETSI */
1357 return;
1358
1359 if (ar->hw->conf.channel->band == IEEE80211_BAND_2GHZ) {
1360 modes = mode_list_2ghz;
1361 nr_modes = ARRAY_SIZE(mode_list_2ghz);
1362 } else {
1363 modes = mode_list_5ghz;
1364 nr_modes = ARRAY_SIZE(mode_list_5ghz);
1365 }
1366
1367 for (i = 0; i < nr_modes; i++) {
1368 u8 c = ctl_grp | modes[i].ctl_mode;
1369 for (ctl_idx = 0; ctl_idx < AR5416_NUM_CTLS; ctl_idx++)
1370 if (c == ar->eeprom.ctl_index[ctl_idx])
1371 break;
1372 if (ctl_idx < AR5416_NUM_CTLS) {
1373 int f_off = 0;
1374
1375 /* determine heav clip parameter from
1376 the 11G edges array */
1377 if (modes[i].ctl_mode == CTL_11G) {
1378 ar->phy_heavy_clip =
1379 ar9170_get_heavy_clip(ar,
1380 EDGES(ctl_idx, 1),
1381 freq, bw);
1382 }
1383
1384 /* adjust freq for 40MHz */
1385 if (modes[i].ctl_mode == CTL_2GHT40 ||
1386 modes[i].ctl_mode == CTL_5GHT40) {
1387 if (bw == AR9170_BW_40_BELOW)
1388 f_off = -10;
1389 else
1390 f_off = 10;
1391 }
1392
1393 modes[i].max_power =
1394 ar9170_get_max_edge_power(ar, EDGES(ctl_idx, 1),
1395 freq+f_off);
1396
1397 /*
1398 * TODO: check if the regulatory max. power is
1399 * controlled by cfg80211 for DFS
1400 * (hpmain applies it to max_power itself for DFS freq)
1401 */
1402
1403 } else {
1404 int k = i;
1405
1406 modes[i].max_power = AR5416_MAX_RATE_POWER;
1407 while (k-- > 0) {
1408 if (modes[k].max_power !=
1409 AR5416_MAX_RATE_POWER) {
1410 modes[i].max_power = modes[k].max_power;
1411 break;
1412 }
1413 }
1414 }
1415
1416 /* apply max power to pwr_cal_data (ar->power_*) */
1417 for (j = 0; j < modes[i].pwr_cal_len; j++) {
1418 modes[i].pwr_cal_data[j] = min(modes[i].pwr_cal_data[j],
1419 modes[i].max_power);
1420 }
1421 }
1422
1423 if (ar->phy_heavy_clip & 0xf0) {
1424 ar->power_2G_ht40[0]--;
1425 ar->power_2G_ht40[1]--;
1426 ar->power_2G_ht40[2]--;
1427 }
1428 if (ar->phy_heavy_clip & 0xf) {
1429 ar->power_2G_ht20[0]++;
1430 ar->power_2G_ht20[1]++;
1431 ar->power_2G_ht20[2]++;
1432 }
1433
1434
1435 #undef EDGES
1436 }
1437
1438 static int ar9170_set_power_cal(struct ar9170 *ar, u32 freq, enum ar9170_bw bw)
1439 {
1440 struct ar9170_calibration_target_power_legacy *ctpl;
1441 struct ar9170_calibration_target_power_ht *ctph;
1442 u8 *ctpres;
1443 int ntargets;
1444 int idx, i, n;
1445 u8 ackpower, ackchains, f;
1446 u8 pwr_freqs[AR5416_MAX_NUM_TGT_PWRS];
1447
1448 if (freq < 3000)
1449 f = freq - 2300;
1450 else
1451 f = (freq - 4800)/5;
1452
1453 /*
1454 * cycle through the various modes
1455 *
1456 * legacy modes first: 5G, 2G CCK, 2G OFDM
1457 */
1458 for (i = 0; i < 3; i++) {
1459 switch (i) {
1460 case 0: /* 5 GHz legacy */
1461 ctpl = &ar->eeprom.cal_tgt_pwr_5G[0];
1462 ntargets = AR5416_NUM_5G_TARGET_PWRS;
1463 ctpres = ar->power_5G_leg;
1464 break;
1465 case 1: /* 2.4 GHz CCK */
1466 ctpl = &ar->eeprom.cal_tgt_pwr_2G_cck[0];
1467 ntargets = AR5416_NUM_2G_CCK_TARGET_PWRS;
1468 ctpres = ar->power_2G_cck;
1469 break;
1470 case 2: /* 2.4 GHz OFDM */
1471 ctpl = &ar->eeprom.cal_tgt_pwr_2G_ofdm[0];
1472 ntargets = AR5416_NUM_2G_OFDM_TARGET_PWRS;
1473 ctpres = ar->power_2G_ofdm;
1474 break;
1475 default:
1476 BUG();
1477 }
1478
1479 for (n = 0; n < ntargets; n++) {
1480 if (ctpl[n].freq == 0xff)
1481 break;
1482 pwr_freqs[n] = ctpl[n].freq;
1483 }
1484 ntargets = n;
1485 idx = ar9170_find_freq_idx(ntargets, pwr_freqs, f);
1486 for (n = 0; n < 4; n++)
1487 ctpres[n] = ar9170_interpolate_u8(
1488 f,
1489 ctpl[idx + 0].freq,
1490 ctpl[idx + 0].power[n],
1491 ctpl[idx + 1].freq,
1492 ctpl[idx + 1].power[n]);
1493 }
1494
1495 /*
1496 * HT modes now: 5G HT20, 5G HT40, 2G CCK, 2G OFDM, 2G HT20, 2G HT40
1497 */
1498 for (i = 0; i < 4; i++) {
1499 switch (i) {
1500 case 0: /* 5 GHz HT 20 */
1501 ctph = &ar->eeprom.cal_tgt_pwr_5G_ht20[0];
1502 ntargets = AR5416_NUM_5G_TARGET_PWRS;
1503 ctpres = ar->power_5G_ht20;
1504 break;
1505 case 1: /* 5 GHz HT 40 */
1506 ctph = &ar->eeprom.cal_tgt_pwr_5G_ht40[0];
1507 ntargets = AR5416_NUM_5G_TARGET_PWRS;
1508 ctpres = ar->power_5G_ht40;
1509 break;
1510 case 2: /* 2.4 GHz HT 20 */
1511 ctph = &ar->eeprom.cal_tgt_pwr_2G_ht20[0];
1512 ntargets = AR5416_NUM_2G_OFDM_TARGET_PWRS;
1513 ctpres = ar->power_2G_ht20;
1514 break;
1515 case 3: /* 2.4 GHz HT 40 */
1516 ctph = &ar->eeprom.cal_tgt_pwr_2G_ht40[0];
1517 ntargets = AR5416_NUM_2G_OFDM_TARGET_PWRS;
1518 ctpres = ar->power_2G_ht40;
1519 break;
1520 default:
1521 BUG();
1522 }
1523
1524 for (n = 0; n < ntargets; n++) {
1525 if (ctph[n].freq == 0xff)
1526 break;
1527 pwr_freqs[n] = ctph[n].freq;
1528 }
1529 ntargets = n;
1530 idx = ar9170_find_freq_idx(ntargets, pwr_freqs, f);
1531 for (n = 0; n < 8; n++)
1532 ctpres[n] = ar9170_interpolate_u8(
1533 f,
1534 ctph[idx + 0].freq,
1535 ctph[idx + 0].power[n],
1536 ctph[idx + 1].freq,
1537 ctph[idx + 1].power[n]);
1538 }
1539
1540
1541 /* calc. conformance test limits and apply to ar->power*[] */
1542 ar9170_calc_ctl(ar, freq, bw);
1543
1544 /* set ACK/CTS TX power */
1545 ar9170_regwrite_begin(ar);
1546
1547 if (ar->eeprom.tx_mask != 1)
1548 ackchains = AR9170_TX_PHY_TXCHAIN_2;
1549 else
1550 ackchains = AR9170_TX_PHY_TXCHAIN_1;
1551
1552 if (freq < 3000)
1553 ackpower = ar->power_2G_ofdm[0] & 0x3f;
1554 else
1555 ackpower = ar->power_5G_leg[0] & 0x3f;
1556
1557 ar9170_regwrite(0x1c3694, ackpower << 20 | ackchains << 26);
1558 ar9170_regwrite(0x1c3bb4, ackpower << 5 | ackchains << 11 |
1559 ackpower << 21 | ackchains << 27);
1560
1561 ar9170_regwrite_finish();
1562 return ar9170_regwrite_result();
1563 }
1564
1565 static int ar9170_calc_noise_dbm(u32 raw_noise)
1566 {
1567 if (raw_noise & 0x100)
1568 return ~((raw_noise & 0x0ff) >> 1);
1569 else
1570 return (raw_noise & 0xff) >> 1;
1571 }
1572
1573 int ar9170_set_channel(struct ar9170 *ar, struct ieee80211_channel *channel,
1574 enum ar9170_rf_init_mode rfi, enum ar9170_bw bw)
1575 {
1576 const struct ar9170_phy_freq_params *freqpar;
1577 u32 cmd, tmp, offs;
1578 __le32 vals[8];
1579 int i, err;
1580 bool bandswitch;
1581
1582 /* clear BB heavy clip enable */
1583 err = ar9170_write_reg(ar, 0x1c59e0, 0x200);
1584 if (err)
1585 return err;
1586
1587 /* may be NULL at first setup */
1588 if (ar->channel)
1589 bandswitch = ar->channel->band != channel->band;
1590 else
1591 bandswitch = true;
1592
1593 if (!ar->hw->wiphy->bands[IEEE80211_BAND_5GHZ] &&
1594 channel->center_freq <= 2417)
1595 bandswitch = true;
1596
1597 err = ar->exec_cmd(ar, AR9170_CMD_FREQ_START, 0, NULL, 0, NULL);
1598 if (err)
1599 return err;
1600
1601 if (rfi != AR9170_RFI_NONE || bandswitch) {
1602 u32 val = 0x400;
1603
1604 if (rfi == AR9170_RFI_COLD)
1605 val = 0x800;
1606
1607 /* warm/cold reset BB/ADDA */
1608 err = ar9170_write_reg(ar, 0x1d4004, val);
1609 if (err)
1610 return err;
1611
1612 err = ar9170_write_reg(ar, 0x1d4004, 0x0);
1613 if (err)
1614 return err;
1615
1616 err = ar9170_init_phy(ar, channel->band);
1617 if (err)
1618 return err;
1619
1620 err = ar9170_init_rf_banks_0_7(ar,
1621 channel->band == IEEE80211_BAND_5GHZ);
1622 if (err)
1623 return err;
1624
1625 cmd = AR9170_CMD_RF_INIT;
1626 } else {
1627 cmd = AR9170_CMD_FREQUENCY;
1628 }
1629
1630 err = ar9170_init_rf_bank4_pwr(ar,
1631 channel->band == IEEE80211_BAND_5GHZ,
1632 channel->center_freq, bw);
1633 if (err)
1634 return err;
1635
1636 switch (bw) {
1637 case AR9170_BW_20:
1638 tmp = 0x240;
1639 offs = 0;
1640 break;
1641 case AR9170_BW_40_BELOW:
1642 tmp = 0x2c4;
1643 offs = 3;
1644 break;
1645 case AR9170_BW_40_ABOVE:
1646 tmp = 0x2d4;
1647 offs = 1;
1648 break;
1649 default:
1650 BUG();
1651 return -ENOSYS;
1652 }
1653
1654 if (ar->eeprom.tx_mask != 1)
1655 tmp |= 0x100;
1656
1657 err = ar9170_write_reg(ar, 0x1c5804, tmp);
1658 if (err)
1659 return err;
1660
1661 err = ar9170_set_freq_cal_data(ar, channel);
1662 if (err)
1663 return err;
1664
1665 err = ar9170_set_power_cal(ar, channel->center_freq, bw);
1666 if (err)
1667 return err;
1668
1669 freqpar = ar9170_get_hw_dyn_params(channel, bw);
1670
1671 vals[0] = cpu_to_le32(channel->center_freq * 1000);
1672 vals[1] = cpu_to_le32(conf_is_ht40(&ar->hw->conf));
1673 vals[2] = cpu_to_le32(offs << 2 | 1);
1674 vals[3] = cpu_to_le32(freqpar->coeff_exp);
1675 vals[4] = cpu_to_le32(freqpar->coeff_man);
1676 vals[5] = cpu_to_le32(freqpar->coeff_exp_shgi);
1677 vals[6] = cpu_to_le32(freqpar->coeff_man_shgi);
1678 vals[7] = cpu_to_le32(1000);
1679
1680 err = ar->exec_cmd(ar, cmd, sizeof(vals), (u8 *)vals,
1681 sizeof(vals), (u8 *)vals);
1682 if (err)
1683 return err;
1684
1685 if (ar->phy_heavy_clip) {
1686 err = ar9170_write_reg(ar, 0x1c59e0,
1687 0x200 | ar->phy_heavy_clip);
1688 if (err) {
1689 if (ar9170_nag_limiter(ar))
1690 wiphy_err(ar->hw->wiphy,
1691 "failed to set heavy clip\n");
1692 }
1693 }
1694
1695 for (i = 0; i < 2; i++) {
1696 ar->noise[i] = ar9170_calc_noise_dbm(
1697 (le32_to_cpu(vals[2 + i]) >> 19) & 0x1ff);
1698
1699 ar->noise[i + 2] = ar9170_calc_noise_dbm(
1700 (le32_to_cpu(vals[5 + i]) >> 23) & 0x1ff);
1701 }
1702
1703 ar->channel = channel;
1704 return 0;
1705 }
Tomato firmware and modifications.