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GUI: Fix Tomato RAF theme for all builds. Compilation typo.
[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / drivers / net / wan / ixp4xx_hss.c
blob001867fa2eb96cf15a24786793fc53957d3a4397
1 /*
2 * Intel IXP4xx HSS (synchronous serial port) driver for Linux
3 *
4 * Copyright (C) 2007-2008 Krzysztof Hałasa <khc@pm.waw.pl>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of version 2 of the GNU General Public License
8 * as published by the Free Software Foundation.
9 */
10
11 #include <linux/bitops.h>
12 #include <linux/cdev.h>
13 #include <linux/dma-mapping.h>
14 #include <linux/dmapool.h>
15 #include <linux/fs.h>
16 #include <linux/hdlc.h>
17 #include <linux/io.h>
18 #include <linux/kernel.h>
19 #include <linux/platform_device.h>
20 #include <linux/poll.h>
21 #include <linux/slab.h>
22 #include <mach/npe.h>
23 #include <mach/qmgr.h>
24
25 #define DEBUG_DESC 0
26 #define DEBUG_RX 0
27 #define DEBUG_TX 0
28 #define DEBUG_PKT_BYTES 0
29 #define DEBUG_CLOSE 0
30
31 #define DRV_NAME "ixp4xx_hss"
32
33 #define PKT_EXTRA_FLAGS 0 /* orig 1 */
34 #define PKT_NUM_PIPES 1 /* 1, 2 or 4 */
35 #define PKT_PIPE_FIFO_SIZEW 4 /* total 4 dwords per HSS */
36
37 #define RX_DESCS 16 /* also length of all RX queues */
38 #define TX_DESCS 16 /* also length of all TX queues */
39
40 #define POOL_ALLOC_SIZE (sizeof(struct desc) * (RX_DESCS + TX_DESCS))
41 #define RX_SIZE (HDLC_MAX_MRU + 4) /* NPE needs more space */
42 #define MAX_CLOSE_WAIT 1000 /* microseconds */
43 #define HSS_COUNT 2
44 #define FRAME_SIZE 256 /* doesn't matter at this point */
45 #define FRAME_OFFSET 0
46 #define MAX_CHANNELS (FRAME_SIZE / 8)
47
48 #define NAPI_WEIGHT 16
49
50 /* Queue IDs */
51 #define HSS0_CHL_RXTRIG_QUEUE 12 /* orig size = 32 dwords */
52 #define HSS0_PKT_RX_QUEUE 13 /* orig size = 32 dwords */
53 #define HSS0_PKT_TX0_QUEUE 14 /* orig size = 16 dwords */
54 #define HSS0_PKT_TX1_QUEUE 15
55 #define HSS0_PKT_TX2_QUEUE 16
56 #define HSS0_PKT_TX3_QUEUE 17
57 #define HSS0_PKT_RXFREE0_QUEUE 18 /* orig size = 16 dwords */
58 #define HSS0_PKT_RXFREE1_QUEUE 19
59 #define HSS0_PKT_RXFREE2_QUEUE 20
60 #define HSS0_PKT_RXFREE3_QUEUE 21
61 #define HSS0_PKT_TXDONE_QUEUE 22 /* orig size = 64 dwords */
62
63 #define HSS1_CHL_RXTRIG_QUEUE 10
64 #define HSS1_PKT_RX_QUEUE 0
65 #define HSS1_PKT_TX0_QUEUE 5
66 #define HSS1_PKT_TX1_QUEUE 6
67 #define HSS1_PKT_TX2_QUEUE 7
68 #define HSS1_PKT_TX3_QUEUE 8
69 #define HSS1_PKT_RXFREE0_QUEUE 1
70 #define HSS1_PKT_RXFREE1_QUEUE 2
71 #define HSS1_PKT_RXFREE2_QUEUE 3
72 #define HSS1_PKT_RXFREE3_QUEUE 4
73 #define HSS1_PKT_TXDONE_QUEUE 9
74
75 #define NPE_PKT_MODE_HDLC 0
76 #define NPE_PKT_MODE_RAW 1
77 #define NPE_PKT_MODE_56KMODE 2
78 #define NPE_PKT_MODE_56KENDIAN_MSB 4
79
80 /* PKT_PIPE_HDLC_CFG_WRITE flags */
81 #define PKT_HDLC_IDLE_ONES 0x1 /* default = flags */
82 #define PKT_HDLC_CRC_32 0x2 /* default = CRC-16 */
83 #define PKT_HDLC_MSB_ENDIAN 0x4 /* default = LE */
84
85
86 /* hss_config, PCRs */
87 /* Frame sync sampling, default = active low */
88 #define PCR_FRM_SYNC_ACTIVE_HIGH 0x40000000
89 #define PCR_FRM_SYNC_FALLINGEDGE 0x80000000
90 #define PCR_FRM_SYNC_RISINGEDGE 0xC0000000
91
92 /* Frame sync pin: input (default) or output generated off a given clk edge */
93 #define PCR_FRM_SYNC_OUTPUT_FALLING 0x20000000
94 #define PCR_FRM_SYNC_OUTPUT_RISING 0x30000000
95
96 /* Frame and data clock sampling on edge, default = falling */
97 #define PCR_FCLK_EDGE_RISING 0x08000000
98 #define PCR_DCLK_EDGE_RISING 0x04000000
99
100 /* Clock direction, default = input */
101 #define PCR_SYNC_CLK_DIR_OUTPUT 0x02000000
102
103 /* Generate/Receive frame pulses, default = enabled */
104 #define PCR_FRM_PULSE_DISABLED 0x01000000
105
106 /* Data rate is full (default) or half the configured clk speed */
107 #define PCR_HALF_CLK_RATE 0x00200000
108
109 /* Invert data between NPE and HSS FIFOs? (default = no) */
110 #define PCR_DATA_POLARITY_INVERT 0x00100000
111
112 /* TX/RX endianness, default = LSB */
113 #define PCR_MSB_ENDIAN 0x00080000
114
115 /* Normal (default) / open drain mode (TX only) */
116 #define PCR_TX_PINS_OPEN_DRAIN 0x00040000
117
118 /* No framing bit transmitted and expected on RX? (default = framing bit) */
119 #define PCR_SOF_NO_FBIT 0x00020000
120
121 /* Drive data pins? */
122 #define PCR_TX_DATA_ENABLE 0x00010000
123
124 /* Voice 56k type: drive the data pins low (default), high, high Z */
125 #define PCR_TX_V56K_HIGH 0x00002000
126 #define PCR_TX_V56K_HIGH_IMP 0x00004000
127
128 /* Unassigned type: drive the data pins low (default), high, high Z */
129 #define PCR_TX_UNASS_HIGH 0x00000800
130 #define PCR_TX_UNASS_HIGH_IMP 0x00001000
131
132 /* T1 @ 1.544MHz only: Fbit dictated in FIFO (default) or high Z */
133 #define PCR_TX_FB_HIGH_IMP 0x00000400
134
135 /* 56k data endiannes - which bit unused: high (default) or low */
136 #define PCR_TX_56KE_BIT_0_UNUSED 0x00000200
137
138 /* 56k data transmission type: 32/8 bit data (default) or 56K data */
139 #define PCR_TX_56KS_56K_DATA 0x00000100
140
141 /* hss_config, cCR */
142 /* Number of packetized clients, default = 1 */
143 #define CCR_NPE_HFIFO_2_HDLC 0x04000000
144 #define CCR_NPE_HFIFO_3_OR_4HDLC 0x08000000
145
146 /* default = no loopback */
147 #define CCR_LOOPBACK 0x02000000
148
149 /* HSS number, default = 0 (first) */
150 #define CCR_SECOND_HSS 0x01000000
151
152
153 /* hss_config, clkCR: main:10, num:10, denom:12 */
154 #define CLK42X_SPEED_EXP ((0x3FF << 22) | ( 2 << 12) | 15) /*65 KHz*/
155
156 #define CLK42X_SPEED_512KHZ (( 130 << 22) | ( 2 << 12) | 15)
157 #define CLK42X_SPEED_1536KHZ (( 43 << 22) | ( 18 << 12) | 47)
158 #define CLK42X_SPEED_1544KHZ (( 43 << 22) | ( 33 << 12) | 192)
159 #define CLK42X_SPEED_2048KHZ (( 32 << 22) | ( 34 << 12) | 63)
160 #define CLK42X_SPEED_4096KHZ (( 16 << 22) | ( 34 << 12) | 127)
161 #define CLK42X_SPEED_8192KHZ (( 8 << 22) | ( 34 << 12) | 255)
162
163 #define CLK46X_SPEED_512KHZ (( 130 << 22) | ( 24 << 12) | 127)
164 #define CLK46X_SPEED_1536KHZ (( 43 << 22) | (152 << 12) | 383)
165 #define CLK46X_SPEED_1544KHZ (( 43 << 22) | ( 66 << 12) | 385)
166 #define CLK46X_SPEED_2048KHZ (( 32 << 22) | (280 << 12) | 511)
167 #define CLK46X_SPEED_4096KHZ (( 16 << 22) | (280 << 12) | 1023)
168 #define CLK46X_SPEED_8192KHZ (( 8 << 22) | (280 << 12) | 2047)
169
170 /*
171 * HSS_CONFIG_CLOCK_CR register consists of 3 parts:
172 * A (10 bits), B (10 bits) and C (12 bits).
173 * IXP42x HSS clock generator operation (verified with an oscilloscope):
174 * Each clock bit takes 7.5 ns (1 / 133.xx MHz).
175 * The clock sequence consists of (C - B) states of 0s and 1s, each state is
176 * A bits wide. It's followed by (B + 1) states of 0s and 1s, each state is
177 * (A + 1) bits wide.
178 *
179 * The resulting average clock frequency (assuming 33.333 MHz oscillator) is:
180 * freq = 66.666 MHz / (A + (B + 1) / (C + 1))
181 * minumum freq = 66.666 MHz / (A + 1)
182 * maximum freq = 66.666 MHz / A
183 *
184 * Example: A = 2, B = 2, C = 7, CLOCK_CR register = 2 << 22 | 2 << 12 | 7
185 * freq = 66.666 MHz / (2 + (2 + 1) / (7 + 1)) = 28.07 MHz (Mb/s).
186 * The clock sequence is: 1100110011 (5 doubles) 000111000 (3 triples).
187 * The sequence takes (C - B) * A + (B + 1) * (A + 1) = 5 * 2 + 3 * 3 bits
188 * = 19 bits (each 7.5 ns long) = 142.5 ns (then the sequence repeats).
189 * The sequence consists of 4 complete clock periods, thus the average
190 * frequency (= clock rate) is 4 / 142.5 ns = 28.07 MHz (Mb/s).
191 * (max specified clock rate for IXP42x HSS is 8.192 Mb/s).
192 */
193
194 /* hss_config, LUT entries */
195 #define TDMMAP_UNASSIGNED 0
196 #define TDMMAP_HDLC 1 /* HDLC - packetized */
197 #define TDMMAP_VOICE56K 2 /* Voice56K - 7-bit channelized */
198 #define TDMMAP_VOICE64K 3 /* Voice64K - 8-bit channelized */
199
200 /* offsets into HSS config */
201 #define HSS_CONFIG_TX_PCR 0x00 /* port configuration registers */
202 #define HSS_CONFIG_RX_PCR 0x04
203 #define HSS_CONFIG_CORE_CR 0x08 /* loopback control, HSS# */
204 #define HSS_CONFIG_CLOCK_CR 0x0C /* clock generator control */
205 #define HSS_CONFIG_TX_FCR 0x10 /* frame configuration registers */
206 #define HSS_CONFIG_RX_FCR 0x14
207 #define HSS_CONFIG_TX_LUT 0x18 /* channel look-up tables */
208 #define HSS_CONFIG_RX_LUT 0x38
209
210
211 /* NPE command codes */
212 /* writes the ConfigWord value to the location specified by offset */
213 #define PORT_CONFIG_WRITE 0x40
214
215 /* triggers the NPE to load the contents of the configuration table */
216 #define PORT_CONFIG_LOAD 0x41
217
218 /* triggers the NPE to return an HssErrorReadResponse message */
219 #define PORT_ERROR_READ 0x42
220
221 /* triggers the NPE to reset internal status and enable the HssPacketized
222 operation for the flow specified by pPipe */
223 #define PKT_PIPE_FLOW_ENABLE 0x50
224 #define PKT_PIPE_FLOW_DISABLE 0x51
225 #define PKT_NUM_PIPES_WRITE 0x52
226 #define PKT_PIPE_FIFO_SIZEW_WRITE 0x53
227 #define PKT_PIPE_HDLC_CFG_WRITE 0x54
228 #define PKT_PIPE_IDLE_PATTERN_WRITE 0x55
229 #define PKT_PIPE_RX_SIZE_WRITE 0x56
230 #define PKT_PIPE_MODE_WRITE 0x57
231
232 /* HDLC packet status values - desc->status */
233 #define ERR_SHUTDOWN 1 /* stop or shutdown occurrance */
234 #define ERR_HDLC_ALIGN 2 /* HDLC alignment error */
235 #define ERR_HDLC_FCS 3 /* HDLC Frame Check Sum error */
236 #define ERR_RXFREE_Q_EMPTY 4 /* RX-free queue became empty while receiving
237 this packet (if buf_len < pkt_len) */
238 #define ERR_HDLC_TOO_LONG 5 /* HDLC frame size too long */
239 #define ERR_HDLC_ABORT 6 /* abort sequence received */
240 #define ERR_DISCONNECTING 7 /* disconnect is in progress */
241
242
243 #ifdef __ARMEB__
244 typedef struct sk_buff buffer_t;
245 #define free_buffer dev_kfree_skb
246 #define free_buffer_irq dev_kfree_skb_irq
247 #else
248 typedef void buffer_t;
249 #define free_buffer kfree
250 #define free_buffer_irq kfree
251 #endif
252
253 struct port {
254 struct device *dev;
255 struct npe *npe;
256 struct net_device *netdev;
257 struct napi_struct napi;
258 struct hss_plat_info *plat;
259 buffer_t *rx_buff_tab[RX_DESCS], *tx_buff_tab[TX_DESCS];
260 struct desc *desc_tab; /* coherent */
261 u32 desc_tab_phys;
262 unsigned int id;
263 unsigned int clock_type, clock_rate, loopback;
264 unsigned int initialized, carrier;
265 u8 hdlc_cfg;
266 u32 clock_reg;
267 };
268
269 /* NPE message structure */
270 struct msg {
271 #ifdef __ARMEB__
272 u8 cmd, unused, hss_port, index;
273 union {
274 struct { u8 data8a, data8b, data8c, data8d; };
275 struct { u16 data16a, data16b; };
276 struct { u32 data32; };
277 };
278 #else
279 u8 index, hss_port, unused, cmd;
280 union {
281 struct { u8 data8d, data8c, data8b, data8a; };
282 struct { u16 data16b, data16a; };
283 struct { u32 data32; };
284 };
285 #endif
286 };
287
288 /* HDLC packet descriptor */
289 struct desc {
290 u32 next; /* pointer to next buffer, unused */
291
292 #ifdef __ARMEB__
293 u16 buf_len; /* buffer length */
294 u16 pkt_len; /* packet length */
295 u32 data; /* pointer to data buffer in RAM */
296 u8 status;
297 u8 error_count;
298 u16 __reserved;
299 #else
300 u16 pkt_len; /* packet length */
301 u16 buf_len; /* buffer length */
302 u32 data; /* pointer to data buffer in RAM */
303 u16 __reserved;
304 u8 error_count;
305 u8 status;
306 #endif
307 u32 __reserved1[4];
308 };
309
310
311 #define rx_desc_phys(port, n) ((port)->desc_tab_phys + \
312 (n) * sizeof(struct desc))
313 #define rx_desc_ptr(port, n) (&(port)->desc_tab[n])
314
315 #define tx_desc_phys(port, n) ((port)->desc_tab_phys + \
316 ((n) + RX_DESCS) * sizeof(struct desc))
317 #define tx_desc_ptr(port, n) (&(port)->desc_tab[(n) + RX_DESCS])
318
319 /*****************************************************************************
320 * global variables
321 ****************************************************************************/
322
323 static int ports_open;
324 static struct dma_pool *dma_pool;
325 static spinlock_t npe_lock;
326
327 static const struct {
328 int tx, txdone, rx, rxfree;
329 }queue_ids[2] = {{HSS0_PKT_TX0_QUEUE, HSS0_PKT_TXDONE_QUEUE, HSS0_PKT_RX_QUEUE,
330 HSS0_PKT_RXFREE0_QUEUE},
331 {HSS1_PKT_TX0_QUEUE, HSS1_PKT_TXDONE_QUEUE, HSS1_PKT_RX_QUEUE,
332 HSS1_PKT_RXFREE0_QUEUE},
333 };
334
335 /*****************************************************************************
336 * utility functions
337 ****************************************************************************/
338
339 static inline struct port* dev_to_port(struct net_device *dev)
340 {
341 return dev_to_hdlc(dev)->priv;
342 }
343
344 #ifndef __ARMEB__
345 static inline void memcpy_swab32(u32 *dest, u32 *src, int cnt)
346 {
347 int i;
348 for (i = 0; i < cnt; i++)
349 dest[i] = swab32(src[i]);
350 }
351 #endif
352
353 /*****************************************************************************
354 * HSS access
355 ****************************************************************************/
356
357 static void hss_npe_send(struct port *port, struct msg *msg, const char* what)
358 {
359 u32 *val = (u32*)msg;
360 if (npe_send_message(port->npe, msg, what)) {
361 printk(KERN_CRIT "HSS-%i: unable to send command [%08X:%08X]"
362 " to %s\n", port->id, val[0], val[1],
363 npe_name(port->npe));
364 BUG();
365 }
366 }
367
368 static void hss_config_set_lut(struct port *port)
369 {
370 struct msg msg;
371 int ch;
372
373 memset(&msg, 0, sizeof(msg));
374 msg.cmd = PORT_CONFIG_WRITE;
375 msg.hss_port = port->id;
376
377 for (ch = 0; ch < MAX_CHANNELS; ch++) {
378 msg.data32 >>= 2;
379 msg.data32 |= TDMMAP_HDLC << 30;
380
381 if (ch % 16 == 15) {
382 msg.index = HSS_CONFIG_TX_LUT + ((ch / 4) & ~3);
383 hss_npe_send(port, &msg, "HSS_SET_TX_LUT");
384
385 msg.index += HSS_CONFIG_RX_LUT - HSS_CONFIG_TX_LUT;
386 hss_npe_send(port, &msg, "HSS_SET_RX_LUT");
387 }
388 }
389 }
390
391 static void hss_config(struct port *port)
392 {
393 struct msg msg;
394
395 memset(&msg, 0, sizeof(msg));
396 msg.cmd = PORT_CONFIG_WRITE;
397 msg.hss_port = port->id;
398 msg.index = HSS_CONFIG_TX_PCR;
399 msg.data32 = PCR_FRM_PULSE_DISABLED | PCR_MSB_ENDIAN |
400 PCR_TX_DATA_ENABLE | PCR_SOF_NO_FBIT;
401 if (port->clock_type == CLOCK_INT)
402 msg.data32 |= PCR_SYNC_CLK_DIR_OUTPUT;
403 hss_npe_send(port, &msg, "HSS_SET_TX_PCR");
404
405 msg.index = HSS_CONFIG_RX_PCR;
406 msg.data32 ^= PCR_TX_DATA_ENABLE | PCR_DCLK_EDGE_RISING;
407 hss_npe_send(port, &msg, "HSS_SET_RX_PCR");
408
409 memset(&msg, 0, sizeof(msg));
410 msg.cmd = PORT_CONFIG_WRITE;
411 msg.hss_port = port->id;
412 msg.index = HSS_CONFIG_CORE_CR;
413 msg.data32 = (port->loopback ? CCR_LOOPBACK : 0) |
414 (port->id ? CCR_SECOND_HSS : 0);
415 hss_npe_send(port, &msg, "HSS_SET_CORE_CR");
416
417 memset(&msg, 0, sizeof(msg));
418 msg.cmd = PORT_CONFIG_WRITE;
419 msg.hss_port = port->id;
420 msg.index = HSS_CONFIG_CLOCK_CR;
421 msg.data32 = port->clock_reg;
422 hss_npe_send(port, &msg, "HSS_SET_CLOCK_CR");
423
424 memset(&msg, 0, sizeof(msg));
425 msg.cmd = PORT_CONFIG_WRITE;
426 msg.hss_port = port->id;
427 msg.index = HSS_CONFIG_TX_FCR;
428 msg.data16a = FRAME_OFFSET;
429 msg.data16b = FRAME_SIZE - 1;
430 hss_npe_send(port, &msg, "HSS_SET_TX_FCR");
431
432 memset(&msg, 0, sizeof(msg));
433 msg.cmd = PORT_CONFIG_WRITE;
434 msg.hss_port = port->id;
435 msg.index = HSS_CONFIG_RX_FCR;
436 msg.data16a = FRAME_OFFSET;
437 msg.data16b = FRAME_SIZE - 1;
438 hss_npe_send(port, &msg, "HSS_SET_RX_FCR");
439
440 hss_config_set_lut(port);
441
442 memset(&msg, 0, sizeof(msg));
443 msg.cmd = PORT_CONFIG_LOAD;
444 msg.hss_port = port->id;
445 hss_npe_send(port, &msg, "HSS_LOAD_CONFIG");
446
447 if (npe_recv_message(port->npe, &msg, "HSS_LOAD_CONFIG") ||
448 /* HSS_LOAD_CONFIG for port #1 returns port_id = #4 */
449 msg.cmd != PORT_CONFIG_LOAD || msg.data32) {
450 printk(KERN_CRIT "HSS-%i: HSS_LOAD_CONFIG failed\n",
451 port->id);
452 BUG();
453 }
454
455 npe_recv_message(port->npe, &msg, "FLUSH_IT");
456 }
457
458 static void hss_set_hdlc_cfg(struct port *port)
459 {
460 struct msg msg;
461
462 memset(&msg, 0, sizeof(msg));
463 msg.cmd = PKT_PIPE_HDLC_CFG_WRITE;
464 msg.hss_port = port->id;
465 msg.data8a = port->hdlc_cfg; /* rx_cfg */
466 msg.data8b = port->hdlc_cfg | (PKT_EXTRA_FLAGS << 3); /* tx_cfg */
467 hss_npe_send(port, &msg, "HSS_SET_HDLC_CFG");
468 }
469
470 static u32 hss_get_status(struct port *port)
471 {
472 struct msg msg;
473
474 memset(&msg, 0, sizeof(msg));
475 msg.cmd = PORT_ERROR_READ;
476 msg.hss_port = port->id;
477 hss_npe_send(port, &msg, "PORT_ERROR_READ");
478 if (npe_recv_message(port->npe, &msg, "PORT_ERROR_READ")) {
479 printk(KERN_CRIT "HSS-%i: unable to read HSS status\n",
480 port->id);
481 BUG();
482 }
483
484 return msg.data32;
485 }
486
487 static void hss_start_hdlc(struct port *port)
488 {
489 struct msg msg;
490
491 memset(&msg, 0, sizeof(msg));
492 msg.cmd = PKT_PIPE_FLOW_ENABLE;
493 msg.hss_port = port->id;
494 msg.data32 = 0;
495 hss_npe_send(port, &msg, "HSS_ENABLE_PKT_PIPE");
496 }
497
498 static void hss_stop_hdlc(struct port *port)
499 {
500 struct msg msg;
501
502 memset(&msg, 0, sizeof(msg));
503 msg.cmd = PKT_PIPE_FLOW_DISABLE;
504 msg.hss_port = port->id;
505 hss_npe_send(port, &msg, "HSS_DISABLE_PKT_PIPE");
506 hss_get_status(port); /* make sure it's halted */
507 }
508
509 static int hss_load_firmware(struct port *port)
510 {
511 struct msg msg;
512 int err;
513
514 if (port->initialized)
515 return 0;
516
517 if (!npe_running(port->npe) &&
518 (err = npe_load_firmware(port->npe, npe_name(port->npe),
519 port->dev)))
520 return err;
521
522 /* HDLC mode configuration */
523 memset(&msg, 0, sizeof(msg));
524 msg.cmd = PKT_NUM_PIPES_WRITE;
525 msg.hss_port = port->id;
526 msg.data8a = PKT_NUM_PIPES;
527 hss_npe_send(port, &msg, "HSS_SET_PKT_PIPES");
528
529 msg.cmd = PKT_PIPE_FIFO_SIZEW_WRITE;
530 msg.data8a = PKT_PIPE_FIFO_SIZEW;
531 hss_npe_send(port, &msg, "HSS_SET_PKT_FIFO");
532
533 msg.cmd = PKT_PIPE_MODE_WRITE;
534 msg.data8a = NPE_PKT_MODE_HDLC;
535 /* msg.data8b = inv_mask */
536 /* msg.data8c = or_mask */
537 hss_npe_send(port, &msg, "HSS_SET_PKT_MODE");
538
539 msg.cmd = PKT_PIPE_RX_SIZE_WRITE;
540 msg.data16a = HDLC_MAX_MRU; /* including CRC */
541 hss_npe_send(port, &msg, "HSS_SET_PKT_RX_SIZE");
542
543 msg.cmd = PKT_PIPE_IDLE_PATTERN_WRITE;
544 msg.data32 = 0x7F7F7F7F;
545 hss_npe_send(port, &msg, "HSS_SET_PKT_IDLE");
546
547 port->initialized = 1;
548 return 0;
549 }
550
551 /*****************************************************************************
552 * packetized (HDLC) operation
553 ****************************************************************************/
554
555 static inline void debug_pkt(struct net_device *dev, const char *func,
556 u8 *data, int len)
557 {
558 #if DEBUG_PKT_BYTES
559 int i;
560
561 printk(KERN_DEBUG "%s: %s(%i)", dev->name, func, len);
562 for (i = 0; i < len; i++) {
563 if (i >= DEBUG_PKT_BYTES)
564 break;
565 printk("%s%02X", !(i % 4) ? " " : "", data[i]);
566 }
567 printk("\n");
568 #endif
569 }
570
571
572 static inline void debug_desc(u32 phys, struct desc *desc)
573 {
574 #if DEBUG_DESC
575 printk(KERN_DEBUG "%X: %X %3X %3X %08X %X %X\n",
576 phys, desc->next, desc->buf_len, desc->pkt_len,
577 desc->data, desc->status, desc->error_count);
578 #endif
579 }
580
581 static inline int queue_get_desc(unsigned int queue, struct port *port,
582 int is_tx)
583 {
584 u32 phys, tab_phys, n_desc;
585 struct desc *tab;
586
587 if (!(phys = qmgr_get_entry(queue)))
588 return -1;
589
590 BUG_ON(phys & 0x1F);
591 tab_phys = is_tx ? tx_desc_phys(port, 0) : rx_desc_phys(port, 0);
592 tab = is_tx ? tx_desc_ptr(port, 0) : rx_desc_ptr(port, 0);
593 n_desc = (phys - tab_phys) / sizeof(struct desc);
594 BUG_ON(n_desc >= (is_tx ? TX_DESCS : RX_DESCS));
595 debug_desc(phys, &tab[n_desc]);
596 BUG_ON(tab[n_desc].next);
597 return n_desc;
598 }
599
600 static inline void queue_put_desc(unsigned int queue, u32 phys,
601 struct desc *desc)
602 {
603 debug_desc(phys, desc);
604 BUG_ON(phys & 0x1F);
605 qmgr_put_entry(queue, phys);
606 /* Don't check for queue overflow here, we've allocated sufficient
607 length and queues >= 32 don't support this check anyway. */
608 }
609
610
611 static inline void dma_unmap_tx(struct port *port, struct desc *desc)
612 {
613 #ifdef __ARMEB__
614 dma_unmap_single(&port->netdev->dev, desc->data,
615 desc->buf_len, DMA_TO_DEVICE);
616 #else
617 dma_unmap_single(&port->netdev->dev, desc->data & ~3,
618 ALIGN((desc->data & 3) + desc->buf_len, 4),
619 DMA_TO_DEVICE);
620 #endif
621 }
622
623
624 static void hss_hdlc_set_carrier(void *pdev, int carrier)
625 {
626 struct net_device *netdev = pdev;
627 struct port *port = dev_to_port(netdev);
628 unsigned long flags;
629
630 spin_lock_irqsave(&npe_lock, flags);
631 port->carrier = carrier;
632 if (!port->loopback) {
633 if (carrier)
634 netif_carrier_on(netdev);
635 else
636 netif_carrier_off(netdev);
637 }
638 spin_unlock_irqrestore(&npe_lock, flags);
639 }
640
641 static void hss_hdlc_rx_irq(void *pdev)
642 {
643 struct net_device *dev = pdev;
644 struct port *port = dev_to_port(dev);
645
646 #if DEBUG_RX
647 printk(KERN_DEBUG "%s: hss_hdlc_rx_irq\n", dev->name);
648 #endif
649 qmgr_disable_irq(queue_ids[port->id].rx);
650 napi_schedule(&port->napi);
651 }
652
653 static int hss_hdlc_poll(struct napi_struct *napi, int budget)
654 {
655 struct port *port = container_of(napi, struct port, napi);
656 struct net_device *dev = port->netdev;
657 unsigned int rxq = queue_ids[port->id].rx;
658 unsigned int rxfreeq = queue_ids[port->id].rxfree;
659 int received = 0;
660
661 #if DEBUG_RX
662 printk(KERN_DEBUG "%s: hss_hdlc_poll\n", dev->name);
663 #endif
664
665 while (received < budget) {
666 struct sk_buff *skb;
667 struct desc *desc;
668 int n;
669 #ifdef __ARMEB__
670 struct sk_buff *temp;
671 u32 phys;
672 #endif
673
674 if ((n = queue_get_desc(rxq, port, 0)) < 0) {
675 #if DEBUG_RX
676 printk(KERN_DEBUG "%s: hss_hdlc_poll"
677 " napi_complete\n", dev->name);
678 #endif
679 napi_complete(napi);
680 qmgr_enable_irq(rxq);
681 if (!qmgr_stat_empty(rxq) &&
682 napi_reschedule(napi)) {
683 #if DEBUG_RX
684 printk(KERN_DEBUG "%s: hss_hdlc_poll"
685 " napi_reschedule succeeded\n",
686 dev->name);
687 #endif
688 qmgr_disable_irq(rxq);
689 continue;
690 }
691 #if DEBUG_RX
692 printk(KERN_DEBUG "%s: hss_hdlc_poll all done\n",
693 dev->name);
694 #endif
695 return received; /* all work done */
696 }
697
698 desc = rx_desc_ptr(port, n);
699 skb = NULL;
700 switch (desc->status) {
701 case 0:
702 #ifdef __ARMEB__
703 if ((skb = netdev_alloc_skb(dev, RX_SIZE)) != NULL) {
704 phys = dma_map_single(&dev->dev, skb->data,
705 RX_SIZE,
706 DMA_FROM_DEVICE);
707 if (dma_mapping_error(&dev->dev, phys)) {
708 dev_kfree_skb(skb);
709 skb = NULL;
710 }
711 }
712 #else
713 skb = netdev_alloc_skb(dev, desc->pkt_len);
714 #endif
715 if (!skb)
716 dev->stats.rx_dropped++;
717 break;
718 case ERR_HDLC_ALIGN:
719 case ERR_HDLC_ABORT:
720 dev->stats.rx_frame_errors++;
721 dev->stats.rx_errors++;
722 break;
723 case ERR_HDLC_FCS:
724 dev->stats.rx_crc_errors++;
725 dev->stats.rx_errors++;
726 break;
727 case ERR_HDLC_TOO_LONG:
728 dev->stats.rx_length_errors++;
729 dev->stats.rx_errors++;
730 break;
731 default:
732 printk(KERN_ERR "%s: hss_hdlc_poll: status 0x%02X"
733 " errors %u\n", dev->name, desc->status,
734 desc->error_count);
735 dev->stats.rx_errors++;
736 }
737
738 if (!skb) {
739 /* put the desc back on RX-ready queue */
740 desc->buf_len = RX_SIZE;
741 desc->pkt_len = desc->status = 0;
742 queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
743 continue;
744 }
745
746 /* process received frame */
747 #ifdef __ARMEB__
748 temp = skb;
749 skb = port->rx_buff_tab[n];
750 dma_unmap_single(&dev->dev, desc->data,
751 RX_SIZE, DMA_FROM_DEVICE);
752 #else
753 dma_sync_single_for_cpu(&dev->dev, desc->data,
754 RX_SIZE, DMA_FROM_DEVICE);
755 memcpy_swab32((u32 *)skb->data, (u32 *)port->rx_buff_tab[n],
756 ALIGN(desc->pkt_len, 4) / 4);
757 #endif
758 skb_put(skb, desc->pkt_len);
759
760 debug_pkt(dev, "hss_hdlc_poll", skb->data, skb->len);
761
762 skb->protocol = hdlc_type_trans(skb, dev);
763 dev->stats.rx_packets++;
764 dev->stats.rx_bytes += skb->len;
765 netif_receive_skb(skb);
766
767 /* put the new buffer on RX-free queue */
768 #ifdef __ARMEB__
769 port->rx_buff_tab[n] = temp;
770 desc->data = phys;
771 #endif
772 desc->buf_len = RX_SIZE;
773 desc->pkt_len = 0;
774 queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
775 received++;
776 }
777 #if DEBUG_RX
778 printk(KERN_DEBUG "hss_hdlc_poll: end, not all work done\n");
779 #endif
780 return received; /* not all work done */
781 }
782
783
784 static void hss_hdlc_txdone_irq(void *pdev)
785 {
786 struct net_device *dev = pdev;
787 struct port *port = dev_to_port(dev);
788 int n_desc;
789
790 #if DEBUG_TX
791 printk(KERN_DEBUG DRV_NAME ": hss_hdlc_txdone_irq\n");
792 #endif
793 while ((n_desc = queue_get_desc(queue_ids[port->id].txdone,
794 port, 1)) >= 0) {
795 struct desc *desc;
796 int start;
797
798 desc = tx_desc_ptr(port, n_desc);
799
800 dev->stats.tx_packets++;
801 dev->stats.tx_bytes += desc->pkt_len;
802
803 dma_unmap_tx(port, desc);
804 #if DEBUG_TX
805 printk(KERN_DEBUG "%s: hss_hdlc_txdone_irq free %p\n",
806 dev->name, port->tx_buff_tab[n_desc]);
807 #endif
808 free_buffer_irq(port->tx_buff_tab[n_desc]);
809 port->tx_buff_tab[n_desc] = NULL;
810
811 start = qmgr_stat_below_low_watermark(port->plat->txreadyq);
812 queue_put_desc(port->plat->txreadyq,
813 tx_desc_phys(port, n_desc), desc);
814 if (start) { /* TX-ready queue was empty */
815 #if DEBUG_TX
816 printk(KERN_DEBUG "%s: hss_hdlc_txdone_irq xmit"
817 " ready\n", dev->name);
818 #endif
819 netif_wake_queue(dev);
820 }
821 }
822 }
823
824 static int hss_hdlc_xmit(struct sk_buff *skb, struct net_device *dev)
825 {
826 struct port *port = dev_to_port(dev);
827 unsigned int txreadyq = port->plat->txreadyq;
828 int len, offset, bytes, n;
829 void *mem;
830 u32 phys;
831 struct desc *desc;
832
833 #if DEBUG_TX
834 printk(KERN_DEBUG "%s: hss_hdlc_xmit\n", dev->name);
835 #endif
836
837 if (unlikely(skb->len > HDLC_MAX_MRU)) {
838 dev_kfree_skb(skb);
839 dev->stats.tx_errors++;
840 return NETDEV_TX_OK;
841 }
842
843 debug_pkt(dev, "hss_hdlc_xmit", skb->data, skb->len);
844
845 len = skb->len;
846 #ifdef __ARMEB__
847 offset = 0; /* no need to keep alignment */
848 bytes = len;
849 mem = skb->data;
850 #else
851 offset = (int)skb->data & 3; /* keep 32-bit alignment */
852 bytes = ALIGN(offset + len, 4);
853 if (!(mem = kmalloc(bytes, GFP_ATOMIC))) {
854 dev_kfree_skb(skb);
855 dev->stats.tx_dropped++;
856 return NETDEV_TX_OK;
857 }
858 memcpy_swab32(mem, (u32 *)((int)skb->data & ~3), bytes / 4);
859 dev_kfree_skb(skb);
860 #endif
861
862 phys = dma_map_single(&dev->dev, mem, bytes, DMA_TO_DEVICE);
863 if (dma_mapping_error(&dev->dev, phys)) {
864 #ifdef __ARMEB__
865 dev_kfree_skb(skb);
866 #else
867 kfree(mem);
868 #endif
869 dev->stats.tx_dropped++;
870 return NETDEV_TX_OK;
871 }
872
873 n = queue_get_desc(txreadyq, port, 1);
874 BUG_ON(n < 0);
875 desc = tx_desc_ptr(port, n);
876
877 #ifdef __ARMEB__
878 port->tx_buff_tab[n] = skb;
879 #else
880 port->tx_buff_tab[n] = mem;
881 #endif
882 desc->data = phys + offset;
883 desc->buf_len = desc->pkt_len = len;
884
885 wmb();
886 queue_put_desc(queue_ids[port->id].tx, tx_desc_phys(port, n), desc);
887
888 if (qmgr_stat_below_low_watermark(txreadyq)) { /* empty */
889 #if DEBUG_TX
890 printk(KERN_DEBUG "%s: hss_hdlc_xmit queue full\n", dev->name);
891 #endif
892 netif_stop_queue(dev);
893 /* we could miss TX ready interrupt */
894 if (!qmgr_stat_below_low_watermark(txreadyq)) {
895 #if DEBUG_TX
896 printk(KERN_DEBUG "%s: hss_hdlc_xmit ready again\n",
897 dev->name);
898 #endif
899 netif_wake_queue(dev);
900 }
901 }
902
903 #if DEBUG_TX
904 printk(KERN_DEBUG "%s: hss_hdlc_xmit end\n", dev->name);
905 #endif
906 return NETDEV_TX_OK;
907 }
908
909
910 static int request_hdlc_queues(struct port *port)
911 {
912 int err;
913
914 err = qmgr_request_queue(queue_ids[port->id].rxfree, RX_DESCS, 0, 0,
915 "%s:RX-free", port->netdev->name);
916 if (err)
917 return err;
918
919 err = qmgr_request_queue(queue_ids[port->id].rx, RX_DESCS, 0, 0,
920 "%s:RX", port->netdev->name);
921 if (err)
922 goto rel_rxfree;
923
924 err = qmgr_request_queue(queue_ids[port->id].tx, TX_DESCS, 0, 0,
925 "%s:TX", port->netdev->name);
926 if (err)
927 goto rel_rx;
928
929 err = qmgr_request_queue(port->plat->txreadyq, TX_DESCS, 0, 0,
930 "%s:TX-ready", port->netdev->name);
931 if (err)
932 goto rel_tx;
933
934 err = qmgr_request_queue(queue_ids[port->id].txdone, TX_DESCS, 0, 0,
935 "%s:TX-done", port->netdev->name);
936 if (err)
937 goto rel_txready;
938 return 0;
939
940 rel_txready:
941 qmgr_release_queue(port->plat->txreadyq);
942 rel_tx:
943 qmgr_release_queue(queue_ids[port->id].tx);
944 rel_rx:
945 qmgr_release_queue(queue_ids[port->id].rx);
946 rel_rxfree:
947 qmgr_release_queue(queue_ids[port->id].rxfree);
948 printk(KERN_DEBUG "%s: unable to request hardware queues\n",
949 port->netdev->name);
950 return err;
951 }
952
953 static void release_hdlc_queues(struct port *port)
954 {
955 qmgr_release_queue(queue_ids[port->id].rxfree);
956 qmgr_release_queue(queue_ids[port->id].rx);
957 qmgr_release_queue(queue_ids[port->id].txdone);
958 qmgr_release_queue(queue_ids[port->id].tx);
959 qmgr_release_queue(port->plat->txreadyq);
960 }
961
962 static int init_hdlc_queues(struct port *port)
963 {
964 int i;
965
966 if (!ports_open)
967 if (!(dma_pool = dma_pool_create(DRV_NAME, NULL,
968 POOL_ALLOC_SIZE, 32, 0)))
969 return -ENOMEM;
970
971 if (!(port->desc_tab = dma_pool_alloc(dma_pool, GFP_KERNEL,
972 &port->desc_tab_phys)))
973 return -ENOMEM;
974 memset(port->desc_tab, 0, POOL_ALLOC_SIZE);
975 memset(port->rx_buff_tab, 0, sizeof(port->rx_buff_tab)); /* tables */
976 memset(port->tx_buff_tab, 0, sizeof(port->tx_buff_tab));
977
978 /* Setup RX buffers */
979 for (i = 0; i < RX_DESCS; i++) {
980 struct desc *desc = rx_desc_ptr(port, i);
981 buffer_t *buff;
982 void *data;
983 #ifdef __ARMEB__
984 if (!(buff = netdev_alloc_skb(port->netdev, RX_SIZE)))
985 return -ENOMEM;
986 data = buff->data;
987 #else
988 if (!(buff = kmalloc(RX_SIZE, GFP_KERNEL)))
989 return -ENOMEM;
990 data = buff;
991 #endif
992 desc->buf_len = RX_SIZE;
993 desc->data = dma_map_single(&port->netdev->dev, data,
994 RX_SIZE, DMA_FROM_DEVICE);
995 if (dma_mapping_error(&port->netdev->dev, desc->data)) {
996 free_buffer(buff);
997 return -EIO;
998 }
999 port->rx_buff_tab[i] = buff;
1000 }
1001
1002 return 0;
1003 }
1004
1005 static void destroy_hdlc_queues(struct port *port)
1006 {
1007 int i;
1008
1009 if (port->desc_tab) {
1010 for (i = 0; i < RX_DESCS; i++) {
1011 struct desc *desc = rx_desc_ptr(port, i);
1012 buffer_t *buff = port->rx_buff_tab[i];
1013 if (buff) {
1014 dma_unmap_single(&port->netdev->dev,
1015 desc->data, RX_SIZE,
1016 DMA_FROM_DEVICE);
1017 free_buffer(buff);
1018 }
1019 }
1020 for (i = 0; i < TX_DESCS; i++) {
1021 struct desc *desc = tx_desc_ptr(port, i);
1022 buffer_t *buff = port->tx_buff_tab[i];
1023 if (buff) {
1024 dma_unmap_tx(port, desc);
1025 free_buffer(buff);
1026 }
1027 }
1028 dma_pool_free(dma_pool, port->desc_tab, port->desc_tab_phys);
1029 port->desc_tab = NULL;
1030 }
1031
1032 if (!ports_open && dma_pool) {
1033 dma_pool_destroy(dma_pool);
1034 dma_pool = NULL;
1035 }
1036 }
1037
1038 static int hss_hdlc_open(struct net_device *dev)
1039 {
1040 struct port *port = dev_to_port(dev);
1041 unsigned long flags;
1042 int i, err = 0;
1043
1044 if ((err = hdlc_open(dev)))
1045 return err;
1046
1047 if ((err = hss_load_firmware(port)))
1048 goto err_hdlc_close;
1049
1050 if ((err = request_hdlc_queues(port)))
1051 goto err_hdlc_close;
1052
1053 if ((err = init_hdlc_queues(port)))
1054 goto err_destroy_queues;
1055
1056 spin_lock_irqsave(&npe_lock, flags);
1057 if (port->plat->open)
1058 if ((err = port->plat->open(port->id, dev,
1059 hss_hdlc_set_carrier)))
1060 goto err_unlock;
1061 spin_unlock_irqrestore(&npe_lock, flags);
1062
1063 /* Populate queues with buffers, no failure after this point */
1064 for (i = 0; i < TX_DESCS; i++)
1065 queue_put_desc(port->plat->txreadyq,
1066 tx_desc_phys(port, i), tx_desc_ptr(port, i));
1067
1068 for (i = 0; i < RX_DESCS; i++)
1069 queue_put_desc(queue_ids[port->id].rxfree,
1070 rx_desc_phys(port, i), rx_desc_ptr(port, i));
1071
1072 napi_enable(&port->napi);
1073 netif_start_queue(dev);
1074
1075 qmgr_set_irq(queue_ids[port->id].rx, QUEUE_IRQ_SRC_NOT_EMPTY,
1076 hss_hdlc_rx_irq, dev);
1077
1078 qmgr_set_irq(queue_ids[port->id].txdone, QUEUE_IRQ_SRC_NOT_EMPTY,
1079 hss_hdlc_txdone_irq, dev);
1080 qmgr_enable_irq(queue_ids[port->id].txdone);
1081
1082 ports_open++;
1083
1084 hss_set_hdlc_cfg(port);
1085 hss_config(port);
1086
1087 hss_start_hdlc(port);
1088
1089 /* we may already have RX data, enables IRQ */
1090 napi_schedule(&port->napi);
1091 return 0;
1092
1093 err_unlock:
1094 spin_unlock_irqrestore(&npe_lock, flags);
1095 err_destroy_queues:
1096 destroy_hdlc_queues(port);
1097 release_hdlc_queues(port);
1098 err_hdlc_close:
1099 hdlc_close(dev);
1100 return err;
1101 }
1102
1103 static int hss_hdlc_close(struct net_device *dev)
1104 {
1105 struct port *port = dev_to_port(dev);
1106 unsigned long flags;
1107 int i, buffs = RX_DESCS; /* allocated RX buffers */
1108
1109 spin_lock_irqsave(&npe_lock, flags);
1110 ports_open--;
1111 qmgr_disable_irq(queue_ids[port->id].rx);
1112 netif_stop_queue(dev);
1113 napi_disable(&port->napi);
1114
1115 hss_stop_hdlc(port);
1116
1117 while (queue_get_desc(queue_ids[port->id].rxfree, port, 0) >= 0)
1118 buffs--;
1119 while (queue_get_desc(queue_ids[port->id].rx, port, 0) >= 0)
1120 buffs--;
1121
1122 if (buffs)
1123 printk(KERN_CRIT "%s: unable to drain RX queue, %i buffer(s)"
1124 " left in NPE\n", dev->name, buffs);
1125
1126 buffs = TX_DESCS;
1127 while (queue_get_desc(queue_ids[port->id].tx, port, 1) >= 0)
1128 buffs--; /* cancel TX */
1129
1130 i = 0;
1131 do {
1132 while (queue_get_desc(port->plat->txreadyq, port, 1) >= 0)
1133 buffs--;
1134 if (!buffs)
1135 break;
1136 } while (++i < MAX_CLOSE_WAIT);
1137
1138 if (buffs)
1139 printk(KERN_CRIT "%s: unable to drain TX queue, %i buffer(s) "
1140 "left in NPE\n", dev->name, buffs);
1141 #if DEBUG_CLOSE
1142 if (!buffs)
1143 printk(KERN_DEBUG "Draining TX queues took %i cycles\n", i);
1144 #endif
1145 qmgr_disable_irq(queue_ids[port->id].txdone);
1146
1147 if (port->plat->close)
1148 port->plat->close(port->id, dev);
1149 spin_unlock_irqrestore(&npe_lock, flags);
1150
1151 destroy_hdlc_queues(port);
1152 release_hdlc_queues(port);
1153 hdlc_close(dev);
1154 return 0;
1155 }
1156
1157
1158 static int hss_hdlc_attach(struct net_device *dev, unsigned short encoding,
1159 unsigned short parity)
1160 {
1161 struct port *port = dev_to_port(dev);
1162
1163 if (encoding != ENCODING_NRZ)
1164 return -EINVAL;
1165
1166 switch(parity) {
1167 case PARITY_CRC16_PR1_CCITT:
1168 port->hdlc_cfg = 0;
1169 return 0;
1170
1171 case PARITY_CRC32_PR1_CCITT:
1172 port->hdlc_cfg = PKT_HDLC_CRC_32;
1173 return 0;
1174
1175 default:
1176 return -EINVAL;
1177 }
1178 }
1179
1180 static u32 check_clock(u32 rate, u32 a, u32 b, u32 c,
1181 u32 *best, u32 *best_diff, u32 *reg)
1182 {
1183 /* a is 10-bit, b is 10-bit, c is 12-bit */
1184 u64 new_rate;
1185 u32 new_diff;
1186
1187 new_rate = ixp4xx_timer_freq * (u64)(c + 1);
1188 do_div(new_rate, a * (c + 1) + b + 1);
1189 new_diff = abs((u32)new_rate - rate);
1190
1191 if (new_diff < *best_diff) {
1192 *best = new_rate;
1193 *best_diff = new_diff;
1194 *reg = (a << 22) | (b << 12) | c;
1195 }
1196 return new_diff;
1197 }
1198
1199 static void find_best_clock(u32 rate, u32 *best, u32 *reg)
1200 {
1201 u32 a, b, diff = 0xFFFFFFFF;
1202
1203 a = ixp4xx_timer_freq / rate;
1204
1205 if (a > 0x3FF) { /* 10-bit value - we can go as slow as ca. 65 kb/s */
1206 check_clock(rate, 0x3FF, 1, 1, best, &diff, reg);
1207 return;
1208 }
1209 if (a == 0) { /* > 66.666 MHz */
1210 a = 1; /* minimum divider is 1 (a = 0, b = 1, c = 1) */
1211 rate = ixp4xx_timer_freq;
1212 }
1213
1214 if (rate * a == ixp4xx_timer_freq) { /* don't divide by 0 later */
1215 check_clock(rate, a - 1, 1, 1, best, &diff, reg);
1216 return;
1217 }
1218
1219 for (b = 0; b < 0x400; b++) {
1220 u64 c = (b + 1) * (u64)rate;
1221 do_div(c, ixp4xx_timer_freq - rate * a);
1222 c--;
1223 if (c >= 0xFFF) { /* 12-bit - no need to check more 'b's */
1224 if (b == 0 && /* also try a bit higher rate */
1225 !check_clock(rate, a - 1, 1, 1, best, &diff, reg))
1226 return;
1227 check_clock(rate, a, b, 0xFFF, best, &diff, reg);
1228 return;
1229 }
1230 if (!check_clock(rate, a, b, c, best, &diff, reg))
1231 return;
1232 if (!check_clock(rate, a, b, c + 1, best, &diff, reg))
1233 return;
1234 }
1235 }
1236
1237 static int hss_hdlc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1238 {
1239 const size_t size = sizeof(sync_serial_settings);
1240 sync_serial_settings new_line;
1241 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1242 struct port *port = dev_to_port(dev);
1243 unsigned long flags;
1244 int clk;
1245
1246 if (cmd != SIOCWANDEV)
1247 return hdlc_ioctl(dev, ifr, cmd);
1248
1249 switch(ifr->ifr_settings.type) {
1250 case IF_GET_IFACE:
1251 ifr->ifr_settings.type = IF_IFACE_V35;
1252 if (ifr->ifr_settings.size < size) {
1253 ifr->ifr_settings.size = size; /* data size wanted */
1254 return -ENOBUFS;
1255 }
1256 memset(&new_line, 0, sizeof(new_line));
1257 new_line.clock_type = port->clock_type;
1258 new_line.clock_rate = port->clock_rate;
1259 new_line.loopback = port->loopback;
1260 if (copy_to_user(line, &new_line, size))
1261 return -EFAULT;
1262 return 0;
1263
1264 case IF_IFACE_SYNC_SERIAL:
1265 case IF_IFACE_V35:
1266 if(!capable(CAP_NET_ADMIN))
1267 return -EPERM;
1268 if (copy_from_user(&new_line, line, size))
1269 return -EFAULT;
1270
1271 clk = new_line.clock_type;
1272 if (port->plat->set_clock)
1273 clk = port->plat->set_clock(port->id, clk);
1274
1275 if (clk != CLOCK_EXT && clk != CLOCK_INT)
1276 return -EINVAL; /* No such clock setting */
1277
1278 if (new_line.loopback != 0 && new_line.loopback != 1)
1279 return -EINVAL;
1280
1281 port->clock_type = clk; /* Update settings */
1282 if (clk == CLOCK_INT)
1283 find_best_clock(new_line.clock_rate, &port->clock_rate,
1284 &port->clock_reg);
1285 else {
1286 port->clock_rate = 0;
1287 port->clock_reg = CLK42X_SPEED_2048KHZ;
1288 }
1289 port->loopback = new_line.loopback;
1290
1291 spin_lock_irqsave(&npe_lock, flags);
1292
1293 if (dev->flags & IFF_UP)
1294 hss_config(port);
1295
1296 if (port->loopback || port->carrier)
1297 netif_carrier_on(port->netdev);
1298 else
1299 netif_carrier_off(port->netdev);
1300 spin_unlock_irqrestore(&npe_lock, flags);
1301
1302 return 0;
1303
1304 default:
1305 return hdlc_ioctl(dev, ifr, cmd);
1306 }
1307 }
1308
1309 /*****************************************************************************
1310 * initialization
1311 ****************************************************************************/
1312
1313 static const struct net_device_ops hss_hdlc_ops = {
1314 .ndo_open = hss_hdlc_open,
1315 .ndo_stop = hss_hdlc_close,
1316 .ndo_change_mtu = hdlc_change_mtu,
1317 .ndo_start_xmit = hdlc_start_xmit,
1318 .ndo_do_ioctl = hss_hdlc_ioctl,
1319 };
1320
1321 static int __devinit hss_init_one(struct platform_device *pdev)
1322 {
1323 struct port *port;
1324 struct net_device *dev;
1325 hdlc_device *hdlc;
1326 int err;
1327
1328 if ((port = kzalloc(sizeof(*port), GFP_KERNEL)) == NULL)
1329 return -ENOMEM;
1330
1331 if ((port->npe = npe_request(0)) == NULL) {
1332 err = -ENODEV;
1333 goto err_free;
1334 }
1335
1336 if ((port->netdev = dev = alloc_hdlcdev(port)) == NULL) {
1337 err = -ENOMEM;
1338 goto err_plat;
1339 }
1340
1341 SET_NETDEV_DEV(dev, &pdev->dev);
1342 hdlc = dev_to_hdlc(dev);
1343 hdlc->attach = hss_hdlc_attach;
1344 hdlc->xmit = hss_hdlc_xmit;
1345 dev->netdev_ops = &hss_hdlc_ops;
1346 dev->tx_queue_len = 100;
1347 port->clock_type = CLOCK_EXT;
1348 port->clock_rate = 0;
1349 port->clock_reg = CLK42X_SPEED_2048KHZ;
1350 port->id = pdev->id;
1351 port->dev = &pdev->dev;
1352 port->plat = pdev->dev.platform_data;
1353 netif_napi_add(dev, &port->napi, hss_hdlc_poll, NAPI_WEIGHT);
1354
1355 if ((err = register_hdlc_device(dev)))
1356 goto err_free_netdev;
1357
1358 platform_set_drvdata(pdev, port);
1359
1360 printk(KERN_INFO "%s: HSS-%i\n", dev->name, port->id);
1361 return 0;
1362
1363 err_free_netdev:
1364 free_netdev(dev);
1365 err_plat:
1366 npe_release(port->npe);
1367 err_free:
1368 kfree(port);
1369 return err;
1370 }
1371
1372 static int __devexit hss_remove_one(struct platform_device *pdev)
1373 {
1374 struct port *port = platform_get_drvdata(pdev);
1375
1376 unregister_hdlc_device(port->netdev);
1377 free_netdev(port->netdev);
1378 npe_release(port->npe);
1379 platform_set_drvdata(pdev, NULL);
1380 kfree(port);
1381 return 0;
1382 }
1383
1384 static struct platform_driver ixp4xx_hss_driver = {
1385 .driver.name = DRV_NAME,
1386 .probe = hss_init_one,
1387 .remove = hss_remove_one,
1388 };
1389
1390 static int __init hss_init_module(void)
1391 {
1392 if ((ixp4xx_read_feature_bits() &
1393 (IXP4XX_FEATURE_HDLC | IXP4XX_FEATURE_HSS)) !=
1394 (IXP4XX_FEATURE_HDLC | IXP4XX_FEATURE_HSS))
1395 return -ENODEV;
1396
1397 spin_lock_init(&npe_lock);
1398
1399 return platform_driver_register(&ixp4xx_hss_driver);
1400 }
1401
1402 static void __exit hss_cleanup_module(void)
1403 {
1404 platform_driver_unregister(&ixp4xx_hss_driver);
1405 }
1406
1407 MODULE_AUTHOR("Krzysztof Halasa");
1408 MODULE_DESCRIPTION("Intel IXP4xx HSS driver");
1409 MODULE_LICENSE("GPL v2");
1410 MODULE_ALIAS("platform:ixp4xx_hss");
1411 module_init(hss_init_module);
1412 module_exit(hss_cleanup_module);
Tomato firmware and modifications.