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GUI: Fix Tomato RAF theme for all builds. Compilation typo.
[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / drivers / net / tulip / uli526x.c
blob2dd6c7ec8d1e24010add0d648146bb7aa43580d8
1 /*
2 This program is free software; you can redistribute it and/or
3 modify it under the terms of the GNU General Public License
4 as published by the Free Software Foundation; either version 2
5 of the License, or (at your option) any later version.
6
7 This program is distributed in the hope that it will be useful,
8 but WITHOUT ANY WARRANTY; without even the implied warranty of
9 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 GNU General Public License for more details.
11
12
13 */
14
15 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
16
17 #define DRV_NAME "uli526x"
18 #define DRV_VERSION "0.9.3"
19 #define DRV_RELDATE "2005-7-29"
20
21 #include <linux/module.h>
22
23 #include <linux/kernel.h>
24 #include <linux/string.h>
25 #include <linux/timer.h>
26 #include <linux/errno.h>
27 #include <linux/ioport.h>
28 #include <linux/interrupt.h>
29 #include <linux/pci.h>
30 #include <linux/init.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/ethtool.h>
34 #include <linux/skbuff.h>
35 #include <linux/delay.h>
36 #include <linux/spinlock.h>
37 #include <linux/dma-mapping.h>
38 #include <linux/bitops.h>
39
40 #include <asm/processor.h>
41 #include <asm/io.h>
42 #include <asm/dma.h>
43 #include <asm/uaccess.h>
44
45
46 /* Board/System/Debug information/definition ---------------- */
47 #define PCI_ULI5261_ID 0x526110B9 /* ULi M5261 ID*/
48 #define PCI_ULI5263_ID 0x526310B9 /* ULi M5263 ID*/
49
50 #define ULI526X_IO_SIZE 0x100
51 #define TX_DESC_CNT 0x20 /* Allocated Tx descriptors */
52 #define RX_DESC_CNT 0x30 /* Allocated Rx descriptors */
53 #define TX_FREE_DESC_CNT (TX_DESC_CNT - 2) /* Max TX packet count */
54 #define TX_WAKE_DESC_CNT (TX_DESC_CNT - 3) /* TX wakeup count */
55 #define DESC_ALL_CNT (TX_DESC_CNT + RX_DESC_CNT)
56 #define TX_BUF_ALLOC 0x600
57 #define RX_ALLOC_SIZE 0x620
58 #define ULI526X_RESET 1
59 #define CR0_DEFAULT 0
60 #define CR6_DEFAULT 0x22200000
61 #define CR7_DEFAULT 0x180c1
62 #define CR15_DEFAULT 0x06 /* TxJabber RxWatchdog */
63 #define TDES0_ERR_MASK 0x4302 /* TXJT, LC, EC, FUE */
64 #define MAX_PACKET_SIZE 1514
65 #define ULI5261_MAX_MULTICAST 14
66 #define RX_COPY_SIZE 100
67 #define MAX_CHECK_PACKET 0x8000
68
69 #define ULI526X_10MHF 0
70 #define ULI526X_100MHF 1
71 #define ULI526X_10MFD 4
72 #define ULI526X_100MFD 5
73 #define ULI526X_AUTO 8
74
75 #define ULI526X_TXTH_72 0x400000 /* TX TH 72 byte */
76 #define ULI526X_TXTH_96 0x404000 /* TX TH 96 byte */
77 #define ULI526X_TXTH_128 0x0000 /* TX TH 128 byte */
78 #define ULI526X_TXTH_256 0x4000 /* TX TH 256 byte */
79 #define ULI526X_TXTH_512 0x8000 /* TX TH 512 byte */
80 #define ULI526X_TXTH_1K 0xC000 /* TX TH 1K byte */
81
82 #define ULI526X_TIMER_WUT (jiffies + HZ * 1)/* timer wakeup time : 1 second */
83 #define ULI526X_TX_TIMEOUT ((16*HZ)/2) /* tx packet time-out time 8 s" */
84 #define ULI526X_TX_KICK (4*HZ/2) /* tx packet Kick-out time 2 s" */
85
86 #define ULI526X_DBUG(dbug_now, msg, value) \
87 do { \
88 if (uli526x_debug || (dbug_now)) \
89 pr_err("%s %lx\n", (msg), (long) (value)); \
90 } while (0)
91
92 #define SHOW_MEDIA_TYPE(mode) \
93 pr_err("Change Speed to %sMhz %s duplex\n", \
94 mode & 1 ? "100" : "10", \
95 mode & 4 ? "full" : "half");
96
97
98 /* CR9 definition: SROM/MII */
99 #define CR9_SROM_READ 0x4800
100 #define CR9_SRCS 0x1
101 #define CR9_SRCLK 0x2
102 #define CR9_CRDOUT 0x8
103 #define SROM_DATA_0 0x0
104 #define SROM_DATA_1 0x4
105 #define PHY_DATA_1 0x20000
106 #define PHY_DATA_0 0x00000
107 #define MDCLKH 0x10000
108
109 #define PHY_POWER_DOWN 0x800
110
111 #define SROM_V41_CODE 0x14
112
113 #define SROM_CLK_WRITE(data, ioaddr) \
114 outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr); \
115 udelay(5); \
116 outl(data|CR9_SROM_READ|CR9_SRCS|CR9_SRCLK,ioaddr); \
117 udelay(5); \
118 outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr); \
119 udelay(5);
120
121 /* Structure/enum declaration ------------------------------- */
122 struct tx_desc {
123 __le32 tdes0, tdes1, tdes2, tdes3; /* Data for the card */
124 char *tx_buf_ptr; /* Data for us */
125 struct tx_desc *next_tx_desc;
126 } __attribute__(( aligned(32) ));
127
128 struct rx_desc {
129 __le32 rdes0, rdes1, rdes2, rdes3; /* Data for the card */
130 struct sk_buff *rx_skb_ptr; /* Data for us */
131 struct rx_desc *next_rx_desc;
132 } __attribute__(( aligned(32) ));
133
134 struct uli526x_board_info {
135 u32 chip_id; /* Chip vendor/Device ID */
136 struct net_device *next_dev; /* next device */
137 struct pci_dev *pdev; /* PCI device */
138 spinlock_t lock;
139
140 long ioaddr; /* I/O base address */
141 u32 cr0_data;
142 u32 cr5_data;
143 u32 cr6_data;
144 u32 cr7_data;
145 u32 cr15_data;
146
147 /* pointer for memory physical address */
148 dma_addr_t buf_pool_dma_ptr; /* Tx buffer pool memory */
149 dma_addr_t buf_pool_dma_start; /* Tx buffer pool align dword */
150 dma_addr_t desc_pool_dma_ptr; /* descriptor pool memory */
151 dma_addr_t first_tx_desc_dma;
152 dma_addr_t first_rx_desc_dma;
153
154 /* descriptor pointer */
155 unsigned char *buf_pool_ptr; /* Tx buffer pool memory */
156 unsigned char *buf_pool_start; /* Tx buffer pool align dword */
157 unsigned char *desc_pool_ptr; /* descriptor pool memory */
158 struct tx_desc *first_tx_desc;
159 struct tx_desc *tx_insert_ptr;
160 struct tx_desc *tx_remove_ptr;
161 struct rx_desc *first_rx_desc;
162 struct rx_desc *rx_insert_ptr;
163 struct rx_desc *rx_ready_ptr; /* packet come pointer */
164 unsigned long tx_packet_cnt; /* transmitted packet count */
165 unsigned long rx_avail_cnt; /* available rx descriptor count */
166 unsigned long interval_rx_cnt; /* rx packet count a callback time */
167
168 u16 dbug_cnt;
169 u16 NIC_capability; /* NIC media capability */
170 u16 PHY_reg4; /* Saved Phyxcer register 4 value */
171
172 u8 media_mode; /* user specify media mode */
173 u8 op_mode; /* real work media mode */
174 u8 phy_addr;
175 u8 link_failed; /* Ever link failed */
176 u8 wait_reset; /* Hardware failed, need to reset */
177 struct timer_list timer;
178
179 /* Driver defined statistic counter */
180 unsigned long tx_fifo_underrun;
181 unsigned long tx_loss_carrier;
182 unsigned long tx_no_carrier;
183 unsigned long tx_late_collision;
184 unsigned long tx_excessive_collision;
185 unsigned long tx_jabber_timeout;
186 unsigned long reset_count;
187 unsigned long reset_cr8;
188 unsigned long reset_fatal;
189 unsigned long reset_TXtimeout;
190
191 /* NIC SROM data */
192 unsigned char srom[128];
193 u8 init;
194 };
195
196 enum uli526x_offsets {
197 DCR0 = 0x00, DCR1 = 0x08, DCR2 = 0x10, DCR3 = 0x18, DCR4 = 0x20,
198 DCR5 = 0x28, DCR6 = 0x30, DCR7 = 0x38, DCR8 = 0x40, DCR9 = 0x48,
199 DCR10 = 0x50, DCR11 = 0x58, DCR12 = 0x60, DCR13 = 0x68, DCR14 = 0x70,
200 DCR15 = 0x78
201 };
202
203 enum uli526x_CR6_bits {
204 CR6_RXSC = 0x2, CR6_PBF = 0x8, CR6_PM = 0x40, CR6_PAM = 0x80,
205 CR6_FDM = 0x200, CR6_TXSC = 0x2000, CR6_STI = 0x100000,
206 CR6_SFT = 0x200000, CR6_RXA = 0x40000000, CR6_NO_PURGE = 0x20000000
207 };
208
209 /* Global variable declaration ----------------------------- */
210 static int __devinitdata printed_version;
211 static const char version[] __devinitconst =
212 KERN_INFO DRV_NAME ": ULi M5261/M5263 net driver, version "
213 DRV_VERSION " (" DRV_RELDATE ")\n";
214
215 static int uli526x_debug;
216 static unsigned char uli526x_media_mode = ULI526X_AUTO;
217 static u32 uli526x_cr6_user_set;
218
219 /* For module input parameter */
220 static int debug;
221 static u32 cr6set;
222 static int mode = 8;
223
224 /* function declaration ------------------------------------- */
225 static int uli526x_open(struct net_device *);
226 static netdev_tx_t uli526x_start_xmit(struct sk_buff *,
227 struct net_device *);
228 static int uli526x_stop(struct net_device *);
229 static void uli526x_set_filter_mode(struct net_device *);
230 static const struct ethtool_ops netdev_ethtool_ops;
231 static u16 read_srom_word(long, int);
232 static irqreturn_t uli526x_interrupt(int, void *);
233 #ifdef CONFIG_NET_POLL_CONTROLLER
234 static void uli526x_poll(struct net_device *dev);
235 #endif
236 static void uli526x_descriptor_init(struct uli526x_board_info *, unsigned long);
237 static void allocate_rx_buffer(struct uli526x_board_info *);
238 static void update_cr6(u32, unsigned long);
239 static void send_filter_frame(struct net_device *, int);
240 static u16 phy_read(unsigned long, u8, u8, u32);
241 static u16 phy_readby_cr10(unsigned long, u8, u8);
242 static void phy_write(unsigned long, u8, u8, u16, u32);
243 static void phy_writeby_cr10(unsigned long, u8, u8, u16);
244 static void phy_write_1bit(unsigned long, u32, u32);
245 static u16 phy_read_1bit(unsigned long, u32);
246 static u8 uli526x_sense_speed(struct uli526x_board_info *);
247 static void uli526x_process_mode(struct uli526x_board_info *);
248 static void uli526x_timer(unsigned long);
249 static void uli526x_rx_packet(struct net_device *, struct uli526x_board_info *);
250 static void uli526x_free_tx_pkt(struct net_device *, struct uli526x_board_info *);
251 static void uli526x_reuse_skb(struct uli526x_board_info *, struct sk_buff *);
252 static void uli526x_dynamic_reset(struct net_device *);
253 static void uli526x_free_rxbuffer(struct uli526x_board_info *);
254 static void uli526x_init(struct net_device *);
255 static void uli526x_set_phyxcer(struct uli526x_board_info *);
256
257 /* ULI526X network board routine ---------------------------- */
258
259 static const struct net_device_ops netdev_ops = {
260 .ndo_open = uli526x_open,
261 .ndo_stop = uli526x_stop,
262 .ndo_start_xmit = uli526x_start_xmit,
263 .ndo_set_multicast_list = uli526x_set_filter_mode,
264 .ndo_change_mtu = eth_change_mtu,
265 .ndo_set_mac_address = eth_mac_addr,
266 .ndo_validate_addr = eth_validate_addr,
267 #ifdef CONFIG_NET_POLL_CONTROLLER
268 .ndo_poll_controller = uli526x_poll,
269 #endif
270 };
271
272 /*
273 * Search ULI526X board, allocate space and register it
274 */
275
276 static int __devinit uli526x_init_one (struct pci_dev *pdev,
277 const struct pci_device_id *ent)
278 {
279 struct uli526x_board_info *db; /* board information structure */
280 struct net_device *dev;
281 int i, err;
282
283 ULI526X_DBUG(0, "uli526x_init_one()", 0);
284
285 if (!printed_version++)
286 printk(version);
287
288 /* Init network device */
289 dev = alloc_etherdev(sizeof(*db));
290 if (dev == NULL)
291 return -ENOMEM;
292 SET_NETDEV_DEV(dev, &pdev->dev);
293
294 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
295 pr_warning("32-bit PCI DMA not available\n");
296 err = -ENODEV;
297 goto err_out_free;
298 }
299
300 /* Enable Master/IO access, Disable memory access */
301 err = pci_enable_device(pdev);
302 if (err)
303 goto err_out_free;
304
305 if (!pci_resource_start(pdev, 0)) {
306 pr_err("I/O base is zero\n");
307 err = -ENODEV;
308 goto err_out_disable;
309 }
310
311 if (pci_resource_len(pdev, 0) < (ULI526X_IO_SIZE) ) {
312 pr_err("Allocated I/O size too small\n");
313 err = -ENODEV;
314 goto err_out_disable;
315 }
316
317 if (pci_request_regions(pdev, DRV_NAME)) {
318 pr_err("Failed to request PCI regions\n");
319 err = -ENODEV;
320 goto err_out_disable;
321 }
322
323 /* Init system & device */
324 db = netdev_priv(dev);
325
326 /* Allocate Tx/Rx descriptor memory */
327 db->desc_pool_ptr = pci_alloc_consistent(pdev, sizeof(struct tx_desc) * DESC_ALL_CNT + 0x20, &db->desc_pool_dma_ptr);
328 if(db->desc_pool_ptr == NULL)
329 {
330 err = -ENOMEM;
331 goto err_out_nomem;
332 }
333 db->buf_pool_ptr = pci_alloc_consistent(pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4, &db->buf_pool_dma_ptr);
334 if(db->buf_pool_ptr == NULL)
335 {
336 err = -ENOMEM;
337 goto err_out_nomem;
338 }
339
340 db->first_tx_desc = (struct tx_desc *) db->desc_pool_ptr;
341 db->first_tx_desc_dma = db->desc_pool_dma_ptr;
342 db->buf_pool_start = db->buf_pool_ptr;
343 db->buf_pool_dma_start = db->buf_pool_dma_ptr;
344
345 db->chip_id = ent->driver_data;
346 db->ioaddr = pci_resource_start(pdev, 0);
347
348 db->pdev = pdev;
349 db->init = 1;
350
351 dev->base_addr = db->ioaddr;
352 dev->irq = pdev->irq;
353 pci_set_drvdata(pdev, dev);
354
355 /* Register some necessary functions */
356 dev->netdev_ops = &netdev_ops;
357 dev->ethtool_ops = &netdev_ethtool_ops;
358
359 spin_lock_init(&db->lock);
360
361
362 /* read 64 word srom data */
363 for (i = 0; i < 64; i++)
364 ((__le16 *) db->srom)[i] = cpu_to_le16(read_srom_word(db->ioaddr, i));
365
366 /* Set Node address */
367 if(((u16 *) db->srom)[0] == 0xffff || ((u16 *) db->srom)[0] == 0) /* SROM absent, so read MAC address from ID Table */
368 {
369 outl(0x10000, db->ioaddr + DCR0); //Diagnosis mode
370 outl(0x1c0, db->ioaddr + DCR13); //Reset dianostic pointer port
371 outl(0, db->ioaddr + DCR14); //Clear reset port
372 outl(0x10, db->ioaddr + DCR14); //Reset ID Table pointer
373 outl(0, db->ioaddr + DCR14); //Clear reset port
374 outl(0, db->ioaddr + DCR13); //Clear CR13
375 outl(0x1b0, db->ioaddr + DCR13); //Select ID Table access port
376 //Read MAC address from CR14
377 for (i = 0; i < 6; i++)
378 dev->dev_addr[i] = inl(db->ioaddr + DCR14);
379 //Read end
380 outl(0, db->ioaddr + DCR13); //Clear CR13
381 outl(0, db->ioaddr + DCR0); //Clear CR0
382 udelay(10);
383 }
384 else /*Exist SROM*/
385 {
386 for (i = 0; i < 6; i++)
387 dev->dev_addr[i] = db->srom[20 + i];
388 }
389 err = register_netdev (dev);
390 if (err)
391 goto err_out_res;
392
393 dev_info(&dev->dev, "ULi M%04lx at pci%s, %pM, irq %d\n",
394 ent->driver_data >> 16, pci_name(pdev),
395 dev->dev_addr, dev->irq);
396
397 pci_set_master(pdev);
398
399 return 0;
400
401 err_out_res:
402 pci_release_regions(pdev);
403 err_out_nomem:
404 if(db->desc_pool_ptr)
405 pci_free_consistent(pdev, sizeof(struct tx_desc) * DESC_ALL_CNT + 0x20,
406 db->desc_pool_ptr, db->desc_pool_dma_ptr);
407
408 if(db->buf_pool_ptr != NULL)
409 pci_free_consistent(pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4,
410 db->buf_pool_ptr, db->buf_pool_dma_ptr);
411 err_out_disable:
412 pci_disable_device(pdev);
413 err_out_free:
414 pci_set_drvdata(pdev, NULL);
415 free_netdev(dev);
416
417 return err;
418 }
419
420
421 static void __devexit uli526x_remove_one (struct pci_dev *pdev)
422 {
423 struct net_device *dev = pci_get_drvdata(pdev);
424 struct uli526x_board_info *db = netdev_priv(dev);
425
426 ULI526X_DBUG(0, "uli526x_remove_one()", 0);
427
428 pci_free_consistent(db->pdev, sizeof(struct tx_desc) *
429 DESC_ALL_CNT + 0x20, db->desc_pool_ptr,
430 db->desc_pool_dma_ptr);
431 pci_free_consistent(db->pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4,
432 db->buf_pool_ptr, db->buf_pool_dma_ptr);
433 unregister_netdev(dev);
434 pci_release_regions(pdev);
435 free_netdev(dev); /* free board information */
436 pci_set_drvdata(pdev, NULL);
437 pci_disable_device(pdev);
438 ULI526X_DBUG(0, "uli526x_remove_one() exit", 0);
439 }
440
441
442 /*
443 * Open the interface.
444 * The interface is opened whenever "ifconfig" activates it.
445 */
446
447 static int uli526x_open(struct net_device *dev)
448 {
449 int ret;
450 struct uli526x_board_info *db = netdev_priv(dev);
451
452 ULI526X_DBUG(0, "uli526x_open", 0);
453
454 /* system variable init */
455 db->cr6_data = CR6_DEFAULT | uli526x_cr6_user_set;
456 db->tx_packet_cnt = 0;
457 db->rx_avail_cnt = 0;
458 db->link_failed = 1;
459 netif_carrier_off(dev);
460 db->wait_reset = 0;
461
462 db->NIC_capability = 0xf; /* All capability*/
463 db->PHY_reg4 = 0x1e0;
464
465 /* CR6 operation mode decision */
466 db->cr6_data |= ULI526X_TXTH_256;
467 db->cr0_data = CR0_DEFAULT;
468
469 /* Initialize ULI526X board */
470 uli526x_init(dev);
471
472 ret = request_irq(dev->irq, uli526x_interrupt, IRQF_SHARED, dev->name, dev);
473 if (ret)
474 return ret;
475
476 /* Active System Interface */
477 netif_wake_queue(dev);
478
479 /* set and active a timer process */
480 init_timer(&db->timer);
481 db->timer.expires = ULI526X_TIMER_WUT + HZ * 2;
482 db->timer.data = (unsigned long)dev;
483 db->timer.function = &uli526x_timer;
484 add_timer(&db->timer);
485
486 return 0;
487 }
488
489
490 /* Initialize ULI526X board
491 * Reset ULI526X board
492 * Initialize TX/Rx descriptor chain structure
493 * Send the set-up frame
494 * Enable Tx/Rx machine
495 */
496
497 static void uli526x_init(struct net_device *dev)
498 {
499 struct uli526x_board_info *db = netdev_priv(dev);
500 unsigned long ioaddr = db->ioaddr;
501 u8 phy_tmp;
502 u8 timeout;
503 u16 phy_value;
504 u16 phy_reg_reset;
505
506
507 ULI526X_DBUG(0, "uli526x_init()", 0);
508
509 /* Reset M526x MAC controller */
510 outl(ULI526X_RESET, ioaddr + DCR0); /* RESET MAC */
511 udelay(100);
512 outl(db->cr0_data, ioaddr + DCR0);
513 udelay(5);
514
515 /* Phy addr : In some boards,M5261/M5263 phy address != 1 */
516 db->phy_addr = 1;
517 for(phy_tmp=0;phy_tmp<32;phy_tmp++)
518 {
519 phy_value=phy_read(db->ioaddr,phy_tmp,3,db->chip_id);//peer add
520 if(phy_value != 0xffff&&phy_value!=0)
521 {
522 db->phy_addr = phy_tmp;
523 break;
524 }
525 }
526 if(phy_tmp == 32)
527 pr_warning("Can not find the phy address!!!");
528 /* Parser SROM and media mode */
529 db->media_mode = uli526x_media_mode;
530
531 /* phyxcer capability setting */
532 phy_reg_reset = phy_read(db->ioaddr, db->phy_addr, 0, db->chip_id);
533 phy_reg_reset = (phy_reg_reset | 0x8000);
534 phy_write(db->ioaddr, db->phy_addr, 0, phy_reg_reset, db->chip_id);
535
536 /* See IEEE 802.3-2002.pdf (Section 2, Chapter "22.2.4 Management
537 * functions") or phy data sheet for details on phy reset
538 */
539 udelay(500);
540 timeout = 10;
541 while (timeout-- &&
542 phy_read(db->ioaddr, db->phy_addr, 0, db->chip_id) & 0x8000)
543 udelay(100);
544
545 /* Process Phyxcer Media Mode */
546 uli526x_set_phyxcer(db);
547
548 /* Media Mode Process */
549 if ( !(db->media_mode & ULI526X_AUTO) )
550 db->op_mode = db->media_mode; /* Force Mode */
551
552 /* Initialize Transmit/Receive decriptor and CR3/4 */
553 uli526x_descriptor_init(db, ioaddr);
554
555 /* Init CR6 to program M526X operation */
556 update_cr6(db->cr6_data, ioaddr);
557
558 /* Send setup frame */
559 send_filter_frame(dev, netdev_mc_count(dev)); /* M5261/M5263 */
560
561 /* Init CR7, interrupt active bit */
562 db->cr7_data = CR7_DEFAULT;
563 outl(db->cr7_data, ioaddr + DCR7);
564
565 /* Init CR15, Tx jabber and Rx watchdog timer */
566 outl(db->cr15_data, ioaddr + DCR15);
567
568 /* Enable ULI526X Tx/Rx function */
569 db->cr6_data |= CR6_RXSC | CR6_TXSC;
570 update_cr6(db->cr6_data, ioaddr);
571 }
572
573
574 /*
575 * Hardware start transmission.
576 * Send a packet to media from the upper layer.
577 */
578
579 static netdev_tx_t uli526x_start_xmit(struct sk_buff *skb,
580 struct net_device *dev)
581 {
582 struct uli526x_board_info *db = netdev_priv(dev);
583 struct tx_desc *txptr;
584 unsigned long flags;
585
586 ULI526X_DBUG(0, "uli526x_start_xmit", 0);
587
588 /* Resource flag check */
589 netif_stop_queue(dev);
590
591 /* Too large packet check */
592 if (skb->len > MAX_PACKET_SIZE) {
593 pr_err("big packet = %d\n", (u16)skb->len);
594 dev_kfree_skb(skb);
595 return NETDEV_TX_OK;
596 }
597
598 spin_lock_irqsave(&db->lock, flags);
599
600 /* No Tx resource check, it never happen nromally */
601 if (db->tx_packet_cnt >= TX_FREE_DESC_CNT) {
602 spin_unlock_irqrestore(&db->lock, flags);
603 pr_err("No Tx resource %ld\n", db->tx_packet_cnt);
604 return NETDEV_TX_BUSY;
605 }
606
607 /* Disable NIC interrupt */
608 outl(0, dev->base_addr + DCR7);
609
610 /* transmit this packet */
611 txptr = db->tx_insert_ptr;
612 skb_copy_from_linear_data(skb, txptr->tx_buf_ptr, skb->len);
613 txptr->tdes1 = cpu_to_le32(0xe1000000 | skb->len);
614
615 /* Point to next transmit free descriptor */
616 db->tx_insert_ptr = txptr->next_tx_desc;
617
618 /* Transmit Packet Process */
619 if ( (db->tx_packet_cnt < TX_DESC_CNT) ) {
620 txptr->tdes0 = cpu_to_le32(0x80000000); /* Set owner bit */
621 db->tx_packet_cnt++; /* Ready to send */
622 outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */
623 dev->trans_start = jiffies; /* saved time stamp */
624 }
625
626 /* Tx resource check */
627 if ( db->tx_packet_cnt < TX_FREE_DESC_CNT )
628 netif_wake_queue(dev);
629
630 /* Restore CR7 to enable interrupt */
631 spin_unlock_irqrestore(&db->lock, flags);
632 outl(db->cr7_data, dev->base_addr + DCR7);
633
634 /* free this SKB */
635 dev_kfree_skb(skb);
636
637 return NETDEV_TX_OK;
638 }
639
640
641 /*
642 * Stop the interface.
643 * The interface is stopped when it is brought.
644 */
645
646 static int uli526x_stop(struct net_device *dev)
647 {
648 struct uli526x_board_info *db = netdev_priv(dev);
649 unsigned long ioaddr = dev->base_addr;
650
651 ULI526X_DBUG(0, "uli526x_stop", 0);
652
653 /* disable system */
654 netif_stop_queue(dev);
655
656 /* deleted timer */
657 del_timer_sync(&db->timer);
658
659 /* Reset & stop ULI526X board */
660 outl(ULI526X_RESET, ioaddr + DCR0);
661 udelay(5);
662 phy_write(db->ioaddr, db->phy_addr, 0, 0x8000, db->chip_id);
663
664 /* free interrupt */
665 free_irq(dev->irq, dev);
666
667 /* free allocated rx buffer */
668 uli526x_free_rxbuffer(db);
669
670
671 return 0;
672 }
673
674
675 /*
676 * M5261/M5263 insterrupt handler
677 * receive the packet to upper layer, free the transmitted packet
678 */
679
680 static irqreturn_t uli526x_interrupt(int irq, void *dev_id)
681 {
682 struct net_device *dev = dev_id;
683 struct uli526x_board_info *db = netdev_priv(dev);
684 unsigned long ioaddr = dev->base_addr;
685 unsigned long flags;
686
687 spin_lock_irqsave(&db->lock, flags);
688 outl(0, ioaddr + DCR7);
689
690 /* Got ULI526X status */
691 db->cr5_data = inl(ioaddr + DCR5);
692 outl(db->cr5_data, ioaddr + DCR5);
693 if ( !(db->cr5_data & 0x180c1) ) {
694 /* Restore CR7 to enable interrupt mask */
695 outl(db->cr7_data, ioaddr + DCR7);
696 spin_unlock_irqrestore(&db->lock, flags);
697 return IRQ_HANDLED;
698 }
699
700 /* Check system status */
701 if (db->cr5_data & 0x2000) {
702 /* system bus error happen */
703 ULI526X_DBUG(1, "System bus error happen. CR5=", db->cr5_data);
704 db->reset_fatal++;
705 db->wait_reset = 1; /* Need to RESET */
706 spin_unlock_irqrestore(&db->lock, flags);
707 return IRQ_HANDLED;
708 }
709
710 /* Received the coming packet */
711 if ( (db->cr5_data & 0x40) && db->rx_avail_cnt )
712 uli526x_rx_packet(dev, db);
713
714 /* reallocate rx descriptor buffer */
715 if (db->rx_avail_cnt<RX_DESC_CNT)
716 allocate_rx_buffer(db);
717
718 /* Free the transmitted descriptor */
719 if ( db->cr5_data & 0x01)
720 uli526x_free_tx_pkt(dev, db);
721
722 /* Restore CR7 to enable interrupt mask */
723 outl(db->cr7_data, ioaddr + DCR7);
724
725 spin_unlock_irqrestore(&db->lock, flags);
726 return IRQ_HANDLED;
727 }
728
729 #ifdef CONFIG_NET_POLL_CONTROLLER
730 static void uli526x_poll(struct net_device *dev)
731 {
732 /* ISR grabs the irqsave lock, so this should be safe */
733 uli526x_interrupt(dev->irq, dev);
734 }
735 #endif
736
737 /*
738 * Free TX resource after TX complete
739 */
740
741 static void uli526x_free_tx_pkt(struct net_device *dev,
742 struct uli526x_board_info * db)
743 {
744 struct tx_desc *txptr;
745 u32 tdes0;
746
747 txptr = db->tx_remove_ptr;
748 while(db->tx_packet_cnt) {
749 tdes0 = le32_to_cpu(txptr->tdes0);
750 /* printk(DRV_NAME ": tdes0=%x\n", tdes0); */
751 if (tdes0 & 0x80000000)
752 break;
753
754 /* A packet sent completed */
755 db->tx_packet_cnt--;
756 dev->stats.tx_packets++;
757
758 /* Transmit statistic counter */
759 if ( tdes0 != 0x7fffffff ) {
760 /* printk(DRV_NAME ": tdes0=%x\n", tdes0); */
761 dev->stats.collisions += (tdes0 >> 3) & 0xf;
762 dev->stats.tx_bytes += le32_to_cpu(txptr->tdes1) & 0x7ff;
763 if (tdes0 & TDES0_ERR_MASK) {
764 dev->stats.tx_errors++;
765 if (tdes0 & 0x0002) { /* UnderRun */
766 db->tx_fifo_underrun++;
767 if ( !(db->cr6_data & CR6_SFT) ) {
768 db->cr6_data = db->cr6_data | CR6_SFT;
769 update_cr6(db->cr6_data, db->ioaddr);
770 }
771 }
772 if (tdes0 & 0x0100)
773 db->tx_excessive_collision++;
774 if (tdes0 & 0x0200)
775 db->tx_late_collision++;
776 if (tdes0 & 0x0400)
777 db->tx_no_carrier++;
778 if (tdes0 & 0x0800)
779 db->tx_loss_carrier++;
780 if (tdes0 & 0x4000)
781 db->tx_jabber_timeout++;
782 }
783 }
784
785 txptr = txptr->next_tx_desc;
786 }/* End of while */
787
788 /* Update TX remove pointer to next */
789 db->tx_remove_ptr = txptr;
790
791 /* Resource available check */
792 if ( db->tx_packet_cnt < TX_WAKE_DESC_CNT )
793 netif_wake_queue(dev); /* Active upper layer, send again */
794 }
795
796
797 /*
798 * Receive the come packet and pass to upper layer
799 */
800
801 static void uli526x_rx_packet(struct net_device *dev, struct uli526x_board_info * db)
802 {
803 struct rx_desc *rxptr;
804 struct sk_buff *skb;
805 int rxlen;
806 u32 rdes0;
807
808 rxptr = db->rx_ready_ptr;
809
810 while(db->rx_avail_cnt) {
811 rdes0 = le32_to_cpu(rxptr->rdes0);
812 if (rdes0 & 0x80000000) /* packet owner check */
813 {
814 break;
815 }
816
817 db->rx_avail_cnt--;
818 db->interval_rx_cnt++;
819
820 pci_unmap_single(db->pdev, le32_to_cpu(rxptr->rdes2), RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
821 if ( (rdes0 & 0x300) != 0x300) {
822 /* A packet without First/Last flag */
823 /* reuse this SKB */
824 ULI526X_DBUG(0, "Reuse SK buffer, rdes0", rdes0);
825 uli526x_reuse_skb(db, rxptr->rx_skb_ptr);
826 } else {
827 /* A packet with First/Last flag */
828 rxlen = ( (rdes0 >> 16) & 0x3fff) - 4;
829
830 /* error summary bit check */
831 if (rdes0 & 0x8000) {
832 /* This is a error packet */
833 //printk(DRV_NAME ": rdes0: %lx\n", rdes0);
834 dev->stats.rx_errors++;
835 if (rdes0 & 1)
836 dev->stats.rx_fifo_errors++;
837 if (rdes0 & 2)
838 dev->stats.rx_crc_errors++;
839 if (rdes0 & 0x80)
840 dev->stats.rx_length_errors++;
841 }
842
843 if ( !(rdes0 & 0x8000) ||
844 ((db->cr6_data & CR6_PM) && (rxlen>6)) ) {
845 struct sk_buff *new_skb = NULL;
846
847 skb = rxptr->rx_skb_ptr;
848
849 /* Good packet, send to upper layer */
850 /* Shorst packet used new SKB */
851 if ((rxlen < RX_COPY_SIZE) &&
852 (((new_skb = dev_alloc_skb(rxlen + 2)) != NULL))) {
853 skb = new_skb;
854 /* size less than COPY_SIZE, allocate a rxlen SKB */
855 skb_reserve(skb, 2); /* 16byte align */
856 memcpy(skb_put(skb, rxlen),
857 skb_tail_pointer(rxptr->rx_skb_ptr),
858 rxlen);
859 uli526x_reuse_skb(db, rxptr->rx_skb_ptr);
860 } else
861 skb_put(skb, rxlen);
862
863 skb->protocol = eth_type_trans(skb, dev);
864 netif_rx(skb);
865 dev->stats.rx_packets++;
866 dev->stats.rx_bytes += rxlen;
867
868 } else {
869 /* Reuse SKB buffer when the packet is error */
870 ULI526X_DBUG(0, "Reuse SK buffer, rdes0", rdes0);
871 uli526x_reuse_skb(db, rxptr->rx_skb_ptr);
872 }
873 }
874
875 rxptr = rxptr->next_rx_desc;
876 }
877
878 db->rx_ready_ptr = rxptr;
879 }
880
881
882 /*
883 * Set ULI526X multicast address
884 */
885
886 static void uli526x_set_filter_mode(struct net_device * dev)
887 {
888 struct uli526x_board_info *db = netdev_priv(dev);
889 unsigned long flags;
890
891 ULI526X_DBUG(0, "uli526x_set_filter_mode()", 0);
892 spin_lock_irqsave(&db->lock, flags);
893
894 if (dev->flags & IFF_PROMISC) {
895 ULI526X_DBUG(0, "Enable PROM Mode", 0);
896 db->cr6_data |= CR6_PM | CR6_PBF;
897 update_cr6(db->cr6_data, db->ioaddr);
898 spin_unlock_irqrestore(&db->lock, flags);
899 return;
900 }
901
902 if (dev->flags & IFF_ALLMULTI ||
903 netdev_mc_count(dev) > ULI5261_MAX_MULTICAST) {
904 ULI526X_DBUG(0, "Pass all multicast address",
905 netdev_mc_count(dev));
906 db->cr6_data &= ~(CR6_PM | CR6_PBF);
907 db->cr6_data |= CR6_PAM;
908 spin_unlock_irqrestore(&db->lock, flags);
909 return;
910 }
911
912 ULI526X_DBUG(0, "Set multicast address", netdev_mc_count(dev));
913 send_filter_frame(dev, netdev_mc_count(dev)); /* M5261/M5263 */
914 spin_unlock_irqrestore(&db->lock, flags);
915 }
916
917 static void
918 ULi_ethtool_gset(struct uli526x_board_info *db, struct ethtool_cmd *ecmd)
919 {
920 ecmd->supported = (SUPPORTED_10baseT_Half |
921 SUPPORTED_10baseT_Full |
922 SUPPORTED_100baseT_Half |
923 SUPPORTED_100baseT_Full |
924 SUPPORTED_Autoneg |
925 SUPPORTED_MII);
926
927 ecmd->advertising = (ADVERTISED_10baseT_Half |
928 ADVERTISED_10baseT_Full |
929 ADVERTISED_100baseT_Half |
930 ADVERTISED_100baseT_Full |
931 ADVERTISED_Autoneg |
932 ADVERTISED_MII);
933
934
935 ecmd->port = PORT_MII;
936 ecmd->phy_address = db->phy_addr;
937
938 ecmd->transceiver = XCVR_EXTERNAL;
939
940 ecmd->speed = 10;
941 ecmd->duplex = DUPLEX_HALF;
942
943 if(db->op_mode==ULI526X_100MHF || db->op_mode==ULI526X_100MFD)
944 {
945 ecmd->speed = 100;
946 }
947 if(db->op_mode==ULI526X_10MFD || db->op_mode==ULI526X_100MFD)
948 {
949 ecmd->duplex = DUPLEX_FULL;
950 }
951 if(db->link_failed)
952 {
953 ecmd->speed = -1;
954 ecmd->duplex = -1;
955 }
956
957 if (db->media_mode & ULI526X_AUTO)
958 {
959 ecmd->autoneg = AUTONEG_ENABLE;
960 }
961 }
962
963 static void netdev_get_drvinfo(struct net_device *dev,
964 struct ethtool_drvinfo *info)
965 {
966 struct uli526x_board_info *np = netdev_priv(dev);
967
968 strcpy(info->driver, DRV_NAME);
969 strcpy(info->version, DRV_VERSION);
970 if (np->pdev)
971 strcpy(info->bus_info, pci_name(np->pdev));
972 else
973 sprintf(info->bus_info, "EISA 0x%lx %d",
974 dev->base_addr, dev->irq);
975 }
976
977 static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) {
978 struct uli526x_board_info *np = netdev_priv(dev);
979
980 ULi_ethtool_gset(np, cmd);
981
982 return 0;
983 }
984
985 static u32 netdev_get_link(struct net_device *dev) {
986 struct uli526x_board_info *np = netdev_priv(dev);
987
988 if(np->link_failed)
989 return 0;
990 else
991 return 1;
992 }
993
994 static void uli526x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
995 {
996 wol->supported = WAKE_PHY | WAKE_MAGIC;
997 wol->wolopts = 0;
998 }
999
1000 static const struct ethtool_ops netdev_ethtool_ops = {
1001 .get_drvinfo = netdev_get_drvinfo,
1002 .get_settings = netdev_get_settings,
1003 .get_link = netdev_get_link,
1004 .get_wol = uli526x_get_wol,
1005 };
1006
1007 /*
1008 * A periodic timer routine
1009 * Dynamic media sense, allocate Rx buffer...
1010 */
1011
1012 static void uli526x_timer(unsigned long data)
1013 {
1014 u32 tmp_cr8;
1015 unsigned char tmp_cr12=0;
1016 struct net_device *dev = (struct net_device *) data;
1017 struct uli526x_board_info *db = netdev_priv(dev);
1018 unsigned long flags;
1019 u8 TmpSpeed=10;
1020
1021 //ULI526X_DBUG(0, "uli526x_timer()", 0);
1022 spin_lock_irqsave(&db->lock, flags);
1023
1024
1025 /* Dynamic reset ULI526X : system error or transmit time-out */
1026 tmp_cr8 = inl(db->ioaddr + DCR8);
1027 if ( (db->interval_rx_cnt==0) && (tmp_cr8) ) {
1028 db->reset_cr8++;
1029 db->wait_reset = 1;
1030 }
1031 db->interval_rx_cnt = 0;
1032
1033 /* TX polling kick monitor */
1034 if ( db->tx_packet_cnt &&
1035 time_after(jiffies, dev_trans_start(dev) + ULI526X_TX_KICK) ) {
1036 outl(0x1, dev->base_addr + DCR1); // Tx polling again
1037
1038 // TX Timeout
1039 if ( time_after(jiffies, dev_trans_start(dev) + ULI526X_TX_TIMEOUT) ) {
1040 db->reset_TXtimeout++;
1041 db->wait_reset = 1;
1042 printk( "%s: Tx timeout - resetting\n",
1043 dev->name);
1044 }
1045 }
1046
1047 if (db->wait_reset) {
1048 ULI526X_DBUG(0, "Dynamic Reset device", db->tx_packet_cnt);
1049 db->reset_count++;
1050 uli526x_dynamic_reset(dev);
1051 db->timer.expires = ULI526X_TIMER_WUT;
1052 add_timer(&db->timer);
1053 spin_unlock_irqrestore(&db->lock, flags);
1054 return;
1055 }
1056
1057 /* Link status check, Dynamic media type change */
1058 if((phy_read(db->ioaddr, db->phy_addr, 5, db->chip_id) & 0x01e0)!=0)
1059 tmp_cr12 = 3;
1060
1061 if ( !(tmp_cr12 & 0x3) && !db->link_failed ) {
1062 /* Link Failed */
1063 ULI526X_DBUG(0, "Link Failed", tmp_cr12);
1064 netif_carrier_off(dev);
1065 pr_info("%s NIC Link is Down\n",dev->name);
1066 db->link_failed = 1;
1067
1068 /* For Force 10/100M Half/Full mode: Enable Auto-Nego mode */
1069 /* AUTO don't need */
1070 if ( !(db->media_mode & 0x8) )
1071 phy_write(db->ioaddr, db->phy_addr, 0, 0x1000, db->chip_id);
1072
1073 /* AUTO mode, if INT phyxcer link failed, select EXT device */
1074 if (db->media_mode & ULI526X_AUTO) {
1075 db->cr6_data&=~0x00000200; /* bit9=0, HD mode */
1076 update_cr6(db->cr6_data, db->ioaddr);
1077 }
1078 } else
1079 if ((tmp_cr12 & 0x3) && db->link_failed) {
1080 ULI526X_DBUG(0, "Link link OK", tmp_cr12);
1081 db->link_failed = 0;
1082
1083 /* Auto Sense Speed */
1084 if ( (db->media_mode & ULI526X_AUTO) &&
1085 uli526x_sense_speed(db) )
1086 db->link_failed = 1;
1087 uli526x_process_mode(db);
1088
1089 if(db->link_failed==0)
1090 {
1091 if(db->op_mode==ULI526X_100MHF || db->op_mode==ULI526X_100MFD)
1092 {
1093 TmpSpeed = 100;
1094 }
1095 if(db->op_mode==ULI526X_10MFD || db->op_mode==ULI526X_100MFD)
1096 {
1097 pr_info("%s NIC Link is Up %d Mbps Full duplex\n",dev->name,TmpSpeed);
1098 }
1099 else
1100 {
1101 pr_info("%s NIC Link is Up %d Mbps Half duplex\n",dev->name,TmpSpeed);
1102 }
1103 netif_carrier_on(dev);
1104 }
1105 /* SHOW_MEDIA_TYPE(db->op_mode); */
1106 }
1107 else if(!(tmp_cr12 & 0x3) && db->link_failed)
1108 {
1109 if(db->init==1)
1110 {
1111 pr_info("%s NIC Link is Down\n",dev->name);
1112 netif_carrier_off(dev);
1113 }
1114 }
1115 db->init=0;
1116
1117 /* Timer active again */
1118 db->timer.expires = ULI526X_TIMER_WUT;
1119 add_timer(&db->timer);
1120 spin_unlock_irqrestore(&db->lock, flags);
1121 }
1122
1123
1124 /*
1125 * Stop ULI526X board
1126 * Free Tx/Rx allocated memory
1127 * Init system variable
1128 */
1129
1130 static void uli526x_reset_prepare(struct net_device *dev)
1131 {
1132 struct uli526x_board_info *db = netdev_priv(dev);
1133
1134 /* Sopt MAC controller */
1135 db->cr6_data &= ~(CR6_RXSC | CR6_TXSC); /* Disable Tx/Rx */
1136 update_cr6(db->cr6_data, dev->base_addr);
1137 outl(0, dev->base_addr + DCR7); /* Disable Interrupt */
1138 outl(inl(dev->base_addr + DCR5), dev->base_addr + DCR5);
1139
1140 /* Disable upper layer interface */
1141 netif_stop_queue(dev);
1142
1143 /* Free Rx Allocate buffer */
1144 uli526x_free_rxbuffer(db);
1145
1146 /* system variable init */
1147 db->tx_packet_cnt = 0;
1148 db->rx_avail_cnt = 0;
1149 db->link_failed = 1;
1150 db->init=1;
1151 db->wait_reset = 0;
1152 }
1153
1154
1155 /*
1156 * Dynamic reset the ULI526X board
1157 * Stop ULI526X board
1158 * Free Tx/Rx allocated memory
1159 * Reset ULI526X board
1160 * Re-initialize ULI526X board
1161 */
1162
1163 static void uli526x_dynamic_reset(struct net_device *dev)
1164 {
1165 ULI526X_DBUG(0, "uli526x_dynamic_reset()", 0);
1166
1167 uli526x_reset_prepare(dev);
1168
1169 /* Re-initialize ULI526X board */
1170 uli526x_init(dev);
1171
1172 /* Restart upper layer interface */
1173 netif_wake_queue(dev);
1174 }
1175
1176
1177 #ifdef CONFIG_PM
1178
1179 /*
1180 * Suspend the interface.
1181 */
1182
1183 static int uli526x_suspend(struct pci_dev *pdev, pm_message_t state)
1184 {
1185 struct net_device *dev = pci_get_drvdata(pdev);
1186 pci_power_t power_state;
1187 int err;
1188
1189 ULI526X_DBUG(0, "uli526x_suspend", 0);
1190
1191 if (!netdev_priv(dev))
1192 return 0;
1193
1194 pci_save_state(pdev);
1195
1196 if (!netif_running(dev))
1197 return 0;
1198
1199 netif_device_detach(dev);
1200 uli526x_reset_prepare(dev);
1201
1202 power_state = pci_choose_state(pdev, state);
1203 pci_enable_wake(pdev, power_state, 0);
1204 err = pci_set_power_state(pdev, power_state);
1205 if (err) {
1206 netif_device_attach(dev);
1207 /* Re-initialize ULI526X board */
1208 uli526x_init(dev);
1209 /* Restart upper layer interface */
1210 netif_wake_queue(dev);
1211 }
1212
1213 return err;
1214 }
1215
1216 /*
1217 * Resume the interface.
1218 */
1219
1220 static int uli526x_resume(struct pci_dev *pdev)
1221 {
1222 struct net_device *dev = pci_get_drvdata(pdev);
1223 int err;
1224
1225 ULI526X_DBUG(0, "uli526x_resume", 0);
1226
1227 if (!netdev_priv(dev))
1228 return 0;
1229
1230 pci_restore_state(pdev);
1231
1232 if (!netif_running(dev))
1233 return 0;
1234
1235 err = pci_set_power_state(pdev, PCI_D0);
1236 if (err) {
1237 dev_warn(&dev->dev, "Could not put device into D0\n");
1238 return err;
1239 }
1240
1241 netif_device_attach(dev);
1242 /* Re-initialize ULI526X board */
1243 uli526x_init(dev);
1244 /* Restart upper layer interface */
1245 netif_wake_queue(dev);
1246
1247 return 0;
1248 }
1249
1250 #else /* !CONFIG_PM */
1251
1252 #define uli526x_suspend NULL
1253 #define uli526x_resume NULL
1254
1255 #endif /* !CONFIG_PM */
1256
1257
1258 /*
1259 * free all allocated rx buffer
1260 */
1261
1262 static void uli526x_free_rxbuffer(struct uli526x_board_info * db)
1263 {
1264 ULI526X_DBUG(0, "uli526x_free_rxbuffer()", 0);
1265
1266 /* free allocated rx buffer */
1267 while (db->rx_avail_cnt) {
1268 dev_kfree_skb(db->rx_ready_ptr->rx_skb_ptr);
1269 db->rx_ready_ptr = db->rx_ready_ptr->next_rx_desc;
1270 db->rx_avail_cnt--;
1271 }
1272 }
1273
1274
1275 /*
1276 * Reuse the SK buffer
1277 */
1278
1279 static void uli526x_reuse_skb(struct uli526x_board_info *db, struct sk_buff * skb)
1280 {
1281 struct rx_desc *rxptr = db->rx_insert_ptr;
1282
1283 if (!(rxptr->rdes0 & cpu_to_le32(0x80000000))) {
1284 rxptr->rx_skb_ptr = skb;
1285 rxptr->rdes2 = cpu_to_le32(pci_map_single(db->pdev,
1286 skb_tail_pointer(skb),
1287 RX_ALLOC_SIZE,
1288 PCI_DMA_FROMDEVICE));
1289 wmb();
1290 rxptr->rdes0 = cpu_to_le32(0x80000000);
1291 db->rx_avail_cnt++;
1292 db->rx_insert_ptr = rxptr->next_rx_desc;
1293 } else
1294 ULI526X_DBUG(0, "SK Buffer reuse method error", db->rx_avail_cnt);
1295 }
1296
1297
1298 /*
1299 * Initialize transmit/Receive descriptor
1300 * Using Chain structure, and allocate Tx/Rx buffer
1301 */
1302
1303 static void uli526x_descriptor_init(struct uli526x_board_info *db, unsigned long ioaddr)
1304 {
1305 struct tx_desc *tmp_tx;
1306 struct rx_desc *tmp_rx;
1307 unsigned char *tmp_buf;
1308 dma_addr_t tmp_tx_dma, tmp_rx_dma;
1309 dma_addr_t tmp_buf_dma;
1310 int i;
1311
1312 ULI526X_DBUG(0, "uli526x_descriptor_init()", 0);
1313
1314 /* tx descriptor start pointer */
1315 db->tx_insert_ptr = db->first_tx_desc;
1316 db->tx_remove_ptr = db->first_tx_desc;
1317 outl(db->first_tx_desc_dma, ioaddr + DCR4); /* TX DESC address */
1318
1319 /* rx descriptor start pointer */
1320 db->first_rx_desc = (void *)db->first_tx_desc + sizeof(struct tx_desc) * TX_DESC_CNT;
1321 db->first_rx_desc_dma = db->first_tx_desc_dma + sizeof(struct tx_desc) * TX_DESC_CNT;
1322 db->rx_insert_ptr = db->first_rx_desc;
1323 db->rx_ready_ptr = db->first_rx_desc;
1324 outl(db->first_rx_desc_dma, ioaddr + DCR3); /* RX DESC address */
1325
1326 /* Init Transmit chain */
1327 tmp_buf = db->buf_pool_start;
1328 tmp_buf_dma = db->buf_pool_dma_start;
1329 tmp_tx_dma = db->first_tx_desc_dma;
1330 for (tmp_tx = db->first_tx_desc, i = 0; i < TX_DESC_CNT; i++, tmp_tx++) {
1331 tmp_tx->tx_buf_ptr = tmp_buf;
1332 tmp_tx->tdes0 = cpu_to_le32(0);
1333 tmp_tx->tdes1 = cpu_to_le32(0x81000000); /* IC, chain */
1334 tmp_tx->tdes2 = cpu_to_le32(tmp_buf_dma);
1335 tmp_tx_dma += sizeof(struct tx_desc);
1336 tmp_tx->tdes3 = cpu_to_le32(tmp_tx_dma);
1337 tmp_tx->next_tx_desc = tmp_tx + 1;
1338 tmp_buf = tmp_buf + TX_BUF_ALLOC;
1339 tmp_buf_dma = tmp_buf_dma + TX_BUF_ALLOC;
1340 }
1341 (--tmp_tx)->tdes3 = cpu_to_le32(db->first_tx_desc_dma);
1342 tmp_tx->next_tx_desc = db->first_tx_desc;
1343
1344 /* Init Receive descriptor chain */
1345 tmp_rx_dma=db->first_rx_desc_dma;
1346 for (tmp_rx = db->first_rx_desc, i = 0; i < RX_DESC_CNT; i++, tmp_rx++) {
1347 tmp_rx->rdes0 = cpu_to_le32(0);
1348 tmp_rx->rdes1 = cpu_to_le32(0x01000600);
1349 tmp_rx_dma += sizeof(struct rx_desc);
1350 tmp_rx->rdes3 = cpu_to_le32(tmp_rx_dma);
1351 tmp_rx->next_rx_desc = tmp_rx + 1;
1352 }
1353 (--tmp_rx)->rdes3 = cpu_to_le32(db->first_rx_desc_dma);
1354 tmp_rx->next_rx_desc = db->first_rx_desc;
1355
1356 /* pre-allocate Rx buffer */
1357 allocate_rx_buffer(db);
1358 }
1359
1360
1361 /*
1362 * Update CR6 value
1363 * Firstly stop ULI526X, then written value and start
1364 */
1365
1366 static void update_cr6(u32 cr6_data, unsigned long ioaddr)
1367 {
1368
1369 outl(cr6_data, ioaddr + DCR6);
1370 udelay(5);
1371 }
1372
1373
1374 /*
1375 * Send a setup frame for M5261/M5263
1376 * This setup frame initialize ULI526X address filter mode
1377 */
1378
1379 #ifdef __BIG_ENDIAN
1380 #define FLT_SHIFT 16
1381 #else
1382 #define FLT_SHIFT 0
1383 #endif
1384
1385 static void send_filter_frame(struct net_device *dev, int mc_cnt)
1386 {
1387 struct uli526x_board_info *db = netdev_priv(dev);
1388 struct netdev_hw_addr *ha;
1389 struct tx_desc *txptr;
1390 u16 * addrptr;
1391 u32 * suptr;
1392 int i;
1393
1394 ULI526X_DBUG(0, "send_filter_frame()", 0);
1395
1396 txptr = db->tx_insert_ptr;
1397 suptr = (u32 *) txptr->tx_buf_ptr;
1398
1399 /* Node address */
1400 addrptr = (u16 *) dev->dev_addr;
1401 *suptr++ = addrptr[0] << FLT_SHIFT;
1402 *suptr++ = addrptr[1] << FLT_SHIFT;
1403 *suptr++ = addrptr[2] << FLT_SHIFT;
1404
1405 /* broadcast address */
1406 *suptr++ = 0xffff << FLT_SHIFT;
1407 *suptr++ = 0xffff << FLT_SHIFT;
1408 *suptr++ = 0xffff << FLT_SHIFT;
1409
1410 /* fit the multicast address */
1411 netdev_for_each_mc_addr(ha, dev) {
1412 addrptr = (u16 *) ha->addr;
1413 *suptr++ = addrptr[0] << FLT_SHIFT;
1414 *suptr++ = addrptr[1] << FLT_SHIFT;
1415 *suptr++ = addrptr[2] << FLT_SHIFT;
1416 }
1417
1418 for (i = netdev_mc_count(dev); i < 14; i++) {
1419 *suptr++ = 0xffff << FLT_SHIFT;
1420 *suptr++ = 0xffff << FLT_SHIFT;
1421 *suptr++ = 0xffff << FLT_SHIFT;
1422 }
1423
1424 /* prepare the setup frame */
1425 db->tx_insert_ptr = txptr->next_tx_desc;
1426 txptr->tdes1 = cpu_to_le32(0x890000c0);
1427
1428 /* Resource Check and Send the setup packet */
1429 if (db->tx_packet_cnt < TX_DESC_CNT) {
1430 /* Resource Empty */
1431 db->tx_packet_cnt++;
1432 txptr->tdes0 = cpu_to_le32(0x80000000);
1433 update_cr6(db->cr6_data | 0x2000, dev->base_addr);
1434 outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */
1435 update_cr6(db->cr6_data, dev->base_addr);
1436 dev->trans_start = jiffies;
1437 } else
1438 pr_err("No Tx resource - Send_filter_frame!\n");
1439 }
1440
1441
1442 /*
1443 * Allocate rx buffer,
1444 * As possible as allocate maxiumn Rx buffer
1445 */
1446
1447 static void allocate_rx_buffer(struct uli526x_board_info *db)
1448 {
1449 struct rx_desc *rxptr;
1450 struct sk_buff *skb;
1451
1452 rxptr = db->rx_insert_ptr;
1453
1454 while(db->rx_avail_cnt < RX_DESC_CNT) {
1455 if ( ( skb = dev_alloc_skb(RX_ALLOC_SIZE) ) == NULL )
1456 break;
1457 rxptr->rx_skb_ptr = skb;
1458 rxptr->rdes2 = cpu_to_le32(pci_map_single(db->pdev,
1459 skb_tail_pointer(skb),
1460 RX_ALLOC_SIZE,
1461 PCI_DMA_FROMDEVICE));
1462 wmb();
1463 rxptr->rdes0 = cpu_to_le32(0x80000000);
1464 rxptr = rxptr->next_rx_desc;
1465 db->rx_avail_cnt++;
1466 }
1467
1468 db->rx_insert_ptr = rxptr;
1469 }
1470
1471
1472 /*
1473 * Read one word data from the serial ROM
1474 */
1475
1476 static u16 read_srom_word(long ioaddr, int offset)
1477 {
1478 int i;
1479 u16 srom_data = 0;
1480 long cr9_ioaddr = ioaddr + DCR9;
1481
1482 outl(CR9_SROM_READ, cr9_ioaddr);
1483 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1484
1485 /* Send the Read Command 110b */
1486 SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
1487 SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
1488 SROM_CLK_WRITE(SROM_DATA_0, cr9_ioaddr);
1489
1490 /* Send the offset */
1491 for (i = 5; i >= 0; i--) {
1492 srom_data = (offset & (1 << i)) ? SROM_DATA_1 : SROM_DATA_0;
1493 SROM_CLK_WRITE(srom_data, cr9_ioaddr);
1494 }
1495
1496 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1497
1498 for (i = 16; i > 0; i--) {
1499 outl(CR9_SROM_READ | CR9_SRCS | CR9_SRCLK, cr9_ioaddr);
1500 udelay(5);
1501 srom_data = (srom_data << 1) | ((inl(cr9_ioaddr) & CR9_CRDOUT) ? 1 : 0);
1502 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1503 udelay(5);
1504 }
1505
1506 outl(CR9_SROM_READ, cr9_ioaddr);
1507 return srom_data;
1508 }
1509
1510
1511 /*
1512 * Auto sense the media mode
1513 */
1514
1515 static u8 uli526x_sense_speed(struct uli526x_board_info * db)
1516 {
1517 u8 ErrFlag = 0;
1518 u16 phy_mode;
1519
1520 phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id);
1521 phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id);
1522
1523 if ( (phy_mode & 0x24) == 0x24 ) {
1524
1525 phy_mode = ((phy_read(db->ioaddr, db->phy_addr, 5, db->chip_id) & 0x01e0)<<7);
1526 if(phy_mode&0x8000)
1527 phy_mode = 0x8000;
1528 else if(phy_mode&0x4000)
1529 phy_mode = 0x4000;
1530 else if(phy_mode&0x2000)
1531 phy_mode = 0x2000;
1532 else
1533 phy_mode = 0x1000;
1534
1535 /* printk(DRV_NAME ": Phy_mode %x ",phy_mode); */
1536 switch (phy_mode) {
1537 case 0x1000: db->op_mode = ULI526X_10MHF; break;
1538 case 0x2000: db->op_mode = ULI526X_10MFD; break;
1539 case 0x4000: db->op_mode = ULI526X_100MHF; break;
1540 case 0x8000: db->op_mode = ULI526X_100MFD; break;
1541 default: db->op_mode = ULI526X_10MHF; ErrFlag = 1; break;
1542 }
1543 } else {
1544 db->op_mode = ULI526X_10MHF;
1545 ULI526X_DBUG(0, "Link Failed :", phy_mode);
1546 ErrFlag = 1;
1547 }
1548
1549 return ErrFlag;
1550 }
1551
1552
1553 /*
1554 * Set 10/100 phyxcer capability
1555 * AUTO mode : phyxcer register4 is NIC capability
1556 * Force mode: phyxcer register4 is the force media
1557 */
1558
1559 static void uli526x_set_phyxcer(struct uli526x_board_info *db)
1560 {
1561 u16 phy_reg;
1562
1563 /* Phyxcer capability setting */
1564 phy_reg = phy_read(db->ioaddr, db->phy_addr, 4, db->chip_id) & ~0x01e0;
1565
1566 if (db->media_mode & ULI526X_AUTO) {
1567 /* AUTO Mode */
1568 phy_reg |= db->PHY_reg4;
1569 } else {
1570 /* Force Mode */
1571 switch(db->media_mode) {
1572 case ULI526X_10MHF: phy_reg |= 0x20; break;
1573 case ULI526X_10MFD: phy_reg |= 0x40; break;
1574 case ULI526X_100MHF: phy_reg |= 0x80; break;
1575 case ULI526X_100MFD: phy_reg |= 0x100; break;
1576 }
1577
1578 }
1579
1580 /* Write new capability to Phyxcer Reg4 */
1581 if ( !(phy_reg & 0x01e0)) {
1582 phy_reg|=db->PHY_reg4;
1583 db->media_mode|=ULI526X_AUTO;
1584 }
1585 phy_write(db->ioaddr, db->phy_addr, 4, phy_reg, db->chip_id);
1586
1587 /* Restart Auto-Negotiation */
1588 phy_write(db->ioaddr, db->phy_addr, 0, 0x1200, db->chip_id);
1589 udelay(50);
1590 }
1591
1592
1593 /*
1594 * Process op-mode
1595 AUTO mode : PHY controller in Auto-negotiation Mode
1596 * Force mode: PHY controller in force mode with HUB
1597 * N-way force capability with SWITCH
1598 */
1599
1600 static void uli526x_process_mode(struct uli526x_board_info *db)
1601 {
1602 u16 phy_reg;
1603
1604 /* Full Duplex Mode Check */
1605 if (db->op_mode & 0x4)
1606 db->cr6_data |= CR6_FDM; /* Set Full Duplex Bit */
1607 else
1608 db->cr6_data &= ~CR6_FDM; /* Clear Full Duplex Bit */
1609
1610 update_cr6(db->cr6_data, db->ioaddr);
1611
1612 /* 10/100M phyxcer force mode need */
1613 if ( !(db->media_mode & 0x8)) {
1614 /* Forece Mode */
1615 phy_reg = phy_read(db->ioaddr, db->phy_addr, 6, db->chip_id);
1616 if ( !(phy_reg & 0x1) ) {
1617 /* parter without N-Way capability */
1618 phy_reg = 0x0;
1619 switch(db->op_mode) {
1620 case ULI526X_10MHF: phy_reg = 0x0; break;
1621 case ULI526X_10MFD: phy_reg = 0x100; break;
1622 case ULI526X_100MHF: phy_reg = 0x2000; break;
1623 case ULI526X_100MFD: phy_reg = 0x2100; break;
1624 }
1625 phy_write(db->ioaddr, db->phy_addr, 0, phy_reg, db->chip_id);
1626 }
1627 }
1628 }
1629
1630
1631 /*
1632 * Write a word to Phy register
1633 */
1634
1635 static void phy_write(unsigned long iobase, u8 phy_addr, u8 offset, u16 phy_data, u32 chip_id)
1636 {
1637 u16 i;
1638 unsigned long ioaddr;
1639
1640 if(chip_id == PCI_ULI5263_ID)
1641 {
1642 phy_writeby_cr10(iobase, phy_addr, offset, phy_data);
1643 return;
1644 }
1645 /* M5261/M5263 Chip */
1646 ioaddr = iobase + DCR9;
1647
1648 /* Send 33 synchronization clock to Phy controller */
1649 for (i = 0; i < 35; i++)
1650 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
1651
1652 /* Send start command(01) to Phy */
1653 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
1654 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
1655
1656 /* Send write command(01) to Phy */
1657 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
1658 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
1659
1660 /* Send Phy address */
1661 for (i = 0x10; i > 0; i = i >> 1)
1662 phy_write_1bit(ioaddr, phy_addr & i ? PHY_DATA_1 : PHY_DATA_0, chip_id);
1663
1664 /* Send register address */
1665 for (i = 0x10; i > 0; i = i >> 1)
1666 phy_write_1bit(ioaddr, offset & i ? PHY_DATA_1 : PHY_DATA_0, chip_id);
1667
1668 /* written trasnition */
1669 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
1670 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
1671
1672 /* Write a word data to PHY controller */
1673 for ( i = 0x8000; i > 0; i >>= 1)
1674 phy_write_1bit(ioaddr, phy_data & i ? PHY_DATA_1 : PHY_DATA_0, chip_id);
1675
1676 }
1677
1678
1679 /*
1680 * Read a word data from phy register
1681 */
1682
1683 static u16 phy_read(unsigned long iobase, u8 phy_addr, u8 offset, u32 chip_id)
1684 {
1685 int i;
1686 u16 phy_data;
1687 unsigned long ioaddr;
1688
1689 if(chip_id == PCI_ULI5263_ID)
1690 return phy_readby_cr10(iobase, phy_addr, offset);
1691 /* M5261/M5263 Chip */
1692 ioaddr = iobase + DCR9;
1693
1694 /* Send 33 synchronization clock to Phy controller */
1695 for (i = 0; i < 35; i++)
1696 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
1697
1698 /* Send start command(01) to Phy */
1699 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
1700 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
1701
1702 /* Send read command(10) to Phy */
1703 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
1704 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
1705
1706 /* Send Phy address */
1707 for (i = 0x10; i > 0; i = i >> 1)
1708 phy_write_1bit(ioaddr, phy_addr & i ? PHY_DATA_1 : PHY_DATA_0, chip_id);
1709
1710 /* Send register address */
1711 for (i = 0x10; i > 0; i = i >> 1)
1712 phy_write_1bit(ioaddr, offset & i ? PHY_DATA_1 : PHY_DATA_0, chip_id);
1713
1714 /* Skip transition state */
1715 phy_read_1bit(ioaddr, chip_id);
1716
1717 /* read 16bit data */
1718 for (phy_data = 0, i = 0; i < 16; i++) {
1719 phy_data <<= 1;
1720 phy_data |= phy_read_1bit(ioaddr, chip_id);
1721 }
1722
1723 return phy_data;
1724 }
1725
1726 static u16 phy_readby_cr10(unsigned long iobase, u8 phy_addr, u8 offset)
1727 {
1728 unsigned long ioaddr,cr10_value;
1729
1730 ioaddr = iobase + DCR10;
1731 cr10_value = phy_addr;
1732 cr10_value = (cr10_value<<5) + offset;
1733 cr10_value = (cr10_value<<16) + 0x08000000;
1734 outl(cr10_value,ioaddr);
1735 udelay(1);
1736 while(1)
1737 {
1738 cr10_value = inl(ioaddr);
1739 if(cr10_value&0x10000000)
1740 break;
1741 }
1742 return (cr10_value&0x0ffff);
1743 }
1744
1745 static void phy_writeby_cr10(unsigned long iobase, u8 phy_addr, u8 offset, u16 phy_data)
1746 {
1747 unsigned long ioaddr,cr10_value;
1748
1749 ioaddr = iobase + DCR10;
1750 cr10_value = phy_addr;
1751 cr10_value = (cr10_value<<5) + offset;
1752 cr10_value = (cr10_value<<16) + 0x04000000 + phy_data;
1753 outl(cr10_value,ioaddr);
1754 udelay(1);
1755 }
1756 /*
1757 * Write one bit data to Phy Controller
1758 */
1759
1760 static void phy_write_1bit(unsigned long ioaddr, u32 phy_data, u32 chip_id)
1761 {
1762 outl(phy_data , ioaddr); /* MII Clock Low */
1763 udelay(1);
1764 outl(phy_data | MDCLKH, ioaddr); /* MII Clock High */
1765 udelay(1);
1766 outl(phy_data , ioaddr); /* MII Clock Low */
1767 udelay(1);
1768 }
1769
1770
1771 /*
1772 * Read one bit phy data from PHY controller
1773 */
1774
1775 static u16 phy_read_1bit(unsigned long ioaddr, u32 chip_id)
1776 {
1777 u16 phy_data;
1778
1779 outl(0x50000 , ioaddr);
1780 udelay(1);
1781 phy_data = ( inl(ioaddr) >> 19 ) & 0x1;
1782 outl(0x40000 , ioaddr);
1783 udelay(1);
1784
1785 return phy_data;
1786 }
1787
1788
1789 static DEFINE_PCI_DEVICE_TABLE(uli526x_pci_tbl) = {
1790 { 0x10B9, 0x5261, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_ULI5261_ID },
1791 { 0x10B9, 0x5263, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_ULI5263_ID },
1792 { 0, }
1793 };
1794 MODULE_DEVICE_TABLE(pci, uli526x_pci_tbl);
1795
1796
1797 static struct pci_driver uli526x_driver = {
1798 .name = "uli526x",
1799 .id_table = uli526x_pci_tbl,
1800 .probe = uli526x_init_one,
1801 .remove = __devexit_p(uli526x_remove_one),
1802 .suspend = uli526x_suspend,
1803 .resume = uli526x_resume,
1804 };
1805
1806 MODULE_AUTHOR("Peer Chen, peer.chen@uli.com.tw");
1807 MODULE_DESCRIPTION("ULi M5261/M5263 fast ethernet driver");
1808 MODULE_LICENSE("GPL");
1809
1810 module_param(debug, int, 0644);
1811 module_param(mode, int, 0);
1812 module_param(cr6set, int, 0);
1813 MODULE_PARM_DESC(debug, "ULi M5261/M5263 enable debugging (0-1)");
1814 MODULE_PARM_DESC(mode, "ULi M5261/M5263: Bit 0: 10/100Mbps, bit 2: duplex, bit 8: HomePNA");
1815
1816 /* Description:
1817 * when user used insmod to add module, system invoked init_module()
1818 * to register the services.
1819 */
1820
1821 static int __init uli526x_init_module(void)
1822 {
1823
1824 printk(version);
1825 printed_version = 1;
1826
1827 ULI526X_DBUG(0, "init_module() ", debug);
1828
1829 if (debug)
1830 uli526x_debug = debug; /* set debug flag */
1831 if (cr6set)
1832 uli526x_cr6_user_set = cr6set;
1833
1834 switch (mode) {
1835 case ULI526X_10MHF:
1836 case ULI526X_100MHF:
1837 case ULI526X_10MFD:
1838 case ULI526X_100MFD:
1839 uli526x_media_mode = mode;
1840 break;
1841 default:
1842 uli526x_media_mode = ULI526X_AUTO;
1843 break;
1844 }
1845
1846 return pci_register_driver(&uli526x_driver);
1847 }
1848
1849
1850 /*
1851 * Description:
1852 * when user used rmmod to delete module, system invoked clean_module()
1853 * to un-register all registered services.
1854 */
1855
1856 static void __exit uli526x_cleanup_module(void)
1857 {
1858 ULI526X_DBUG(0, "uli526x_clean_module() ", debug);
1859 pci_unregister_driver(&uli526x_driver);
1860 }
1861
1862 module_init(uli526x_init_module);
1863 module_exit(uli526x_cleanup_module);
Tomato firmware and modifications.