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GUI: Fix Tomato RAF theme for all builds. Compilation typo.
[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / drivers / net / tc35815.c
blob2be521d273c0146182d613032d9a471fce6da1d4
1 /*
2 * tc35815.c: A TOSHIBA TC35815CF PCI 10/100Mbps ethernet driver for linux.
3 *
4 * Based on skelton.c by Donald Becker.
5 *
6 * This driver is a replacement of older and less maintained version.
7 * This is a header of the older version:
8 * -----<snip>-----
9 * Copyright 2001 MontaVista Software Inc.
10 * Author: MontaVista Software, Inc.
11 * ahennessy@mvista.com
12 * Copyright (C) 2000-2001 Toshiba Corporation
13 * static const char *version =
14 * "tc35815.c:v0.00 26/07/2000 by Toshiba Corporation\n";
15 * -----<snip>-----
16 *
17 * This file is subject to the terms and conditions of the GNU General Public
18 * License. See the file "COPYING" in the main directory of this archive
19 * for more details.
20 *
21 * (C) Copyright TOSHIBA CORPORATION 2004-2005
22 * All Rights Reserved.
23 */
24
25 #define DRV_VERSION "1.39"
26 static const char *version = "tc35815.c:v" DRV_VERSION "\n";
27 #define MODNAME "tc35815"
28
29 #include <linux/module.h>
30 #include <linux/kernel.h>
31 #include <linux/types.h>
32 #include <linux/fcntl.h>
33 #include <linux/interrupt.h>
34 #include <linux/ioport.h>
35 #include <linux/in.h>
36 #include <linux/if_vlan.h>
37 #include <linux/slab.h>
38 #include <linux/string.h>
39 #include <linux/spinlock.h>
40 #include <linux/errno.h>
41 #include <linux/init.h>
42 #include <linux/netdevice.h>
43 #include <linux/etherdevice.h>
44 #include <linux/skbuff.h>
45 #include <linux/delay.h>
46 #include <linux/pci.h>
47 #include <linux/phy.h>
48 #include <linux/workqueue.h>
49 #include <linux/platform_device.h>
50 #include <asm/io.h>
51 #include <asm/byteorder.h>
52
53 enum tc35815_chiptype {
54 TC35815CF = 0,
55 TC35815_NWU,
56 TC35815_TX4939,
57 };
58
59 /* indexed by tc35815_chiptype, above */
60 static const struct {
61 const char *name;
62 } chip_info[] __devinitdata = {
63 { "TOSHIBA TC35815CF 10/100BaseTX" },
64 { "TOSHIBA TC35815 with Wake on LAN" },
65 { "TOSHIBA TC35815/TX4939" },
66 };
67
68 static DEFINE_PCI_DEVICE_TABLE(tc35815_pci_tbl) = {
69 {PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC35815CF), .driver_data = TC35815CF },
70 {PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC35815_NWU), .driver_data = TC35815_NWU },
71 {PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC35815_TX4939), .driver_data = TC35815_TX4939 },
72 {0,}
73 };
74 MODULE_DEVICE_TABLE(pci, tc35815_pci_tbl);
75
76 /* see MODULE_PARM_DESC */
77 static struct tc35815_options {
78 int speed;
79 int duplex;
80 } options;
81
82 /*
83 * Registers
84 */
85 struct tc35815_regs {
86 __u32 DMA_Ctl; /* 0x00 */
87 __u32 TxFrmPtr;
88 __u32 TxThrsh;
89 __u32 TxPollCtr;
90 __u32 BLFrmPtr;
91 __u32 RxFragSize;
92 __u32 Int_En;
93 __u32 FDA_Bas;
94 __u32 FDA_Lim; /* 0x20 */
95 __u32 Int_Src;
96 __u32 unused0[2];
97 __u32 PauseCnt;
98 __u32 RemPauCnt;
99 __u32 TxCtlFrmStat;
100 __u32 unused1;
101 __u32 MAC_Ctl; /* 0x40 */
102 __u32 CAM_Ctl;
103 __u32 Tx_Ctl;
104 __u32 Tx_Stat;
105 __u32 Rx_Ctl;
106 __u32 Rx_Stat;
107 __u32 MD_Data;
108 __u32 MD_CA;
109 __u32 CAM_Adr; /* 0x60 */
110 __u32 CAM_Data;
111 __u32 CAM_Ena;
112 __u32 PROM_Ctl;
113 __u32 PROM_Data;
114 __u32 Algn_Cnt;
115 __u32 CRC_Cnt;
116 __u32 Miss_Cnt;
117 };
118
119 /*
120 * Bit assignments
121 */
122 /* DMA_Ctl bit asign ------------------------------------------------------- */
123 #define DMA_RxAlign 0x00c00000 /* 1:Reception Alignment */
124 #define DMA_RxAlign_1 0x00400000
125 #define DMA_RxAlign_2 0x00800000
126 #define DMA_RxAlign_3 0x00c00000
127 #define DMA_M66EnStat 0x00080000 /* 1:66MHz Enable State */
128 #define DMA_IntMask 0x00040000 /* 1:Interupt mask */
129 #define DMA_SWIntReq 0x00020000 /* 1:Software Interrupt request */
130 #define DMA_TxWakeUp 0x00010000 /* 1:Transmit Wake Up */
131 #define DMA_RxBigE 0x00008000 /* 1:Receive Big Endian */
132 #define DMA_TxBigE 0x00004000 /* 1:Transmit Big Endian */
133 #define DMA_TestMode 0x00002000 /* 1:Test Mode */
134 #define DMA_PowrMgmnt 0x00001000 /* 1:Power Management */
135 #define DMA_DmBurst_Mask 0x000001fc /* DMA Burst size */
136
137 /* RxFragSize bit asign ---------------------------------------------------- */
138 #define RxFrag_EnPack 0x00008000 /* 1:Enable Packing */
139 #define RxFrag_MinFragMask 0x00000ffc /* Minimum Fragment */
140
141 /* MAC_Ctl bit asign ------------------------------------------------------- */
142 #define MAC_Link10 0x00008000 /* 1:Link Status 10Mbits */
143 #define MAC_EnMissRoll 0x00002000 /* 1:Enable Missed Roll */
144 #define MAC_MissRoll 0x00000400 /* 1:Missed Roll */
145 #define MAC_Loop10 0x00000080 /* 1:Loop 10 Mbps */
146 #define MAC_Conn_Auto 0x00000000 /*00:Connection mode (Automatic) */
147 #define MAC_Conn_10M 0x00000020 /*01: (10Mbps endec)*/
148 #define MAC_Conn_Mll 0x00000040 /*10: (Mll clock) */
149 #define MAC_MacLoop 0x00000010 /* 1:MAC Loopback */
150 #define MAC_FullDup 0x00000008 /* 1:Full Duplex 0:Half Duplex */
151 #define MAC_Reset 0x00000004 /* 1:Software Reset */
152 #define MAC_HaltImm 0x00000002 /* 1:Halt Immediate */
153 #define MAC_HaltReq 0x00000001 /* 1:Halt request */
154
155 /* PROM_Ctl bit asign ------------------------------------------------------ */
156 #define PROM_Busy 0x00008000 /* 1:Busy (Start Operation) */
157 #define PROM_Read 0x00004000 /*10:Read operation */
158 #define PROM_Write 0x00002000 /*01:Write operation */
159 #define PROM_Erase 0x00006000 /*11:Erase operation */
160 /*00:Enable or Disable Writting, */
161 /* as specified in PROM_Addr. */
162 #define PROM_Addr_Ena 0x00000030 /*11xxxx:PROM Write enable */
163 /*00xxxx: disable */
164
165 /* CAM_Ctl bit asign ------------------------------------------------------- */
166 #define CAM_CompEn 0x00000010 /* 1:CAM Compare Enable */
167 #define CAM_NegCAM 0x00000008 /* 1:Reject packets CAM recognizes,*/
168 /* accept other */
169 #define CAM_BroadAcc 0x00000004 /* 1:Broadcast assept */
170 #define CAM_GroupAcc 0x00000002 /* 1:Multicast assept */
171 #define CAM_StationAcc 0x00000001 /* 1:unicast accept */
172
173 /* CAM_Ena bit asign ------------------------------------------------------- */
174 #define CAM_ENTRY_MAX 21 /* CAM Data entry max count */
175 #define CAM_Ena_Mask ((1<<CAM_ENTRY_MAX)-1) /* CAM Enable bits (Max 21bits) */
176 #define CAM_Ena_Bit(index) (1 << (index))
177 #define CAM_ENTRY_DESTINATION 0
178 #define CAM_ENTRY_SOURCE 1
179 #define CAM_ENTRY_MACCTL 20
180
181 /* Tx_Ctl bit asign -------------------------------------------------------- */
182 #define Tx_En 0x00000001 /* 1:Transmit enable */
183 #define Tx_TxHalt 0x00000002 /* 1:Transmit Halt Request */
184 #define Tx_NoPad 0x00000004 /* 1:Suppress Padding */
185 #define Tx_NoCRC 0x00000008 /* 1:Suppress Padding */
186 #define Tx_FBack 0x00000010 /* 1:Fast Back-off */
187 #define Tx_EnUnder 0x00000100 /* 1:Enable Underrun */
188 #define Tx_EnExDefer 0x00000200 /* 1:Enable Excessive Deferral */
189 #define Tx_EnLCarr 0x00000400 /* 1:Enable Lost Carrier */
190 #define Tx_EnExColl 0x00000800 /* 1:Enable Excessive Collision */
191 #define Tx_EnLateColl 0x00001000 /* 1:Enable Late Collision */
192 #define Tx_EnTxPar 0x00002000 /* 1:Enable Transmit Parity */
193 #define Tx_EnComp 0x00004000 /* 1:Enable Completion */
194
195 /* Tx_Stat bit asign ------------------------------------------------------- */
196 #define Tx_TxColl_MASK 0x0000000F /* Tx Collision Count */
197 #define Tx_ExColl 0x00000010 /* Excessive Collision */
198 #define Tx_TXDefer 0x00000020 /* Transmit Defered */
199 #define Tx_Paused 0x00000040 /* Transmit Paused */
200 #define Tx_IntTx 0x00000080 /* Interrupt on Tx */
201 #define Tx_Under 0x00000100 /* Underrun */
202 #define Tx_Defer 0x00000200 /* Deferral */
203 #define Tx_NCarr 0x00000400 /* No Carrier */
204 #define Tx_10Stat 0x00000800 /* 10Mbps Status */
205 #define Tx_LateColl 0x00001000 /* Late Collision */
206 #define Tx_TxPar 0x00002000 /* Tx Parity Error */
207 #define Tx_Comp 0x00004000 /* Completion */
208 #define Tx_Halted 0x00008000 /* Tx Halted */
209 #define Tx_SQErr 0x00010000 /* Signal Quality Error(SQE) */
210
211 /* Rx_Ctl bit asign -------------------------------------------------------- */
212 #define Rx_EnGood 0x00004000 /* 1:Enable Good */
213 #define Rx_EnRxPar 0x00002000 /* 1:Enable Receive Parity */
214 #define Rx_EnLongErr 0x00000800 /* 1:Enable Long Error */
215 #define Rx_EnOver 0x00000400 /* 1:Enable OverFlow */
216 #define Rx_EnCRCErr 0x00000200 /* 1:Enable CRC Error */
217 #define Rx_EnAlign 0x00000100 /* 1:Enable Alignment */
218 #define Rx_IgnoreCRC 0x00000040 /* 1:Ignore CRC Value */
219 #define Rx_StripCRC 0x00000010 /* 1:Strip CRC Value */
220 #define Rx_ShortEn 0x00000008 /* 1:Short Enable */
221 #define Rx_LongEn 0x00000004 /* 1:Long Enable */
222 #define Rx_RxHalt 0x00000002 /* 1:Receive Halt Request */
223 #define Rx_RxEn 0x00000001 /* 1:Receive Intrrupt Enable */
224
225 /* Rx_Stat bit asign ------------------------------------------------------- */
226 #define Rx_Halted 0x00008000 /* Rx Halted */
227 #define Rx_Good 0x00004000 /* Rx Good */
228 #define Rx_RxPar 0x00002000 /* Rx Parity Error */
229 #define Rx_TypePkt 0x00001000 /* Rx Type Packet */
230 #define Rx_LongErr 0x00000800 /* Rx Long Error */
231 #define Rx_Over 0x00000400 /* Rx Overflow */
232 #define Rx_CRCErr 0x00000200 /* Rx CRC Error */
233 #define Rx_Align 0x00000100 /* Rx Alignment Error */
234 #define Rx_10Stat 0x00000080 /* Rx 10Mbps Status */
235 #define Rx_IntRx 0x00000040 /* Rx Interrupt */
236 #define Rx_CtlRecd 0x00000020 /* Rx Control Receive */
237 #define Rx_InLenErr 0x00000010 /* Rx In Range Frame Length Error */
238
239 #define Rx_Stat_Mask 0x0000FFF0 /* Rx All Status Mask */
240
241 /* Int_En bit asign -------------------------------------------------------- */
242 #define Int_NRAbtEn 0x00000800 /* 1:Non-recoverable Abort Enable */
243 #define Int_TxCtlCmpEn 0x00000400 /* 1:Transmit Ctl Complete Enable */
244 #define Int_DmParErrEn 0x00000200 /* 1:DMA Parity Error Enable */
245 #define Int_DParDEn 0x00000100 /* 1:Data Parity Error Enable */
246 #define Int_EarNotEn 0x00000080 /* 1:Early Notify Enable */
247 #define Int_DParErrEn 0x00000040 /* 1:Detected Parity Error Enable */
248 #define Int_SSysErrEn 0x00000020 /* 1:Signalled System Error Enable */
249 #define Int_RMasAbtEn 0x00000010 /* 1:Received Master Abort Enable */
250 #define Int_RTargAbtEn 0x00000008 /* 1:Received Target Abort Enable */
251 #define Int_STargAbtEn 0x00000004 /* 1:Signalled Target Abort Enable */
252 #define Int_BLExEn 0x00000002 /* 1:Buffer List Exhausted Enable */
253 #define Int_FDAExEn 0x00000001 /* 1:Free Descriptor Area */
254 /* Exhausted Enable */
255
256 /* Int_Src bit asign ------------------------------------------------------- */
257 #define Int_NRabt 0x00004000 /* 1:Non Recoverable error */
258 #define Int_DmParErrStat 0x00002000 /* 1:DMA Parity Error & Clear */
259 #define Int_BLEx 0x00001000 /* 1:Buffer List Empty & Clear */
260 #define Int_FDAEx 0x00000800 /* 1:FDA Empty & Clear */
261 #define Int_IntNRAbt 0x00000400 /* 1:Non Recoverable Abort */
262 #define Int_IntCmp 0x00000200 /* 1:MAC control packet complete */
263 #define Int_IntExBD 0x00000100 /* 1:Interrupt Extra BD & Clear */
264 #define Int_DmParErr 0x00000080 /* 1:DMA Parity Error & Clear */
265 #define Int_IntEarNot 0x00000040 /* 1:Receive Data write & Clear */
266 #define Int_SWInt 0x00000020 /* 1:Software request & Clear */
267 #define Int_IntBLEx 0x00000010 /* 1:Buffer List Empty & Clear */
268 #define Int_IntFDAEx 0x00000008 /* 1:FDA Empty & Clear */
269 #define Int_IntPCI 0x00000004 /* 1:PCI controller & Clear */
270 #define Int_IntMacRx 0x00000002 /* 1:Rx controller & Clear */
271 #define Int_IntMacTx 0x00000001 /* 1:Tx controller & Clear */
272
273 /* MD_CA bit asign --------------------------------------------------------- */
274 #define MD_CA_PreSup 0x00001000 /* 1:Preamble Supress */
275 #define MD_CA_Busy 0x00000800 /* 1:Busy (Start Operation) */
276 #define MD_CA_Wr 0x00000400 /* 1:Write 0:Read */
277
278
279 /*
280 * Descriptors
281 */
282
283 /* Frame descripter */
284 struct FDesc {
285 volatile __u32 FDNext;
286 volatile __u32 FDSystem;
287 volatile __u32 FDStat;
288 volatile __u32 FDCtl;
289 };
290
291 /* Buffer descripter */
292 struct BDesc {
293 volatile __u32 BuffData;
294 volatile __u32 BDCtl;
295 };
296
297 #define FD_ALIGN 16
298
299 /* Frame Descripter bit asign ---------------------------------------------- */
300 #define FD_FDLength_MASK 0x0000FFFF /* Length MASK */
301 #define FD_BDCnt_MASK 0x001F0000 /* BD count MASK in FD */
302 #define FD_FrmOpt_MASK 0x7C000000 /* Frame option MASK */
303 #define FD_FrmOpt_BigEndian 0x40000000 /* Tx/Rx */
304 #define FD_FrmOpt_IntTx 0x20000000 /* Tx only */
305 #define FD_FrmOpt_NoCRC 0x10000000 /* Tx only */
306 #define FD_FrmOpt_NoPadding 0x08000000 /* Tx only */
307 #define FD_FrmOpt_Packing 0x04000000 /* Rx only */
308 #define FD_CownsFD 0x80000000 /* FD Controller owner bit */
309 #define FD_Next_EOL 0x00000001 /* FD EOL indicator */
310 #define FD_BDCnt_SHIFT 16
311
312 /* Buffer Descripter bit asign --------------------------------------------- */
313 #define BD_BuffLength_MASK 0x0000FFFF /* Recieve Data Size */
314 #define BD_RxBDID_MASK 0x00FF0000 /* BD ID Number MASK */
315 #define BD_RxBDSeqN_MASK 0x7F000000 /* Rx BD Sequence Number */
316 #define BD_CownsBD 0x80000000 /* BD Controller owner bit */
317 #define BD_RxBDID_SHIFT 16
318 #define BD_RxBDSeqN_SHIFT 24
319
320
321 /* Some useful constants. */
322
323 #define TX_CTL_CMD (Tx_EnTxPar | Tx_EnLateColl | \
324 Tx_EnExColl | Tx_EnLCarr | Tx_EnExDefer | Tx_EnUnder | \
325 Tx_En) /* maybe 0x7b01 */
326 /* Do not use Rx_StripCRC -- it causes trouble on BLEx/FDAEx condition */
327 #define RX_CTL_CMD (Rx_EnGood | Rx_EnRxPar | Rx_EnLongErr | Rx_EnOver \
328 | Rx_EnCRCErr | Rx_EnAlign | Rx_RxEn) /* maybe 0x6f01 */
329 #define INT_EN_CMD (Int_NRAbtEn | \
330 Int_DmParErrEn | Int_DParDEn | Int_DParErrEn | \
331 Int_SSysErrEn | Int_RMasAbtEn | Int_RTargAbtEn | \
332 Int_STargAbtEn | \
333 Int_BLExEn | Int_FDAExEn) /* maybe 0xb7f*/
334 #define DMA_CTL_CMD DMA_BURST_SIZE
335 #define HAVE_DMA_RXALIGN(lp) likely((lp)->chiptype != TC35815CF)
336
337 /* Tuning parameters */
338 #define DMA_BURST_SIZE 32
339 #define TX_THRESHOLD 1024
340 /* used threshold with packet max byte for low pci transfer ability.*/
341 #define TX_THRESHOLD_MAX 1536
342 /* setting threshold max value when overrun error occured this count. */
343 #define TX_THRESHOLD_KEEP_LIMIT 10
344
345 /* 16 + RX_BUF_NUM * 8 + RX_FD_NUM * 16 + TX_FD_NUM * 32 <= PAGE_SIZE*FD_PAGE_NUM */
346 #define FD_PAGE_NUM 4
347 #define RX_BUF_NUM 128 /* < 256 */
348 #define RX_FD_NUM 256 /* >= 32 */
349 #define TX_FD_NUM 128
350 #if RX_CTL_CMD & Rx_LongEn
351 #define RX_BUF_SIZE PAGE_SIZE
352 #elif RX_CTL_CMD & Rx_StripCRC
353 #define RX_BUF_SIZE \
354 L1_CACHE_ALIGN(ETH_FRAME_LEN + VLAN_HLEN + NET_IP_ALIGN)
355 #else
356 #define RX_BUF_SIZE \
357 L1_CACHE_ALIGN(ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN + NET_IP_ALIGN)
358 #endif
359 #define RX_FD_RESERVE (2 / 2) /* max 2 BD per RxFD */
360 #define NAPI_WEIGHT 16
361
362 struct TxFD {
363 struct FDesc fd;
364 struct BDesc bd;
365 struct BDesc unused;
366 };
367
368 struct RxFD {
369 struct FDesc fd;
370 struct BDesc bd[0]; /* variable length */
371 };
372
373 struct FrFD {
374 struct FDesc fd;
375 struct BDesc bd[RX_BUF_NUM];
376 };
377
378
379 #define tc_readl(addr) ioread32(addr)
380 #define tc_writel(d, addr) iowrite32(d, addr)
381
382 #define TC35815_TX_TIMEOUT msecs_to_jiffies(400)
383
384 /* Information that need to be kept for each controller. */
385 struct tc35815_local {
386 struct pci_dev *pci_dev;
387
388 struct net_device *dev;
389 struct napi_struct napi;
390
391 /* statistics */
392 struct {
393 int max_tx_qlen;
394 int tx_ints;
395 int rx_ints;
396 int tx_underrun;
397 } lstats;
398
399 /* Tx control lock. This protects the transmit buffer ring
400 * state along with the "tx full" state of the driver. This
401 * means all netif_queue flow control actions are protected
402 * by this lock as well.
403 */
404 spinlock_t lock;
405 spinlock_t rx_lock;
406
407 struct mii_bus *mii_bus;
408 struct phy_device *phy_dev;
409 int duplex;
410 int speed;
411 int link;
412 struct work_struct restart_work;
413
414 /*
415 * Transmitting: Batch Mode.
416 * 1 BD in 1 TxFD.
417 * Receiving: Non-Packing Mode.
418 * 1 circular FD for Free Buffer List.
419 * RX_BUF_NUM BD in Free Buffer FD.
420 * One Free Buffer BD has ETH_FRAME_LEN data buffer.
421 */
422 void *fd_buf; /* for TxFD, RxFD, FrFD */
423 dma_addr_t fd_buf_dma;
424 struct TxFD *tfd_base;
425 unsigned int tfd_start;
426 unsigned int tfd_end;
427 struct RxFD *rfd_base;
428 struct RxFD *rfd_limit;
429 struct RxFD *rfd_cur;
430 struct FrFD *fbl_ptr;
431 unsigned int fbl_count;
432 struct {
433 struct sk_buff *skb;
434 dma_addr_t skb_dma;
435 } tx_skbs[TX_FD_NUM], rx_skbs[RX_BUF_NUM];
436 u32 msg_enable;
437 enum tc35815_chiptype chiptype;
438 };
439
440 static inline dma_addr_t fd_virt_to_bus(struct tc35815_local *lp, void *virt)
441 {
442 return lp->fd_buf_dma + ((u8 *)virt - (u8 *)lp->fd_buf);
443 }
444 #ifdef DEBUG
445 static inline void *fd_bus_to_virt(struct tc35815_local *lp, dma_addr_t bus)
446 {
447 return (void *)((u8 *)lp->fd_buf + (bus - lp->fd_buf_dma));
448 }
449 #endif
450 static struct sk_buff *alloc_rxbuf_skb(struct net_device *dev,
451 struct pci_dev *hwdev,
452 dma_addr_t *dma_handle)
453 {
454 struct sk_buff *skb;
455 skb = dev_alloc_skb(RX_BUF_SIZE);
456 if (!skb)
457 return NULL;
458 *dma_handle = pci_map_single(hwdev, skb->data, RX_BUF_SIZE,
459 PCI_DMA_FROMDEVICE);
460 if (pci_dma_mapping_error(hwdev, *dma_handle)) {
461 dev_kfree_skb_any(skb);
462 return NULL;
463 }
464 skb_reserve(skb, 2); /* make IP header 4byte aligned */
465 return skb;
466 }
467
468 static void free_rxbuf_skb(struct pci_dev *hwdev, struct sk_buff *skb, dma_addr_t dma_handle)
469 {
470 pci_unmap_single(hwdev, dma_handle, RX_BUF_SIZE,
471 PCI_DMA_FROMDEVICE);
472 dev_kfree_skb_any(skb);
473 }
474
475 /* Index to functions, as function prototypes. */
476
477 static int tc35815_open(struct net_device *dev);
478 static int tc35815_send_packet(struct sk_buff *skb, struct net_device *dev);
479 static irqreturn_t tc35815_interrupt(int irq, void *dev_id);
480 static int tc35815_rx(struct net_device *dev, int limit);
481 static int tc35815_poll(struct napi_struct *napi, int budget);
482 static void tc35815_txdone(struct net_device *dev);
483 static int tc35815_close(struct net_device *dev);
484 static struct net_device_stats *tc35815_get_stats(struct net_device *dev);
485 static void tc35815_set_multicast_list(struct net_device *dev);
486 static void tc35815_tx_timeout(struct net_device *dev);
487 static int tc35815_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
488 #ifdef CONFIG_NET_POLL_CONTROLLER
489 static void tc35815_poll_controller(struct net_device *dev);
490 #endif
491 static const struct ethtool_ops tc35815_ethtool_ops;
492
493 /* Example routines you must write ;->. */
494 static void tc35815_chip_reset(struct net_device *dev);
495 static void tc35815_chip_init(struct net_device *dev);
496
497 #ifdef DEBUG
498 static void panic_queues(struct net_device *dev);
499 #endif
500
501 static void tc35815_restart_work(struct work_struct *work);
502
503 static int tc_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
504 {
505 struct net_device *dev = bus->priv;
506 struct tc35815_regs __iomem *tr =
507 (struct tc35815_regs __iomem *)dev->base_addr;
508 unsigned long timeout = jiffies + HZ;
509
510 tc_writel(MD_CA_Busy | (mii_id << 5) | (regnum & 0x1f), &tr->MD_CA);
511 udelay(12); /* it takes 32 x 400ns at least */
512 while (tc_readl(&tr->MD_CA) & MD_CA_Busy) {
513 if (time_after(jiffies, timeout))
514 return -EIO;
515 cpu_relax();
516 }
517 return tc_readl(&tr->MD_Data) & 0xffff;
518 }
519
520 static int tc_mdio_write(struct mii_bus *bus, int mii_id, int regnum, u16 val)
521 {
522 struct net_device *dev = bus->priv;
523 struct tc35815_regs __iomem *tr =
524 (struct tc35815_regs __iomem *)dev->base_addr;
525 unsigned long timeout = jiffies + HZ;
526
527 tc_writel(val, &tr->MD_Data);
528 tc_writel(MD_CA_Busy | MD_CA_Wr | (mii_id << 5) | (regnum & 0x1f),
529 &tr->MD_CA);
530 udelay(12); /* it takes 32 x 400ns at least */
531 while (tc_readl(&tr->MD_CA) & MD_CA_Busy) {
532 if (time_after(jiffies, timeout))
533 return -EIO;
534 cpu_relax();
535 }
536 return 0;
537 }
538
539 static void tc_handle_link_change(struct net_device *dev)
540 {
541 struct tc35815_local *lp = netdev_priv(dev);
542 struct phy_device *phydev = lp->phy_dev;
543 unsigned long flags;
544 int status_change = 0;
545
546 spin_lock_irqsave(&lp->lock, flags);
547 if (phydev->link &&
548 (lp->speed != phydev->speed || lp->duplex != phydev->duplex)) {
549 struct tc35815_regs __iomem *tr =
550 (struct tc35815_regs __iomem *)dev->base_addr;
551 u32 reg;
552
553 reg = tc_readl(&tr->MAC_Ctl);
554 reg |= MAC_HaltReq;
555 tc_writel(reg, &tr->MAC_Ctl);
556 if (phydev->duplex == DUPLEX_FULL)
557 reg |= MAC_FullDup;
558 else
559 reg &= ~MAC_FullDup;
560 tc_writel(reg, &tr->MAC_Ctl);
561 reg &= ~MAC_HaltReq;
562 tc_writel(reg, &tr->MAC_Ctl);
563
564 /*
565 * TX4939 PCFG.SPEEDn bit will be changed on
566 * NETDEV_CHANGE event.
567 */
568 if (phydev->duplex == DUPLEX_HALF &&
569 lp->chiptype != TC35815_TX4939)
570 tc_writel(tc_readl(&tr->Tx_Ctl) | Tx_EnLCarr,
571 &tr->Tx_Ctl);
572
573 lp->speed = phydev->speed;
574 lp->duplex = phydev->duplex;
575 status_change = 1;
576 }
577
578 if (phydev->link != lp->link) {
579 if (phydev->link) {
580 /* delayed promiscuous enabling */
581 if (dev->flags & IFF_PROMISC)
582 tc35815_set_multicast_list(dev);
583 } else {
584 lp->speed = 0;
585 lp->duplex = -1;
586 }
587 lp->link = phydev->link;
588
589 status_change = 1;
590 }
591 spin_unlock_irqrestore(&lp->lock, flags);
592
593 if (status_change && netif_msg_link(lp)) {
594 phy_print_status(phydev);
595 pr_debug("%s: MII BMCR %04x BMSR %04x LPA %04x\n",
596 dev->name,
597 phy_read(phydev, MII_BMCR),
598 phy_read(phydev, MII_BMSR),
599 phy_read(phydev, MII_LPA));
600 }
601 }
602
603 static int tc_mii_probe(struct net_device *dev)
604 {
605 struct tc35815_local *lp = netdev_priv(dev);
606 struct phy_device *phydev = NULL;
607 int phy_addr;
608 u32 dropmask;
609
610 /* find the first phy */
611 for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
612 if (lp->mii_bus->phy_map[phy_addr]) {
613 if (phydev) {
614 printk(KERN_ERR "%s: multiple PHYs found\n",
615 dev->name);
616 return -EINVAL;
617 }
618 phydev = lp->mii_bus->phy_map[phy_addr];
619 break;
620 }
621 }
622
623 if (!phydev) {
624 printk(KERN_ERR "%s: no PHY found\n", dev->name);
625 return -ENODEV;
626 }
627
628 /* attach the mac to the phy */
629 phydev = phy_connect(dev, dev_name(&phydev->dev),
630 &tc_handle_link_change, 0,
631 lp->chiptype == TC35815_TX4939 ?
632 PHY_INTERFACE_MODE_RMII : PHY_INTERFACE_MODE_MII);
633 if (IS_ERR(phydev)) {
634 printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
635 return PTR_ERR(phydev);
636 }
637 printk(KERN_INFO "%s: attached PHY driver [%s] "
638 "(mii_bus:phy_addr=%s, id=%x)\n",
639 dev->name, phydev->drv->name, dev_name(&phydev->dev),
640 phydev->phy_id);
641
642 /* mask with MAC supported features */
643 phydev->supported &= PHY_BASIC_FEATURES;
644 dropmask = 0;
645 if (options.speed == 10)
646 dropmask |= SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full;
647 else if (options.speed == 100)
648 dropmask |= SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full;
649 if (options.duplex == 1)
650 dropmask |= SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Full;
651 else if (options.duplex == 2)
652 dropmask |= SUPPORTED_10baseT_Half | SUPPORTED_100baseT_Half;
653 phydev->supported &= ~dropmask;
654 phydev->advertising = phydev->supported;
655
656 lp->link = 0;
657 lp->speed = 0;
658 lp->duplex = -1;
659 lp->phy_dev = phydev;
660
661 return 0;
662 }
663
664 static int tc_mii_init(struct net_device *dev)
665 {
666 struct tc35815_local *lp = netdev_priv(dev);
667 int err;
668 int i;
669
670 lp->mii_bus = mdiobus_alloc();
671 if (lp->mii_bus == NULL) {
672 err = -ENOMEM;
673 goto err_out;
674 }
675
676 lp->mii_bus->name = "tc35815_mii_bus";
677 lp->mii_bus->read = tc_mdio_read;
678 lp->mii_bus->write = tc_mdio_write;
679 snprintf(lp->mii_bus->id, MII_BUS_ID_SIZE, "%x",
680 (lp->pci_dev->bus->number << 8) | lp->pci_dev->devfn);
681 lp->mii_bus->priv = dev;
682 lp->mii_bus->parent = &lp->pci_dev->dev;
683 lp->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
684 if (!lp->mii_bus->irq) {
685 err = -ENOMEM;
686 goto err_out_free_mii_bus;
687 }
688
689 for (i = 0; i < PHY_MAX_ADDR; i++)
690 lp->mii_bus->irq[i] = PHY_POLL;
691
692 err = mdiobus_register(lp->mii_bus);
693 if (err)
694 goto err_out_free_mdio_irq;
695 err = tc_mii_probe(dev);
696 if (err)
697 goto err_out_unregister_bus;
698 return 0;
699
700 err_out_unregister_bus:
701 mdiobus_unregister(lp->mii_bus);
702 err_out_free_mdio_irq:
703 kfree(lp->mii_bus->irq);
704 err_out_free_mii_bus:
705 mdiobus_free(lp->mii_bus);
706 err_out:
707 return err;
708 }
709
710 #ifdef CONFIG_CPU_TX49XX
711 /*
712 * Find a platform_device providing a MAC address. The platform code
713 * should provide a "tc35815-mac" device with a MAC address in its
714 * platform_data.
715 */
716 static int __devinit tc35815_mac_match(struct device *dev, void *data)
717 {
718 struct platform_device *plat_dev = to_platform_device(dev);
719 struct pci_dev *pci_dev = data;
720 unsigned int id = pci_dev->irq;
721 return !strcmp(plat_dev->name, "tc35815-mac") && plat_dev->id == id;
722 }
723
724 static int __devinit tc35815_read_plat_dev_addr(struct net_device *dev)
725 {
726 struct tc35815_local *lp = netdev_priv(dev);
727 struct device *pd = bus_find_device(&platform_bus_type, NULL,
728 lp->pci_dev, tc35815_mac_match);
729 if (pd) {
730 if (pd->platform_data)
731 memcpy(dev->dev_addr, pd->platform_data, ETH_ALEN);
732 put_device(pd);
733 return is_valid_ether_addr(dev->dev_addr) ? 0 : -ENODEV;
734 }
735 return -ENODEV;
736 }
737 #else
738 static int __devinit tc35815_read_plat_dev_addr(struct net_device *dev)
739 {
740 return -ENODEV;
741 }
742 #endif
743
744 static int __devinit tc35815_init_dev_addr(struct net_device *dev)
745 {
746 struct tc35815_regs __iomem *tr =
747 (struct tc35815_regs __iomem *)dev->base_addr;
748 int i;
749
750 while (tc_readl(&tr->PROM_Ctl) & PROM_Busy)
751 ;
752 for (i = 0; i < 6; i += 2) {
753 unsigned short data;
754 tc_writel(PROM_Busy | PROM_Read | (i / 2 + 2), &tr->PROM_Ctl);
755 while (tc_readl(&tr->PROM_Ctl) & PROM_Busy)
756 ;
757 data = tc_readl(&tr->PROM_Data);
758 dev->dev_addr[i] = data & 0xff;
759 dev->dev_addr[i+1] = data >> 8;
760 }
761 if (!is_valid_ether_addr(dev->dev_addr))
762 return tc35815_read_plat_dev_addr(dev);
763 return 0;
764 }
765
766 static const struct net_device_ops tc35815_netdev_ops = {
767 .ndo_open = tc35815_open,
768 .ndo_stop = tc35815_close,
769 .ndo_start_xmit = tc35815_send_packet,
770 .ndo_get_stats = tc35815_get_stats,
771 .ndo_set_multicast_list = tc35815_set_multicast_list,
772 .ndo_tx_timeout = tc35815_tx_timeout,
773 .ndo_do_ioctl = tc35815_ioctl,
774 .ndo_validate_addr = eth_validate_addr,
775 .ndo_change_mtu = eth_change_mtu,
776 .ndo_set_mac_address = eth_mac_addr,
777 #ifdef CONFIG_NET_POLL_CONTROLLER
778 .ndo_poll_controller = tc35815_poll_controller,
779 #endif
780 };
781
782 static int __devinit tc35815_init_one(struct pci_dev *pdev,
783 const struct pci_device_id *ent)
784 {
785 void __iomem *ioaddr = NULL;
786 struct net_device *dev;
787 struct tc35815_local *lp;
788 int rc;
789
790 static int printed_version;
791 if (!printed_version++) {
792 printk(version);
793 dev_printk(KERN_DEBUG, &pdev->dev,
794 "speed:%d duplex:%d\n",
795 options.speed, options.duplex);
796 }
797
798 if (!pdev->irq) {
799 dev_warn(&pdev->dev, "no IRQ assigned.\n");
800 return -ENODEV;
801 }
802
803 /* dev zeroed in alloc_etherdev */
804 dev = alloc_etherdev(sizeof(*lp));
805 if (dev == NULL) {
806 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
807 return -ENOMEM;
808 }
809 SET_NETDEV_DEV(dev, &pdev->dev);
810 lp = netdev_priv(dev);
811 lp->dev = dev;
812
813 /* enable device (incl. PCI PM wakeup), and bus-mastering */
814 rc = pcim_enable_device(pdev);
815 if (rc)
816 goto err_out;
817 rc = pcim_iomap_regions(pdev, 1 << 1, MODNAME);
818 if (rc)
819 goto err_out;
820 pci_set_master(pdev);
821 ioaddr = pcim_iomap_table(pdev)[1];
822
823 /* Initialize the device structure. */
824 dev->netdev_ops = &tc35815_netdev_ops;
825 dev->ethtool_ops = &tc35815_ethtool_ops;
826 dev->watchdog_timeo = TC35815_TX_TIMEOUT;
827 netif_napi_add(dev, &lp->napi, tc35815_poll, NAPI_WEIGHT);
828
829 dev->irq = pdev->irq;
830 dev->base_addr = (unsigned long)ioaddr;
831
832 INIT_WORK(&lp->restart_work, tc35815_restart_work);
833 spin_lock_init(&lp->lock);
834 spin_lock_init(&lp->rx_lock);
835 lp->pci_dev = pdev;
836 lp->chiptype = ent->driver_data;
837
838 lp->msg_enable = NETIF_MSG_TX_ERR | NETIF_MSG_HW | NETIF_MSG_DRV | NETIF_MSG_LINK;
839 pci_set_drvdata(pdev, dev);
840
841 /* Soft reset the chip. */
842 tc35815_chip_reset(dev);
843
844 /* Retrieve the ethernet address. */
845 if (tc35815_init_dev_addr(dev)) {
846 dev_warn(&pdev->dev, "not valid ether addr\n");
847 random_ether_addr(dev->dev_addr);
848 }
849
850 rc = register_netdev(dev);
851 if (rc)
852 goto err_out;
853
854 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
855 printk(KERN_INFO "%s: %s at 0x%lx, %pM, IRQ %d\n",
856 dev->name,
857 chip_info[ent->driver_data].name,
858 dev->base_addr,
859 dev->dev_addr,
860 dev->irq);
861
862 rc = tc_mii_init(dev);
863 if (rc)
864 goto err_out_unregister;
865
866 return 0;
867
868 err_out_unregister:
869 unregister_netdev(dev);
870 err_out:
871 free_netdev(dev);
872 return rc;
873 }
874
875
876 static void __devexit tc35815_remove_one(struct pci_dev *pdev)
877 {
878 struct net_device *dev = pci_get_drvdata(pdev);
879 struct tc35815_local *lp = netdev_priv(dev);
880
881 phy_disconnect(lp->phy_dev);
882 mdiobus_unregister(lp->mii_bus);
883 kfree(lp->mii_bus->irq);
884 mdiobus_free(lp->mii_bus);
885 unregister_netdev(dev);
886 free_netdev(dev);
887 pci_set_drvdata(pdev, NULL);
888 }
889
890 static int
891 tc35815_init_queues(struct net_device *dev)
892 {
893 struct tc35815_local *lp = netdev_priv(dev);
894 int i;
895 unsigned long fd_addr;
896
897 if (!lp->fd_buf) {
898 BUG_ON(sizeof(struct FDesc) +
899 sizeof(struct BDesc) * RX_BUF_NUM +
900 sizeof(struct FDesc) * RX_FD_NUM +
901 sizeof(struct TxFD) * TX_FD_NUM >
902 PAGE_SIZE * FD_PAGE_NUM);
903
904 lp->fd_buf = pci_alloc_consistent(lp->pci_dev,
905 PAGE_SIZE * FD_PAGE_NUM,
906 &lp->fd_buf_dma);
907 if (!lp->fd_buf)
908 return -ENOMEM;
909 for (i = 0; i < RX_BUF_NUM; i++) {
910 lp->rx_skbs[i].skb =
911 alloc_rxbuf_skb(dev, lp->pci_dev,
912 &lp->rx_skbs[i].skb_dma);
913 if (!lp->rx_skbs[i].skb) {
914 while (--i >= 0) {
915 free_rxbuf_skb(lp->pci_dev,
916 lp->rx_skbs[i].skb,
917 lp->rx_skbs[i].skb_dma);
918 lp->rx_skbs[i].skb = NULL;
919 }
920 pci_free_consistent(lp->pci_dev,
921 PAGE_SIZE * FD_PAGE_NUM,
922 lp->fd_buf,
923 lp->fd_buf_dma);
924 lp->fd_buf = NULL;
925 return -ENOMEM;
926 }
927 }
928 printk(KERN_DEBUG "%s: FD buf %p DataBuf",
929 dev->name, lp->fd_buf);
930 printk("\n");
931 } else {
932 for (i = 0; i < FD_PAGE_NUM; i++)
933 clear_page((void *)((unsigned long)lp->fd_buf +
934 i * PAGE_SIZE));
935 }
936 fd_addr = (unsigned long)lp->fd_buf;
937
938 /* Free Descriptors (for Receive) */
939 lp->rfd_base = (struct RxFD *)fd_addr;
940 fd_addr += sizeof(struct RxFD) * RX_FD_NUM;
941 for (i = 0; i < RX_FD_NUM; i++)
942 lp->rfd_base[i].fd.FDCtl = cpu_to_le32(FD_CownsFD);
943 lp->rfd_cur = lp->rfd_base;
944 lp->rfd_limit = (struct RxFD *)fd_addr - (RX_FD_RESERVE + 1);
945
946 /* Transmit Descriptors */
947 lp->tfd_base = (struct TxFD *)fd_addr;
948 fd_addr += sizeof(struct TxFD) * TX_FD_NUM;
949 for (i = 0; i < TX_FD_NUM; i++) {
950 lp->tfd_base[i].fd.FDNext = cpu_to_le32(fd_virt_to_bus(lp, &lp->tfd_base[i+1]));
951 lp->tfd_base[i].fd.FDSystem = cpu_to_le32(0xffffffff);
952 lp->tfd_base[i].fd.FDCtl = cpu_to_le32(0);
953 }
954 lp->tfd_base[TX_FD_NUM-1].fd.FDNext = cpu_to_le32(fd_virt_to_bus(lp, &lp->tfd_base[0]));
955 lp->tfd_start = 0;
956 lp->tfd_end = 0;
957
958 /* Buffer List (for Receive) */
959 lp->fbl_ptr = (struct FrFD *)fd_addr;
960 lp->fbl_ptr->fd.FDNext = cpu_to_le32(fd_virt_to_bus(lp, lp->fbl_ptr));
961 lp->fbl_ptr->fd.FDCtl = cpu_to_le32(RX_BUF_NUM | FD_CownsFD);
962 /*
963 * move all allocated skbs to head of rx_skbs[] array.
964 * fbl_count mighe not be RX_BUF_NUM if alloc_rxbuf_skb() in
965 * tc35815_rx() had failed.
966 */
967 lp->fbl_count = 0;
968 for (i = 0; i < RX_BUF_NUM; i++) {
969 if (lp->rx_skbs[i].skb) {
970 if (i != lp->fbl_count) {
971 lp->rx_skbs[lp->fbl_count].skb =
972 lp->rx_skbs[i].skb;
973 lp->rx_skbs[lp->fbl_count].skb_dma =
974 lp->rx_skbs[i].skb_dma;
975 }
976 lp->fbl_count++;
977 }
978 }
979 for (i = 0; i < RX_BUF_NUM; i++) {
980 if (i >= lp->fbl_count) {
981 lp->fbl_ptr->bd[i].BuffData = 0;
982 lp->fbl_ptr->bd[i].BDCtl = 0;
983 continue;
984 }
985 lp->fbl_ptr->bd[i].BuffData =
986 cpu_to_le32(lp->rx_skbs[i].skb_dma);
987 /* BDID is index of FrFD.bd[] */
988 lp->fbl_ptr->bd[i].BDCtl =
989 cpu_to_le32(BD_CownsBD | (i << BD_RxBDID_SHIFT) |
990 RX_BUF_SIZE);
991 }
992
993 printk(KERN_DEBUG "%s: TxFD %p RxFD %p FrFD %p\n",
994 dev->name, lp->tfd_base, lp->rfd_base, lp->fbl_ptr);
995 return 0;
996 }
997
998 static void
999 tc35815_clear_queues(struct net_device *dev)
1000 {
1001 struct tc35815_local *lp = netdev_priv(dev);
1002 int i;
1003
1004 for (i = 0; i < TX_FD_NUM; i++) {
1005 u32 fdsystem = le32_to_cpu(lp->tfd_base[i].fd.FDSystem);
1006 struct sk_buff *skb =
1007 fdsystem != 0xffffffff ?
1008 lp->tx_skbs[fdsystem].skb : NULL;
1009 #ifdef DEBUG
1010 if (lp->tx_skbs[i].skb != skb) {
1011 printk("%s: tx_skbs mismatch(%d).\n", dev->name, i);
1012 panic_queues(dev);
1013 }
1014 #else
1015 BUG_ON(lp->tx_skbs[i].skb != skb);
1016 #endif
1017 if (skb) {
1018 pci_unmap_single(lp->pci_dev, lp->tx_skbs[i].skb_dma, skb->len, PCI_DMA_TODEVICE);
1019 lp->tx_skbs[i].skb = NULL;
1020 lp->tx_skbs[i].skb_dma = 0;
1021 dev_kfree_skb_any(skb);
1022 }
1023 lp->tfd_base[i].fd.FDSystem = cpu_to_le32(0xffffffff);
1024 }
1025
1026 tc35815_init_queues(dev);
1027 }
1028
1029 static void
1030 tc35815_free_queues(struct net_device *dev)
1031 {
1032 struct tc35815_local *lp = netdev_priv(dev);
1033 int i;
1034
1035 if (lp->tfd_base) {
1036 for (i = 0; i < TX_FD_NUM; i++) {
1037 u32 fdsystem = le32_to_cpu(lp->tfd_base[i].fd.FDSystem);
1038 struct sk_buff *skb =
1039 fdsystem != 0xffffffff ?
1040 lp->tx_skbs[fdsystem].skb : NULL;
1041 #ifdef DEBUG
1042 if (lp->tx_skbs[i].skb != skb) {
1043 printk("%s: tx_skbs mismatch(%d).\n", dev->name, i);
1044 panic_queues(dev);
1045 }
1046 #else
1047 BUG_ON(lp->tx_skbs[i].skb != skb);
1048 #endif
1049 if (skb) {
1050 dev_kfree_skb(skb);
1051 pci_unmap_single(lp->pci_dev, lp->tx_skbs[i].skb_dma, skb->len, PCI_DMA_TODEVICE);
1052 lp->tx_skbs[i].skb = NULL;
1053 lp->tx_skbs[i].skb_dma = 0;
1054 }
1055 lp->tfd_base[i].fd.FDSystem = cpu_to_le32(0xffffffff);
1056 }
1057 }
1058
1059 lp->rfd_base = NULL;
1060 lp->rfd_limit = NULL;
1061 lp->rfd_cur = NULL;
1062 lp->fbl_ptr = NULL;
1063
1064 for (i = 0; i < RX_BUF_NUM; i++) {
1065 if (lp->rx_skbs[i].skb) {
1066 free_rxbuf_skb(lp->pci_dev, lp->rx_skbs[i].skb,
1067 lp->rx_skbs[i].skb_dma);
1068 lp->rx_skbs[i].skb = NULL;
1069 }
1070 }
1071 if (lp->fd_buf) {
1072 pci_free_consistent(lp->pci_dev, PAGE_SIZE * FD_PAGE_NUM,
1073 lp->fd_buf, lp->fd_buf_dma);
1074 lp->fd_buf = NULL;
1075 }
1076 }
1077
1078 static void
1079 dump_txfd(struct TxFD *fd)
1080 {
1081 printk("TxFD(%p): %08x %08x %08x %08x\n", fd,
1082 le32_to_cpu(fd->fd.FDNext),
1083 le32_to_cpu(fd->fd.FDSystem),
1084 le32_to_cpu(fd->fd.FDStat),
1085 le32_to_cpu(fd->fd.FDCtl));
1086 printk("BD: ");
1087 printk(" %08x %08x",
1088 le32_to_cpu(fd->bd.BuffData),
1089 le32_to_cpu(fd->bd.BDCtl));
1090 printk("\n");
1091 }
1092
1093 static int
1094 dump_rxfd(struct RxFD *fd)
1095 {
1096 int i, bd_count = (le32_to_cpu(fd->fd.FDCtl) & FD_BDCnt_MASK) >> FD_BDCnt_SHIFT;
1097 if (bd_count > 8)
1098 bd_count = 8;
1099 printk("RxFD(%p): %08x %08x %08x %08x\n", fd,
1100 le32_to_cpu(fd->fd.FDNext),
1101 le32_to_cpu(fd->fd.FDSystem),
1102 le32_to_cpu(fd->fd.FDStat),
1103 le32_to_cpu(fd->fd.FDCtl));
1104 if (le32_to_cpu(fd->fd.FDCtl) & FD_CownsFD)
1105 return 0;
1106 printk("BD: ");
1107 for (i = 0; i < bd_count; i++)
1108 printk(" %08x %08x",
1109 le32_to_cpu(fd->bd[i].BuffData),
1110 le32_to_cpu(fd->bd[i].BDCtl));
1111 printk("\n");
1112 return bd_count;
1113 }
1114
1115 #ifdef DEBUG
1116 static void
1117 dump_frfd(struct FrFD *fd)
1118 {
1119 int i;
1120 printk("FrFD(%p): %08x %08x %08x %08x\n", fd,
1121 le32_to_cpu(fd->fd.FDNext),
1122 le32_to_cpu(fd->fd.FDSystem),
1123 le32_to_cpu(fd->fd.FDStat),
1124 le32_to_cpu(fd->fd.FDCtl));
1125 printk("BD: ");
1126 for (i = 0; i < RX_BUF_NUM; i++)
1127 printk(" %08x %08x",
1128 le32_to_cpu(fd->bd[i].BuffData),
1129 le32_to_cpu(fd->bd[i].BDCtl));
1130 printk("\n");
1131 }
1132
1133 static void
1134 panic_queues(struct net_device *dev)
1135 {
1136 struct tc35815_local *lp = netdev_priv(dev);
1137 int i;
1138
1139 printk("TxFD base %p, start %u, end %u\n",
1140 lp->tfd_base, lp->tfd_start, lp->tfd_end);
1141 printk("RxFD base %p limit %p cur %p\n",
1142 lp->rfd_base, lp->rfd_limit, lp->rfd_cur);
1143 printk("FrFD %p\n", lp->fbl_ptr);
1144 for (i = 0; i < TX_FD_NUM; i++)
1145 dump_txfd(&lp->tfd_base[i]);
1146 for (i = 0; i < RX_FD_NUM; i++) {
1147 int bd_count = dump_rxfd(&lp->rfd_base[i]);
1148 i += (bd_count + 1) / 2; /* skip BDs */
1149 }
1150 dump_frfd(lp->fbl_ptr);
1151 panic("%s: Illegal queue state.", dev->name);
1152 }
1153 #endif
1154
1155 static void print_eth(const u8 *add)
1156 {
1157 printk(KERN_DEBUG "print_eth(%p)\n", add);
1158 printk(KERN_DEBUG " %pM => %pM : %02x%02x\n",
1159 add + 6, add, add[12], add[13]);
1160 }
1161
1162 static int tc35815_tx_full(struct net_device *dev)
1163 {
1164 struct tc35815_local *lp = netdev_priv(dev);
1165 return ((lp->tfd_start + 1) % TX_FD_NUM == lp->tfd_end);
1166 }
1167
1168 static void tc35815_restart(struct net_device *dev)
1169 {
1170 struct tc35815_local *lp = netdev_priv(dev);
1171
1172 if (lp->phy_dev) {
1173 int timeout;
1174
1175 phy_write(lp->phy_dev, MII_BMCR, BMCR_RESET);
1176 timeout = 100;
1177 while (--timeout) {
1178 if (!(phy_read(lp->phy_dev, MII_BMCR) & BMCR_RESET))
1179 break;
1180 udelay(1);
1181 }
1182 if (!timeout)
1183 printk(KERN_ERR "%s: BMCR reset failed.\n", dev->name);
1184 }
1185
1186 spin_lock_bh(&lp->rx_lock);
1187 spin_lock_irq(&lp->lock);
1188 tc35815_chip_reset(dev);
1189 tc35815_clear_queues(dev);
1190 tc35815_chip_init(dev);
1191 /* Reconfigure CAM again since tc35815_chip_init() initialize it. */
1192 tc35815_set_multicast_list(dev);
1193 spin_unlock_irq(&lp->lock);
1194 spin_unlock_bh(&lp->rx_lock);
1195
1196 netif_wake_queue(dev);
1197 }
1198
1199 static void tc35815_restart_work(struct work_struct *work)
1200 {
1201 struct tc35815_local *lp =
1202 container_of(work, struct tc35815_local, restart_work);
1203 struct net_device *dev = lp->dev;
1204
1205 tc35815_restart(dev);
1206 }
1207
1208 static void tc35815_schedule_restart(struct net_device *dev)
1209 {
1210 struct tc35815_local *lp = netdev_priv(dev);
1211 struct tc35815_regs __iomem *tr =
1212 (struct tc35815_regs __iomem *)dev->base_addr;
1213 unsigned long flags;
1214
1215 /* disable interrupts */
1216 spin_lock_irqsave(&lp->lock, flags);
1217 tc_writel(0, &tr->Int_En);
1218 tc_writel(tc_readl(&tr->DMA_Ctl) | DMA_IntMask, &tr->DMA_Ctl);
1219 schedule_work(&lp->restart_work);
1220 spin_unlock_irqrestore(&lp->lock, flags);
1221 }
1222
1223 static void tc35815_tx_timeout(struct net_device *dev)
1224 {
1225 struct tc35815_regs __iomem *tr =
1226 (struct tc35815_regs __iomem *)dev->base_addr;
1227
1228 printk(KERN_WARNING "%s: transmit timed out, status %#x\n",
1229 dev->name, tc_readl(&tr->Tx_Stat));
1230
1231 /* Try to restart the adaptor. */
1232 tc35815_schedule_restart(dev);
1233 dev->stats.tx_errors++;
1234 }
1235
1236 /*
1237 * Open/initialize the controller. This is called (in the current kernel)
1238 * sometime after booting when the 'ifconfig' program is run.
1239 *
1240 * This routine should set everything up anew at each open, even
1241 * registers that "should" only need to be set once at boot, so that
1242 * there is non-reboot way to recover if something goes wrong.
1243 */
1244 static int
1245 tc35815_open(struct net_device *dev)
1246 {
1247 struct tc35815_local *lp = netdev_priv(dev);
1248
1249 /*
1250 * This is used if the interrupt line can turned off (shared).
1251 * See 3c503.c for an example of selecting the IRQ at config-time.
1252 */
1253 if (request_irq(dev->irq, tc35815_interrupt, IRQF_SHARED,
1254 dev->name, dev))
1255 return -EAGAIN;
1256
1257 tc35815_chip_reset(dev);
1258
1259 if (tc35815_init_queues(dev) != 0) {
1260 free_irq(dev->irq, dev);
1261 return -EAGAIN;
1262 }
1263
1264 napi_enable(&lp->napi);
1265
1266 /* Reset the hardware here. Don't forget to set the station address. */
1267 spin_lock_irq(&lp->lock);
1268 tc35815_chip_init(dev);
1269 spin_unlock_irq(&lp->lock);
1270
1271 netif_carrier_off(dev);
1272 /* schedule a link state check */
1273 phy_start(lp->phy_dev);
1274
1275 /* We are now ready to accept transmit requeusts from
1276 * the queueing layer of the networking.
1277 */
1278 netif_start_queue(dev);
1279
1280 return 0;
1281 }
1282
1283 /* This will only be invoked if your driver is _not_ in XOFF state.
1284 * What this means is that you need not check it, and that this
1285 * invariant will hold if you make sure that the netif_*_queue()
1286 * calls are done at the proper times.
1287 */
1288 static int tc35815_send_packet(struct sk_buff *skb, struct net_device *dev)
1289 {
1290 struct tc35815_local *lp = netdev_priv(dev);
1291 struct TxFD *txfd;
1292 unsigned long flags;
1293
1294 /* If some error occurs while trying to transmit this
1295 * packet, you should return '1' from this function.
1296 * In such a case you _may not_ do anything to the
1297 * SKB, it is still owned by the network queueing
1298 * layer when an error is returned. This means you
1299 * may not modify any SKB fields, you may not free
1300 * the SKB, etc.
1301 */
1302
1303 /* This is the most common case for modern hardware.
1304 * The spinlock protects this code from the TX complete
1305 * hardware interrupt handler. Queue flow control is
1306 * thus managed under this lock as well.
1307 */
1308 spin_lock_irqsave(&lp->lock, flags);
1309
1310 /* failsafe... (handle txdone now if half of FDs are used) */
1311 if ((lp->tfd_start + TX_FD_NUM - lp->tfd_end) % TX_FD_NUM >
1312 TX_FD_NUM / 2)
1313 tc35815_txdone(dev);
1314
1315 if (netif_msg_pktdata(lp))
1316 print_eth(skb->data);
1317 #ifdef DEBUG
1318 if (lp->tx_skbs[lp->tfd_start].skb) {
1319 printk("%s: tx_skbs conflict.\n", dev->name);
1320 panic_queues(dev);
1321 }
1322 #else
1323 BUG_ON(lp->tx_skbs[lp->tfd_start].skb);
1324 #endif
1325 lp->tx_skbs[lp->tfd_start].skb = skb;
1326 lp->tx_skbs[lp->tfd_start].skb_dma = pci_map_single(lp->pci_dev, skb->data, skb->len, PCI_DMA_TODEVICE);
1327
1328 /*add to ring */
1329 txfd = &lp->tfd_base[lp->tfd_start];
1330 txfd->bd.BuffData = cpu_to_le32(lp->tx_skbs[lp->tfd_start].skb_dma);
1331 txfd->bd.BDCtl = cpu_to_le32(skb->len);
1332 txfd->fd.FDSystem = cpu_to_le32(lp->tfd_start);
1333 txfd->fd.FDCtl = cpu_to_le32(FD_CownsFD | (1 << FD_BDCnt_SHIFT));
1334
1335 if (lp->tfd_start == lp->tfd_end) {
1336 struct tc35815_regs __iomem *tr =
1337 (struct tc35815_regs __iomem *)dev->base_addr;
1338 /* Start DMA Transmitter. */
1339 txfd->fd.FDNext |= cpu_to_le32(FD_Next_EOL);
1340 txfd->fd.FDCtl |= cpu_to_le32(FD_FrmOpt_IntTx);
1341 if (netif_msg_tx_queued(lp)) {
1342 printk("%s: starting TxFD.\n", dev->name);
1343 dump_txfd(txfd);
1344 }
1345 tc_writel(fd_virt_to_bus(lp, txfd), &tr->TxFrmPtr);
1346 } else {
1347 txfd->fd.FDNext &= cpu_to_le32(~FD_Next_EOL);
1348 if (netif_msg_tx_queued(lp)) {
1349 printk("%s: queueing TxFD.\n", dev->name);
1350 dump_txfd(txfd);
1351 }
1352 }
1353 lp->tfd_start = (lp->tfd_start + 1) % TX_FD_NUM;
1354
1355 /* If we just used up the very last entry in the
1356 * TX ring on this device, tell the queueing
1357 * layer to send no more.
1358 */
1359 if (tc35815_tx_full(dev)) {
1360 if (netif_msg_tx_queued(lp))
1361 printk(KERN_WARNING "%s: TxFD Exhausted.\n", dev->name);
1362 netif_stop_queue(dev);
1363 }
1364
1365 /* When the TX completion hw interrupt arrives, this
1366 * is when the transmit statistics are updated.
1367 */
1368
1369 spin_unlock_irqrestore(&lp->lock, flags);
1370 return NETDEV_TX_OK;
1371 }
1372
1373 #define FATAL_ERROR_INT \
1374 (Int_IntPCI | Int_DmParErr | Int_IntNRAbt)
1375 static void tc35815_fatal_error_interrupt(struct net_device *dev, u32 status)
1376 {
1377 static int count;
1378 printk(KERN_WARNING "%s: Fatal Error Intterrupt (%#x):",
1379 dev->name, status);
1380 if (status & Int_IntPCI)
1381 printk(" IntPCI");
1382 if (status & Int_DmParErr)
1383 printk(" DmParErr");
1384 if (status & Int_IntNRAbt)
1385 printk(" IntNRAbt");
1386 printk("\n");
1387 if (count++ > 100)
1388 panic("%s: Too many fatal errors.", dev->name);
1389 printk(KERN_WARNING "%s: Resetting ...\n", dev->name);
1390 /* Try to restart the adaptor. */
1391 tc35815_schedule_restart(dev);
1392 }
1393
1394 static int tc35815_do_interrupt(struct net_device *dev, u32 status, int limit)
1395 {
1396 struct tc35815_local *lp = netdev_priv(dev);
1397 int ret = -1;
1398
1399 /* Fatal errors... */
1400 if (status & FATAL_ERROR_INT) {
1401 tc35815_fatal_error_interrupt(dev, status);
1402 return 0;
1403 }
1404 /* recoverable errors */
1405 if (status & Int_IntFDAEx) {
1406 if (netif_msg_rx_err(lp))
1407 dev_warn(&dev->dev,
1408 "Free Descriptor Area Exhausted (%#x).\n",
1409 status);
1410 dev->stats.rx_dropped++;
1411 ret = 0;
1412 }
1413 if (status & Int_IntBLEx) {
1414 if (netif_msg_rx_err(lp))
1415 dev_warn(&dev->dev,
1416 "Buffer List Exhausted (%#x).\n",
1417 status);
1418 dev->stats.rx_dropped++;
1419 ret = 0;
1420 }
1421 if (status & Int_IntExBD) {
1422 if (netif_msg_rx_err(lp))
1423 dev_warn(&dev->dev,
1424 "Excessive Buffer Descriptiors (%#x).\n",
1425 status);
1426 dev->stats.rx_length_errors++;
1427 ret = 0;
1428 }
1429
1430 /* normal notification */
1431 if (status & Int_IntMacRx) {
1432 /* Got a packet(s). */
1433 ret = tc35815_rx(dev, limit);
1434 lp->lstats.rx_ints++;
1435 }
1436 if (status & Int_IntMacTx) {
1437 /* Transmit complete. */
1438 lp->lstats.tx_ints++;
1439 spin_lock_irq(&lp->lock);
1440 tc35815_txdone(dev);
1441 spin_unlock_irq(&lp->lock);
1442 if (ret < 0)
1443 ret = 0;
1444 }
1445 return ret;
1446 }
1447
1448 /*
1449 * The typical workload of the driver:
1450 * Handle the network interface interrupts.
1451 */
1452 static irqreturn_t tc35815_interrupt(int irq, void *dev_id)
1453 {
1454 struct net_device *dev = dev_id;
1455 struct tc35815_local *lp = netdev_priv(dev);
1456 struct tc35815_regs __iomem *tr =
1457 (struct tc35815_regs __iomem *)dev->base_addr;
1458 u32 dmactl = tc_readl(&tr->DMA_Ctl);
1459
1460 if (!(dmactl & DMA_IntMask)) {
1461 /* disable interrupts */
1462 tc_writel(dmactl | DMA_IntMask, &tr->DMA_Ctl);
1463 if (napi_schedule_prep(&lp->napi))
1464 __napi_schedule(&lp->napi);
1465 else {
1466 printk(KERN_ERR "%s: interrupt taken in poll\n",
1467 dev->name);
1468 BUG();
1469 }
1470 (void)tc_readl(&tr->Int_Src); /* flush */
1471 return IRQ_HANDLED;
1472 }
1473 return IRQ_NONE;
1474 }
1475
1476 #ifdef CONFIG_NET_POLL_CONTROLLER
1477 static void tc35815_poll_controller(struct net_device *dev)
1478 {
1479 disable_irq(dev->irq);
1480 tc35815_interrupt(dev->irq, dev);
1481 enable_irq(dev->irq);
1482 }
1483 #endif
1484
1485 /* We have a good packet(s), get it/them out of the buffers. */
1486 static int
1487 tc35815_rx(struct net_device *dev, int limit)
1488 {
1489 struct tc35815_local *lp = netdev_priv(dev);
1490 unsigned int fdctl;
1491 int i;
1492 int received = 0;
1493
1494 while (!((fdctl = le32_to_cpu(lp->rfd_cur->fd.FDCtl)) & FD_CownsFD)) {
1495 int status = le32_to_cpu(lp->rfd_cur->fd.FDStat);
1496 int pkt_len = fdctl & FD_FDLength_MASK;
1497 int bd_count = (fdctl & FD_BDCnt_MASK) >> FD_BDCnt_SHIFT;
1498 #ifdef DEBUG
1499 struct RxFD *next_rfd;
1500 #endif
1501 #if (RX_CTL_CMD & Rx_StripCRC) == 0
1502 pkt_len -= ETH_FCS_LEN;
1503 #endif
1504
1505 if (netif_msg_rx_status(lp))
1506 dump_rxfd(lp->rfd_cur);
1507 if (status & Rx_Good) {
1508 struct sk_buff *skb;
1509 unsigned char *data;
1510 int cur_bd;
1511
1512 if (--limit < 0)
1513 break;
1514 BUG_ON(bd_count > 1);
1515 cur_bd = (le32_to_cpu(lp->rfd_cur->bd[0].BDCtl)
1516 & BD_RxBDID_MASK) >> BD_RxBDID_SHIFT;
1517 #ifdef DEBUG
1518 if (cur_bd >= RX_BUF_NUM) {
1519 printk("%s: invalid BDID.\n", dev->name);
1520 panic_queues(dev);
1521 }
1522 BUG_ON(lp->rx_skbs[cur_bd].skb_dma !=
1523 (le32_to_cpu(lp->rfd_cur->bd[0].BuffData) & ~3));
1524 if (!lp->rx_skbs[cur_bd].skb) {
1525 printk("%s: NULL skb.\n", dev->name);
1526 panic_queues(dev);
1527 }
1528 #else
1529 BUG_ON(cur_bd >= RX_BUF_NUM);
1530 #endif
1531 skb = lp->rx_skbs[cur_bd].skb;
1532 prefetch(skb->data);
1533 lp->rx_skbs[cur_bd].skb = NULL;
1534 pci_unmap_single(lp->pci_dev,
1535 lp->rx_skbs[cur_bd].skb_dma,
1536 RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
1537 if (!HAVE_DMA_RXALIGN(lp) && NET_IP_ALIGN)
1538 memmove(skb->data, skb->data - NET_IP_ALIGN,
1539 pkt_len);
1540 data = skb_put(skb, pkt_len);
1541 if (netif_msg_pktdata(lp))
1542 print_eth(data);
1543 skb->protocol = eth_type_trans(skb, dev);
1544 netif_receive_skb(skb);
1545 received++;
1546 dev->stats.rx_packets++;
1547 dev->stats.rx_bytes += pkt_len;
1548 } else {
1549 dev->stats.rx_errors++;
1550 if (netif_msg_rx_err(lp))
1551 dev_info(&dev->dev, "Rx error (status %x)\n",
1552 status & Rx_Stat_Mask);
1553 if ((status & Rx_LongErr) && (status & Rx_CRCErr)) {
1554 status &= ~(Rx_LongErr|Rx_CRCErr);
1555 status |= Rx_Over;
1556 }
1557 if (status & Rx_LongErr)
1558 dev->stats.rx_length_errors++;
1559 if (status & Rx_Over)
1560 dev->stats.rx_fifo_errors++;
1561 if (status & Rx_CRCErr)
1562 dev->stats.rx_crc_errors++;
1563 if (status & Rx_Align)
1564 dev->stats.rx_frame_errors++;
1565 }
1566
1567 if (bd_count > 0) {
1568 /* put Free Buffer back to controller */
1569 int bdctl = le32_to_cpu(lp->rfd_cur->bd[bd_count - 1].BDCtl);
1570 unsigned char id =
1571 (bdctl & BD_RxBDID_MASK) >> BD_RxBDID_SHIFT;
1572 #ifdef DEBUG
1573 if (id >= RX_BUF_NUM) {
1574 printk("%s: invalid BDID.\n", dev->name);
1575 panic_queues(dev);
1576 }
1577 #else
1578 BUG_ON(id >= RX_BUF_NUM);
1579 #endif
1580 /* free old buffers */
1581 lp->fbl_count--;
1582 while (lp->fbl_count < RX_BUF_NUM)
1583 {
1584 unsigned char curid =
1585 (id + 1 + lp->fbl_count) % RX_BUF_NUM;
1586 struct BDesc *bd = &lp->fbl_ptr->bd[curid];
1587 #ifdef DEBUG
1588 bdctl = le32_to_cpu(bd->BDCtl);
1589 if (bdctl & BD_CownsBD) {
1590 printk("%s: Freeing invalid BD.\n",
1591 dev->name);
1592 panic_queues(dev);
1593 }
1594 #endif
1595 /* pass BD to controller */
1596 if (!lp->rx_skbs[curid].skb) {
1597 lp->rx_skbs[curid].skb =
1598 alloc_rxbuf_skb(dev,
1599 lp->pci_dev,
1600 &lp->rx_skbs[curid].skb_dma);
1601 if (!lp->rx_skbs[curid].skb)
1602 break; /* try on next reception */
1603 bd->BuffData = cpu_to_le32(lp->rx_skbs[curid].skb_dma);
1604 }
1605 /* Note: BDLength was modified by chip. */
1606 bd->BDCtl = cpu_to_le32(BD_CownsBD |
1607 (curid << BD_RxBDID_SHIFT) |
1608 RX_BUF_SIZE);
1609 lp->fbl_count++;
1610 }
1611 }
1612
1613 /* put RxFD back to controller */
1614 #ifdef DEBUG
1615 next_rfd = fd_bus_to_virt(lp,
1616 le32_to_cpu(lp->rfd_cur->fd.FDNext));
1617 if (next_rfd < lp->rfd_base || next_rfd > lp->rfd_limit) {
1618 printk("%s: RxFD FDNext invalid.\n", dev->name);
1619 panic_queues(dev);
1620 }
1621 #endif
1622 for (i = 0; i < (bd_count + 1) / 2 + 1; i++) {
1623 /* pass FD to controller */
1624 #ifdef DEBUG
1625 lp->rfd_cur->fd.FDNext = cpu_to_le32(0xdeaddead);
1626 #else
1627 lp->rfd_cur->fd.FDNext = cpu_to_le32(FD_Next_EOL);
1628 #endif
1629 lp->rfd_cur->fd.FDCtl = cpu_to_le32(FD_CownsFD);
1630 lp->rfd_cur++;
1631 }
1632 if (lp->rfd_cur > lp->rfd_limit)
1633 lp->rfd_cur = lp->rfd_base;
1634 #ifdef DEBUG
1635 if (lp->rfd_cur != next_rfd)
1636 printk("rfd_cur = %p, next_rfd %p\n",
1637 lp->rfd_cur, next_rfd);
1638 #endif
1639 }
1640
1641 return received;
1642 }
1643
1644 static int tc35815_poll(struct napi_struct *napi, int budget)
1645 {
1646 struct tc35815_local *lp = container_of(napi, struct tc35815_local, napi);
1647 struct net_device *dev = lp->dev;
1648 struct tc35815_regs __iomem *tr =
1649 (struct tc35815_regs __iomem *)dev->base_addr;
1650 int received = 0, handled;
1651 u32 status;
1652
1653 spin_lock(&lp->rx_lock);
1654 status = tc_readl(&tr->Int_Src);
1655 do {
1656 /* BLEx, FDAEx will be cleared later */
1657 tc_writel(status & ~(Int_BLEx | Int_FDAEx),
1658 &tr->Int_Src); /* write to clear */
1659
1660 handled = tc35815_do_interrupt(dev, status, budget - received);
1661 if (status & (Int_BLEx | Int_FDAEx))
1662 tc_writel(status & (Int_BLEx | Int_FDAEx),
1663 &tr->Int_Src);
1664 if (handled >= 0) {
1665 received += handled;
1666 if (received >= budget)
1667 break;
1668 }
1669 status = tc_readl(&tr->Int_Src);
1670 } while (status);
1671 spin_unlock(&lp->rx_lock);
1672
1673 if (received < budget) {
1674 napi_complete(napi);
1675 /* enable interrupts */
1676 tc_writel(tc_readl(&tr->DMA_Ctl) & ~DMA_IntMask, &tr->DMA_Ctl);
1677 }
1678 return received;
1679 }
1680
1681 #define TX_STA_ERR (Tx_ExColl|Tx_Under|Tx_Defer|Tx_NCarr|Tx_LateColl|Tx_TxPar|Tx_SQErr)
1682
1683 static void
1684 tc35815_check_tx_stat(struct net_device *dev, int status)
1685 {
1686 struct tc35815_local *lp = netdev_priv(dev);
1687 const char *msg = NULL;
1688
1689 /* count collisions */
1690 if (status & Tx_ExColl)
1691 dev->stats.collisions += 16;
1692 if (status & Tx_TxColl_MASK)
1693 dev->stats.collisions += status & Tx_TxColl_MASK;
1694
1695 /* TX4939 does not have NCarr */
1696 if (lp->chiptype == TC35815_TX4939)
1697 status &= ~Tx_NCarr;
1698 if (!lp->link || lp->duplex == DUPLEX_FULL)
1699 status &= ~Tx_NCarr;
1700
1701 if (!(status & TX_STA_ERR)) {
1702 /* no error. */
1703 dev->stats.tx_packets++;
1704 return;
1705 }
1706
1707 dev->stats.tx_errors++;
1708 if (status & Tx_ExColl) {
1709 dev->stats.tx_aborted_errors++;
1710 msg = "Excessive Collision.";
1711 }
1712 if (status & Tx_Under) {
1713 dev->stats.tx_fifo_errors++;
1714 msg = "Tx FIFO Underrun.";
1715 if (lp->lstats.tx_underrun < TX_THRESHOLD_KEEP_LIMIT) {
1716 lp->lstats.tx_underrun++;
1717 if (lp->lstats.tx_underrun >= TX_THRESHOLD_KEEP_LIMIT) {
1718 struct tc35815_regs __iomem *tr =
1719 (struct tc35815_regs __iomem *)dev->base_addr;
1720 tc_writel(TX_THRESHOLD_MAX, &tr->TxThrsh);
1721 msg = "Tx FIFO Underrun.Change Tx threshold to max.";
1722 }
1723 }
1724 }
1725 if (status & Tx_Defer) {
1726 dev->stats.tx_fifo_errors++;
1727 msg = "Excessive Deferral.";
1728 }
1729 if (status & Tx_NCarr) {
1730 dev->stats.tx_carrier_errors++;
1731 msg = "Lost Carrier Sense.";
1732 }
1733 if (status & Tx_LateColl) {
1734 dev->stats.tx_aborted_errors++;
1735 msg = "Late Collision.";
1736 }
1737 if (status & Tx_TxPar) {
1738 dev->stats.tx_fifo_errors++;
1739 msg = "Transmit Parity Error.";
1740 }
1741 if (status & Tx_SQErr) {
1742 dev->stats.tx_heartbeat_errors++;
1743 msg = "Signal Quality Error.";
1744 }
1745 if (msg && netif_msg_tx_err(lp))
1746 printk(KERN_WARNING "%s: %s (%#x)\n", dev->name, msg, status);
1747 }
1748
1749 /* This handles TX complete events posted by the device
1750 * via interrupts.
1751 */
1752 static void
1753 tc35815_txdone(struct net_device *dev)
1754 {
1755 struct tc35815_local *lp = netdev_priv(dev);
1756 struct TxFD *txfd;
1757 unsigned int fdctl;
1758
1759 txfd = &lp->tfd_base[lp->tfd_end];
1760 while (lp->tfd_start != lp->tfd_end &&
1761 !((fdctl = le32_to_cpu(txfd->fd.FDCtl)) & FD_CownsFD)) {
1762 int status = le32_to_cpu(txfd->fd.FDStat);
1763 struct sk_buff *skb;
1764 unsigned long fdnext = le32_to_cpu(txfd->fd.FDNext);
1765 u32 fdsystem = le32_to_cpu(txfd->fd.FDSystem);
1766
1767 if (netif_msg_tx_done(lp)) {
1768 printk("%s: complete TxFD.\n", dev->name);
1769 dump_txfd(txfd);
1770 }
1771 tc35815_check_tx_stat(dev, status);
1772
1773 skb = fdsystem != 0xffffffff ?
1774 lp->tx_skbs[fdsystem].skb : NULL;
1775 #ifdef DEBUG
1776 if (lp->tx_skbs[lp->tfd_end].skb != skb) {
1777 printk("%s: tx_skbs mismatch.\n", dev->name);
1778 panic_queues(dev);
1779 }
1780 #else
1781 BUG_ON(lp->tx_skbs[lp->tfd_end].skb != skb);
1782 #endif
1783 if (skb) {
1784 dev->stats.tx_bytes += skb->len;
1785 pci_unmap_single(lp->pci_dev, lp->tx_skbs[lp->tfd_end].skb_dma, skb->len, PCI_DMA_TODEVICE);
1786 lp->tx_skbs[lp->tfd_end].skb = NULL;
1787 lp->tx_skbs[lp->tfd_end].skb_dma = 0;
1788 dev_kfree_skb_any(skb);
1789 }
1790 txfd->fd.FDSystem = cpu_to_le32(0xffffffff);
1791
1792 lp->tfd_end = (lp->tfd_end + 1) % TX_FD_NUM;
1793 txfd = &lp->tfd_base[lp->tfd_end];
1794 #ifdef DEBUG
1795 if ((fdnext & ~FD_Next_EOL) != fd_virt_to_bus(lp, txfd)) {
1796 printk("%s: TxFD FDNext invalid.\n", dev->name);
1797 panic_queues(dev);
1798 }
1799 #endif
1800 if (fdnext & FD_Next_EOL) {
1801 /* DMA Transmitter has been stopping... */
1802 if (lp->tfd_end != lp->tfd_start) {
1803 struct tc35815_regs __iomem *tr =
1804 (struct tc35815_regs __iomem *)dev->base_addr;
1805 int head = (lp->tfd_start + TX_FD_NUM - 1) % TX_FD_NUM;
1806 struct TxFD *txhead = &lp->tfd_base[head];
1807 int qlen = (lp->tfd_start + TX_FD_NUM
1808 - lp->tfd_end) % TX_FD_NUM;
1809
1810 #ifdef DEBUG
1811 if (!(le32_to_cpu(txfd->fd.FDCtl) & FD_CownsFD)) {
1812 printk("%s: TxFD FDCtl invalid.\n", dev->name);
1813 panic_queues(dev);
1814 }
1815 #endif
1816 /* log max queue length */
1817 if (lp->lstats.max_tx_qlen < qlen)
1818 lp->lstats.max_tx_qlen = qlen;
1819
1820
1821 /* start DMA Transmitter again */
1822 txhead->fd.FDNext |= cpu_to_le32(FD_Next_EOL);
1823 txhead->fd.FDCtl |= cpu_to_le32(FD_FrmOpt_IntTx);
1824 if (netif_msg_tx_queued(lp)) {
1825 printk("%s: start TxFD on queue.\n",
1826 dev->name);
1827 dump_txfd(txfd);
1828 }
1829 tc_writel(fd_virt_to_bus(lp, txfd), &tr->TxFrmPtr);
1830 }
1831 break;
1832 }
1833 }
1834
1835 /* If we had stopped the queue due to a "tx full"
1836 * condition, and space has now been made available,
1837 * wake up the queue.
1838 */
1839 if (netif_queue_stopped(dev) && !tc35815_tx_full(dev))
1840 netif_wake_queue(dev);
1841 }
1842
1843 /* The inverse routine to tc35815_open(). */
1844 static int
1845 tc35815_close(struct net_device *dev)
1846 {
1847 struct tc35815_local *lp = netdev_priv(dev);
1848
1849 netif_stop_queue(dev);
1850 napi_disable(&lp->napi);
1851 if (lp->phy_dev)
1852 phy_stop(lp->phy_dev);
1853 cancel_work_sync(&lp->restart_work);
1854
1855 /* Flush the Tx and disable Rx here. */
1856 tc35815_chip_reset(dev);
1857 free_irq(dev->irq, dev);
1858
1859 tc35815_free_queues(dev);
1860
1861 return 0;
1862
1863 }
1864
1865 /*
1866 * Get the current statistics.
1867 * This may be called with the card open or closed.
1868 */
1869 static struct net_device_stats *tc35815_get_stats(struct net_device *dev)
1870 {
1871 struct tc35815_regs __iomem *tr =
1872 (struct tc35815_regs __iomem *)dev->base_addr;
1873 if (netif_running(dev))
1874 /* Update the statistics from the device registers. */
1875 dev->stats.rx_missed_errors += tc_readl(&tr->Miss_Cnt);
1876
1877 return &dev->stats;
1878 }
1879
1880 static void tc35815_set_cam_entry(struct net_device *dev, int index, unsigned char *addr)
1881 {
1882 struct tc35815_local *lp = netdev_priv(dev);
1883 struct tc35815_regs __iomem *tr =
1884 (struct tc35815_regs __iomem *)dev->base_addr;
1885 int cam_index = index * 6;
1886 u32 cam_data;
1887 u32 saved_addr;
1888
1889 saved_addr = tc_readl(&tr->CAM_Adr);
1890
1891 if (netif_msg_hw(lp))
1892 printk(KERN_DEBUG "%s: CAM %d: %pM\n",
1893 dev->name, index, addr);
1894 if (index & 1) {
1895 /* read modify write */
1896 tc_writel(cam_index - 2, &tr->CAM_Adr);
1897 cam_data = tc_readl(&tr->CAM_Data) & 0xffff0000;
1898 cam_data |= addr[0] << 8 | addr[1];
1899 tc_writel(cam_data, &tr->CAM_Data);
1900 /* write whole word */
1901 tc_writel(cam_index + 2, &tr->CAM_Adr);
1902 cam_data = (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) | addr[5];
1903 tc_writel(cam_data, &tr->CAM_Data);
1904 } else {
1905 /* write whole word */
1906 tc_writel(cam_index, &tr->CAM_Adr);
1907 cam_data = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
1908 tc_writel(cam_data, &tr->CAM_Data);
1909 /* read modify write */
1910 tc_writel(cam_index + 4, &tr->CAM_Adr);
1911 cam_data = tc_readl(&tr->CAM_Data) & 0x0000ffff;
1912 cam_data |= addr[4] << 24 | (addr[5] << 16);
1913 tc_writel(cam_data, &tr->CAM_Data);
1914 }
1915
1916 tc_writel(saved_addr, &tr->CAM_Adr);
1917 }
1918
1919
1920 /*
1921 * Set or clear the multicast filter for this adaptor.
1922 * num_addrs == -1 Promiscuous mode, receive all packets
1923 * num_addrs == 0 Normal mode, clear multicast list
1924 * num_addrs > 0 Multicast mode, receive normal and MC packets,
1925 * and do best-effort filtering.
1926 */
1927 static void
1928 tc35815_set_multicast_list(struct net_device *dev)
1929 {
1930 struct tc35815_regs __iomem *tr =
1931 (struct tc35815_regs __iomem *)dev->base_addr;
1932
1933 if (dev->flags & IFF_PROMISC) {
1934 /* With some (all?) 100MHalf HUB, controller will hang
1935 * if we enabled promiscuous mode before linkup... */
1936 struct tc35815_local *lp = netdev_priv(dev);
1937
1938 if (!lp->link)
1939 return;
1940 /* Enable promiscuous mode */
1941 tc_writel(CAM_CompEn | CAM_BroadAcc | CAM_GroupAcc | CAM_StationAcc, &tr->CAM_Ctl);
1942 } else if ((dev->flags & IFF_ALLMULTI) ||
1943 netdev_mc_count(dev) > CAM_ENTRY_MAX - 3) {
1944 /* CAM 0, 1, 20 are reserved. */
1945 /* Disable promiscuous mode, use normal mode. */
1946 tc_writel(CAM_CompEn | CAM_BroadAcc | CAM_GroupAcc, &tr->CAM_Ctl);
1947 } else if (!netdev_mc_empty(dev)) {
1948 struct netdev_hw_addr *ha;
1949 int i;
1950 int ena_bits = CAM_Ena_Bit(CAM_ENTRY_SOURCE);
1951
1952 tc_writel(0, &tr->CAM_Ctl);
1953 /* Walk the address list, and load the filter */
1954 i = 0;
1955 netdev_for_each_mc_addr(ha, dev) {
1956 /* entry 0,1 is reserved. */
1957 tc35815_set_cam_entry(dev, i + 2, ha->addr);
1958 ena_bits |= CAM_Ena_Bit(i + 2);
1959 i++;
1960 }
1961 tc_writel(ena_bits, &tr->CAM_Ena);
1962 tc_writel(CAM_CompEn | CAM_BroadAcc, &tr->CAM_Ctl);
1963 } else {
1964 tc_writel(CAM_Ena_Bit(CAM_ENTRY_SOURCE), &tr->CAM_Ena);
1965 tc_writel(CAM_CompEn | CAM_BroadAcc, &tr->CAM_Ctl);
1966 }
1967 }
1968
1969 static void tc35815_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1970 {
1971 struct tc35815_local *lp = netdev_priv(dev);
1972 strcpy(info->driver, MODNAME);
1973 strcpy(info->version, DRV_VERSION);
1974 strcpy(info->bus_info, pci_name(lp->pci_dev));
1975 }
1976
1977 static int tc35815_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1978 {
1979 struct tc35815_local *lp = netdev_priv(dev);
1980
1981 if (!lp->phy_dev)
1982 return -ENODEV;
1983 return phy_ethtool_gset(lp->phy_dev, cmd);
1984 }
1985
1986 static int tc35815_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1987 {
1988 struct tc35815_local *lp = netdev_priv(dev);
1989
1990 if (!lp->phy_dev)
1991 return -ENODEV;
1992 return phy_ethtool_sset(lp->phy_dev, cmd);
1993 }
1994
1995 static u32 tc35815_get_msglevel(struct net_device *dev)
1996 {
1997 struct tc35815_local *lp = netdev_priv(dev);
1998 return lp->msg_enable;
1999 }
2000
2001 static void tc35815_set_msglevel(struct net_device *dev, u32 datum)
2002 {
2003 struct tc35815_local *lp = netdev_priv(dev);
2004 lp->msg_enable = datum;
2005 }
2006
2007 static int tc35815_get_sset_count(struct net_device *dev, int sset)
2008 {
2009 struct tc35815_local *lp = netdev_priv(dev);
2010
2011 switch (sset) {
2012 case ETH_SS_STATS:
2013 return sizeof(lp->lstats) / sizeof(int);
2014 default:
2015 return -EOPNOTSUPP;
2016 }
2017 }
2018
2019 static void tc35815_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *stats, u64 *data)
2020 {
2021 struct tc35815_local *lp = netdev_priv(dev);
2022 data[0] = lp->lstats.max_tx_qlen;
2023 data[1] = lp->lstats.tx_ints;
2024 data[2] = lp->lstats.rx_ints;
2025 data[3] = lp->lstats.tx_underrun;
2026 }
2027
2028 static struct {
2029 const char str[ETH_GSTRING_LEN];
2030 } ethtool_stats_keys[] = {
2031 { "max_tx_qlen" },
2032 { "tx_ints" },
2033 { "rx_ints" },
2034 { "tx_underrun" },
2035 };
2036
2037 static void tc35815_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2038 {
2039 memcpy(data, ethtool_stats_keys, sizeof(ethtool_stats_keys));
2040 }
2041
2042 static const struct ethtool_ops tc35815_ethtool_ops = {
2043 .get_drvinfo = tc35815_get_drvinfo,
2044 .get_settings = tc35815_get_settings,
2045 .set_settings = tc35815_set_settings,
2046 .get_link = ethtool_op_get_link,
2047 .get_msglevel = tc35815_get_msglevel,
2048 .set_msglevel = tc35815_set_msglevel,
2049 .get_strings = tc35815_get_strings,
2050 .get_sset_count = tc35815_get_sset_count,
2051 .get_ethtool_stats = tc35815_get_ethtool_stats,
2052 };
2053
2054 static int tc35815_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2055 {
2056 struct tc35815_local *lp = netdev_priv(dev);
2057
2058 if (!netif_running(dev))
2059 return -EINVAL;
2060 if (!lp->phy_dev)
2061 return -ENODEV;
2062 return phy_mii_ioctl(lp->phy_dev, rq, cmd);
2063 }
2064
2065 static void tc35815_chip_reset(struct net_device *dev)
2066 {
2067 struct tc35815_regs __iomem *tr =
2068 (struct tc35815_regs __iomem *)dev->base_addr;
2069 int i;
2070 /* reset the controller */
2071 tc_writel(MAC_Reset, &tr->MAC_Ctl);
2072 udelay(4); /* 3200ns */
2073 i = 0;
2074 while (tc_readl(&tr->MAC_Ctl) & MAC_Reset) {
2075 if (i++ > 100) {
2076 printk(KERN_ERR "%s: MAC reset failed.\n", dev->name);
2077 break;
2078 }
2079 mdelay(1);
2080 }
2081 tc_writel(0, &tr->MAC_Ctl);
2082
2083 /* initialize registers to default value */
2084 tc_writel(0, &tr->DMA_Ctl);
2085 tc_writel(0, &tr->TxThrsh);
2086 tc_writel(0, &tr->TxPollCtr);
2087 tc_writel(0, &tr->RxFragSize);
2088 tc_writel(0, &tr->Int_En);
2089 tc_writel(0, &tr->FDA_Bas);
2090 tc_writel(0, &tr->FDA_Lim);
2091 tc_writel(0xffffffff, &tr->Int_Src); /* Write 1 to clear */
2092 tc_writel(0, &tr->CAM_Ctl);
2093 tc_writel(0, &tr->Tx_Ctl);
2094 tc_writel(0, &tr->Rx_Ctl);
2095 tc_writel(0, &tr->CAM_Ena);
2096 (void)tc_readl(&tr->Miss_Cnt); /* Read to clear */
2097
2098 /* initialize internal SRAM */
2099 tc_writel(DMA_TestMode, &tr->DMA_Ctl);
2100 for (i = 0; i < 0x1000; i += 4) {
2101 tc_writel(i, &tr->CAM_Adr);
2102 tc_writel(0, &tr->CAM_Data);
2103 }
2104 tc_writel(0, &tr->DMA_Ctl);
2105 }
2106
2107 static void tc35815_chip_init(struct net_device *dev)
2108 {
2109 struct tc35815_local *lp = netdev_priv(dev);
2110 struct tc35815_regs __iomem *tr =
2111 (struct tc35815_regs __iomem *)dev->base_addr;
2112 unsigned long txctl = TX_CTL_CMD;
2113
2114 /* load station address to CAM */
2115 tc35815_set_cam_entry(dev, CAM_ENTRY_SOURCE, dev->dev_addr);
2116
2117 /* Enable CAM (broadcast and unicast) */
2118 tc_writel(CAM_Ena_Bit(CAM_ENTRY_SOURCE), &tr->CAM_Ena);
2119 tc_writel(CAM_CompEn | CAM_BroadAcc, &tr->CAM_Ctl);
2120
2121 /* Use DMA_RxAlign_2 to make IP header 4-byte aligned. */
2122 if (HAVE_DMA_RXALIGN(lp))
2123 tc_writel(DMA_BURST_SIZE | DMA_RxAlign_2, &tr->DMA_Ctl);
2124 else
2125 tc_writel(DMA_BURST_SIZE, &tr->DMA_Ctl);
2126 tc_writel(0, &tr->TxPollCtr); /* Batch mode */
2127 tc_writel(TX_THRESHOLD, &tr->TxThrsh);
2128 tc_writel(INT_EN_CMD, &tr->Int_En);
2129
2130 /* set queues */
2131 tc_writel(fd_virt_to_bus(lp, lp->rfd_base), &tr->FDA_Bas);
2132 tc_writel((unsigned long)lp->rfd_limit - (unsigned long)lp->rfd_base,
2133 &tr->FDA_Lim);
2134 /*
2135 * Activation method:
2136 * First, enable the MAC Transmitter and the DMA Receive circuits.
2137 * Then enable the DMA Transmitter and the MAC Receive circuits.
2138 */
2139 tc_writel(fd_virt_to_bus(lp, lp->fbl_ptr), &tr->BLFrmPtr); /* start DMA receiver */
2140 tc_writel(RX_CTL_CMD, &tr->Rx_Ctl); /* start MAC receiver */
2141
2142 /* start MAC transmitter */
2143 /* TX4939 does not have EnLCarr */
2144 if (lp->chiptype == TC35815_TX4939)
2145 txctl &= ~Tx_EnLCarr;
2146 if (!lp->phy_dev || !lp->link || lp->duplex == DUPLEX_FULL)
2147 txctl &= ~Tx_EnLCarr;
2148 tc_writel(txctl, &tr->Tx_Ctl);
2149 }
2150
2151 #ifdef CONFIG_PM
2152 static int tc35815_suspend(struct pci_dev *pdev, pm_message_t state)
2153 {
2154 struct net_device *dev = pci_get_drvdata(pdev);
2155 struct tc35815_local *lp = netdev_priv(dev);
2156 unsigned long flags;
2157
2158 pci_save_state(pdev);
2159 if (!netif_running(dev))
2160 return 0;
2161 netif_device_detach(dev);
2162 if (lp->phy_dev)
2163 phy_stop(lp->phy_dev);
2164 spin_lock_irqsave(&lp->lock, flags);
2165 tc35815_chip_reset(dev);
2166 spin_unlock_irqrestore(&lp->lock, flags);
2167 pci_set_power_state(pdev, PCI_D3hot);
2168 return 0;
2169 }
2170
2171 static int tc35815_resume(struct pci_dev *pdev)
2172 {
2173 struct net_device *dev = pci_get_drvdata(pdev);
2174 struct tc35815_local *lp = netdev_priv(dev);
2175
2176 pci_restore_state(pdev);
2177 if (!netif_running(dev))
2178 return 0;
2179 pci_set_power_state(pdev, PCI_D0);
2180 tc35815_restart(dev);
2181 netif_carrier_off(dev);
2182 if (lp->phy_dev)
2183 phy_start(lp->phy_dev);
2184 netif_device_attach(dev);
2185 return 0;
2186 }
2187 #endif /* CONFIG_PM */
2188
2189 static struct pci_driver tc35815_pci_driver = {
2190 .name = MODNAME,
2191 .id_table = tc35815_pci_tbl,
2192 .probe = tc35815_init_one,
2193 .remove = __devexit_p(tc35815_remove_one),
2194 #ifdef CONFIG_PM
2195 .suspend = tc35815_suspend,
2196 .resume = tc35815_resume,
2197 #endif
2198 };
2199
2200 module_param_named(speed, options.speed, int, 0);
2201 MODULE_PARM_DESC(speed, "0:auto, 10:10Mbps, 100:100Mbps");
2202 module_param_named(duplex, options.duplex, int, 0);
2203 MODULE_PARM_DESC(duplex, "0:auto, 1:half, 2:full");
2204
2205 static int __init tc35815_init_module(void)
2206 {
2207 return pci_register_driver(&tc35815_pci_driver);
2208 }
2209
2210 static void __exit tc35815_cleanup_module(void)
2211 {
2212 pci_unregister_driver(&tc35815_pci_driver);
2213 }
2214
2215 module_init(tc35815_init_module);
2216 module_exit(tc35815_cleanup_module);
2217
2218 MODULE_DESCRIPTION("TOSHIBA TC35815 PCI 10M/100M Ethernet driver");
2219 MODULE_LICENSE("GPL");
Tomato firmware and modifications.