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GUI: Fix Tomato RAF theme for all builds. Compilation typo.
[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / drivers / net / sun3lance.c
blob468260745e2aa1538f697bd9dc72141ea85873d0
1 /* sun3lance.c: Ethernet driver for SUN3 Lance chip */
2 /*
3
4 Sun3 Lance ethernet driver, by Sam Creasey (sammy@users.qual.net).
5 This driver is a part of the linux kernel, and is thus distributed
6 under the GNU General Public License.
7
8 The values used in LANCE_OBIO and LANCE_IRQ seem to be empirically
9 true for the correct IRQ and address of the lance registers. They
10 have not been widely tested, however. What we probably need is a
11 "proper" way to search for a device in the sun3's prom, but, alas,
12 linux has no such thing.
13
14 This driver is largely based on atarilance.c, by Roman Hodek. Other
15 sources of inspiration were the NetBSD sun3 am7990 driver, and the
16 linux sparc lance driver (sunlance.c).
17
18 There are more assumptions made throughout this driver, it almost
19 certainly still needs work, but it does work at least for RARP/BOOTP and
20 mounting the root NFS filesystem.
21
22 */
23
24 static char *version = "sun3lance.c: v1.2 1/12/2001 Sam Creasey (sammy@sammy.net)\n";
25
26 #include <linux/module.h>
27 #include <linux/stddef.h>
28 #include <linux/kernel.h>
29 #include <linux/string.h>
30 #include <linux/errno.h>
31 #include <linux/interrupt.h>
32 #include <linux/init.h>
33 #include <linux/ioport.h>
34 #include <linux/delay.h>
35 #include <linux/netdevice.h>
36 #include <linux/etherdevice.h>
37 #include <linux/skbuff.h>
38 #include <linux/bitops.h>
39
40 #include <asm/cacheflush.h>
41 #include <asm/setup.h>
42 #include <asm/irq.h>
43 #include <asm/io.h>
44 #include <asm/pgtable.h>
45 #include <asm/dvma.h>
46 #include <asm/idprom.h>
47 #include <asm/machines.h>
48
49 #ifdef CONFIG_SUN3
50 #include <asm/sun3mmu.h>
51 #else
52 #include <asm/sun3xprom.h>
53 #endif
54
55 /* sun3/60 addr/irq for the lance chip. If your sun is different,
56 change this. */
57 #define LANCE_OBIO 0x120000
58 #define LANCE_IRQ IRQ_AUTO_3
59
60 /* Debug level:
61 * 0 = silent, print only serious errors
62 * 1 = normal, print error messages
63 * 2 = debug, print debug infos
64 * 3 = debug, print even more debug infos (packet data)
65 */
66
67 #define LANCE_DEBUG 0
68
69 #ifdef LANCE_DEBUG
70 static int lance_debug = LANCE_DEBUG;
71 #else
72 static int lance_debug = 1;
73 #endif
74 module_param(lance_debug, int, 0);
75 MODULE_PARM_DESC(lance_debug, "SUN3 Lance debug level (0-3)");
76 MODULE_LICENSE("GPL");
77
78 #define DPRINTK(n,a) \
79 do { \
80 if (lance_debug >= n) \
81 printk a; \
82 } while( 0 )
83
84
85 /* we're only using 32k of memory, so we use 4 TX
86 buffers and 16 RX buffers. These values are expressed as log2. */
87
88 #define TX_LOG_RING_SIZE 3
89 #define RX_LOG_RING_SIZE 5
90
91 /* These are the derived values */
92
93 #define TX_RING_SIZE (1 << TX_LOG_RING_SIZE)
94 #define TX_RING_LEN_BITS (TX_LOG_RING_SIZE << 5)
95 #define TX_RING_MOD_MASK (TX_RING_SIZE - 1)
96
97 #define RX_RING_SIZE (1 << RX_LOG_RING_SIZE)
98 #define RX_RING_LEN_BITS (RX_LOG_RING_SIZE << 5)
99 #define RX_RING_MOD_MASK (RX_RING_SIZE - 1)
100
101 /* Definitions for packet buffer access: */
102 #define PKT_BUF_SZ 1544
103
104 /* Get the address of a packet buffer corresponding to a given buffer head */
105 #define PKTBUF_ADDR(head) (void *)((unsigned long)(MEM) | (head)->base)
106
107
108 /* The LANCE Rx and Tx ring descriptors. */
109 struct lance_rx_head {
110 unsigned short base; /* Low word of base addr */
111 volatile unsigned char flag;
112 unsigned char base_hi; /* High word of base addr (unused) */
113 short buf_length; /* This length is 2s complement! */
114 volatile short msg_length; /* This length is "normal". */
115 };
116
117 struct lance_tx_head {
118 unsigned short base; /* Low word of base addr */
119 volatile unsigned char flag;
120 unsigned char base_hi; /* High word of base addr (unused) */
121 short length; /* Length is 2s complement! */
122 volatile short misc;
123 };
124
125 /* The LANCE initialization block, described in databook. */
126 struct lance_init_block {
127 unsigned short mode; /* Pre-set mode */
128 unsigned char hwaddr[6]; /* Physical ethernet address */
129 unsigned int filter[2]; /* Multicast filter (unused). */
130 /* Receive and transmit ring base, along with length bits. */
131 unsigned short rdra;
132 unsigned short rlen;
133 unsigned short tdra;
134 unsigned short tlen;
135 unsigned short pad[4]; /* is thie needed? */
136 };
137
138 /* The whole layout of the Lance shared memory */
139 struct lance_memory {
140 struct lance_init_block init;
141 struct lance_tx_head tx_head[TX_RING_SIZE];
142 struct lance_rx_head rx_head[RX_RING_SIZE];
143 char rx_data[RX_RING_SIZE][PKT_BUF_SZ];
144 char tx_data[TX_RING_SIZE][PKT_BUF_SZ];
145 };
146
147 /* The driver's private device structure */
148
149 struct lance_private {
150 volatile unsigned short *iobase;
151 struct lance_memory *mem;
152 int new_rx, new_tx; /* The next free ring entry */
153 int old_tx, old_rx; /* ring entry to be processed */
154 /* These two must be longs for set_bit() */
155 long tx_full;
156 long lock;
157 };
158
159 /* I/O register access macros */
160
161 #define MEM lp->mem
162 #define DREG lp->iobase[0]
163 #define AREG lp->iobase[1]
164 #define REGA(a) (*( AREG = (a), &DREG ))
165
166 /* Definitions for the Lance */
167
168 /* tx_head flags */
169 #define TMD1_ENP 0x01 /* end of packet */
170 #define TMD1_STP 0x02 /* start of packet */
171 #define TMD1_DEF 0x04 /* deferred */
172 #define TMD1_ONE 0x08 /* one retry needed */
173 #define TMD1_MORE 0x10 /* more than one retry needed */
174 #define TMD1_ERR 0x40 /* error summary */
175 #define TMD1_OWN 0x80 /* ownership (set: chip owns) */
176
177 #define TMD1_OWN_CHIP TMD1_OWN
178 #define TMD1_OWN_HOST 0
179
180 /* tx_head misc field */
181 #define TMD3_TDR 0x03FF /* Time Domain Reflectometry counter */
182 #define TMD3_RTRY 0x0400 /* failed after 16 retries */
183 #define TMD3_LCAR 0x0800 /* carrier lost */
184 #define TMD3_LCOL 0x1000 /* late collision */
185 #define TMD3_UFLO 0x4000 /* underflow (late memory) */
186 #define TMD3_BUFF 0x8000 /* buffering error (no ENP) */
187
188 /* rx_head flags */
189 #define RMD1_ENP 0x01 /* end of packet */
190 #define RMD1_STP 0x02 /* start of packet */
191 #define RMD1_BUFF 0x04 /* buffer error */
192 #define RMD1_CRC 0x08 /* CRC error */
193 #define RMD1_OFLO 0x10 /* overflow */
194 #define RMD1_FRAM 0x20 /* framing error */
195 #define RMD1_ERR 0x40 /* error summary */
196 #define RMD1_OWN 0x80 /* ownership (set: ship owns) */
197
198 #define RMD1_OWN_CHIP RMD1_OWN
199 #define RMD1_OWN_HOST 0
200
201 /* register names */
202 #define CSR0 0 /* mode/status */
203 #define CSR1 1 /* init block addr (low) */
204 #define CSR2 2 /* init block addr (high) */
205 #define CSR3 3 /* misc */
206 #define CSR8 8 /* address filter */
207 #define CSR15 15 /* promiscuous mode */
208
209 /* CSR0 */
210 /* (R=readable, W=writeable, S=set on write, C=clear on write) */
211 #define CSR0_INIT 0x0001 /* initialize (RS) */
212 #define CSR0_STRT 0x0002 /* start (RS) */
213 #define CSR0_STOP 0x0004 /* stop (RS) */
214 #define CSR0_TDMD 0x0008 /* transmit demand (RS) */
215 #define CSR0_TXON 0x0010 /* transmitter on (R) */
216 #define CSR0_RXON 0x0020 /* receiver on (R) */
217 #define CSR0_INEA 0x0040 /* interrupt enable (RW) */
218 #define CSR0_INTR 0x0080 /* interrupt active (R) */
219 #define CSR0_IDON 0x0100 /* initialization done (RC) */
220 #define CSR0_TINT 0x0200 /* transmitter interrupt (RC) */
221 #define CSR0_RINT 0x0400 /* receiver interrupt (RC) */
222 #define CSR0_MERR 0x0800 /* memory error (RC) */
223 #define CSR0_MISS 0x1000 /* missed frame (RC) */
224 #define CSR0_CERR 0x2000 /* carrier error (no heartbeat :-) (RC) */
225 #define CSR0_BABL 0x4000 /* babble: tx-ed too many bits (RC) */
226 #define CSR0_ERR 0x8000 /* error (RC) */
227
228 /* CSR3 */
229 #define CSR3_BCON 0x0001 /* byte control */
230 #define CSR3_ACON 0x0002 /* ALE control */
231 #define CSR3_BSWP 0x0004 /* byte swap (1=big endian) */
232
233 /***************************** Prototypes *****************************/
234
235 static int lance_probe( struct net_device *dev);
236 static int lance_open( struct net_device *dev );
237 static void lance_init_ring( struct net_device *dev );
238 static int lance_start_xmit( struct sk_buff *skb, struct net_device *dev );
239 static irqreturn_t lance_interrupt( int irq, void *dev_id);
240 static int lance_rx( struct net_device *dev );
241 static int lance_close( struct net_device *dev );
242 static void set_multicast_list( struct net_device *dev );
243
244 /************************* End of Prototypes **************************/
245
246 struct net_device * __init sun3lance_probe(int unit)
247 {
248 struct net_device *dev;
249 static int found;
250 int err = -ENODEV;
251
252 if (!MACH_IS_SUN3 && !MACH_IS_SUN3X)
253 return ERR_PTR(-ENODEV);
254
255 /* check that this machine has an onboard lance */
256 switch(idprom->id_machtype) {
257 case SM_SUN3|SM_3_50:
258 case SM_SUN3|SM_3_60:
259 case SM_SUN3X|SM_3_80:
260 /* these machines have lance */
261 break;
262
263 default:
264 return ERR_PTR(-ENODEV);
265 }
266
267 if (found)
268 return ERR_PTR(-ENODEV);
269
270 dev = alloc_etherdev(sizeof(struct lance_private));
271 if (!dev)
272 return ERR_PTR(-ENOMEM);
273 if (unit >= 0) {
274 sprintf(dev->name, "eth%d", unit);
275 netdev_boot_setup_check(dev);
276 }
277
278 if (!lance_probe(dev))
279 goto out;
280
281 err = register_netdev(dev);
282 if (err)
283 goto out1;
284 found = 1;
285 return dev;
286
287 out1:
288 #ifdef CONFIG_SUN3
289 iounmap((void __iomem *)dev->base_addr);
290 #endif
291 out:
292 free_netdev(dev);
293 return ERR_PTR(err);
294 }
295
296 static const struct net_device_ops lance_netdev_ops = {
297 .ndo_open = lance_open,
298 .ndo_stop = lance_close,
299 .ndo_start_xmit = lance_start_xmit,
300 .ndo_set_multicast_list = set_multicast_list,
301 .ndo_set_mac_address = NULL,
302 .ndo_change_mtu = eth_change_mtu,
303 .ndo_validate_addr = eth_validate_addr,
304 };
305
306 static int __init lance_probe( struct net_device *dev)
307 {
308 unsigned long ioaddr;
309
310 struct lance_private *lp;
311 int i;
312 static int did_version;
313 volatile unsigned short *ioaddr_probe;
314 unsigned short tmp1, tmp2;
315
316 #ifdef CONFIG_SUN3
317 ioaddr = (unsigned long)ioremap(LANCE_OBIO, PAGE_SIZE);
318 if (!ioaddr)
319 return 0;
320 #else
321 ioaddr = SUN3X_LANCE;
322 #endif
323
324 /* test to see if there's really a lance here */
325 /* (CSRO_INIT shouldn't be readable) */
326
327 ioaddr_probe = (volatile unsigned short *)ioaddr;
328 tmp1 = ioaddr_probe[0];
329 tmp2 = ioaddr_probe[1];
330
331 ioaddr_probe[1] = CSR0;
332 ioaddr_probe[0] = CSR0_INIT | CSR0_STOP;
333
334 if(ioaddr_probe[0] != CSR0_STOP) {
335 ioaddr_probe[0] = tmp1;
336 ioaddr_probe[1] = tmp2;
337
338 #ifdef CONFIG_SUN3
339 iounmap((void __iomem *)ioaddr);
340 #endif
341 return 0;
342 }
343
344 lp = netdev_priv(dev);
345
346 MEM = dvma_malloc_align(sizeof(struct lance_memory), 0x10000);
347 if (MEM == NULL) {
348 #ifdef CONFIG_SUN3
349 iounmap((void __iomem *)ioaddr);
350 #endif
351 printk(KERN_WARNING "SUN3 Lance couldn't allocate DVMA memory\n");
352 return 0;
353 }
354
355 lp->iobase = (volatile unsigned short *)ioaddr;
356 dev->base_addr = (unsigned long)ioaddr; /* informational only */
357
358 REGA(CSR0) = CSR0_STOP;
359
360 if (request_irq(LANCE_IRQ, lance_interrupt, IRQF_DISABLED, "SUN3 Lance", dev) < 0) {
361 #ifdef CONFIG_SUN3
362 iounmap((void __iomem *)ioaddr);
363 #endif
364 dvma_free((void *)MEM);
365 printk(KERN_WARNING "SUN3 Lance unable to allocate IRQ\n");
366 return 0;
367 }
368 dev->irq = (unsigned short)LANCE_IRQ;
369
370
371 printk("%s: SUN3 Lance at io %#lx, mem %#lx, irq %d, hwaddr ",
372 dev->name,
373 (unsigned long)ioaddr,
374 (unsigned long)MEM,
375 dev->irq);
376
377 /* copy in the ethernet address from the prom */
378 for(i = 0; i < 6 ; i++)
379 dev->dev_addr[i] = idprom->id_ethaddr[i];
380
381 /* tell the card it's ether address, bytes swapped */
382 MEM->init.hwaddr[0] = dev->dev_addr[1];
383 MEM->init.hwaddr[1] = dev->dev_addr[0];
384 MEM->init.hwaddr[2] = dev->dev_addr[3];
385 MEM->init.hwaddr[3] = dev->dev_addr[2];
386 MEM->init.hwaddr[4] = dev->dev_addr[5];
387 MEM->init.hwaddr[5] = dev->dev_addr[4];
388
389 printk("%pM\n", dev->dev_addr);
390
391 MEM->init.mode = 0x0000;
392 MEM->init.filter[0] = 0x00000000;
393 MEM->init.filter[1] = 0x00000000;
394 MEM->init.rdra = dvma_vtob(MEM->rx_head);
395 MEM->init.rlen = (RX_LOG_RING_SIZE << 13) |
396 (dvma_vtob(MEM->rx_head) >> 16);
397 MEM->init.tdra = dvma_vtob(MEM->tx_head);
398 MEM->init.tlen = (TX_LOG_RING_SIZE << 13) |
399 (dvma_vtob(MEM->tx_head) >> 16);
400
401 DPRINTK(2, ("initaddr: %08lx rx_ring: %08lx tx_ring: %08lx\n",
402 dvma_vtob(&(MEM->init)), dvma_vtob(MEM->rx_head),
403 (dvma_vtob(MEM->tx_head))));
404
405 if (did_version++ == 0)
406 printk( version );
407
408 dev->netdev_ops = &lance_netdev_ops;
409 // KLUDGE -- REMOVE ME
410 set_bit(__LINK_STATE_PRESENT, &dev->state);
411
412
413 return 1;
414 }
415
416 static int lance_open( struct net_device *dev )
417 {
418 struct lance_private *lp = netdev_priv(dev);
419 int i;
420
421 DPRINTK( 2, ( "%s: lance_open()\n", dev->name ));
422
423 REGA(CSR0) = CSR0_STOP;
424
425 lance_init_ring(dev);
426
427 /* From now on, AREG is kept to point to CSR0 */
428 REGA(CSR0) = CSR0_INIT;
429
430 i = 1000000;
431 while (--i > 0)
432 if (DREG & CSR0_IDON)
433 break;
434 if (i <= 0 || (DREG & CSR0_ERR)) {
435 DPRINTK( 2, ( "lance_open(): opening %s failed, i=%d, csr0=%04x\n",
436 dev->name, i, DREG ));
437 DREG = CSR0_STOP;
438 return( -EIO );
439 }
440
441 DREG = CSR0_IDON | CSR0_STRT | CSR0_INEA;
442
443 netif_start_queue(dev);
444
445 DPRINTK( 2, ( "%s: LANCE is open, csr0 %04x\n", dev->name, DREG ));
446
447 return( 0 );
448 }
449
450
451 /* Initialize the LANCE Rx and Tx rings. */
452
453 static void lance_init_ring( struct net_device *dev )
454 {
455 struct lance_private *lp = netdev_priv(dev);
456 int i;
457
458 lp->lock = 0;
459 lp->tx_full = 0;
460 lp->new_rx = lp->new_tx = 0;
461 lp->old_rx = lp->old_tx = 0;
462
463 for( i = 0; i < TX_RING_SIZE; i++ ) {
464 MEM->tx_head[i].base = dvma_vtob(MEM->tx_data[i]);
465 MEM->tx_head[i].flag = 0;
466 MEM->tx_head[i].base_hi =
467 (dvma_vtob(MEM->tx_data[i])) >>16;
468 MEM->tx_head[i].length = 0;
469 MEM->tx_head[i].misc = 0;
470 }
471
472 for( i = 0; i < RX_RING_SIZE; i++ ) {
473 MEM->rx_head[i].base = dvma_vtob(MEM->rx_data[i]);
474 MEM->rx_head[i].flag = RMD1_OWN_CHIP;
475 MEM->rx_head[i].base_hi =
476 (dvma_vtob(MEM->rx_data[i])) >> 16;
477 MEM->rx_head[i].buf_length = -PKT_BUF_SZ | 0xf000;
478 MEM->rx_head[i].msg_length = 0;
479 }
480
481 /* tell the card it's ether address, bytes swapped */
482 MEM->init.hwaddr[0] = dev->dev_addr[1];
483 MEM->init.hwaddr[1] = dev->dev_addr[0];
484 MEM->init.hwaddr[2] = dev->dev_addr[3];
485 MEM->init.hwaddr[3] = dev->dev_addr[2];
486 MEM->init.hwaddr[4] = dev->dev_addr[5];
487 MEM->init.hwaddr[5] = dev->dev_addr[4];
488
489 MEM->init.mode = 0x0000;
490 MEM->init.filter[0] = 0x00000000;
491 MEM->init.filter[1] = 0x00000000;
492 MEM->init.rdra = dvma_vtob(MEM->rx_head);
493 MEM->init.rlen = (RX_LOG_RING_SIZE << 13) |
494 (dvma_vtob(MEM->rx_head) >> 16);
495 MEM->init.tdra = dvma_vtob(MEM->tx_head);
496 MEM->init.tlen = (TX_LOG_RING_SIZE << 13) |
497 (dvma_vtob(MEM->tx_head) >> 16);
498
499
500 /* tell the lance the address of its init block */
501 REGA(CSR1) = dvma_vtob(&(MEM->init));
502 REGA(CSR2) = dvma_vtob(&(MEM->init)) >> 16;
503
504 #ifdef CONFIG_SUN3X
505 REGA(CSR3) = CSR3_BSWP | CSR3_ACON | CSR3_BCON;
506 #else
507 REGA(CSR3) = CSR3_BSWP;
508 #endif
509
510 }
511
512
513 static int lance_start_xmit( struct sk_buff *skb, struct net_device *dev )
514 {
515 struct lance_private *lp = netdev_priv(dev);
516 int entry, len;
517 struct lance_tx_head *head;
518 unsigned long flags;
519
520 DPRINTK( 1, ( "%s: transmit start.\n",
521 dev->name));
522
523 /* Transmitter timeout, serious problems. */
524 if (netif_queue_stopped(dev)) {
525 int tickssofar = jiffies - dev_trans_start(dev);
526 if (tickssofar < HZ/5)
527 return NETDEV_TX_BUSY;
528
529 DPRINTK( 1, ( "%s: transmit timed out, status %04x, resetting.\n",
530 dev->name, DREG ));
531 DREG = CSR0_STOP;
532 /*
533 * Always set BSWP after a STOP as STOP puts it back into
534 * little endian mode.
535 */
536 REGA(CSR3) = CSR3_BSWP;
537 dev->stats.tx_errors++;
538
539 if(lance_debug >= 2) {
540 int i;
541 printk("Ring data: old_tx %d new_tx %d%s new_rx %d\n",
542 lp->old_tx, lp->new_tx,
543 lp->tx_full ? " (full)" : "",
544 lp->new_rx );
545 for( i = 0 ; i < RX_RING_SIZE; i++ )
546 printk( "rx #%d: base=%04x blen=%04x mlen=%04x\n",
547 i, MEM->rx_head[i].base,
548 -MEM->rx_head[i].buf_length,
549 MEM->rx_head[i].msg_length);
550 for( i = 0 ; i < TX_RING_SIZE; i++ )
551 printk("tx #%d: base=%04x len=%04x misc=%04x\n",
552 i, MEM->tx_head[i].base,
553 -MEM->tx_head[i].length,
554 MEM->tx_head[i].misc );
555 }
556
557 lance_init_ring(dev);
558 REGA( CSR0 ) = CSR0_INEA | CSR0_INIT | CSR0_STRT;
559
560 netif_start_queue(dev);
561
562 return NETDEV_TX_OK;
563 }
564
565
566 /* Block a timer-based transmit from overlapping. This could better be
567 done with atomic_swap(1, dev->tbusy), but set_bit() works as well. */
568
569 /* Block a timer-based transmit from overlapping with us by
570 stopping the queue for a bit... */
571
572 netif_stop_queue(dev);
573
574 if (test_and_set_bit( 0, (void*)&lp->lock ) != 0) {
575 printk( "%s: tx queue lock!.\n", dev->name);
576 /* don't clear dev->tbusy flag. */
577 return NETDEV_TX_BUSY;
578 }
579
580 AREG = CSR0;
581 DPRINTK( 2, ( "%s: lance_start_xmit() called, csr0 %4.4x.\n",
582 dev->name, DREG ));
583
584 #ifdef CONFIG_SUN3X
585 /* this weirdness doesn't appear on sun3... */
586 if(!(DREG & CSR0_INIT)) {
587 DPRINTK( 1, ("INIT not set, reinitializing...\n"));
588 REGA( CSR0 ) = CSR0_STOP;
589 lance_init_ring(dev);
590 REGA( CSR0 ) = CSR0_INIT | CSR0_STRT;
591 }
592 #endif
593
594 /* Fill in a Tx ring entry */
595 /* We're not prepared for the int until the last flags are set/reset.
596 * And the int may happen already after setting the OWN_CHIP... */
597 local_irq_save(flags);
598
599 /* Mask to ring buffer boundary. */
600 entry = lp->new_tx;
601 head = &(MEM->tx_head[entry]);
602
603 /* Caution: the write order is important here, set the "ownership" bits
604 * last.
605 */
606
607 /* the sun3's lance needs it's buffer padded to the minimum
608 size */
609 len = (ETH_ZLEN < skb->len) ? skb->len : ETH_ZLEN;
610
611 // head->length = -len;
612 head->length = (-len) | 0xf000;
613 head->misc = 0;
614
615 skb_copy_from_linear_data(skb, PKTBUF_ADDR(head), skb->len);
616 if (len != skb->len)
617 memset(PKTBUF_ADDR(head) + skb->len, 0, len-skb->len);
618
619 head->flag = TMD1_OWN_CHIP | TMD1_ENP | TMD1_STP;
620 lp->new_tx = (lp->new_tx + 1) & TX_RING_MOD_MASK;
621 dev->stats.tx_bytes += skb->len;
622
623 /* Trigger an immediate send poll. */
624 REGA(CSR0) = CSR0_INEA | CSR0_TDMD | CSR0_STRT;
625 AREG = CSR0;
626 DPRINTK( 2, ( "%s: lance_start_xmit() exiting, csr0 %4.4x.\n",
627 dev->name, DREG ));
628 dev_kfree_skb(skb);
629
630 lp->lock = 0;
631 if ((MEM->tx_head[(entry+1) & TX_RING_MOD_MASK].flag & TMD1_OWN) ==
632 TMD1_OWN_HOST)
633 netif_start_queue(dev);
634
635 local_irq_restore(flags);
636
637 return NETDEV_TX_OK;
638 }
639
640 /* The LANCE interrupt handler. */
641
642 static irqreturn_t lance_interrupt( int irq, void *dev_id)
643 {
644 struct net_device *dev = dev_id;
645 struct lance_private *lp = netdev_priv(dev);
646 int csr0;
647 static int in_interrupt;
648
649 if (dev == NULL) {
650 DPRINTK( 1, ( "lance_interrupt(): invalid dev_id\n" ));
651 return IRQ_NONE;
652 }
653
654 if (in_interrupt)
655 DPRINTK( 2, ( "%s: Re-entering the interrupt handler.\n", dev->name ));
656 in_interrupt = 1;
657
658 still_more:
659 flush_cache_all();
660
661 AREG = CSR0;
662 csr0 = DREG;
663
664 /* ack interrupts */
665 DREG = csr0 & (CSR0_TINT | CSR0_RINT | CSR0_IDON);
666
667 /* clear errors */
668 if(csr0 & CSR0_ERR)
669 DREG = CSR0_BABL | CSR0_MERR | CSR0_CERR | CSR0_MISS;
670
671
672 DPRINTK( 2, ( "%s: interrupt csr0=%04x new csr=%04x.\n",
673 dev->name, csr0, DREG ));
674
675 if (csr0 & CSR0_TINT) { /* Tx-done interrupt */
676 int old_tx = lp->old_tx;
677
678 // if(lance_debug >= 3) {
679 // int i;
680 //
681 // printk("%s: tx int\n", dev->name);
682 //
683 // for(i = 0; i < TX_RING_SIZE; i++)
684 // printk("ring %d flag=%04x\n", i,
685 // MEM->tx_head[i].flag);
686 // }
687
688 while( old_tx != lp->new_tx) {
689 struct lance_tx_head *head = &(MEM->tx_head[old_tx]);
690
691 DPRINTK(3, ("on tx_ring %d\n", old_tx));
692
693 if (head->flag & TMD1_OWN_CHIP)
694 break; /* It still hasn't been Txed */
695
696 if (head->flag & TMD1_ERR) {
697 int status = head->misc;
698 dev->stats.tx_errors++;
699 if (status & TMD3_RTRY) dev->stats.tx_aborted_errors++;
700 if (status & TMD3_LCAR) dev->stats.tx_carrier_errors++;
701 if (status & TMD3_LCOL) dev->stats.tx_window_errors++;
702 if (status & (TMD3_UFLO | TMD3_BUFF)) {
703 dev->stats.tx_fifo_errors++;
704 printk("%s: Tx FIFO error\n",
705 dev->name);
706 REGA(CSR0) = CSR0_STOP;
707 REGA(CSR3) = CSR3_BSWP;
708 lance_init_ring(dev);
709 REGA(CSR0) = CSR0_STRT | CSR0_INEA;
710 return IRQ_HANDLED;
711 }
712 } else if(head->flag & (TMD1_ENP | TMD1_STP)) {
713
714 head->flag &= ~(TMD1_ENP | TMD1_STP);
715 if(head->flag & (TMD1_ONE | TMD1_MORE))
716 dev->stats.collisions++;
717
718 dev->stats.tx_packets++;
719 DPRINTK(3, ("cleared tx ring %d\n", old_tx));
720 }
721 old_tx = (old_tx +1) & TX_RING_MOD_MASK;
722 }
723
724 lp->old_tx = old_tx;
725 }
726
727
728 if (netif_queue_stopped(dev)) {
729 /* The ring is no longer full, clear tbusy. */
730 netif_start_queue(dev);
731 netif_wake_queue(dev);
732 }
733
734 if (csr0 & CSR0_RINT) /* Rx interrupt */
735 lance_rx( dev );
736
737 /* Log misc errors. */
738 if (csr0 & CSR0_BABL) dev->stats.tx_errors++; /* Tx babble. */
739 if (csr0 & CSR0_MISS) dev->stats.rx_errors++; /* Missed a Rx frame. */
740 if (csr0 & CSR0_MERR) {
741 DPRINTK( 1, ( "%s: Bus master arbitration failure (?!?), "
742 "status %04x.\n", dev->name, csr0 ));
743 /* Restart the chip. */
744 REGA(CSR0) = CSR0_STOP;
745 REGA(CSR3) = CSR3_BSWP;
746 lance_init_ring(dev);
747 REGA(CSR0) = CSR0_STRT | CSR0_INEA;
748 }
749
750
751 /* Clear any other interrupt, and set interrupt enable. */
752 // DREG = CSR0_BABL | CSR0_CERR | CSR0_MISS | CSR0_MERR |
753 // CSR0_IDON | CSR0_INEA;
754
755 REGA(CSR0) = CSR0_INEA;
756
757 if(DREG & (CSR0_RINT | CSR0_TINT)) {
758 DPRINTK(2, ("restarting interrupt, csr0=%#04x\n", DREG));
759 goto still_more;
760 }
761
762 DPRINTK( 2, ( "%s: exiting interrupt, csr0=%#04x.\n",
763 dev->name, DREG ));
764 in_interrupt = 0;
765 return IRQ_HANDLED;
766 }
767
768 /* get packet, toss into skbuff */
769 static int lance_rx( struct net_device *dev )
770 {
771 struct lance_private *lp = netdev_priv(dev);
772 int entry = lp->new_rx;
773
774 /* If we own the next entry, it's a new packet. Send it up. */
775 while( (MEM->rx_head[entry].flag & RMD1_OWN) == RMD1_OWN_HOST ) {
776 struct lance_rx_head *head = &(MEM->rx_head[entry]);
777 int status = head->flag;
778
779 if (status != (RMD1_ENP|RMD1_STP)) { /* There was an error. */
780 /* There is a tricky error noted by John Murphy,
781 <murf@perftech.com> to Russ Nelson: Even with
782 full-sized buffers it's possible for a jabber packet to use two
783 buffers, with only the last correctly noting the error. */
784 if (status & RMD1_ENP) /* Only count a general error at the */
785 dev->stats.rx_errors++; /* end of a packet.*/
786 if (status & RMD1_FRAM) dev->stats.rx_frame_errors++;
787 if (status & RMD1_OFLO) dev->stats.rx_over_errors++;
788 if (status & RMD1_CRC) dev->stats.rx_crc_errors++;
789 if (status & RMD1_BUFF) dev->stats.rx_fifo_errors++;
790 head->flag &= (RMD1_ENP|RMD1_STP);
791 } else {
792 /* Malloc up new buffer, compatible with net-3. */
793 // short pkt_len = head->msg_length;// & 0xfff;
794 short pkt_len = (head->msg_length & 0xfff) - 4;
795 struct sk_buff *skb;
796
797 if (pkt_len < 60) {
798 printk( "%s: Runt packet!\n", dev->name );
799 dev->stats.rx_errors++;
800 }
801 else {
802 skb = dev_alloc_skb( pkt_len+2 );
803 if (skb == NULL) {
804 DPRINTK( 1, ( "%s: Memory squeeze, deferring packet.\n",
805 dev->name ));
806
807 dev->stats.rx_dropped++;
808 head->msg_length = 0;
809 head->flag |= RMD1_OWN_CHIP;
810 lp->new_rx = (lp->new_rx+1) &
811 RX_RING_MOD_MASK;
812 }
813
814 if (lance_debug >= 3) {
815 u_char *data = PKTBUF_ADDR(head);
816 printk( "%s: RX pkt %d type 0x%04x len %d\n ", dev->name, entry, ((u_short *)data)[6], pkt_len);
817 }
818
819
820 skb_reserve( skb, 2 ); /* 16 byte align */
821 skb_put( skb, pkt_len ); /* Make room */
822 skb_copy_to_linear_data(skb,
823 PKTBUF_ADDR(head),
824 pkt_len);
825
826 skb->protocol = eth_type_trans( skb, dev );
827 netif_rx( skb );
828 dev->stats.rx_packets++;
829 dev->stats.rx_bytes += pkt_len;
830 }
831 }
832
833 // head->buf_length = -PKT_BUF_SZ | 0xf000;
834 head->msg_length = 0;
835 head->flag = RMD1_OWN_CHIP;
836
837 entry = lp->new_rx = (lp->new_rx +1) & RX_RING_MOD_MASK;
838 }
839
840 /* From lance.c (Donald Becker): */
841 /* We should check that at least two ring entries are free.
842 If not, we should free one and mark stats->rx_dropped++. */
843
844 return 0;
845 }
846
847
848 static int lance_close( struct net_device *dev )
849 {
850 struct lance_private *lp = netdev_priv(dev);
851
852 netif_stop_queue(dev);
853
854 AREG = CSR0;
855
856 DPRINTK( 2, ( "%s: Shutting down ethercard, status was %2.2x.\n",
857 dev->name, DREG ));
858
859 /* We stop the LANCE here -- it occasionally polls
860 memory if we don't. */
861 DREG = CSR0_STOP;
862 return 0;
863 }
864
865
866 /* Set or clear the multicast filter for this adaptor.
867 num_addrs == -1 Promiscuous mode, receive all packets
868 num_addrs == 0 Normal mode, clear multicast list
869 num_addrs > 0 Multicast mode, receive normal and MC packets, and do
870 best-effort filtering.
871 */
872
873 /* completely untested on a sun3 */
874 static void set_multicast_list( struct net_device *dev )
875 {
876 struct lance_private *lp = netdev_priv(dev);
877
878 if(netif_queue_stopped(dev))
879 /* Only possible if board is already started */
880 return;
881
882 /* We take the simple way out and always enable promiscuous mode. */
883 DREG = CSR0_STOP; /* Temporarily stop the lance. */
884
885 if (dev->flags & IFF_PROMISC) {
886 /* Log any net taps. */
887 DPRINTK( 3, ( "%s: Promiscuous mode enabled.\n", dev->name ));
888 REGA( CSR15 ) = 0x8000; /* Set promiscuous mode */
889 } else {
890 short multicast_table[4];
891 int num_addrs = netdev_mc_count(dev);
892 int i;
893 /* We don't use the multicast table, but rely on upper-layer
894 * filtering. */
895 memset( multicast_table, (num_addrs == 0) ? 0 : -1,
896 sizeof(multicast_table) );
897 for( i = 0; i < 4; i++ )
898 REGA( CSR8+i ) = multicast_table[i];
899 REGA( CSR15 ) = 0; /* Unset promiscuous mode */
900 }
901
902 /*
903 * Always set BSWP after a STOP as STOP puts it back into
904 * little endian mode.
905 */
906 REGA( CSR3 ) = CSR3_BSWP;
907
908 /* Resume normal operation and reset AREG to CSR0 */
909 REGA( CSR0 ) = CSR0_IDON | CSR0_INEA | CSR0_STRT;
910 }
911
912
913 #ifdef MODULE
914
915 static struct net_device *sun3lance_dev;
916
917 int __init init_module(void)
918 {
919 sun3lance_dev = sun3lance_probe(-1);
920 if (IS_ERR(sun3lance_dev))
921 return PTR_ERR(sun3lance_dev);
922 return 0;
923 }
924
925 void __exit cleanup_module(void)
926 {
927 unregister_netdev(sun3lance_dev);
928 #ifdef CONFIG_SUN3
929 iounmap((void __iomem *)sun3lance_dev->base_addr);
930 #endif
931 free_netdev(sun3lance_dev);
932 }
933
934 #endif /* MODULE */
Tomato firmware and modifications.