1 /****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2007-2009 Solarflare Communications Inc.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published
7 * by the Free Software Foundation, incorporated herein by reference.
10 #include <linux/delay.h>
11 #include <linux/rtnetlink.h>
12 #include <linux/seq_file.h>
13 #include <linux/slab.h>
19 #include "workarounds.h"
22 /* We expect these MMDs to be in the package. SFT9001 also has a
23 * clause 22 extension MMD, but since it doesn't have all the generic
24 * MMD registers it is pointless to include it here.
26 #define TENXPRESS_REQUIRED_DEVS (MDIO_DEVS_PMAPMD | \
31 #define SFX7101_LOOPBACKS ((1 << LOOPBACK_PHYXS) | \
32 (1 << LOOPBACK_PCS) | \
33 (1 << LOOPBACK_PMAPMD) | \
34 (1 << LOOPBACK_PHYXS_WS))
36 #define SFT9001_LOOPBACKS ((1 << LOOPBACK_GPHY) | \
37 (1 << LOOPBACK_PHYXS) | \
38 (1 << LOOPBACK_PCS) | \
39 (1 << LOOPBACK_PMAPMD) | \
40 (1 << LOOPBACK_PHYXS_WS))
42 /* We complain if we fail to see the link partner as 10G capable this many
43 * times in a row (must be > 1 as sampling the autoneg. registers is racy)
45 #define MAX_BAD_LP_TRIES (5)
47 /* Extended control register */
48 #define PMA_PMD_XCONTROL_REG 49152
49 #define PMA_PMD_EXT_GMII_EN_LBN 1
50 #define PMA_PMD_EXT_GMII_EN_WIDTH 1
51 #define PMA_PMD_EXT_CLK_OUT_LBN 2
52 #define PMA_PMD_EXT_CLK_OUT_WIDTH 1
53 #define PMA_PMD_LNPGA_POWERDOWN_LBN 8 /* SFX7101 only */
54 #define PMA_PMD_LNPGA_POWERDOWN_WIDTH 1
55 #define PMA_PMD_EXT_CLK312_LBN 8 /* SFT9001 only */
56 #define PMA_PMD_EXT_CLK312_WIDTH 1
57 #define PMA_PMD_EXT_LPOWER_LBN 12
58 #define PMA_PMD_EXT_LPOWER_WIDTH 1
59 #define PMA_PMD_EXT_ROBUST_LBN 14
60 #define PMA_PMD_EXT_ROBUST_WIDTH 1
61 #define PMA_PMD_EXT_SSR_LBN 15
62 #define PMA_PMD_EXT_SSR_WIDTH 1
64 /* extended status register */
65 #define PMA_PMD_XSTATUS_REG 49153
66 #define PMA_PMD_XSTAT_MDIX_LBN 14
67 #define PMA_PMD_XSTAT_FLP_LBN (12)
69 /* LED control register */
70 #define PMA_PMD_LED_CTRL_REG 49159
71 #define PMA_PMA_LED_ACTIVITY_LBN (3)
73 /* LED function override register */
74 #define PMA_PMD_LED_OVERR_REG 49161
75 /* Bit positions for different LEDs (there are more but not wired on SFE4001)*/
76 #define PMA_PMD_LED_LINK_LBN (0)
77 #define PMA_PMD_LED_SPEED_LBN (2)
78 #define PMA_PMD_LED_TX_LBN (4)
79 #define PMA_PMD_LED_RX_LBN (6)
80 /* Override settings */
81 #define PMA_PMD_LED_AUTO (0) /* H/W control */
82 #define PMA_PMD_LED_ON (1)
83 #define PMA_PMD_LED_OFF (2)
84 #define PMA_PMD_LED_FLASH (3)
85 #define PMA_PMD_LED_MASK 3
86 /* All LEDs under hardware control */
87 #define SFT9001_PMA_PMD_LED_DEFAULT 0
88 /* Green and Amber under hardware control, Red off */
89 #define SFX7101_PMA_PMD_LED_DEFAULT (PMA_PMD_LED_OFF << PMA_PMD_LED_RX_LBN)
91 #define PMA_PMD_SPEED_ENABLE_REG 49192
92 #define PMA_PMD_100TX_ADV_LBN 1
93 #define PMA_PMD_100TX_ADV_WIDTH 1
94 #define PMA_PMD_1000T_ADV_LBN 2
95 #define PMA_PMD_1000T_ADV_WIDTH 1
96 #define PMA_PMD_10000T_ADV_LBN 3
97 #define PMA_PMD_10000T_ADV_WIDTH 1
98 #define PMA_PMD_SPEED_LBN 4
99 #define PMA_PMD_SPEED_WIDTH 4
101 /* Cable diagnostics - SFT9001 only */
102 #define PMA_PMD_CDIAG_CTRL_REG 49213
103 #define CDIAG_CTRL_IMMED_LBN 15
104 #define CDIAG_CTRL_BRK_LINK_LBN 12
105 #define CDIAG_CTRL_IN_PROG_LBN 11
106 #define CDIAG_CTRL_LEN_UNIT_LBN 10
107 #define CDIAG_CTRL_LEN_METRES 1
108 #define PMA_PMD_CDIAG_RES_REG 49174
109 #define CDIAG_RES_A_LBN 12
110 #define CDIAG_RES_B_LBN 8
111 #define CDIAG_RES_C_LBN 4
112 #define CDIAG_RES_D_LBN 0
113 #define CDIAG_RES_WIDTH 4
114 #define CDIAG_RES_OPEN 2
115 #define CDIAG_RES_OK 1
116 #define CDIAG_RES_INVALID 0
117 /* Set of 4 registers for pairs A-D */
118 #define PMA_PMD_CDIAG_LEN_REG 49175
120 /* Serdes control registers - SFT9001 only */
121 #define PMA_PMD_CSERDES_CTRL_REG 64258
122 /* Set the 156.25 MHz output to 312.5 MHz to drive Falcon's XMAC */
123 #define PMA_PMD_CSERDES_DEFAULT 0x000f
125 /* Misc register defines - SFX7101 only */
126 #define PCS_CLOCK_CTRL_REG 55297
127 #define PLL312_RST_N_LBN 2
129 #define PCS_SOFT_RST2_REG 55302
130 #define SERDES_RST_N_LBN 13
131 #define XGXS_RST_N_LBN 12
133 #define PCS_TEST_SELECT_REG 55303 /* PRM 10.5.8 */
134 #define CLK312_EN_LBN 3
136 /* PHYXS registers */
137 #define PHYXS_XCONTROL_REG 49152
138 #define PHYXS_RESET_LBN 15
139 #define PHYXS_RESET_WIDTH 1
141 #define PHYXS_TEST1 (49162)
142 #define LOOPBACK_NEAR_LBN (8)
143 #define LOOPBACK_NEAR_WIDTH (1)
145 /* Boot status register */
146 #define PCS_BOOT_STATUS_REG 53248
147 #define PCS_BOOT_FATAL_ERROR_LBN 0
148 #define PCS_BOOT_PROGRESS_LBN 1
149 #define PCS_BOOT_PROGRESS_WIDTH 2
150 #define PCS_BOOT_PROGRESS_INIT 0
151 #define PCS_BOOT_PROGRESS_WAIT_MDIO 1
152 #define PCS_BOOT_PROGRESS_CHECKSUM 2
153 #define PCS_BOOT_PROGRESS_JUMP 3
154 #define PCS_BOOT_DOWNLOAD_WAIT_LBN 3
155 #define PCS_BOOT_CODE_STARTED_LBN 4
157 /* 100M/1G PHY registers */
158 #define GPHY_XCONTROL_REG 49152
159 #define GPHY_ISOLATE_LBN 10
160 #define GPHY_ISOLATE_WIDTH 1
161 #define GPHY_DUPLEX_LBN 8
162 #define GPHY_DUPLEX_WIDTH 1
163 #define GPHY_LOOPBACK_NEAR_LBN 14
164 #define GPHY_LOOPBACK_NEAR_WIDTH 1
166 #define C22EXT_STATUS_REG 49153
167 #define C22EXT_STATUS_LINK_LBN 2
168 #define C22EXT_STATUS_LINK_WIDTH 1
170 #define C22EXT_MSTSLV_CTRL 49161
171 #define C22EXT_MSTSLV_CTRL_ADV_1000_HD_LBN 8
172 #define C22EXT_MSTSLV_CTRL_ADV_1000_FD_LBN 9
174 #define C22EXT_MSTSLV_STATUS 49162
175 #define C22EXT_MSTSLV_STATUS_LP_1000_HD_LBN 10
176 #define C22EXT_MSTSLV_STATUS_LP_1000_FD_LBN 11
178 /* Time to wait between powering down the LNPGA and turning off the power
180 #define LNPGA_PDOWN_WAIT (HZ / 5)
182 struct tenxpress_phy_data
{
183 enum efx_loopback_mode loopback_mode
;
184 enum efx_phy_mode phy_mode
;
188 static ssize_t
show_phy_short_reach(struct device
*dev
,
189 struct device_attribute
*attr
, char *buf
)
191 struct efx_nic
*efx
= pci_get_drvdata(to_pci_dev(dev
));
194 reg
= efx_mdio_read(efx
, MDIO_MMD_PMAPMD
, MDIO_PMA_10GBT_TXPWR
);
195 return sprintf(buf
, "%d\n", !!(reg
& MDIO_PMA_10GBT_TXPWR_SHORT
));
198 static ssize_t
set_phy_short_reach(struct device
*dev
,
199 struct device_attribute
*attr
,
200 const char *buf
, size_t count
)
202 struct efx_nic
*efx
= pci_get_drvdata(to_pci_dev(dev
));
206 if (efx
->state
!= STATE_RUNNING
) {
209 efx_mdio_set_flag(efx
, MDIO_MMD_PMAPMD
, MDIO_PMA_10GBT_TXPWR
,
210 MDIO_PMA_10GBT_TXPWR_SHORT
,
211 count
!= 0 && *buf
!= '0');
212 rc
= efx_reconfigure_port(efx
);
216 return rc
< 0 ? rc
: (ssize_t
)count
;
219 static DEVICE_ATTR(phy_short_reach
, 0644, show_phy_short_reach
,
220 set_phy_short_reach
);
222 int sft9001_wait_boot(struct efx_nic
*efx
)
224 unsigned long timeout
= jiffies
+ HZ
+ 1;
228 boot_stat
= efx_mdio_read(efx
, MDIO_MMD_PCS
,
229 PCS_BOOT_STATUS_REG
);
230 if (boot_stat
>= 0) {
231 netif_dbg(efx
, hw
, efx
->net_dev
,
232 "PHY boot status = %#x\n", boot_stat
);
234 ((1 << PCS_BOOT_FATAL_ERROR_LBN
) |
235 (3 << PCS_BOOT_PROGRESS_LBN
) |
236 (1 << PCS_BOOT_DOWNLOAD_WAIT_LBN
) |
237 (1 << PCS_BOOT_CODE_STARTED_LBN
))) {
238 case ((1 << PCS_BOOT_FATAL_ERROR_LBN
) |
239 (PCS_BOOT_PROGRESS_CHECKSUM
<<
240 PCS_BOOT_PROGRESS_LBN
)):
241 case ((1 << PCS_BOOT_FATAL_ERROR_LBN
) |
242 (PCS_BOOT_PROGRESS_INIT
<<
243 PCS_BOOT_PROGRESS_LBN
) |
244 (1 << PCS_BOOT_DOWNLOAD_WAIT_LBN
)):
246 case ((PCS_BOOT_PROGRESS_WAIT_MDIO
<<
247 PCS_BOOT_PROGRESS_LBN
) |
248 (1 << PCS_BOOT_DOWNLOAD_WAIT_LBN
)):
249 return (efx
->phy_mode
& PHY_MODE_SPECIAL
) ?
251 case ((PCS_BOOT_PROGRESS_JUMP
<<
252 PCS_BOOT_PROGRESS_LBN
) |
253 (1 << PCS_BOOT_CODE_STARTED_LBN
)):
254 case ((PCS_BOOT_PROGRESS_JUMP
<<
255 PCS_BOOT_PROGRESS_LBN
) |
256 (1 << PCS_BOOT_DOWNLOAD_WAIT_LBN
) |
257 (1 << PCS_BOOT_CODE_STARTED_LBN
)):
258 return (efx
->phy_mode
& PHY_MODE_SPECIAL
) ?
261 if (boot_stat
& (1 << PCS_BOOT_FATAL_ERROR_LBN
))
267 if (time_after_eq(jiffies
, timeout
))
274 static int tenxpress_init(struct efx_nic
*efx
)
278 if (efx
->phy_type
== PHY_TYPE_SFX7101
) {
279 /* Enable 312.5 MHz clock */
280 efx_mdio_write(efx
, MDIO_MMD_PCS
, PCS_TEST_SELECT_REG
,
283 /* Enable 312.5 MHz clock and GMII */
284 reg
= efx_mdio_read(efx
, MDIO_MMD_PMAPMD
, PMA_PMD_XCONTROL_REG
);
285 reg
|= ((1 << PMA_PMD_EXT_GMII_EN_LBN
) |
286 (1 << PMA_PMD_EXT_CLK_OUT_LBN
) |
287 (1 << PMA_PMD_EXT_CLK312_LBN
) |
288 (1 << PMA_PMD_EXT_ROBUST_LBN
));
290 efx_mdio_write(efx
, MDIO_MMD_PMAPMD
, PMA_PMD_XCONTROL_REG
, reg
);
291 efx_mdio_set_flag(efx
, MDIO_MMD_C22EXT
,
292 GPHY_XCONTROL_REG
, 1 << GPHY_ISOLATE_LBN
,
296 /* Set the LEDs up as: Green = Link, Amber = Link/Act, Red = Off */
297 if (efx
->phy_type
== PHY_TYPE_SFX7101
) {
298 efx_mdio_set_flag(efx
, MDIO_MMD_PMAPMD
, PMA_PMD_LED_CTRL_REG
,
299 1 << PMA_PMA_LED_ACTIVITY_LBN
, true);
300 efx_mdio_write(efx
, MDIO_MMD_PMAPMD
, PMA_PMD_LED_OVERR_REG
,
301 SFX7101_PMA_PMD_LED_DEFAULT
);
307 static int tenxpress_phy_probe(struct efx_nic
*efx
)
309 struct tenxpress_phy_data
*phy_data
;
312 /* Allocate phy private storage */
313 phy_data
= kzalloc(sizeof(*phy_data
), GFP_KERNEL
);
316 efx
->phy_data
= phy_data
;
317 phy_data
->phy_mode
= efx
->phy_mode
;
319 /* Create any special files */
320 if (efx
->phy_type
== PHY_TYPE_SFT9001B
) {
321 rc
= device_create_file(&efx
->pci_dev
->dev
,
322 &dev_attr_phy_short_reach
);
327 if (efx
->phy_type
== PHY_TYPE_SFX7101
) {
328 efx
->mdio
.mmds
= TENXPRESS_REQUIRED_DEVS
;
329 efx
->mdio
.mode_support
= MDIO_SUPPORTS_C45
;
331 efx
->loopback_modes
= SFX7101_LOOPBACKS
| FALCON_XMAC_LOOPBACKS
;
333 efx
->link_advertising
= (ADVERTISED_TP
| ADVERTISED_Autoneg
|
334 ADVERTISED_10000baseT_Full
);
336 efx
->mdio
.mmds
= TENXPRESS_REQUIRED_DEVS
;
337 efx
->mdio
.mode_support
= MDIO_SUPPORTS_C45
| MDIO_EMULATE_C22
;
339 efx
->loopback_modes
= (SFT9001_LOOPBACKS
|
340 FALCON_XMAC_LOOPBACKS
|
341 FALCON_GMAC_LOOPBACKS
);
343 efx
->link_advertising
= (ADVERTISED_TP
| ADVERTISED_Autoneg
|
344 ADVERTISED_10000baseT_Full
|
345 ADVERTISED_1000baseT_Full
|
346 ADVERTISED_100baseT_Full
);
352 kfree(efx
->phy_data
);
353 efx
->phy_data
= NULL
;
357 static int tenxpress_phy_init(struct efx_nic
*efx
)
361 falcon_board(efx
)->type
->init_phy(efx
);
363 if (!(efx
->phy_mode
& PHY_MODE_SPECIAL
)) {
364 if (efx
->phy_type
== PHY_TYPE_SFT9001A
) {
366 reg
= efx_mdio_read(efx
, MDIO_MMD_PMAPMD
,
367 PMA_PMD_XCONTROL_REG
);
368 reg
|= (1 << PMA_PMD_EXT_SSR_LBN
);
369 efx_mdio_write(efx
, MDIO_MMD_PMAPMD
,
370 PMA_PMD_XCONTROL_REG
, reg
);
374 rc
= efx_mdio_wait_reset_mmds(efx
, TENXPRESS_REQUIRED_DEVS
);
378 rc
= efx_mdio_check_mmds(efx
, TENXPRESS_REQUIRED_DEVS
, 0);
383 rc
= tenxpress_init(efx
);
387 /* Reinitialise flow control settings */
388 efx_link_set_wanted_fc(efx
, efx
->wanted_fc
);
389 efx_mdio_an_reconfigure(efx
);
391 schedule_timeout_uninterruptible(HZ
/ 5); /* 200ms */
393 /* Let XGXS and SerDes out of reset */
394 falcon_reset_xaui(efx
);
399 /* Perform a "special software reset" on the PHY. The caller is
400 * responsible for saving and restoring the PHY hardware registers
401 * properly, and masking/unmasking LASI */
402 static int tenxpress_special_reset(struct efx_nic
*efx
)
406 /* The XGMAC clock is driven from the SFC7101/SFT9001 312MHz clock, so
407 * a special software reset can glitch the XGMAC sufficiently for stats
408 * requests to fail. */
409 falcon_stop_nic_stats(efx
);
412 reg
= efx_mdio_read(efx
, MDIO_MMD_PMAPMD
, PMA_PMD_XCONTROL_REG
);
413 reg
|= (1 << PMA_PMD_EXT_SSR_LBN
);
414 efx_mdio_write(efx
, MDIO_MMD_PMAPMD
, PMA_PMD_XCONTROL_REG
, reg
);
418 /* Wait for the blocks to come out of reset */
419 rc
= efx_mdio_wait_reset_mmds(efx
, TENXPRESS_REQUIRED_DEVS
);
423 /* Try and reconfigure the device */
424 rc
= tenxpress_init(efx
);
428 /* Wait for the XGXS state machine to churn */
431 falcon_start_nic_stats(efx
);
435 static void sfx7101_check_bad_lp(struct efx_nic
*efx
, bool link_ok
)
437 struct tenxpress_phy_data
*pd
= efx
->phy_data
;
444 /* Check that AN has started but not completed. */
445 reg
= efx_mdio_read(efx
, MDIO_MMD_AN
, MDIO_STAT1
);
446 if (!(reg
& MDIO_AN_STAT1_LPABLE
))
447 return; /* LP status is unknown */
448 bad_lp
= !(reg
& MDIO_AN_STAT1_COMPLETE
);
453 /* Nothing to do if all is well and was previously so. */
454 if (!pd
->bad_lp_tries
)
457 /* Use the RX (red) LED as an error indicator once we've seen AN
458 * failure several times in a row, and also log a message. */
459 if (!bad_lp
|| pd
->bad_lp_tries
== MAX_BAD_LP_TRIES
) {
460 reg
= efx_mdio_read(efx
, MDIO_MMD_PMAPMD
,
461 PMA_PMD_LED_OVERR_REG
);
462 reg
&= ~(PMA_PMD_LED_MASK
<< PMA_PMD_LED_RX_LBN
);
464 reg
|= PMA_PMD_LED_OFF
<< PMA_PMD_LED_RX_LBN
;
466 reg
|= PMA_PMD_LED_FLASH
<< PMA_PMD_LED_RX_LBN
;
467 netif_err(efx
, link
, efx
->net_dev
,
468 "appears to be plugged into a port"
469 " that is not 10GBASE-T capable. The PHY"
470 " supports 10GBASE-T ONLY, so no link can"
471 " be established\n");
473 efx_mdio_write(efx
, MDIO_MMD_PMAPMD
,
474 PMA_PMD_LED_OVERR_REG
, reg
);
475 pd
->bad_lp_tries
= bad_lp
;
479 static bool sfx7101_link_ok(struct efx_nic
*efx
)
481 return efx_mdio_links_ok(efx
,
487 static bool sft9001_link_ok(struct efx_nic
*efx
, struct ethtool_cmd
*ecmd
)
491 if (efx_phy_mode_disabled(efx
->phy_mode
))
493 else if (efx
->loopback_mode
== LOOPBACK_GPHY
)
495 else if (efx
->loopback_mode
)
496 return efx_mdio_links_ok(efx
,
500 /* We must use the same definition of link state as LASI,
501 * otherwise we can miss a link state transition
503 if (ecmd
->speed
== 10000) {
504 reg
= efx_mdio_read(efx
, MDIO_MMD_PCS
, MDIO_PCS_10GBRT_STAT1
);
505 return reg
& MDIO_PCS_10GBRT_STAT1_BLKLK
;
507 reg
= efx_mdio_read(efx
, MDIO_MMD_C22EXT
, C22EXT_STATUS_REG
);
508 return reg
& (1 << C22EXT_STATUS_LINK_LBN
);
512 static void tenxpress_ext_loopback(struct efx_nic
*efx
)
514 efx_mdio_set_flag(efx
, MDIO_MMD_PHYXS
, PHYXS_TEST1
,
515 1 << LOOPBACK_NEAR_LBN
,
516 efx
->loopback_mode
== LOOPBACK_PHYXS
);
517 if (efx
->phy_type
!= PHY_TYPE_SFX7101
)
518 efx_mdio_set_flag(efx
, MDIO_MMD_C22EXT
, GPHY_XCONTROL_REG
,
519 1 << GPHY_LOOPBACK_NEAR_LBN
,
520 efx
->loopback_mode
== LOOPBACK_GPHY
);
523 static void tenxpress_low_power(struct efx_nic
*efx
)
525 if (efx
->phy_type
== PHY_TYPE_SFX7101
)
526 efx_mdio_set_mmds_lpower(
527 efx
, !!(efx
->phy_mode
& PHY_MODE_LOW_POWER
),
528 TENXPRESS_REQUIRED_DEVS
);
531 efx
, MDIO_MMD_PMAPMD
, PMA_PMD_XCONTROL_REG
,
532 1 << PMA_PMD_EXT_LPOWER_LBN
,
533 !!(efx
->phy_mode
& PHY_MODE_LOW_POWER
));
536 static int tenxpress_phy_reconfigure(struct efx_nic
*efx
)
538 struct tenxpress_phy_data
*phy_data
= efx
->phy_data
;
539 bool phy_mode_change
, loop_reset
;
541 if (efx
->phy_mode
& (PHY_MODE_OFF
| PHY_MODE_SPECIAL
)) {
542 phy_data
->phy_mode
= efx
->phy_mode
;
546 phy_mode_change
= (efx
->phy_mode
== PHY_MODE_NORMAL
&&
547 phy_data
->phy_mode
!= PHY_MODE_NORMAL
);
548 loop_reset
= (LOOPBACK_OUT_OF(phy_data
, efx
, LOOPBACKS_EXTERNAL(efx
)) ||
549 LOOPBACK_CHANGED(phy_data
, efx
, 1 << LOOPBACK_GPHY
));
551 if (loop_reset
|| phy_mode_change
) {
552 tenxpress_special_reset(efx
);
554 /* Reset XAUI if we were in 10G, and are staying
555 * in 10G. If we're moving into and out of 10G
556 * then xaui will be reset anyway */
558 falcon_reset_xaui(efx
);
561 tenxpress_low_power(efx
);
562 efx_mdio_transmit_disable(efx
);
563 efx_mdio_phy_reconfigure(efx
);
564 tenxpress_ext_loopback(efx
);
565 efx_mdio_an_reconfigure(efx
);
567 phy_data
->loopback_mode
= efx
->loopback_mode
;
568 phy_data
->phy_mode
= efx
->phy_mode
;
574 tenxpress_get_settings(struct efx_nic
*efx
, struct ethtool_cmd
*ecmd
);
576 /* Poll for link state changes */
577 static bool tenxpress_phy_poll(struct efx_nic
*efx
)
579 struct efx_link_state old_state
= efx
->link_state
;
581 if (efx
->phy_type
== PHY_TYPE_SFX7101
) {
582 efx
->link_state
.up
= sfx7101_link_ok(efx
);
583 efx
->link_state
.speed
= 10000;
584 efx
->link_state
.fd
= true;
585 efx
->link_state
.fc
= efx_mdio_get_pause(efx
);
587 sfx7101_check_bad_lp(efx
, efx
->link_state
.up
);
589 struct ethtool_cmd ecmd
;
591 /* Check the LASI alarm first */
592 if (efx
->loopback_mode
== LOOPBACK_NONE
&&
593 !(efx_mdio_read(efx
, MDIO_MMD_PMAPMD
, MDIO_PMA_LASI_STAT
) &
594 MDIO_PMA_LASI_LSALARM
))
597 tenxpress_get_settings(efx
, &ecmd
);
599 efx
->link_state
.up
= sft9001_link_ok(efx
, &ecmd
);
600 efx
->link_state
.speed
= ecmd
.speed
;
601 efx
->link_state
.fd
= (ecmd
.duplex
== DUPLEX_FULL
);
602 efx
->link_state
.fc
= efx_mdio_get_pause(efx
);
605 return !efx_link_state_equal(&efx
->link_state
, &old_state
);
608 static void sfx7101_phy_fini(struct efx_nic
*efx
)
612 /* Power down the LNPGA */
613 reg
= (1 << PMA_PMD_LNPGA_POWERDOWN_LBN
);
614 efx_mdio_write(efx
, MDIO_MMD_PMAPMD
, PMA_PMD_XCONTROL_REG
, reg
);
616 /* Waiting here ensures that the board fini, which can turn
617 * off the power to the PHY, won't get run until the LNPGA
618 * powerdown has been given long enough to complete. */
619 schedule_timeout_uninterruptible(LNPGA_PDOWN_WAIT
); /* 200 ms */
622 static void tenxpress_phy_remove(struct efx_nic
*efx
)
624 if (efx
->phy_type
== PHY_TYPE_SFT9001B
)
625 device_remove_file(&efx
->pci_dev
->dev
,
626 &dev_attr_phy_short_reach
);
628 kfree(efx
->phy_data
);
629 efx
->phy_data
= NULL
;
633 /* Override the RX, TX and link LEDs */
634 void tenxpress_set_id_led(struct efx_nic
*efx
, enum efx_led_mode mode
)
640 reg
= (PMA_PMD_LED_OFF
<< PMA_PMD_LED_TX_LBN
) |
641 (PMA_PMD_LED_OFF
<< PMA_PMD_LED_RX_LBN
) |
642 (PMA_PMD_LED_OFF
<< PMA_PMD_LED_LINK_LBN
);
645 reg
= (PMA_PMD_LED_ON
<< PMA_PMD_LED_TX_LBN
) |
646 (PMA_PMD_LED_ON
<< PMA_PMD_LED_RX_LBN
) |
647 (PMA_PMD_LED_ON
<< PMA_PMD_LED_LINK_LBN
);
650 if (efx
->phy_type
== PHY_TYPE_SFX7101
)
651 reg
= SFX7101_PMA_PMD_LED_DEFAULT
;
653 reg
= SFT9001_PMA_PMD_LED_DEFAULT
;
657 efx_mdio_write(efx
, MDIO_MMD_PMAPMD
, PMA_PMD_LED_OVERR_REG
, reg
);
660 static const char *const sfx7101_test_names
[] = {
664 static const char *sfx7101_test_name(struct efx_nic
*efx
, unsigned int index
)
666 if (index
< ARRAY_SIZE(sfx7101_test_names
))
667 return sfx7101_test_names
[index
];
672 sfx7101_run_tests(struct efx_nic
*efx
, int *results
, unsigned flags
)
676 if (!(flags
& ETH_TEST_FL_OFFLINE
))
679 /* BIST is automatically run after a special software reset */
680 rc
= tenxpress_special_reset(efx
);
681 results
[0] = rc
? -1 : 1;
683 efx_mdio_an_reconfigure(efx
);
688 static const char *const sft9001_test_names
[] = {
690 "cable.pairA.status",
691 "cable.pairB.status",
692 "cable.pairC.status",
693 "cable.pairD.status",
694 "cable.pairA.length",
695 "cable.pairB.length",
696 "cable.pairC.length",
697 "cable.pairD.length",
700 static const char *sft9001_test_name(struct efx_nic
*efx
, unsigned int index
)
702 if (index
< ARRAY_SIZE(sft9001_test_names
))
703 return sft9001_test_names
[index
];
707 static int sft9001_run_tests(struct efx_nic
*efx
, int *results
, unsigned flags
)
709 int rc
= 0, rc2
, i
, ctrl_reg
, res_reg
;
711 /* Initialise cable diagnostic results to unknown failure */
712 for (i
= 1; i
< 9; ++i
)
715 /* Run cable diagnostics; wait up to 5 seconds for them to complete.
716 * A cable fault is not a self-test failure, but a timeout is. */
717 ctrl_reg
= ((1 << CDIAG_CTRL_IMMED_LBN
) |
718 (CDIAG_CTRL_LEN_METRES
<< CDIAG_CTRL_LEN_UNIT_LBN
));
719 if (flags
& ETH_TEST_FL_OFFLINE
) {
720 /* Break the link in order to run full diagnostics. We
721 * must reset the PHY to resume normal service. */
722 ctrl_reg
|= (1 << CDIAG_CTRL_BRK_LINK_LBN
);
724 efx_mdio_write(efx
, MDIO_MMD_PMAPMD
, PMA_PMD_CDIAG_CTRL_REG
,
727 while (efx_mdio_read(efx
, MDIO_MMD_PMAPMD
, PMA_PMD_CDIAG_CTRL_REG
) &
728 (1 << CDIAG_CTRL_IN_PROG_LBN
)) {
735 res_reg
= efx_mdio_read(efx
, MDIO_MMD_PMAPMD
, PMA_PMD_CDIAG_RES_REG
);
736 for (i
= 0; i
< 4; i
++) {
738 (res_reg
>> (CDIAG_RES_A_LBN
- i
* CDIAG_RES_WIDTH
))
739 & ((1 << CDIAG_RES_WIDTH
) - 1);
740 int len_reg
= efx_mdio_read(efx
, MDIO_MMD_PMAPMD
,
741 PMA_PMD_CDIAG_LEN_REG
+ i
);
742 if (pair_res
== CDIAG_RES_OK
)
744 else if (pair_res
== CDIAG_RES_INVALID
)
747 results
[1 + i
] = -pair_res
;
748 if (pair_res
!= CDIAG_RES_INVALID
&&
749 pair_res
!= CDIAG_RES_OPEN
&&
751 results
[5 + i
] = len_reg
;
755 if (flags
& ETH_TEST_FL_OFFLINE
) {
756 /* Reset, running the BIST and then resuming normal service. */
757 rc2
= tenxpress_special_reset(efx
);
758 results
[0] = rc2
? -1 : 1;
762 efx_mdio_an_reconfigure(efx
);
769 tenxpress_get_settings(struct efx_nic
*efx
, struct ethtool_cmd
*ecmd
)
771 u32 adv
= 0, lpa
= 0;
774 if (efx
->phy_type
!= PHY_TYPE_SFX7101
) {
775 reg
= efx_mdio_read(efx
, MDIO_MMD_C22EXT
, C22EXT_MSTSLV_CTRL
);
776 if (reg
& (1 << C22EXT_MSTSLV_CTRL_ADV_1000_FD_LBN
))
777 adv
|= ADVERTISED_1000baseT_Full
;
778 reg
= efx_mdio_read(efx
, MDIO_MMD_C22EXT
, C22EXT_MSTSLV_STATUS
);
779 if (reg
& (1 << C22EXT_MSTSLV_STATUS_LP_1000_HD_LBN
))
780 lpa
|= ADVERTISED_1000baseT_Half
;
781 if (reg
& (1 << C22EXT_MSTSLV_STATUS_LP_1000_FD_LBN
))
782 lpa
|= ADVERTISED_1000baseT_Full
;
784 reg
= efx_mdio_read(efx
, MDIO_MMD_AN
, MDIO_AN_10GBT_CTRL
);
785 if (reg
& MDIO_AN_10GBT_CTRL_ADV10G
)
786 adv
|= ADVERTISED_10000baseT_Full
;
787 reg
= efx_mdio_read(efx
, MDIO_MMD_AN
, MDIO_AN_10GBT_STAT
);
788 if (reg
& MDIO_AN_10GBT_STAT_LP10G
)
789 lpa
|= ADVERTISED_10000baseT_Full
;
791 mdio45_ethtool_gset_npage(&efx
->mdio
, ecmd
, adv
, lpa
);
793 if (efx
->phy_type
!= PHY_TYPE_SFX7101
) {
794 ecmd
->supported
|= (SUPPORTED_100baseT_Full
|
795 SUPPORTED_1000baseT_Full
);
796 if (ecmd
->speed
!= SPEED_10000
) {
798 (efx_mdio_read(efx
, MDIO_MMD_PMAPMD
,
799 PMA_PMD_XSTATUS_REG
) &
800 (1 << PMA_PMD_XSTAT_MDIX_LBN
))
801 ? ETH_TP_MDI_X
: ETH_TP_MDI
;
805 /* In loopback, the PHY automatically brings up the correct interface,
806 * but doesn't advertise the correct speed. So override it */
807 if (efx
->loopback_mode
== LOOPBACK_GPHY
)
808 ecmd
->speed
= SPEED_1000
;
809 else if (LOOPBACK_EXTERNAL(efx
))
810 ecmd
->speed
= SPEED_10000
;
813 static int tenxpress_set_settings(struct efx_nic
*efx
, struct ethtool_cmd
*ecmd
)
818 return efx_mdio_set_settings(efx
, ecmd
);
821 static void sfx7101_set_npage_adv(struct efx_nic
*efx
, u32 advertising
)
823 efx_mdio_set_flag(efx
, MDIO_MMD_AN
, MDIO_AN_10GBT_CTRL
,
824 MDIO_AN_10GBT_CTRL_ADV10G
,
825 advertising
& ADVERTISED_10000baseT_Full
);
828 static void sft9001_set_npage_adv(struct efx_nic
*efx
, u32 advertising
)
830 efx_mdio_set_flag(efx
, MDIO_MMD_C22EXT
, C22EXT_MSTSLV_CTRL
,
831 1 << C22EXT_MSTSLV_CTRL_ADV_1000_FD_LBN
,
832 advertising
& ADVERTISED_1000baseT_Full
);
833 efx_mdio_set_flag(efx
, MDIO_MMD_AN
, MDIO_AN_10GBT_CTRL
,
834 MDIO_AN_10GBT_CTRL_ADV10G
,
835 advertising
& ADVERTISED_10000baseT_Full
);
838 struct efx_phy_operations falcon_sfx7101_phy_ops
= {
839 .probe
= tenxpress_phy_probe
,
840 .init
= tenxpress_phy_init
,
841 .reconfigure
= tenxpress_phy_reconfigure
,
842 .poll
= tenxpress_phy_poll
,
843 .fini
= sfx7101_phy_fini
,
844 .remove
= tenxpress_phy_remove
,
845 .get_settings
= tenxpress_get_settings
,
846 .set_settings
= tenxpress_set_settings
,
847 .set_npage_adv
= sfx7101_set_npage_adv
,
848 .test_alive
= efx_mdio_test_alive
,
849 .test_name
= sfx7101_test_name
,
850 .run_tests
= sfx7101_run_tests
,
853 struct efx_phy_operations falcon_sft9001_phy_ops
= {
854 .probe
= tenxpress_phy_probe
,
855 .init
= tenxpress_phy_init
,
856 .reconfigure
= tenxpress_phy_reconfigure
,
857 .poll
= tenxpress_phy_poll
,
858 .fini
= efx_port_dummy_op_void
,
859 .remove
= tenxpress_phy_remove
,
860 .get_settings
= tenxpress_get_settings
,
861 .set_settings
= tenxpress_set_settings
,
862 .set_npage_adv
= sft9001_set_npage_adv
,
863 .test_alive
= efx_mdio_test_alive
,
864 .test_name
= sft9001_test_name
,
865 .run_tests
= sft9001_run_tests
,