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GUI: Fix Tomato RAF theme for all builds. Compilation typo.
[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / drivers / net / qlcnic / qlcnic.h
blob970389331bbc4cb5c91da180fd04d282db872ac5
1 /*
2 * Copyright (C) 2009 - QLogic Corporation.
3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
18 * MA 02111-1307, USA.
19 *
20 * The full GNU General Public License is included in this distribution
21 * in the file called "COPYING".
22 *
23 */
24
25 #ifndef _QLCNIC_H_
26 #define _QLCNIC_H_
27
28 #include <linux/module.h>
29 #include <linux/kernel.h>
30 #include <linux/types.h>
31 #include <linux/ioport.h>
32 #include <linux/pci.h>
33 #include <linux/netdevice.h>
34 #include <linux/etherdevice.h>
35 #include <linux/ip.h>
36 #include <linux/in.h>
37 #include <linux/tcp.h>
38 #include <linux/skbuff.h>
39 #include <linux/firmware.h>
40
41 #include <linux/ethtool.h>
42 #include <linux/mii.h>
43 #include <linux/timer.h>
44
45 #include <linux/vmalloc.h>
46
47 #include <linux/io.h>
48 #include <asm/byteorder.h>
49
50 #include "qlcnic_hdr.h"
51
52 #define _QLCNIC_LINUX_MAJOR 5
53 #define _QLCNIC_LINUX_MINOR 0
54 #define _QLCNIC_LINUX_SUBVERSION 7
55 #define QLCNIC_LINUX_VERSIONID "5.0.7"
56 #define QLCNIC_DRV_IDC_VER 0x01
57
58 #define QLCNIC_VERSION_CODE(a, b, c) (((a) << 24) + ((b) << 16) + (c))
59 #define _major(v) (((v) >> 24) & 0xff)
60 #define _minor(v) (((v) >> 16) & 0xff)
61 #define _build(v) ((v) & 0xffff)
62
63 /* version in image has weird encoding:
64 * 7:0 - major
65 * 15:8 - minor
66 * 31:16 - build (little endian)
67 */
68 #define QLCNIC_DECODE_VERSION(v) \
69 QLCNIC_VERSION_CODE(((v) & 0xff), (((v) >> 8) & 0xff), ((v) >> 16))
70
71 #define QLCNIC_MIN_FW_VERSION QLCNIC_VERSION_CODE(4, 4, 2)
72 #define QLCNIC_NUM_FLASH_SECTORS (64)
73 #define QLCNIC_FLASH_SECTOR_SIZE (64 * 1024)
74 #define QLCNIC_FLASH_TOTAL_SIZE (QLCNIC_NUM_FLASH_SECTORS \
75 * QLCNIC_FLASH_SECTOR_SIZE)
76
77 #define RCV_DESC_RINGSIZE(rds_ring) \
78 (sizeof(struct rcv_desc) * (rds_ring)->num_desc)
79 #define RCV_BUFF_RINGSIZE(rds_ring) \
80 (sizeof(struct qlcnic_rx_buffer) * rds_ring->num_desc)
81 #define STATUS_DESC_RINGSIZE(sds_ring) \
82 (sizeof(struct status_desc) * (sds_ring)->num_desc)
83 #define TX_BUFF_RINGSIZE(tx_ring) \
84 (sizeof(struct qlcnic_cmd_buffer) * tx_ring->num_desc)
85 #define TX_DESC_RINGSIZE(tx_ring) \
86 (sizeof(struct cmd_desc_type0) * tx_ring->num_desc)
87
88 #define QLCNIC_P3P_A0 0x50
89
90 #define QLCNIC_IS_REVISION_P3P(REVISION) (REVISION >= QLCNIC_P3P_A0)
91
92 #define FIRST_PAGE_GROUP_START 0
93 #define FIRST_PAGE_GROUP_END 0x100000
94
95 #define P3_MAX_MTU (9600)
96 #define QLCNIC_MAX_ETHERHDR 32 /* This contains some padding */
97
98 #define QLCNIC_P3_RX_BUF_MAX_LEN (QLCNIC_MAX_ETHERHDR + ETH_DATA_LEN)
99 #define QLCNIC_P3_RX_JUMBO_BUF_MAX_LEN (QLCNIC_MAX_ETHERHDR + P3_MAX_MTU)
100 #define QLCNIC_CT_DEFAULT_RX_BUF_LEN 2048
101 #define QLCNIC_LRO_BUFFER_EXTRA 2048
102
103 /* Opcodes to be used with the commands */
104 #define TX_ETHER_PKT 0x01
105 #define TX_TCP_PKT 0x02
106 #define TX_UDP_PKT 0x03
107 #define TX_IP_PKT 0x04
108 #define TX_TCP_LSO 0x05
109 #define TX_TCP_LSO6 0x06
110 #define TX_IPSEC 0x07
111 #define TX_IPSEC_CMD 0x0a
112 #define TX_TCPV6_PKT 0x0b
113 #define TX_UDPV6_PKT 0x0c
114
115 /* Tx defines */
116 #define MAX_TSO_HEADER_DESC 2
117 #define MGMT_CMD_DESC_RESV 4
118 #define TX_STOP_THRESH ((MAX_SKB_FRAGS >> 2) + MAX_TSO_HEADER_DESC \
119 + MGMT_CMD_DESC_RESV)
120 #define QLCNIC_MAX_TX_TIMEOUTS 2
121
122 /*
123 * Following are the states of the Phantom. Phantom will set them and
124 * Host will read to check if the fields are correct.
125 */
126 #define PHAN_INITIALIZE_FAILED 0xffff
127 #define PHAN_INITIALIZE_COMPLETE 0xff01
128
129 /* Host writes the following to notify that it has done the init-handshake */
130 #define PHAN_INITIALIZE_ACK 0xf00f
131 #define PHAN_PEG_RCV_INITIALIZED 0xff01
132
133 #define NUM_RCV_DESC_RINGS 3
134 #define NUM_STS_DESC_RINGS 4
135
136 #define RCV_RING_NORMAL 0
137 #define RCV_RING_JUMBO 1
138
139 #define MIN_CMD_DESCRIPTORS 64
140 #define MIN_RCV_DESCRIPTORS 64
141 #define MIN_JUMBO_DESCRIPTORS 32
142
143 #define MAX_CMD_DESCRIPTORS 1024
144 #define MAX_RCV_DESCRIPTORS_1G 4096
145 #define MAX_RCV_DESCRIPTORS_10G 8192
146 #define MAX_JUMBO_RCV_DESCRIPTORS_1G 512
147 #define MAX_JUMBO_RCV_DESCRIPTORS_10G 1024
148
149 #define DEFAULT_RCV_DESCRIPTORS_1G 2048
150 #define DEFAULT_RCV_DESCRIPTORS_10G 4096
151
152 #define get_next_index(index, length) \
153 (((index) + 1) & ((length) - 1))
154
155 /*
156 * Following data structures describe the descriptors that will be used.
157 * Added fileds of tcpHdrSize and ipHdrSize, The driver needs to do it only when
158 * we are doing LSO (above the 1500 size packet) only.
159 */
160
161 #define FLAGS_VLAN_TAGGED 0x10
162 #define FLAGS_VLAN_OOB 0x40
163
164 #define qlcnic_set_tx_vlan_tci(cmd_desc, v) \
165 (cmd_desc)->vlan_TCI = cpu_to_le16(v);
166 #define qlcnic_set_cmd_desc_port(cmd_desc, var) \
167 ((cmd_desc)->port_ctxid |= ((var) & 0x0F))
168 #define qlcnic_set_cmd_desc_ctxid(cmd_desc, var) \
169 ((cmd_desc)->port_ctxid |= ((var) << 4 & 0xF0))
170
171 #define qlcnic_set_tx_port(_desc, _port) \
172 ((_desc)->port_ctxid = ((_port) & 0xf) | (((_port) << 4) & 0xf0))
173
174 #define qlcnic_set_tx_flags_opcode(_desc, _flags, _opcode) \
175 ((_desc)->flags_opcode = \
176 cpu_to_le16(((_flags) & 0x7f) | (((_opcode) & 0x3f) << 7)))
177
178 #define qlcnic_set_tx_frags_len(_desc, _frags, _len) \
179 ((_desc)->nfrags__length = \
180 cpu_to_le32(((_frags) & 0xff) | (((_len) & 0xffffff) << 8)))
181
182 struct cmd_desc_type0 {
183 u8 tcp_hdr_offset; /* For LSO only */
184 u8 ip_hdr_offset; /* For LSO only */
185 __le16 flags_opcode; /* 15:13 unused, 12:7 opcode, 6:0 flags */
186 __le32 nfrags__length; /* 31:8 total len, 7:0 frag count */
187
188 __le64 addr_buffer2;
189
190 __le16 reference_handle;
191 __le16 mss;
192 u8 port_ctxid; /* 7:4 ctxid 3:0 port */
193 u8 total_hdr_length; /* LSO only : MAC+IP+TCP Hdr size */
194 __le16 conn_id; /* IPSec offoad only */
195
196 __le64 addr_buffer3;
197 __le64 addr_buffer1;
198
199 __le16 buffer_length[4];
200
201 __le64 addr_buffer4;
202
203 u8 eth_addr[ETH_ALEN];
204 __le16 vlan_TCI;
205
206 } __attribute__ ((aligned(64)));
207
208 /* Note: sizeof(rcv_desc) should always be a mutliple of 2 */
209 struct rcv_desc {
210 __le16 reference_handle;
211 __le16 reserved;
212 __le32 buffer_length; /* allocated buffer length (usually 2K) */
213 __le64 addr_buffer;
214 };
215
216 /* opcode field in status_desc */
217 #define QLCNIC_SYN_OFFLOAD 0x03
218 #define QLCNIC_RXPKT_DESC 0x04
219 #define QLCNIC_OLD_RXPKT_DESC 0x3f
220 #define QLCNIC_RESPONSE_DESC 0x05
221 #define QLCNIC_LRO_DESC 0x12
222
223 /* for status field in status_desc */
224 #define STATUS_CKSUM_OK (2)
225
226 /* owner bits of status_desc */
227 #define STATUS_OWNER_HOST (0x1ULL << 56)
228 #define STATUS_OWNER_PHANTOM (0x2ULL << 56)
229
230 /* Status descriptor:
231 0-3 port, 4-7 status, 8-11 type, 12-27 total_length
232 28-43 reference_handle, 44-47 protocol, 48-52 pkt_offset
233 53-55 desc_cnt, 56-57 owner, 58-63 opcode
234 */
235 #define qlcnic_get_sts_port(sts_data) \
236 ((sts_data) & 0x0F)
237 #define qlcnic_get_sts_status(sts_data) \
238 (((sts_data) >> 4) & 0x0F)
239 #define qlcnic_get_sts_type(sts_data) \
240 (((sts_data) >> 8) & 0x0F)
241 #define qlcnic_get_sts_totallength(sts_data) \
242 (((sts_data) >> 12) & 0xFFFF)
243 #define qlcnic_get_sts_refhandle(sts_data) \
244 (((sts_data) >> 28) & 0xFFFF)
245 #define qlcnic_get_sts_prot(sts_data) \
246 (((sts_data) >> 44) & 0x0F)
247 #define qlcnic_get_sts_pkt_offset(sts_data) \
248 (((sts_data) >> 48) & 0x1F)
249 #define qlcnic_get_sts_desc_cnt(sts_data) \
250 (((sts_data) >> 53) & 0x7)
251 #define qlcnic_get_sts_opcode(sts_data) \
252 (((sts_data) >> 58) & 0x03F)
253
254 #define qlcnic_get_lro_sts_refhandle(sts_data) \
255 ((sts_data) & 0x0FFFF)
256 #define qlcnic_get_lro_sts_length(sts_data) \
257 (((sts_data) >> 16) & 0x0FFFF)
258 #define qlcnic_get_lro_sts_l2_hdr_offset(sts_data) \
259 (((sts_data) >> 32) & 0x0FF)
260 #define qlcnic_get_lro_sts_l4_hdr_offset(sts_data) \
261 (((sts_data) >> 40) & 0x0FF)
262 #define qlcnic_get_lro_sts_timestamp(sts_data) \
263 (((sts_data) >> 48) & 0x1)
264 #define qlcnic_get_lro_sts_type(sts_data) \
265 (((sts_data) >> 49) & 0x7)
266 #define qlcnic_get_lro_sts_push_flag(sts_data) \
267 (((sts_data) >> 52) & 0x1)
268 #define qlcnic_get_lro_sts_seq_number(sts_data) \
269 ((sts_data) & 0x0FFFFFFFF)
270
271
272 struct status_desc {
273 __le64 status_desc_data[2];
274 } __attribute__ ((aligned(16)));
275
276 /* UNIFIED ROMIMAGE */
277 #define QLCNIC_UNI_FW_MIN_SIZE 0xc8000
278 #define QLCNIC_UNI_DIR_SECT_PRODUCT_TBL 0x0
279 #define QLCNIC_UNI_DIR_SECT_BOOTLD 0x6
280 #define QLCNIC_UNI_DIR_SECT_FW 0x7
281
282 /*Offsets */
283 #define QLCNIC_UNI_CHIP_REV_OFF 10
284 #define QLCNIC_UNI_FLAGS_OFF 11
285 #define QLCNIC_UNI_BIOS_VERSION_OFF 12
286 #define QLCNIC_UNI_BOOTLD_IDX_OFF 27
287 #define QLCNIC_UNI_FIRMWARE_IDX_OFF 29
288
289 struct uni_table_desc{
290 u32 findex;
291 u32 num_entries;
292 u32 entry_size;
293 u32 reserved[5];
294 };
295
296 struct uni_data_desc{
297 u32 findex;
298 u32 size;
299 u32 reserved[5];
300 };
301
302 /* Magic number to let user know flash is programmed */
303 #define QLCNIC_BDINFO_MAGIC 0x12345678
304
305 #define QLCNIC_BRDTYPE_P3_REF_QG 0x0021
306 #define QLCNIC_BRDTYPE_P3_HMEZ 0x0022
307 #define QLCNIC_BRDTYPE_P3_10G_CX4_LP 0x0023
308 #define QLCNIC_BRDTYPE_P3_4_GB 0x0024
309 #define QLCNIC_BRDTYPE_P3_IMEZ 0x0025
310 #define QLCNIC_BRDTYPE_P3_10G_SFP_PLUS 0x0026
311 #define QLCNIC_BRDTYPE_P3_10000_BASE_T 0x0027
312 #define QLCNIC_BRDTYPE_P3_XG_LOM 0x0028
313 #define QLCNIC_BRDTYPE_P3_4_GB_MM 0x0029
314 #define QLCNIC_BRDTYPE_P3_10G_SFP_CT 0x002a
315 #define QLCNIC_BRDTYPE_P3_10G_SFP_QT 0x002b
316 #define QLCNIC_BRDTYPE_P3_10G_CX4 0x0031
317 #define QLCNIC_BRDTYPE_P3_10G_XFP 0x0032
318 #define QLCNIC_BRDTYPE_P3_10G_TP 0x0080
319
320 #define QLCNIC_MSIX_TABLE_OFFSET 0x44
321
322 /* Flash memory map */
323 #define QLCNIC_BRDCFG_START 0x4000 /* board config */
324 #define QLCNIC_BOOTLD_START 0x10000 /* bootld */
325 #define QLCNIC_IMAGE_START 0x43000 /* compressed image */
326 #define QLCNIC_USER_START 0x3E8000 /* Firmare info */
327
328 #define QLCNIC_FW_VERSION_OFFSET (QLCNIC_USER_START+0x408)
329 #define QLCNIC_FW_SIZE_OFFSET (QLCNIC_USER_START+0x40c)
330 #define QLCNIC_FW_SERIAL_NUM_OFFSET (QLCNIC_USER_START+0x81c)
331 #define QLCNIC_BIOS_VERSION_OFFSET (QLCNIC_USER_START+0x83c)
332
333 #define QLCNIC_BRDTYPE_OFFSET (QLCNIC_BRDCFG_START+0x8)
334 #define QLCNIC_FW_MAGIC_OFFSET (QLCNIC_BRDCFG_START+0x128)
335
336 #define QLCNIC_FW_MIN_SIZE (0x3fffff)
337 #define QLCNIC_UNIFIED_ROMIMAGE 0
338 #define QLCNIC_FLASH_ROMIMAGE 1
339 #define QLCNIC_UNKNOWN_ROMIMAGE 0xff
340
341 #define QLCNIC_UNIFIED_ROMIMAGE_NAME "phanfw.bin"
342 #define QLCNIC_FLASH_ROMIMAGE_NAME "flash"
343
344 extern char qlcnic_driver_name[];
345
346 /* Number of status descriptors to handle per interrupt */
347 #define MAX_STATUS_HANDLE (64)
348
349 /*
350 * qlcnic_skb_frag{} is to contain mapping info for each SG list. This
351 * has to be freed when DMA is complete. This is part of qlcnic_tx_buffer{}.
352 */
353 struct qlcnic_skb_frag {
354 u64 dma;
355 u64 length;
356 };
357
358 struct qlcnic_recv_crb {
359 u32 crb_rcv_producer[NUM_RCV_DESC_RINGS];
360 u32 crb_sts_consumer[NUM_STS_DESC_RINGS];
361 u32 sw_int_mask[NUM_STS_DESC_RINGS];
362 };
363
364 /* Following defines are for the state of the buffers */
365 #define QLCNIC_BUFFER_FREE 0
366 #define QLCNIC_BUFFER_BUSY 1
367
368 /*
369 * There will be one qlcnic_buffer per skb packet. These will be
370 * used to save the dma info for pci_unmap_page()
371 */
372 struct qlcnic_cmd_buffer {
373 struct sk_buff *skb;
374 struct qlcnic_skb_frag frag_array[MAX_SKB_FRAGS + 1];
375 u32 frag_count;
376 };
377
378 /* In rx_buffer, we do not need multiple fragments as is a single buffer */
379 struct qlcnic_rx_buffer {
380 struct list_head list;
381 struct sk_buff *skb;
382 u64 dma;
383 u16 ref_handle;
384 };
385
386 /* Board types */
387 #define QLCNIC_GBE 0x01
388 #define QLCNIC_XGBE 0x02
389
390 /*
391 * One hardware_context{} per adapter
392 * contains interrupt info as well shared hardware info.
393 */
394 struct qlcnic_hardware_context {
395 void __iomem *pci_base0;
396 void __iomem *ocm_win_crb;
397
398 unsigned long pci_len0;
399
400 rwlock_t crb_lock;
401 struct mutex mem_lock;
402
403 u8 revision_id;
404 u8 pci_func;
405 u8 linkup;
406 u16 port_type;
407 u16 board_type;
408 };
409
410 struct qlcnic_adapter_stats {
411 u64 xmitcalled;
412 u64 xmitfinished;
413 u64 rxdropped;
414 u64 txdropped;
415 u64 csummed;
416 u64 rx_pkts;
417 u64 lro_pkts;
418 u64 rxbytes;
419 u64 txbytes;
420 u64 lrobytes;
421 u64 lso_frames;
422 u64 xmit_on;
423 u64 xmit_off;
424 u64 skb_alloc_failure;
425 u64 null_rxbuf;
426 u64 rx_dma_map_error;
427 u64 tx_dma_map_error;
428 };
429
430 /*
431 * Rcv Descriptor Context. One such per Rcv Descriptor. There may
432 * be one Rcv Descriptor for normal packets, one for jumbo and may be others.
433 */
434 struct qlcnic_host_rds_ring {
435 u32 producer;
436 u32 num_desc;
437 u32 dma_size;
438 u32 skb_size;
439 u32 flags;
440 void __iomem *crb_rcv_producer;
441 struct rcv_desc *desc_head;
442 struct qlcnic_rx_buffer *rx_buf_arr;
443 struct list_head free_list;
444 spinlock_t lock;
445 dma_addr_t phys_addr;
446 };
447
448 struct qlcnic_host_sds_ring {
449 u32 consumer;
450 u32 num_desc;
451 void __iomem *crb_sts_consumer;
452 void __iomem *crb_intr_mask;
453
454 struct status_desc *desc_head;
455 struct qlcnic_adapter *adapter;
456 struct napi_struct napi;
457 struct list_head free_list[NUM_RCV_DESC_RINGS];
458
459 int irq;
460
461 dma_addr_t phys_addr;
462 char name[IFNAMSIZ+4];
463 };
464
465 struct qlcnic_host_tx_ring {
466 u32 producer;
467 __le32 *hw_consumer;
468 u32 sw_consumer;
469 void __iomem *crb_cmd_producer;
470 u32 num_desc;
471
472 struct netdev_queue *txq;
473
474 struct qlcnic_cmd_buffer *cmd_buf_arr;
475 struct cmd_desc_type0 *desc_head;
476 dma_addr_t phys_addr;
477 dma_addr_t hw_cons_phys_addr;
478 };
479
480 /*
481 * Receive context. There is one such structure per instance of the
482 * receive processing. Any state information that is relevant to
483 * the receive, and is must be in this structure. The global data may be
484 * present elsewhere.
485 */
486 struct qlcnic_recv_context {
487 u32 state;
488 u16 context_id;
489 u16 virt_port;
490
491 struct qlcnic_host_rds_ring *rds_rings;
492 struct qlcnic_host_sds_ring *sds_rings;
493 };
494
495 /* HW context creation */
496
497 #define QLCNIC_OS_CRB_RETRY_COUNT 4000
498 #define QLCNIC_CDRP_SIGNATURE_MAKE(pcifn, version) \
499 (((pcifn) & 0xff) | (((version) & 0xff) << 8) | (0xcafe << 16))
500
501 #define QLCNIC_CDRP_CMD_BIT 0x80000000
502
503 /*
504 * All responses must have the QLCNIC_CDRP_CMD_BIT cleared
505 * in the crb QLCNIC_CDRP_CRB_OFFSET.
506 */
507 #define QLCNIC_CDRP_FORM_RSP(rsp) (rsp)
508 #define QLCNIC_CDRP_IS_RSP(rsp) (((rsp) & QLCNIC_CDRP_CMD_BIT) == 0)
509
510 #define QLCNIC_CDRP_RSP_OK 0x00000001
511 #define QLCNIC_CDRP_RSP_FAIL 0x00000002
512 #define QLCNIC_CDRP_RSP_TIMEOUT 0x00000003
513
514 /*
515 * All commands must have the QLCNIC_CDRP_CMD_BIT set in
516 * the crb QLCNIC_CDRP_CRB_OFFSET.
517 */
518 #define QLCNIC_CDRP_FORM_CMD(cmd) (QLCNIC_CDRP_CMD_BIT | (cmd))
519 #define QLCNIC_CDRP_IS_CMD(cmd) (((cmd) & QLCNIC_CDRP_CMD_BIT) != 0)
520
521 #define QLCNIC_CDRP_CMD_SUBMIT_CAPABILITIES 0x00000001
522 #define QLCNIC_CDRP_CMD_READ_MAX_RDS_PER_CTX 0x00000002
523 #define QLCNIC_CDRP_CMD_READ_MAX_SDS_PER_CTX 0x00000003
524 #define QLCNIC_CDRP_CMD_READ_MAX_RULES_PER_CTX 0x00000004
525 #define QLCNIC_CDRP_CMD_READ_MAX_RX_CTX 0x00000005
526 #define QLCNIC_CDRP_CMD_READ_MAX_TX_CTX 0x00000006
527 #define QLCNIC_CDRP_CMD_CREATE_RX_CTX 0x00000007
528 #define QLCNIC_CDRP_CMD_DESTROY_RX_CTX 0x00000008
529 #define QLCNIC_CDRP_CMD_CREATE_TX_CTX 0x00000009
530 #define QLCNIC_CDRP_CMD_DESTROY_TX_CTX 0x0000000a
531 #define QLCNIC_CDRP_CMD_SETUP_STATISTICS 0x0000000e
532 #define QLCNIC_CDRP_CMD_GET_STATISTICS 0x0000000f
533 #define QLCNIC_CDRP_CMD_DELETE_STATISTICS 0x00000010
534 #define QLCNIC_CDRP_CMD_SET_MTU 0x00000012
535 #define QLCNIC_CDRP_CMD_READ_PHY 0x00000013
536 #define QLCNIC_CDRP_CMD_WRITE_PHY 0x00000014
537 #define QLCNIC_CDRP_CMD_READ_HW_REG 0x00000015
538 #define QLCNIC_CDRP_CMD_GET_FLOW_CTL 0x00000016
539 #define QLCNIC_CDRP_CMD_SET_FLOW_CTL 0x00000017
540 #define QLCNIC_CDRP_CMD_READ_MAX_MTU 0x00000018
541 #define QLCNIC_CDRP_CMD_READ_MAX_LRO 0x00000019
542 #define QLCNIC_CDRP_CMD_CONFIGURE_TOE 0x0000001a
543 #define QLCNIC_CDRP_CMD_FUNC_ATTRIB 0x0000001b
544 #define QLCNIC_CDRP_CMD_READ_PEXQ_PARAMETERS 0x0000001c
545 #define QLCNIC_CDRP_CMD_GET_LIC_CAPABILITIES 0x0000001d
546 #define QLCNIC_CDRP_CMD_READ_MAX_LRO_PER_BOARD 0x0000001e
547 #define QLCNIC_CDRP_CMD_MAC_ADDRESS 0x0000001f
548
549 #define QLCNIC_CDRP_CMD_GET_PCI_INFO 0x00000020
550 #define QLCNIC_CDRP_CMD_GET_NIC_INFO 0x00000021
551 #define QLCNIC_CDRP_CMD_SET_NIC_INFO 0x00000022
552 #define QLCNIC_CDRP_CMD_RESET_NPAR 0x00000023
553 #define QLCNIC_CDRP_CMD_GET_ESWITCH_CAPABILITY 0x00000024
554 #define QLCNIC_CDRP_CMD_TOGGLE_ESWITCH 0x00000025
555 #define QLCNIC_CDRP_CMD_GET_ESWITCH_STATUS 0x00000026
556 #define QLCNIC_CDRP_CMD_SET_PORTMIRRORING 0x00000027
557 #define QLCNIC_CDRP_CMD_CONFIGURE_ESWITCH 0x00000028
558
559 #define QLCNIC_RCODE_SUCCESS 0
560 #define QLCNIC_RCODE_TIMEOUT 17
561 #define QLCNIC_DESTROY_CTX_RESET 0
562
563 /*
564 * Capabilities Announced
565 */
566 #define QLCNIC_CAP0_LEGACY_CONTEXT (1)
567 #define QLCNIC_CAP0_LEGACY_MN (1 << 2)
568 #define QLCNIC_CAP0_LSO (1 << 6)
569 #define QLCNIC_CAP0_JUMBO_CONTIGUOUS (1 << 7)
570 #define QLCNIC_CAP0_LRO_CONTIGUOUS (1 << 8)
571 #define QLCNIC_CAP0_VALIDOFF (1 << 11)
572
573 /*
574 * Context state
575 */
576 #define QLCNIC_HOST_CTX_STATE_FREED 0
577 #define QLCNIC_HOST_CTX_STATE_ACTIVE 2
578
579 /*
580 * Rx context
581 */
582
583 struct qlcnic_hostrq_sds_ring {
584 __le64 host_phys_addr; /* Ring base addr */
585 __le32 ring_size; /* Ring entries */
586 __le16 msi_index;
587 __le16 rsvd; /* Padding */
588 };
589
590 struct qlcnic_hostrq_rds_ring {
591 __le64 host_phys_addr; /* Ring base addr */
592 __le64 buff_size; /* Packet buffer size */
593 __le32 ring_size; /* Ring entries */
594 __le32 ring_kind; /* Class of ring */
595 };
596
597 struct qlcnic_hostrq_rx_ctx {
598 __le64 host_rsp_dma_addr; /* Response dma'd here */
599 __le32 capabilities[4]; /* Flag bit vector */
600 __le32 host_int_crb_mode; /* Interrupt crb usage */
601 __le32 host_rds_crb_mode; /* RDS crb usage */
602 /* These ring offsets are relative to data[0] below */
603 __le32 rds_ring_offset; /* Offset to RDS config */
604 __le32 sds_ring_offset; /* Offset to SDS config */
605 __le16 num_rds_rings; /* Count of RDS rings */
606 __le16 num_sds_rings; /* Count of SDS rings */
607 __le16 valid_field_offset;
608 u8 txrx_sds_binding;
609 u8 msix_handler;
610 u8 reserved[128]; /* reserve space for future expansion*/
611 /* MUST BE 64-bit aligned.
612 The following is packed:
613 - N hostrq_rds_rings
614 - N hostrq_sds_rings */
615 char data[0];
616 };
617
618 struct qlcnic_cardrsp_rds_ring{
619 __le32 host_producer_crb; /* Crb to use */
620 __le32 rsvd1; /* Padding */
621 };
622
623 struct qlcnic_cardrsp_sds_ring {
624 __le32 host_consumer_crb; /* Crb to use */
625 __le32 interrupt_crb; /* Crb to use */
626 };
627
628 struct qlcnic_cardrsp_rx_ctx {
629 /* These ring offsets are relative to data[0] below */
630 __le32 rds_ring_offset; /* Offset to RDS config */
631 __le32 sds_ring_offset; /* Offset to SDS config */
632 __le32 host_ctx_state; /* Starting State */
633 __le32 num_fn_per_port; /* How many PCI fn share the port */
634 __le16 num_rds_rings; /* Count of RDS rings */
635 __le16 num_sds_rings; /* Count of SDS rings */
636 __le16 context_id; /* Handle for context */
637 u8 phys_port; /* Physical id of port */
638 u8 virt_port; /* Virtual/Logical id of port */
639 u8 reserved[128]; /* save space for future expansion */
640 /* MUST BE 64-bit aligned.
641 The following is packed:
642 - N cardrsp_rds_rings
643 - N cardrs_sds_rings */
644 char data[0];
645 };
646
647 #define SIZEOF_HOSTRQ_RX(HOSTRQ_RX, rds_rings, sds_rings) \
648 (sizeof(HOSTRQ_RX) + \
649 (rds_rings)*(sizeof(struct qlcnic_hostrq_rds_ring)) + \
650 (sds_rings)*(sizeof(struct qlcnic_hostrq_sds_ring)))
651
652 #define SIZEOF_CARDRSP_RX(CARDRSP_RX, rds_rings, sds_rings) \
653 (sizeof(CARDRSP_RX) + \
654 (rds_rings)*(sizeof(struct qlcnic_cardrsp_rds_ring)) + \
655 (sds_rings)*(sizeof(struct qlcnic_cardrsp_sds_ring)))
656
657 /*
658 * Tx context
659 */
660
661 struct qlcnic_hostrq_cds_ring {
662 __le64 host_phys_addr; /* Ring base addr */
663 __le32 ring_size; /* Ring entries */
664 __le32 rsvd; /* Padding */
665 };
666
667 struct qlcnic_hostrq_tx_ctx {
668 __le64 host_rsp_dma_addr; /* Response dma'd here */
669 __le64 cmd_cons_dma_addr; /* */
670 __le64 dummy_dma_addr; /* */
671 __le32 capabilities[4]; /* Flag bit vector */
672 __le32 host_int_crb_mode; /* Interrupt crb usage */
673 __le32 rsvd1; /* Padding */
674 __le16 rsvd2; /* Padding */
675 __le16 interrupt_ctl;
676 __le16 msi_index;
677 __le16 rsvd3; /* Padding */
678 struct qlcnic_hostrq_cds_ring cds_ring; /* Desc of cds ring */
679 u8 reserved[128]; /* future expansion */
680 };
681
682 struct qlcnic_cardrsp_cds_ring {
683 __le32 host_producer_crb; /* Crb to use */
684 __le32 interrupt_crb; /* Crb to use */
685 };
686
687 struct qlcnic_cardrsp_tx_ctx {
688 __le32 host_ctx_state; /* Starting state */
689 __le16 context_id; /* Handle for context */
690 u8 phys_port; /* Physical id of port */
691 u8 virt_port; /* Virtual/Logical id of port */
692 struct qlcnic_cardrsp_cds_ring cds_ring; /* Card cds settings */
693 u8 reserved[128]; /* future expansion */
694 };
695
696 #define SIZEOF_HOSTRQ_TX(HOSTRQ_TX) (sizeof(HOSTRQ_TX))
697 #define SIZEOF_CARDRSP_TX(CARDRSP_TX) (sizeof(CARDRSP_TX))
698
699 /* CRB */
700
701 #define QLCNIC_HOST_RDS_CRB_MODE_UNIQUE 0
702 #define QLCNIC_HOST_RDS_CRB_MODE_SHARED 1
703 #define QLCNIC_HOST_RDS_CRB_MODE_CUSTOM 2
704 #define QLCNIC_HOST_RDS_CRB_MODE_MAX 3
705
706 #define QLCNIC_HOST_INT_CRB_MODE_UNIQUE 0
707 #define QLCNIC_HOST_INT_CRB_MODE_SHARED 1
708 #define QLCNIC_HOST_INT_CRB_MODE_NORX 2
709 #define QLCNIC_HOST_INT_CRB_MODE_NOTX 3
710 #define QLCNIC_HOST_INT_CRB_MODE_NORXTX 4
711
712
713 /* MAC */
714
715 #define MC_COUNT_P3 38
716
717 #define QLCNIC_MAC_NOOP 0
718 #define QLCNIC_MAC_ADD 1
719 #define QLCNIC_MAC_DEL 2
720
721 struct qlcnic_mac_list_s {
722 struct list_head list;
723 uint8_t mac_addr[ETH_ALEN+2];
724 };
725
726 /*
727 * Interrupt coalescing defaults. The defaults are for 1500 MTU. It is
728 * adjusted based on configured MTU.
729 */
730 #define QLCNIC_DEFAULT_INTR_COALESCE_RX_TIME_US 3
731 #define QLCNIC_DEFAULT_INTR_COALESCE_RX_PACKETS 256
732 #define QLCNIC_DEFAULT_INTR_COALESCE_TX_PACKETS 64
733 #define QLCNIC_DEFAULT_INTR_COALESCE_TX_TIME_US 4
734
735 #define QLCNIC_INTR_DEFAULT 0x04
736
737 union qlcnic_nic_intr_coalesce_data {
738 struct {
739 u16 rx_packets;
740 u16 rx_time_us;
741 u16 tx_packets;
742 u16 tx_time_us;
743 } data;
744 u64 word;
745 };
746
747 struct qlcnic_nic_intr_coalesce {
748 u16 stats_time_us;
749 u16 rate_sample_time;
750 u16 flags;
751 u16 rsvd_1;
752 u32 low_threshold;
753 u32 high_threshold;
754 union qlcnic_nic_intr_coalesce_data normal;
755 union qlcnic_nic_intr_coalesce_data low;
756 union qlcnic_nic_intr_coalesce_data high;
757 union qlcnic_nic_intr_coalesce_data irq;
758 };
759
760 #define QLCNIC_HOST_REQUEST 0x13
761 #define QLCNIC_REQUEST 0x14
762
763 #define QLCNIC_MAC_EVENT 0x1
764
765 #define QLCNIC_IP_UP 2
766 #define QLCNIC_IP_DOWN 3
767
768 /*
769 * Driver --> Firmware
770 */
771 #define QLCNIC_H2C_OPCODE_START 0
772 #define QLCNIC_H2C_OPCODE_CONFIG_RSS 1
773 #define QLCNIC_H2C_OPCODE_CONFIG_RSS_TBL 2
774 #define QLCNIC_H2C_OPCODE_CONFIG_INTR_COALESCE 3
775 #define QLCNIC_H2C_OPCODE_CONFIG_LED 4
776 #define QLCNIC_H2C_OPCODE_CONFIG_PROMISCUOUS 5
777 #define QLCNIC_H2C_OPCODE_CONFIG_L2_MAC 6
778 #define QLCNIC_H2C_OPCODE_LRO_REQUEST 7
779 #define QLCNIC_H2C_OPCODE_GET_SNMP_STATS 8
780 #define QLCNIC_H2C_OPCODE_PROXY_START_REQUEST 9
781 #define QLCNIC_H2C_OPCODE_PROXY_STOP_REQUEST 10
782 #define QLCNIC_H2C_OPCODE_PROXY_SET_MTU 11
783 #define QLCNIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE 12
784 #define QLCNIC_H2C_OPCODE_GET_FINGER_PRINT_REQUEST 13
785 #define QLCNIC_H2C_OPCODE_INSTALL_LICENSE_REQUEST 14
786 #define QLCNIC_H2C_OPCODE_GET_LICENSE_CAPABILITY_REQUEST 15
787 #define QLCNIC_H2C_OPCODE_GET_NET_STATS 16
788 #define QLCNIC_H2C_OPCODE_PROXY_UPDATE_P2V 17
789 #define QLCNIC_H2C_OPCODE_CONFIG_IPADDR 18
790 #define QLCNIC_H2C_OPCODE_CONFIG_LOOPBACK 19
791 #define QLCNIC_H2C_OPCODE_PROXY_STOP_DONE 20
792 #define QLCNIC_H2C_OPCODE_GET_LINKEVENT 21
793 #define QLCNIC_C2C_OPCODE 22
794 #define QLCNIC_H2C_OPCODE_CONFIG_BRIDGING 23
795 #define QLCNIC_H2C_OPCODE_CONFIG_HW_LRO 24
796 #define QLCNIC_H2C_OPCODE_LAST 25
797 /*
798 * Firmware --> Driver
799 */
800
801 #define QLCNIC_C2H_OPCODE_START 128
802 #define QLCNIC_C2H_OPCODE_CONFIG_RSS_RESPONSE 129
803 #define QLCNIC_C2H_OPCODE_CONFIG_RSS_TBL_RESPONSE 130
804 #define QLCNIC_C2H_OPCODE_CONFIG_MAC_RESPONSE 131
805 #define QLCNIC_C2H_OPCODE_CONFIG_PROMISCUOUS_RESPONSE 132
806 #define QLCNIC_C2H_OPCODE_CONFIG_L2_MAC_RESPONSE 133
807 #define QLCNIC_C2H_OPCODE_LRO_DELETE_RESPONSE 134
808 #define QLCNIC_C2H_OPCODE_LRO_ADD_FAILURE_RESPONSE 135
809 #define QLCNIC_C2H_OPCODE_GET_SNMP_STATS 136
810 #define QLCNIC_C2H_OPCODE_GET_FINGER_PRINT_REPLY 137
811 #define QLCNIC_C2H_OPCODE_INSTALL_LICENSE_REPLY 138
812 #define QLCNIC_C2H_OPCODE_GET_LICENSE_CAPABILITIES_REPLY 139
813 #define QLCNIC_C2H_OPCODE_GET_NET_STATS_RESPONSE 140
814 #define QLCNIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE 141
815 #define QLCNIC_C2H_OPCODE_LAST 142
816
817 #define VPORT_MISS_MODE_DROP 0 /* drop all unmatched */
818 #define VPORT_MISS_MODE_ACCEPT_ALL 1 /* accept all packets */
819 #define VPORT_MISS_MODE_ACCEPT_MULTI 2 /* accept unmatched multicast */
820
821 #define QLCNIC_LRO_REQUEST_CLEANUP 4
822
823 /* Capabilites received */
824 #define QLCNIC_FW_CAPABILITY_TSO BIT_1
825 #define QLCNIC_FW_CAPABILITY_BDG BIT_8
826 #define QLCNIC_FW_CAPABILITY_FVLANTX BIT_9
827 #define QLCNIC_FW_CAPABILITY_HW_LRO BIT_10
828
829 /* module types */
830 #define LINKEVENT_MODULE_NOT_PRESENT 1
831 #define LINKEVENT_MODULE_OPTICAL_UNKNOWN 2
832 #define LINKEVENT_MODULE_OPTICAL_SRLR 3
833 #define LINKEVENT_MODULE_OPTICAL_LRM 4
834 #define LINKEVENT_MODULE_OPTICAL_SFP_1G 5
835 #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE 6
836 #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN 7
837 #define LINKEVENT_MODULE_TWINAX 8
838
839 #define LINKSPEED_10GBPS 10000
840 #define LINKSPEED_1GBPS 1000
841 #define LINKSPEED_100MBPS 100
842 #define LINKSPEED_10MBPS 10
843
844 #define LINKSPEED_ENCODED_10MBPS 0
845 #define LINKSPEED_ENCODED_100MBPS 1
846 #define LINKSPEED_ENCODED_1GBPS 2
847
848 #define LINKEVENT_AUTONEG_DISABLED 0
849 #define LINKEVENT_AUTONEG_ENABLED 1
850
851 #define LINKEVENT_HALF_DUPLEX 0
852 #define LINKEVENT_FULL_DUPLEX 1
853
854 #define LINKEVENT_LINKSPEED_MBPS 0
855 #define LINKEVENT_LINKSPEED_ENCODED 1
856
857 #define AUTO_FW_RESET_ENABLED 0x01
858 /* firmware response header:
859 * 63:58 - message type
860 * 57:56 - owner
861 * 55:53 - desc count
862 * 52:48 - reserved
863 * 47:40 - completion id
864 * 39:32 - opcode
865 * 31:16 - error code
866 * 15:00 - reserved
867 */
868 #define qlcnic_get_nic_msg_opcode(msg_hdr) \
869 ((msg_hdr >> 32) & 0xFF)
870
871 struct qlcnic_fw_msg {
872 union {
873 struct {
874 u64 hdr;
875 u64 body[7];
876 };
877 u64 words[8];
878 };
879 };
880
881 struct qlcnic_nic_req {
882 __le64 qhdr;
883 __le64 req_hdr;
884 __le64 words[6];
885 };
886
887 struct qlcnic_mac_req {
888 u8 op;
889 u8 tag;
890 u8 mac_addr[6];
891 };
892
893 #define QLCNIC_MSI_ENABLED 0x02
894 #define QLCNIC_MSIX_ENABLED 0x04
895 #define QLCNIC_LRO_ENABLED 0x08
896 #define QLCNIC_BRIDGE_ENABLED 0X10
897 #define QLCNIC_DIAG_ENABLED 0x20
898 #define QLCNIC_ESWITCH_ENABLED 0x40
899 #define QLCNIC_IS_MSI_FAMILY(adapter) \
900 ((adapter)->flags & (QLCNIC_MSI_ENABLED | QLCNIC_MSIX_ENABLED))
901
902 #define MSIX_ENTRIES_PER_ADAPTER NUM_STS_DESC_RINGS
903 #define QLCNIC_MSIX_TBL_SPACE 8192
904 #define QLCNIC_PCI_REG_MSIX_TBL 0x44
905 #define QLCNIC_MSIX_TBL_PGSIZE 4096
906
907 #define QLCNIC_NETDEV_WEIGHT 128
908 #define QLCNIC_ADAPTER_UP_MAGIC 777
909
910 #define __QLCNIC_FW_ATTACHED 0
911 #define __QLCNIC_DEV_UP 1
912 #define __QLCNIC_RESETTING 2
913 #define __QLCNIC_START_FW 4
914 #define __QLCNIC_AER 5
915
916 #define QLCNIC_INTERRUPT_TEST 1
917 #define QLCNIC_LOOPBACK_TEST 2
918
919 struct qlcnic_adapter {
920 struct qlcnic_hardware_context ahw;
921
922 struct net_device *netdev;
923 struct pci_dev *pdev;
924 struct list_head mac_list;
925
926 spinlock_t tx_clean_lock;
927
928 u16 num_txd;
929 u16 num_rxd;
930 u16 num_jumbo_rxd;
931
932 u8 max_rds_rings;
933 u8 max_sds_rings;
934 u8 driver_mismatch;
935 u8 msix_supported;
936 u8 rx_csum;
937 u8 portnum;
938 u8 physical_port;
939 u8 reset_context;
940
941 u8 mc_enabled;
942 u8 max_mc_count;
943 u8 rss_supported;
944 u8 fw_wait_cnt;
945 u8 fw_fail_cnt;
946 u8 tx_timeo_cnt;
947 u8 need_fw_reset;
948
949 u8 has_link_events;
950 u8 fw_type;
951 u16 tx_context_id;
952 u16 is_up;
953
954 u16 link_speed;
955 u16 link_duplex;
956 u16 link_autoneg;
957 u16 module_type;
958
959 u16 op_mode;
960 u16 switch_mode;
961 u16 max_tx_ques;
962 u16 max_rx_ques;
963 u16 max_mtu;
964
965 u32 fw_hal_version;
966 u32 capabilities;
967 u32 flags;
968 u32 irq;
969 u32 temp;
970
971 u32 int_vec_bit;
972 u32 heartbit;
973
974 u8 max_mac_filters;
975 u8 dev_state;
976 u8 diag_test;
977 u8 diag_cnt;
978 u8 reset_ack_timeo;
979 u8 dev_init_timeo;
980 u16 msg_enable;
981
982 u8 mac_addr[ETH_ALEN];
983
984 u64 dev_rst_time;
985
986 struct qlcnic_npar_info *npars;
987 struct qlcnic_eswitch *eswitch;
988 struct qlcnic_nic_template *nic_ops;
989
990 struct qlcnic_adapter_stats stats;
991
992 struct qlcnic_recv_context recv_ctx;
993 struct qlcnic_host_tx_ring *tx_ring;
994
995 void __iomem *tgt_mask_reg;
996 void __iomem *tgt_status_reg;
997 void __iomem *crb_int_state_reg;
998 void __iomem *isr_int_vec;
999
1000 struct msix_entry msix_entries[MSIX_ENTRIES_PER_ADAPTER];
1001
1002 struct delayed_work fw_work;
1003
1004 struct qlcnic_nic_intr_coalesce coal;
1005
1006 unsigned long state;
1007 __le32 file_prd_off; /*File fw product offset*/
1008 u32 fw_version;
1009 const struct firmware *fw;
1010 };
1011
1012 struct qlcnic_info {
1013 __le16 pci_func;
1014 __le16 op_mode; /* 1 = Priv, 2 = NP, 3 = NP passthru */
1015 __le16 phys_port;
1016 __le16 switch_mode; /* 0 = disabled, 1 = int, 2 = ext */
1017
1018 __le32 capabilities;
1019 u8 max_mac_filters;
1020 u8 reserved1;
1021 __le16 max_mtu;
1022
1023 __le16 max_tx_ques;
1024 __le16 max_rx_ques;
1025 __le16 min_tx_bw;
1026 __le16 max_tx_bw;
1027 u8 reserved2[104];
1028 };
1029
1030 struct qlcnic_pci_info {
1031 __le16 id; /* pci function id */
1032 __le16 active; /* 1 = Enabled */
1033 __le16 type; /* 1 = NIC, 2 = FCoE, 3 = iSCSI */
1034 __le16 default_port; /* default port number */
1035
1036 __le16 tx_min_bw; /* Multiple of 100mbpc */
1037 __le16 tx_max_bw;
1038 __le16 reserved1[2];
1039
1040 u8 mac[ETH_ALEN];
1041 u8 reserved2[106];
1042 };
1043
1044 struct qlcnic_npar_info {
1045 u16 vlan_id;
1046 u16 min_bw;
1047 u16 max_bw;
1048 u8 phy_port;
1049 u8 type;
1050 u8 active;
1051 u8 enable_pm;
1052 u8 dest_npar;
1053 u8 host_vlan_tag;
1054 u8 promisc_mode;
1055 u8 discard_tagged;
1056 u8 mac_learning;
1057 };
1058 struct qlcnic_eswitch {
1059 u8 port;
1060 u8 active_vports;
1061 u8 active_vlans;
1062 u8 active_ucast_filters;
1063 u8 max_ucast_filters;
1064 u8 max_active_vlans;
1065
1066 u32 flags;
1067 #define QLCNIC_SWITCH_ENABLE BIT_1
1068 #define QLCNIC_SWITCH_VLAN_FILTERING BIT_2
1069 #define QLCNIC_SWITCH_PROMISC_MODE BIT_3
1070 #define QLCNIC_SWITCH_PORT_MIRRORING BIT_4
1071 };
1072
1073
1074 /* Return codes for Error handling */
1075 #define QL_STATUS_INVALID_PARAM -1
1076
1077 #define MAX_BW 100
1078 #define MIN_BW 1
1079 #define MAX_VLAN_ID 4095
1080 #define MIN_VLAN_ID 2
1081 #define MAX_TX_QUEUES 1
1082 #define MAX_RX_QUEUES 4
1083 #define DEFAULT_MAC_LEARN 1
1084
1085 #define IS_VALID_VLAN(vlan) (vlan >= MIN_VLAN_ID && vlan <= MAX_VLAN_ID)
1086 #define IS_VALID_BW(bw) (bw >= MIN_BW && bw <= MAX_BW)
1087 #define IS_VALID_TX_QUEUES(que) (que > 0 && que <= MAX_TX_QUEUES)
1088 #define IS_VALID_RX_QUEUES(que) (que > 0 && que <= MAX_RX_QUEUES)
1089 #define IS_VALID_MODE(mode) (mode == 0 || mode == 1)
1090
1091 struct qlcnic_pci_func_cfg {
1092 u16 func_type;
1093 u16 min_bw;
1094 u16 max_bw;
1095 u16 port_num;
1096 u8 pci_func;
1097 u8 func_state;
1098 u8 def_mac_addr[6];
1099 };
1100
1101 struct qlcnic_npar_func_cfg {
1102 u32 fw_capab;
1103 u16 port_num;
1104 u16 min_bw;
1105 u16 max_bw;
1106 u16 max_tx_queues;
1107 u16 max_rx_queues;
1108 u8 pci_func;
1109 u8 op_mode;
1110 };
1111
1112 struct qlcnic_pm_func_cfg {
1113 u8 pci_func;
1114 u8 action;
1115 u8 dest_npar;
1116 u8 reserved[5];
1117 };
1118
1119 struct qlcnic_esw_func_cfg {
1120 u16 vlan_id;
1121 u8 pci_func;
1122 u8 host_vlan_tag;
1123 u8 promisc_mode;
1124 u8 discard_tagged;
1125 u8 mac_learning;
1126 u8 reserved;
1127 };
1128
1129 int qlcnic_fw_cmd_query_phy(struct qlcnic_adapter *adapter, u32 reg, u32 *val);
1130 int qlcnic_fw_cmd_set_phy(struct qlcnic_adapter *adapter, u32 reg, u32 val);
1131
1132 u32 qlcnic_hw_read_wx_2M(struct qlcnic_adapter *adapter, ulong off);
1133 int qlcnic_hw_write_wx_2M(struct qlcnic_adapter *, ulong off, u32 data);
1134 int qlcnic_pci_mem_write_2M(struct qlcnic_adapter *, u64 off, u64 data);
1135 int qlcnic_pci_mem_read_2M(struct qlcnic_adapter *, u64 off, u64 *data);
1136 void qlcnic_pci_camqm_read_2M(struct qlcnic_adapter *, u64, u64 *);
1137 void qlcnic_pci_camqm_write_2M(struct qlcnic_adapter *, u64, u64);
1138
1139 #define ADDR_IN_RANGE(addr, low, high) \
1140 (((addr) < (high)) && ((addr) >= (low)))
1141
1142 #define QLCRD32(adapter, off) \
1143 (qlcnic_hw_read_wx_2M(adapter, off))
1144 #define QLCWR32(adapter, off, val) \
1145 (qlcnic_hw_write_wx_2M(adapter, off, val))
1146
1147 int qlcnic_pcie_sem_lock(struct qlcnic_adapter *, int, u32);
1148 void qlcnic_pcie_sem_unlock(struct qlcnic_adapter *, int);
1149
1150 #define qlcnic_rom_lock(a) \
1151 qlcnic_pcie_sem_lock((a), 2, QLCNIC_ROM_LOCK_ID)
1152 #define qlcnic_rom_unlock(a) \
1153 qlcnic_pcie_sem_unlock((a), 2)
1154 #define qlcnic_phy_lock(a) \
1155 qlcnic_pcie_sem_lock((a), 3, QLCNIC_PHY_LOCK_ID)
1156 #define qlcnic_phy_unlock(a) \
1157 qlcnic_pcie_sem_unlock((a), 3)
1158 #define qlcnic_api_lock(a) \
1159 qlcnic_pcie_sem_lock((a), 5, 0)
1160 #define qlcnic_api_unlock(a) \
1161 qlcnic_pcie_sem_unlock((a), 5)
1162 #define qlcnic_sw_lock(a) \
1163 qlcnic_pcie_sem_lock((a), 6, 0)
1164 #define qlcnic_sw_unlock(a) \
1165 qlcnic_pcie_sem_unlock((a), 6)
1166 #define crb_win_lock(a) \
1167 qlcnic_pcie_sem_lock((a), 7, QLCNIC_CRB_WIN_LOCK_ID)
1168 #define crb_win_unlock(a) \
1169 qlcnic_pcie_sem_unlock((a), 7)
1170
1171 int qlcnic_get_board_info(struct qlcnic_adapter *adapter);
1172 int qlcnic_wol_supported(struct qlcnic_adapter *adapter);
1173 int qlcnic_config_led(struct qlcnic_adapter *adapter, u32 state, u32 rate);
1174
1175 /* Functions from qlcnic_init.c */
1176 int qlcnic_load_firmware(struct qlcnic_adapter *adapter);
1177 int qlcnic_need_fw_reset(struct qlcnic_adapter *adapter);
1178 void qlcnic_request_firmware(struct qlcnic_adapter *adapter);
1179 void qlcnic_release_firmware(struct qlcnic_adapter *adapter);
1180 int qlcnic_pinit_from_rom(struct qlcnic_adapter *adapter);
1181 int qlcnic_setup_idc_param(struct qlcnic_adapter *adapter);
1182 int qlcnic_check_flash_fw_ver(struct qlcnic_adapter *adapter);
1183
1184 int qlcnic_rom_fast_read(struct qlcnic_adapter *adapter, int addr, int *valp);
1185 int qlcnic_rom_fast_read_words(struct qlcnic_adapter *adapter, int addr,
1186 u8 *bytes, size_t size);
1187 int qlcnic_alloc_sw_resources(struct qlcnic_adapter *adapter);
1188 void qlcnic_free_sw_resources(struct qlcnic_adapter *adapter);
1189
1190 void __iomem *qlcnic_get_ioaddr(struct qlcnic_adapter *, u32);
1191
1192 int qlcnic_alloc_hw_resources(struct qlcnic_adapter *adapter);
1193 void qlcnic_free_hw_resources(struct qlcnic_adapter *adapter);
1194
1195 int qlcnic_fw_create_ctx(struct qlcnic_adapter *adapter);
1196 void qlcnic_fw_destroy_ctx(struct qlcnic_adapter *adapter);
1197
1198 void qlcnic_reset_rx_buffers_list(struct qlcnic_adapter *adapter);
1199 void qlcnic_release_rx_buffers(struct qlcnic_adapter *adapter);
1200 void qlcnic_release_tx_buffers(struct qlcnic_adapter *adapter);
1201
1202 int qlcnic_init_firmware(struct qlcnic_adapter *adapter);
1203 void qlcnic_watchdog_task(struct work_struct *work);
1204 void qlcnic_post_rx_buffers(struct qlcnic_adapter *adapter, u32 ringid,
1205 struct qlcnic_host_rds_ring *rds_ring);
1206 int qlcnic_process_rcv_ring(struct qlcnic_host_sds_ring *sds_ring, int max);
1207 void qlcnic_set_multi(struct net_device *netdev);
1208 void qlcnic_free_mac_list(struct qlcnic_adapter *adapter);
1209 int qlcnic_nic_set_promisc(struct qlcnic_adapter *adapter, u32);
1210 int qlcnic_config_intr_coalesce(struct qlcnic_adapter *adapter);
1211 int qlcnic_config_rss(struct qlcnic_adapter *adapter, int enable);
1212 int qlcnic_config_ipaddr(struct qlcnic_adapter *adapter, u32 ip, int cmd);
1213 int qlcnic_linkevent_request(struct qlcnic_adapter *adapter, int enable);
1214 void qlcnic_advert_link_change(struct qlcnic_adapter *adapter, int linkup);
1215
1216 int qlcnic_fw_cmd_set_mtu(struct qlcnic_adapter *adapter, int mtu);
1217 int qlcnic_change_mtu(struct net_device *netdev, int new_mtu);
1218 int qlcnic_config_hw_lro(struct qlcnic_adapter *adapter, int enable);
1219 int qlcnic_config_bridged_mode(struct qlcnic_adapter *adapter, u32 enable);
1220 int qlcnic_send_lro_cleanup(struct qlcnic_adapter *adapter);
1221 void qlcnic_update_cmd_producer(struct qlcnic_adapter *adapter,
1222 struct qlcnic_host_tx_ring *tx_ring);
1223 int qlcnic_get_mac_addr(struct qlcnic_adapter *adapter, u8 *mac);
1224 void qlcnic_clear_ilb_mode(struct qlcnic_adapter *adapter);
1225 int qlcnic_set_ilb_mode(struct qlcnic_adapter *adapter);
1226 void qlcnic_fetch_mac(struct qlcnic_adapter *, u32, u32, u8, u8 *);
1227
1228 /* Functions from qlcnic_main.c */
1229 int qlcnic_reset_context(struct qlcnic_adapter *);
1230 u32 qlcnic_issue_cmd(struct qlcnic_adapter *adapter,
1231 u32 pci_fn, u32 version, u32 arg1, u32 arg2, u32 arg3, u32 cmd);
1232 void qlcnic_diag_free_res(struct net_device *netdev, int max_sds_rings);
1233 int qlcnic_diag_alloc_res(struct net_device *netdev, int test);
1234 int qlcnic_check_loopback_buff(unsigned char *data);
1235 netdev_tx_t qlcnic_xmit_frame(struct sk_buff *skb, struct net_device *netdev);
1236 void qlcnic_process_rcv_ring_diag(struct qlcnic_host_sds_ring *sds_ring);
1237
1238 /* Management functions */
1239 int qlcnic_set_mac_address(struct qlcnic_adapter *, u8*);
1240 int qlcnic_get_mac_address(struct qlcnic_adapter *, u8*);
1241 int qlcnic_get_nic_info(struct qlcnic_adapter *, struct qlcnic_info *, u8);
1242 int qlcnic_set_nic_info(struct qlcnic_adapter *, struct qlcnic_info *);
1243 int qlcnic_get_pci_info(struct qlcnic_adapter *, struct qlcnic_pci_info*);
1244 int qlcnic_reset_partition(struct qlcnic_adapter *, u8);
1245
1246 /* eSwitch management functions */
1247 int qlcnic_get_eswitch_capabilities(struct qlcnic_adapter *, u8,
1248 struct qlcnic_eswitch *);
1249 int qlcnic_get_eswitch_status(struct qlcnic_adapter *, u8,
1250 struct qlcnic_eswitch *);
1251 int qlcnic_toggle_eswitch(struct qlcnic_adapter *, u8, u8);
1252 int qlcnic_config_switch_port(struct qlcnic_adapter *, u8, int, u8, u8,
1253 u8, u8, u16);
1254 int qlcnic_config_port_mirroring(struct qlcnic_adapter *, u8, u8, u8);
1255 extern int qlcnic_config_tso;
1256
1257 /*
1258 * QLOGIC Board information
1259 */
1260
1261 #define QLCNIC_MAX_BOARD_NAME_LEN 100
1262 struct qlcnic_brdinfo {
1263 unsigned short vendor;
1264 unsigned short device;
1265 unsigned short sub_vendor;
1266 unsigned short sub_device;
1267 char short_name[QLCNIC_MAX_BOARD_NAME_LEN];
1268 };
1269
1270 static const struct qlcnic_brdinfo qlcnic_boards[] = {
1271 {0x1077, 0x8020, 0x1077, 0x203,
1272 "8200 Series Single Port 10GbE Converged Network Adapter "
1273 "(TCP/IP Networking)"},
1274 {0x1077, 0x8020, 0x1077, 0x207,
1275 "8200 Series Dual Port 10GbE Converged Network Adapter "
1276 "(TCP/IP Networking)"},
1277 {0x1077, 0x8020, 0x1077, 0x20b,
1278 "3200 Series Dual Port 10Gb Intelligent Ethernet Adapter"},
1279 {0x1077, 0x8020, 0x1077, 0x20c,
1280 "3200 Series Quad Port 1Gb Intelligent Ethernet Adapter"},
1281 {0x1077, 0x8020, 0x1077, 0x20f,
1282 "3200 Series Single Port 10Gb Intelligent Ethernet Adapter"},
1283 {0x1077, 0x8020, 0x0, 0x0, "cLOM8214 1/10GbE Controller"},
1284 };
1285
1286 #define NUM_SUPPORTED_BOARDS ARRAY_SIZE(qlcnic_boards)
1287
1288 static inline u32 qlcnic_tx_avail(struct qlcnic_host_tx_ring *tx_ring)
1289 {
1290 smp_mb();
1291 if (tx_ring->producer < tx_ring->sw_consumer)
1292 return tx_ring->sw_consumer - tx_ring->producer;
1293 else
1294 return tx_ring->sw_consumer + tx_ring->num_desc -
1295 tx_ring->producer;
1296 }
1297
1298 extern const struct ethtool_ops qlcnic_ethtool_ops;
1299
1300 struct qlcnic_nic_template {
1301 int (*get_mac_addr) (struct qlcnic_adapter *, u8*);
1302 int (*config_bridged_mode) (struct qlcnic_adapter *, u32);
1303 int (*config_led) (struct qlcnic_adapter *, u32, u32);
1304 int (*start_firmware) (struct qlcnic_adapter *);
1305 };
1306
1307 #define QLCDB(adapter, lvl, _fmt, _args...) do { \
1308 if (NETIF_MSG_##lvl & adapter->msg_enable) \
1309 printk(KERN_INFO "%s: %s: " _fmt, \
1310 dev_name(&adapter->pdev->dev), \
1311 __func__, ##_args); \
1312 } while (0)
1313
1314 #endif /* __QLCNIC_H_ */
Tomato firmware and modifications.