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GUI: Fix Tomato RAF theme for all builds. Compilation typo.
[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / drivers / net / ixgbe / ixgbe_main.c
blob06a0e576838372151a05a791143428c2a5326916
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2010 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #include <linux/types.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/vmalloc.h>
33 #include <linux/string.h>
34 #include <linux/in.h>
35 #include <linux/ip.h>
36 #include <linux/tcp.h>
37 #include <linux/pkt_sched.h>
38 #include <linux/ipv6.h>
39 #include <linux/slab.h>
40 #include <net/checksum.h>
41 #include <net/ip6_checksum.h>
42 #include <linux/ethtool.h>
43 #include <linux/if_vlan.h>
44 #include <scsi/fc/fc_fcoe.h>
45
46 #include "ixgbe.h"
47 #include "ixgbe_common.h"
48 #include "ixgbe_dcb_82599.h"
49 #include "ixgbe_sriov.h"
50
51 char ixgbe_driver_name[] = "ixgbe";
52 static const char ixgbe_driver_string[] =
53 "Intel(R) 10 Gigabit PCI Express Network Driver";
54
55 #define DRV_VERSION "2.0.84-k2"
56 const char ixgbe_driver_version[] = DRV_VERSION;
57 static char ixgbe_copyright[] = "Copyright (c) 1999-2010 Intel Corporation.";
58
59 static const struct ixgbe_info *ixgbe_info_tbl[] = {
60 [board_82598] = &ixgbe_82598_info,
61 [board_82599] = &ixgbe_82599_info,
62 };
63
64 /* ixgbe_pci_tbl - PCI Device ID Table
65 *
66 * Wildcard entries (PCI_ANY_ID) should come last
67 * Last entry must be all 0s
68 *
69 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
70 * Class, Class Mask, private data (not used) }
71 */
72 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
73 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
74 board_82598 },
75 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
76 board_82598 },
77 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
78 board_82598 },
79 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
80 board_82598 },
81 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
82 board_82598 },
83 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
84 board_82598 },
85 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
86 board_82598 },
87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
88 board_82598 },
89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
90 board_82598 },
91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
92 board_82598 },
93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
94 board_82598 },
95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
96 board_82598 },
97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
98 board_82599 },
99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
100 board_82599 },
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
102 board_82599 },
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
104 board_82599 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
106 board_82599 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
108 board_82599 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
110 board_82599 },
111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM),
112 board_82599 },
113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
114 board_82599 },
115
116 /* required last entry */
117 {0, }
118 };
119 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
120
121 #ifdef CONFIG_IXGBE_DCA
122 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
123 void *p);
124 static struct notifier_block dca_notifier = {
125 .notifier_call = ixgbe_notify_dca,
126 .next = NULL,
127 .priority = 0
128 };
129 #endif
130
131 #ifdef CONFIG_PCI_IOV
132 static unsigned int max_vfs;
133 module_param(max_vfs, uint, 0);
134 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
135 "per physical function");
136 #endif /* CONFIG_PCI_IOV */
137
138 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
139 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
140 MODULE_LICENSE("GPL");
141 MODULE_VERSION(DRV_VERSION);
142
143 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
144
145 static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
146 {
147 struct ixgbe_hw *hw = &adapter->hw;
148 u32 gcr;
149 u32 gpie;
150 u32 vmdctl;
151
152 #ifdef CONFIG_PCI_IOV
153 /* disable iov and allow time for transactions to clear */
154 pci_disable_sriov(adapter->pdev);
155 #endif
156
157 /* turn off device IOV mode */
158 gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
159 gcr &= ~(IXGBE_GCR_EXT_SRIOV);
160 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
161 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
162 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
163 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
164
165 /* set default pool back to 0 */
166 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
167 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
168 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
169
170 /* take a breather then clean up driver data */
171 msleep(100);
172 if (adapter->vfinfo)
173 kfree(adapter->vfinfo);
174 adapter->vfinfo = NULL;
175
176 adapter->num_vfs = 0;
177 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
178 }
179
180 struct ixgbe_reg_info {
181 u32 ofs;
182 char *name;
183 };
184
185 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
186
187 /* General Registers */
188 {IXGBE_CTRL, "CTRL"},
189 {IXGBE_STATUS, "STATUS"},
190 {IXGBE_CTRL_EXT, "CTRL_EXT"},
191
192 /* Interrupt Registers */
193 {IXGBE_EICR, "EICR"},
194
195 /* RX Registers */
196 {IXGBE_SRRCTL(0), "SRRCTL"},
197 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
198 {IXGBE_RDLEN(0), "RDLEN"},
199 {IXGBE_RDH(0), "RDH"},
200 {IXGBE_RDT(0), "RDT"},
201 {IXGBE_RXDCTL(0), "RXDCTL"},
202 {IXGBE_RDBAL(0), "RDBAL"},
203 {IXGBE_RDBAH(0), "RDBAH"},
204
205 /* TX Registers */
206 {IXGBE_TDBAL(0), "TDBAL"},
207 {IXGBE_TDBAH(0), "TDBAH"},
208 {IXGBE_TDLEN(0), "TDLEN"},
209 {IXGBE_TDH(0), "TDH"},
210 {IXGBE_TDT(0), "TDT"},
211 {IXGBE_TXDCTL(0), "TXDCTL"},
212
213 /* List Terminator */
214 {}
215 };
216
217
218 /*
219 * ixgbe_regdump - register printout routine
220 */
221 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
222 {
223 int i = 0, j = 0;
224 char rname[16];
225 u32 regs[64];
226
227 switch (reginfo->ofs) {
228 case IXGBE_SRRCTL(0):
229 for (i = 0; i < 64; i++)
230 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
231 break;
232 case IXGBE_DCA_RXCTRL(0):
233 for (i = 0; i < 64; i++)
234 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
235 break;
236 case IXGBE_RDLEN(0):
237 for (i = 0; i < 64; i++)
238 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
239 break;
240 case IXGBE_RDH(0):
241 for (i = 0; i < 64; i++)
242 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
243 break;
244 case IXGBE_RDT(0):
245 for (i = 0; i < 64; i++)
246 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
247 break;
248 case IXGBE_RXDCTL(0):
249 for (i = 0; i < 64; i++)
250 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
251 break;
252 case IXGBE_RDBAL(0):
253 for (i = 0; i < 64; i++)
254 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
255 break;
256 case IXGBE_RDBAH(0):
257 for (i = 0; i < 64; i++)
258 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
259 break;
260 case IXGBE_TDBAL(0):
261 for (i = 0; i < 64; i++)
262 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
263 break;
264 case IXGBE_TDBAH(0):
265 for (i = 0; i < 64; i++)
266 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
267 break;
268 case IXGBE_TDLEN(0):
269 for (i = 0; i < 64; i++)
270 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
271 break;
272 case IXGBE_TDH(0):
273 for (i = 0; i < 64; i++)
274 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
275 break;
276 case IXGBE_TDT(0):
277 for (i = 0; i < 64; i++)
278 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
279 break;
280 case IXGBE_TXDCTL(0):
281 for (i = 0; i < 64; i++)
282 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
283 break;
284 default:
285 printk(KERN_INFO "%-15s %08x\n", reginfo->name,
286 IXGBE_READ_REG(hw, reginfo->ofs));
287 return;
288 }
289
290 for (i = 0; i < 8; i++) {
291 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
292 printk(KERN_ERR "%-15s ", rname);
293 for (j = 0; j < 8; j++)
294 printk(KERN_CONT "%08x ", regs[i*8+j]);
295 printk(KERN_CONT "\n");
296 }
297
298 }
299
300 /*
301 * ixgbe_dump - Print registers, tx-rings and rx-rings
302 */
303 static void ixgbe_dump(struct ixgbe_adapter *adapter)
304 {
305 struct net_device *netdev = adapter->netdev;
306 struct ixgbe_hw *hw = &adapter->hw;
307 struct ixgbe_reg_info *reginfo;
308 int n = 0;
309 struct ixgbe_ring *tx_ring;
310 struct ixgbe_tx_buffer *tx_buffer_info;
311 union ixgbe_adv_tx_desc *tx_desc;
312 struct my_u0 { u64 a; u64 b; } *u0;
313 struct ixgbe_ring *rx_ring;
314 union ixgbe_adv_rx_desc *rx_desc;
315 struct ixgbe_rx_buffer *rx_buffer_info;
316 u32 staterr;
317 int i = 0;
318
319 if (!netif_msg_hw(adapter))
320 return;
321
322 /* Print netdevice Info */
323 if (netdev) {
324 dev_info(&adapter->pdev->dev, "Net device Info\n");
325 printk(KERN_INFO "Device Name state "
326 "trans_start last_rx\n");
327 printk(KERN_INFO "%-15s %016lX %016lX %016lX\n",
328 netdev->name,
329 netdev->state,
330 netdev->trans_start,
331 netdev->last_rx);
332 }
333
334 /* Print Registers */
335 dev_info(&adapter->pdev->dev, "Register Dump\n");
336 printk(KERN_INFO " Register Name Value\n");
337 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
338 reginfo->name; reginfo++) {
339 ixgbe_regdump(hw, reginfo);
340 }
341
342 /* Print TX Ring Summary */
343 if (!netdev || !netif_running(netdev))
344 goto exit;
345
346 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
347 printk(KERN_INFO "Queue [NTU] [NTC] [bi(ntc)->dma ] "
348 "leng ntw timestamp\n");
349 for (n = 0; n < adapter->num_tx_queues; n++) {
350 tx_ring = adapter->tx_ring[n];
351 tx_buffer_info =
352 &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
353 printk(KERN_INFO " %5d %5X %5X %016llX %04X %3X %016llX\n",
354 n, tx_ring->next_to_use, tx_ring->next_to_clean,
355 (u64)tx_buffer_info->dma,
356 tx_buffer_info->length,
357 tx_buffer_info->next_to_watch,
358 (u64)tx_buffer_info->time_stamp);
359 }
360
361 /* Print TX Rings */
362 if (!netif_msg_tx_done(adapter))
363 goto rx_ring_summary;
364
365 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
366
367 /* Transmit Descriptor Formats
368 *
369 * Advanced Transmit Descriptor
370 * +--------------------------------------------------------------+
371 * 0 | Buffer Address [63:0] |
372 * +--------------------------------------------------------------+
373 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
374 * +--------------------------------------------------------------+
375 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
376 */
377
378 for (n = 0; n < adapter->num_tx_queues; n++) {
379 tx_ring = adapter->tx_ring[n];
380 printk(KERN_INFO "------------------------------------\n");
381 printk(KERN_INFO "TX QUEUE INDEX = %d\n", tx_ring->queue_index);
382 printk(KERN_INFO "------------------------------------\n");
383 printk(KERN_INFO "T [desc] [address 63:0 ] "
384 "[PlPOIdStDDt Ln] [bi->dma ] "
385 "leng ntw timestamp bi->skb\n");
386
387 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
388 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
389 tx_buffer_info = &tx_ring->tx_buffer_info[i];
390 u0 = (struct my_u0 *)tx_desc;
391 printk(KERN_INFO "T [0x%03X] %016llX %016llX %016llX"
392 " %04X %3X %016llX %p", i,
393 le64_to_cpu(u0->a),
394 le64_to_cpu(u0->b),
395 (u64)tx_buffer_info->dma,
396 tx_buffer_info->length,
397 tx_buffer_info->next_to_watch,
398 (u64)tx_buffer_info->time_stamp,
399 tx_buffer_info->skb);
400 if (i == tx_ring->next_to_use &&
401 i == tx_ring->next_to_clean)
402 printk(KERN_CONT " NTC/U\n");
403 else if (i == tx_ring->next_to_use)
404 printk(KERN_CONT " NTU\n");
405 else if (i == tx_ring->next_to_clean)
406 printk(KERN_CONT " NTC\n");
407 else
408 printk(KERN_CONT "\n");
409
410 if (netif_msg_pktdata(adapter) &&
411 tx_buffer_info->dma != 0)
412 print_hex_dump(KERN_INFO, "",
413 DUMP_PREFIX_ADDRESS, 16, 1,
414 phys_to_virt(tx_buffer_info->dma),
415 tx_buffer_info->length, true);
416 }
417 }
418
419 /* Print RX Rings Summary */
420 rx_ring_summary:
421 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
422 printk(KERN_INFO "Queue [NTU] [NTC]\n");
423 for (n = 0; n < adapter->num_rx_queues; n++) {
424 rx_ring = adapter->rx_ring[n];
425 printk(KERN_INFO "%5d %5X %5X\n", n,
426 rx_ring->next_to_use, rx_ring->next_to_clean);
427 }
428
429 /* Print RX Rings */
430 if (!netif_msg_rx_status(adapter))
431 goto exit;
432
433 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
434
435 /* Advanced Receive Descriptor (Read) Format
436 * 63 1 0
437 * +-----------------------------------------------------+
438 * 0 | Packet Buffer Address [63:1] |A0/NSE|
439 * +----------------------------------------------+------+
440 * 8 | Header Buffer Address [63:1] | DD |
441 * +-----------------------------------------------------+
442 *
443 *
444 * Advanced Receive Descriptor (Write-Back) Format
445 *
446 * 63 48 47 32 31 30 21 20 16 15 4 3 0
447 * +------------------------------------------------------+
448 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
449 * | Checksum Ident | | | | Type | Type |
450 * +------------------------------------------------------+
451 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
452 * +------------------------------------------------------+
453 * 63 48 47 32 31 20 19 0
454 */
455 for (n = 0; n < adapter->num_rx_queues; n++) {
456 rx_ring = adapter->rx_ring[n];
457 printk(KERN_INFO "------------------------------------\n");
458 printk(KERN_INFO "RX QUEUE INDEX = %d\n", rx_ring->queue_index);
459 printk(KERN_INFO "------------------------------------\n");
460 printk(KERN_INFO "R [desc] [ PktBuf A0] "
461 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
462 "<-- Adv Rx Read format\n");
463 printk(KERN_INFO "RWB[desc] [PcsmIpSHl PtRs] "
464 "[vl er S cks ln] ---------------- [bi->skb] "
465 "<-- Adv Rx Write-Back format\n");
466
467 for (i = 0; i < rx_ring->count; i++) {
468 rx_buffer_info = &rx_ring->rx_buffer_info[i];
469 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
470 u0 = (struct my_u0 *)rx_desc;
471 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
472 if (staterr & IXGBE_RXD_STAT_DD) {
473 /* Descriptor Done */
474 printk(KERN_INFO "RWB[0x%03X] %016llX "
475 "%016llX ---------------- %p", i,
476 le64_to_cpu(u0->a),
477 le64_to_cpu(u0->b),
478 rx_buffer_info->skb);
479 } else {
480 printk(KERN_INFO "R [0x%03X] %016llX "
481 "%016llX %016llX %p", i,
482 le64_to_cpu(u0->a),
483 le64_to_cpu(u0->b),
484 (u64)rx_buffer_info->dma,
485 rx_buffer_info->skb);
486
487 if (netif_msg_pktdata(adapter)) {
488 print_hex_dump(KERN_INFO, "",
489 DUMP_PREFIX_ADDRESS, 16, 1,
490 phys_to_virt(rx_buffer_info->dma),
491 rx_ring->rx_buf_len, true);
492
493 if (rx_ring->rx_buf_len
494 < IXGBE_RXBUFFER_2048)
495 print_hex_dump(KERN_INFO, "",
496 DUMP_PREFIX_ADDRESS, 16, 1,
497 phys_to_virt(
498 rx_buffer_info->page_dma +
499 rx_buffer_info->page_offset
500 ),
501 PAGE_SIZE/2, true);
502 }
503 }
504
505 if (i == rx_ring->next_to_use)
506 printk(KERN_CONT " NTU\n");
507 else if (i == rx_ring->next_to_clean)
508 printk(KERN_CONT " NTC\n");
509 else
510 printk(KERN_CONT "\n");
511
512 }
513 }
514
515 exit:
516 return;
517 }
518
519 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
520 {
521 u32 ctrl_ext;
522
523 /* Let firmware take over control of h/w */
524 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
525 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
526 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
527 }
528
529 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
530 {
531 u32 ctrl_ext;
532
533 /* Let firmware know the driver has taken over */
534 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
535 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
536 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
537 }
538
539 /*
540 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
541 * @adapter: pointer to adapter struct
542 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
543 * @queue: queue to map the corresponding interrupt to
544 * @msix_vector: the vector to map to the corresponding queue
545 *
546 */
547 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
548 u8 queue, u8 msix_vector)
549 {
550 u32 ivar, index;
551 struct ixgbe_hw *hw = &adapter->hw;
552 switch (hw->mac.type) {
553 case ixgbe_mac_82598EB:
554 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
555 if (direction == -1)
556 direction = 0;
557 index = (((direction * 64) + queue) >> 2) & 0x1F;
558 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
559 ivar &= ~(0xFF << (8 * (queue & 0x3)));
560 ivar |= (msix_vector << (8 * (queue & 0x3)));
561 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
562 break;
563 case ixgbe_mac_82599EB:
564 if (direction == -1) {
565 /* other causes */
566 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
567 index = ((queue & 1) * 8);
568 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
569 ivar &= ~(0xFF << index);
570 ivar |= (msix_vector << index);
571 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
572 break;
573 } else {
574 /* tx or rx causes */
575 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
576 index = ((16 * (queue & 1)) + (8 * direction));
577 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
578 ivar &= ~(0xFF << index);
579 ivar |= (msix_vector << index);
580 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
581 break;
582 }
583 default:
584 break;
585 }
586 }
587
588 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
589 u64 qmask)
590 {
591 u32 mask;
592
593 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
594 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
595 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
596 } else {
597 mask = (qmask & 0xFFFFFFFF);
598 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
599 mask = (qmask >> 32);
600 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
601 }
602 }
603
604 static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
605 struct ixgbe_tx_buffer
606 *tx_buffer_info)
607 {
608 if (tx_buffer_info->dma) {
609 if (tx_buffer_info->mapped_as_page)
610 dma_unmap_page(&adapter->pdev->dev,
611 tx_buffer_info->dma,
612 tx_buffer_info->length,
613 DMA_TO_DEVICE);
614 else
615 dma_unmap_single(&adapter->pdev->dev,
616 tx_buffer_info->dma,
617 tx_buffer_info->length,
618 DMA_TO_DEVICE);
619 tx_buffer_info->dma = 0;
620 }
621 if (tx_buffer_info->skb) {
622 dev_kfree_skb_any(tx_buffer_info->skb);
623 tx_buffer_info->skb = NULL;
624 }
625 tx_buffer_info->time_stamp = 0;
626 /* tx_buffer_info must be completely set up in the transmit path */
627 }
628
629 /**
630 * ixgbe_tx_xon_state - check the tx ring xon state
631 * @adapter: the ixgbe adapter
632 * @tx_ring: the corresponding tx_ring
633 *
634 * If not in DCB mode, checks TFCS.TXOFF, otherwise, find out the
635 * corresponding TC of this tx_ring when checking TFCS.
636 *
637 * Returns : true if in xon state (currently not paused)
638 */
639 static inline bool ixgbe_tx_xon_state(struct ixgbe_adapter *adapter,
640 struct ixgbe_ring *tx_ring)
641 {
642 u32 txoff = IXGBE_TFCS_TXOFF;
643
644 #ifdef CONFIG_IXGBE_DCB
645 if (adapter->dcb_cfg.pfc_mode_enable) {
646 int tc;
647 int reg_idx = tx_ring->reg_idx;
648 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
649
650 switch (adapter->hw.mac.type) {
651 case ixgbe_mac_82598EB:
652 tc = reg_idx >> 2;
653 txoff = IXGBE_TFCS_TXOFF0;
654 break;
655 case ixgbe_mac_82599EB:
656 tc = 0;
657 txoff = IXGBE_TFCS_TXOFF;
658 if (dcb_i == 8) {
659 /* TC0, TC1 */
660 tc = reg_idx >> 5;
661 if (tc == 2) /* TC2, TC3 */
662 tc += (reg_idx - 64) >> 4;
663 else if (tc == 3) /* TC4, TC5, TC6, TC7 */
664 tc += 1 + ((reg_idx - 96) >> 3);
665 } else if (dcb_i == 4) {
666 /* TC0, TC1 */
667 tc = reg_idx >> 6;
668 if (tc == 1) {
669 tc += (reg_idx - 64) >> 5;
670 if (tc == 2) /* TC2, TC3 */
671 tc += (reg_idx - 96) >> 4;
672 }
673 }
674 break;
675 default:
676 tc = 0;
677 }
678 txoff <<= tc;
679 }
680 #endif
681 return IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & txoff;
682 }
683
684 static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
685 struct ixgbe_ring *tx_ring,
686 unsigned int eop)
687 {
688 struct ixgbe_hw *hw = &adapter->hw;
689
690 /* Detect a transmit hang in hardware, this serializes the
691 * check with the clearing of time_stamp and movement of eop */
692 adapter->detect_tx_hung = false;
693 if (tx_ring->tx_buffer_info[eop].time_stamp &&
694 time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
695 ixgbe_tx_xon_state(adapter, tx_ring)) {
696 /* detected Tx unit hang */
697 union ixgbe_adv_tx_desc *tx_desc;
698 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
699 e_err(drv, "Detected Tx Unit Hang\n"
700 " Tx Queue <%d>\n"
701 " TDH, TDT <%x>, <%x>\n"
702 " next_to_use <%x>\n"
703 " next_to_clean <%x>\n"
704 "tx_buffer_info[next_to_clean]\n"
705 " time_stamp <%lx>\n"
706 " jiffies <%lx>\n",
707 tx_ring->queue_index,
708 IXGBE_READ_REG(hw, tx_ring->head),
709 IXGBE_READ_REG(hw, tx_ring->tail),
710 tx_ring->next_to_use, eop,
711 tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
712 return true;
713 }
714
715 return false;
716 }
717
718 #define IXGBE_MAX_TXD_PWR 14
719 #define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
720
721 /* Tx Descriptors needed, worst case */
722 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
723 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
724 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
725 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
726
727 static void ixgbe_tx_timeout(struct net_device *netdev);
728
729 /**
730 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
731 * @q_vector: structure containing interrupt and ring information
732 * @tx_ring: tx ring to clean
733 **/
734 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
735 struct ixgbe_ring *tx_ring)
736 {
737 struct ixgbe_adapter *adapter = q_vector->adapter;
738 struct net_device *netdev = adapter->netdev;
739 union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
740 struct ixgbe_tx_buffer *tx_buffer_info;
741 unsigned int i, eop, count = 0;
742 unsigned int total_bytes = 0, total_packets = 0;
743
744 i = tx_ring->next_to_clean;
745 eop = tx_ring->tx_buffer_info[i].next_to_watch;
746 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
747
748 while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
749 (count < tx_ring->work_limit)) {
750 bool cleaned = false;
751 rmb(); /* read buffer_info after eop_desc */
752 for ( ; !cleaned; count++) {
753 struct sk_buff *skb;
754 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
755 tx_buffer_info = &tx_ring->tx_buffer_info[i];
756 cleaned = (i == eop);
757 skb = tx_buffer_info->skb;
758
759 if (cleaned && skb) {
760 unsigned int segs, bytecount;
761 unsigned int hlen = skb_headlen(skb);
762
763 /* gso_segs is currently only valid for tcp */
764 segs = skb_shinfo(skb)->gso_segs ?: 1;
765 #ifdef IXGBE_FCOE
766 /* adjust for FCoE Sequence Offload */
767 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
768 && (skb->protocol == htons(ETH_P_FCOE)) &&
769 skb_is_gso(skb)) {
770 hlen = skb_transport_offset(skb) +
771 sizeof(struct fc_frame_header) +
772 sizeof(struct fcoe_crc_eof);
773 segs = DIV_ROUND_UP(skb->len - hlen,
774 skb_shinfo(skb)->gso_size);
775 }
776 #endif /* IXGBE_FCOE */
777 /* multiply data chunks by size of headers */
778 bytecount = ((segs - 1) * hlen) + skb->len;
779 total_packets += segs;
780 total_bytes += bytecount;
781 }
782
783 ixgbe_unmap_and_free_tx_resource(adapter,
784 tx_buffer_info);
785
786 tx_desc->wb.status = 0;
787
788 i++;
789 if (i == tx_ring->count)
790 i = 0;
791 }
792
793 eop = tx_ring->tx_buffer_info[i].next_to_watch;
794 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
795 }
796
797 tx_ring->next_to_clean = i;
798
799 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
800 if (unlikely(count && netif_carrier_ok(netdev) &&
801 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
802 /* Make sure that anybody stopping the queue after this
803 * sees the new next_to_clean.
804 */
805 smp_mb();
806 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
807 !test_bit(__IXGBE_DOWN, &adapter->state)) {
808 netif_wake_subqueue(netdev, tx_ring->queue_index);
809 ++tx_ring->restart_queue;
810 }
811 }
812
813 if (adapter->detect_tx_hung) {
814 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
815 /* schedule immediate reset if we believe we hung */
816 e_info(probe, "tx hang %d detected, resetting "
817 "adapter\n", adapter->tx_timeout_count + 1);
818 ixgbe_tx_timeout(adapter->netdev);
819 }
820 }
821
822 /* re-arm the interrupt */
823 if (count >= tx_ring->work_limit)
824 ixgbe_irq_rearm_queues(adapter, ((u64)1 << q_vector->v_idx));
825
826 tx_ring->total_bytes += total_bytes;
827 tx_ring->total_packets += total_packets;
828 tx_ring->stats.packets += total_packets;
829 tx_ring->stats.bytes += total_bytes;
830 return (count < tx_ring->work_limit);
831 }
832
833 #ifdef CONFIG_IXGBE_DCA
834 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
835 struct ixgbe_ring *rx_ring)
836 {
837 u32 rxctrl;
838 int cpu = get_cpu();
839 int q = rx_ring->reg_idx;
840
841 if (rx_ring->cpu != cpu) {
842 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
843 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
844 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
845 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
846 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
847 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
848 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
849 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
850 }
851 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
852 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
853 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
854 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
855 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
856 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
857 rx_ring->cpu = cpu;
858 }
859 put_cpu();
860 }
861
862 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
863 struct ixgbe_ring *tx_ring)
864 {
865 u32 txctrl;
866 int cpu = get_cpu();
867 int q = tx_ring->reg_idx;
868 struct ixgbe_hw *hw = &adapter->hw;
869
870 if (tx_ring->cpu != cpu) {
871 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
872 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(q));
873 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
874 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
875 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
876 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(q), txctrl);
877 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
878 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(q));
879 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
880 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
881 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
882 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
883 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(q), txctrl);
884 }
885 tx_ring->cpu = cpu;
886 }
887 put_cpu();
888 }
889
890 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
891 {
892 int i;
893
894 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
895 return;
896
897 /* always use CB2 mode, difference is masked in the CB driver */
898 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
899
900 for (i = 0; i < adapter->num_tx_queues; i++) {
901 adapter->tx_ring[i]->cpu = -1;
902 ixgbe_update_tx_dca(adapter, adapter->tx_ring[i]);
903 }
904 for (i = 0; i < adapter->num_rx_queues; i++) {
905 adapter->rx_ring[i]->cpu = -1;
906 ixgbe_update_rx_dca(adapter, adapter->rx_ring[i]);
907 }
908 }
909
910 static int __ixgbe_notify_dca(struct device *dev, void *data)
911 {
912 struct net_device *netdev = dev_get_drvdata(dev);
913 struct ixgbe_adapter *adapter = netdev_priv(netdev);
914 unsigned long event = *(unsigned long *)data;
915
916 switch (event) {
917 case DCA_PROVIDER_ADD:
918 /* if we're already enabled, don't do it again */
919 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
920 break;
921 if (dca_add_requester(dev) == 0) {
922 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
923 ixgbe_setup_dca(adapter);
924 break;
925 }
926 /* Fall Through since DCA is disabled. */
927 case DCA_PROVIDER_REMOVE:
928 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
929 dca_remove_requester(dev);
930 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
931 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
932 }
933 break;
934 }
935
936 return 0;
937 }
938
939 #endif /* CONFIG_IXGBE_DCA */
940 /**
941 * ixgbe_receive_skb - Send a completed packet up the stack
942 * @adapter: board private structure
943 * @skb: packet to send up
944 * @status: hardware indication of status of receive
945 * @rx_ring: rx descriptor ring (for a specific queue) to setup
946 * @rx_desc: rx descriptor
947 **/
948 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
949 struct sk_buff *skb, u8 status,
950 struct ixgbe_ring *ring,
951 union ixgbe_adv_rx_desc *rx_desc)
952 {
953 struct ixgbe_adapter *adapter = q_vector->adapter;
954 struct napi_struct *napi = &q_vector->napi;
955 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
956 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
957
958 skb_record_rx_queue(skb, ring->queue_index);
959 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
960 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
961 vlan_gro_receive(napi, adapter->vlgrp, tag, skb);
962 else
963 napi_gro_receive(napi, skb);
964 } else {
965 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
966 vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
967 else
968 netif_rx(skb);
969 }
970 }
971
972 /**
973 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
974 * @adapter: address of board private structure
975 * @status_err: hardware indication of status of receive
976 * @skb: skb currently being received and modified
977 **/
978 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
979 union ixgbe_adv_rx_desc *rx_desc,
980 struct sk_buff *skb)
981 {
982 u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
983
984 skb->ip_summed = CHECKSUM_NONE;
985
986 /* Rx csum disabled */
987 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
988 return;
989
990 /* if IP and error */
991 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
992 (status_err & IXGBE_RXDADV_ERR_IPE)) {
993 adapter->hw_csum_rx_error++;
994 return;
995 }
996
997 if (!(status_err & IXGBE_RXD_STAT_L4CS))
998 return;
999
1000 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
1001 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1002
1003 /*
1004 * 82599 errata, UDP frames with a 0 checksum can be marked as
1005 * checksum errors.
1006 */
1007 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
1008 (adapter->hw.mac.type == ixgbe_mac_82599EB))
1009 return;
1010
1011 adapter->hw_csum_rx_error++;
1012 return;
1013 }
1014
1015 /* It must be a TCP or UDP packet with a valid checksum */
1016 skb->ip_summed = CHECKSUM_UNNECESSARY;
1017 }
1018
1019 static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
1020 struct ixgbe_ring *rx_ring, u32 val)
1021 {
1022 /*
1023 * Force memory writes to complete before letting h/w
1024 * know there are new descriptors to fetch. (Only
1025 * applicable for weak-ordered memory model archs,
1026 * such as IA-64).
1027 */
1028 wmb();
1029 IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
1030 }
1031
1032 /**
1033 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
1034 * @adapter: address of board private structure
1035 **/
1036 static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
1037 struct ixgbe_ring *rx_ring,
1038 int cleaned_count)
1039 {
1040 struct pci_dev *pdev = adapter->pdev;
1041 union ixgbe_adv_rx_desc *rx_desc;
1042 struct ixgbe_rx_buffer *bi;
1043 unsigned int i;
1044
1045 i = rx_ring->next_to_use;
1046 bi = &rx_ring->rx_buffer_info[i];
1047
1048 while (cleaned_count--) {
1049 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
1050
1051 if (!bi->page_dma &&
1052 (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)) {
1053 if (!bi->page) {
1054 bi->page = alloc_page(GFP_ATOMIC);
1055 if (!bi->page) {
1056 adapter->alloc_rx_page_failed++;
1057 goto no_buffers;
1058 }
1059 bi->page_offset = 0;
1060 } else {
1061 /* use a half page if we're re-using */
1062 bi->page_offset ^= (PAGE_SIZE / 2);
1063 }
1064
1065 bi->page_dma = dma_map_page(&pdev->dev, bi->page,
1066 bi->page_offset,
1067 (PAGE_SIZE / 2),
1068 DMA_FROM_DEVICE);
1069 }
1070
1071 if (!bi->skb) {
1072 struct sk_buff *skb;
1073 /* netdev_alloc_skb reserves 32 bytes up front!! */
1074 uint bufsz = rx_ring->rx_buf_len + SMP_CACHE_BYTES;
1075 skb = netdev_alloc_skb(adapter->netdev, bufsz);
1076
1077 if (!skb) {
1078 adapter->alloc_rx_buff_failed++;
1079 goto no_buffers;
1080 }
1081
1082 /* advance the data pointer to the next cache line */
1083 skb_reserve(skb, (PTR_ALIGN(skb->data, SMP_CACHE_BYTES)
1084 - skb->data));
1085
1086 bi->skb = skb;
1087 bi->dma = dma_map_single(&pdev->dev, skb->data,
1088 rx_ring->rx_buf_len,
1089 DMA_FROM_DEVICE);
1090 }
1091 /* Refresh the desc even if buffer_addrs didn't change because
1092 * each write-back erases this info. */
1093 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
1094 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1095 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
1096 } else {
1097 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
1098 }
1099
1100 i++;
1101 if (i == rx_ring->count)
1102 i = 0;
1103 bi = &rx_ring->rx_buffer_info[i];
1104 }
1105
1106 no_buffers:
1107 if (rx_ring->next_to_use != i) {
1108 rx_ring->next_to_use = i;
1109 if (i-- == 0)
1110 i = (rx_ring->count - 1);
1111
1112 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
1113 }
1114 }
1115
1116 static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
1117 {
1118 return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
1119 }
1120
1121 static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
1122 {
1123 return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1124 }
1125
1126 static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
1127 {
1128 return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
1129 IXGBE_RXDADV_RSCCNT_MASK) >>
1130 IXGBE_RXDADV_RSCCNT_SHIFT;
1131 }
1132
1133 /**
1134 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1135 * @skb: pointer to the last skb in the rsc queue
1136 * @count: pointer to number of packets coalesced in this context
1137 *
1138 * This function changes a queue full of hw rsc buffers into a completed
1139 * packet. It uses the ->prev pointers to find the first packet and then
1140 * turns it into the frag list owner.
1141 **/
1142 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb,
1143 u64 *count)
1144 {
1145 unsigned int frag_list_size = 0;
1146
1147 while (skb->prev) {
1148 struct sk_buff *prev = skb->prev;
1149 frag_list_size += skb->len;
1150 skb->prev = NULL;
1151 skb = prev;
1152 *count += 1;
1153 }
1154
1155 skb_shinfo(skb)->frag_list = skb->next;
1156 skb->next = NULL;
1157 skb->len += frag_list_size;
1158 skb->data_len += frag_list_size;
1159 skb->truesize += frag_list_size;
1160 return skb;
1161 }
1162
1163 struct ixgbe_rsc_cb {
1164 dma_addr_t dma;
1165 bool delay_unmap;
1166 };
1167
1168 #define IXGBE_RSC_CB(skb) ((struct ixgbe_rsc_cb *)(skb)->cb)
1169
1170 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
1171 struct ixgbe_ring *rx_ring,
1172 int *work_done, int work_to_do)
1173 {
1174 struct ixgbe_adapter *adapter = q_vector->adapter;
1175 struct net_device *netdev = adapter->netdev;
1176 struct pci_dev *pdev = adapter->pdev;
1177 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1178 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1179 struct sk_buff *skb;
1180 unsigned int i, rsc_count = 0;
1181 u32 len, staterr;
1182 u16 hdr_info;
1183 bool cleaned = false;
1184 int cleaned_count = 0;
1185 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1186 #ifdef IXGBE_FCOE
1187 int ddp_bytes = 0;
1188 #endif /* IXGBE_FCOE */
1189
1190 i = rx_ring->next_to_clean;
1191 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
1192 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1193 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1194
1195 while (staterr & IXGBE_RXD_STAT_DD) {
1196 u32 upper_len = 0;
1197 if (*work_done >= work_to_do)
1198 break;
1199 (*work_done)++;
1200
1201 rmb(); /* read descriptor and rx_buffer_info after status DD */
1202 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
1203 hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
1204 len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
1205 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
1206 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1207 if ((len > IXGBE_RX_HDR_SIZE) ||
1208 (upper_len && !(hdr_info & IXGBE_RXDADV_SPH)))
1209 len = IXGBE_RX_HDR_SIZE;
1210 } else {
1211 len = le16_to_cpu(rx_desc->wb.upper.length);
1212 }
1213
1214 cleaned = true;
1215 skb = rx_buffer_info->skb;
1216 prefetch(skb->data);
1217 rx_buffer_info->skb = NULL;
1218
1219 if (rx_buffer_info->dma) {
1220 if ((adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
1221 (!(staterr & IXGBE_RXD_STAT_EOP)) &&
1222 (!(skb->prev))) {
1223 /*
1224 * When HWRSC is enabled, delay unmapping
1225 * of the first packet. It carries the
1226 * header information, HW may still
1227 * access the header after the writeback.
1228 * Only unmap it when EOP is reached
1229 */
1230 IXGBE_RSC_CB(skb)->delay_unmap = true;
1231 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
1232 } else {
1233 dma_unmap_single(&pdev->dev,
1234 rx_buffer_info->dma,
1235 rx_ring->rx_buf_len,
1236 DMA_FROM_DEVICE);
1237 }
1238 rx_buffer_info->dma = 0;
1239 skb_put(skb, len);
1240 }
1241
1242 if (upper_len) {
1243 dma_unmap_page(&pdev->dev, rx_buffer_info->page_dma,
1244 PAGE_SIZE / 2, DMA_FROM_DEVICE);
1245 rx_buffer_info->page_dma = 0;
1246 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1247 rx_buffer_info->page,
1248 rx_buffer_info->page_offset,
1249 upper_len);
1250
1251 if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
1252 (page_count(rx_buffer_info->page) != 1))
1253 rx_buffer_info->page = NULL;
1254 else
1255 get_page(rx_buffer_info->page);
1256
1257 skb->len += upper_len;
1258 skb->data_len += upper_len;
1259 skb->truesize += upper_len;
1260 }
1261
1262 i++;
1263 if (i == rx_ring->count)
1264 i = 0;
1265
1266 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
1267 prefetch(next_rxd);
1268 cleaned_count++;
1269
1270 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
1271 rsc_count = ixgbe_get_rsc_count(rx_desc);
1272
1273 if (rsc_count) {
1274 u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1275 IXGBE_RXDADV_NEXTP_SHIFT;
1276 next_buffer = &rx_ring->rx_buffer_info[nextp];
1277 } else {
1278 next_buffer = &rx_ring->rx_buffer_info[i];
1279 }
1280
1281 if (staterr & IXGBE_RXD_STAT_EOP) {
1282 if (skb->prev)
1283 skb = ixgbe_transform_rsc_queue(skb, &(rx_ring->rsc_count));
1284 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
1285 if (IXGBE_RSC_CB(skb)->delay_unmap) {
1286 dma_unmap_single(&pdev->dev,
1287 IXGBE_RSC_CB(skb)->dma,
1288 rx_ring->rx_buf_len,
1289 DMA_FROM_DEVICE);
1290 IXGBE_RSC_CB(skb)->dma = 0;
1291 IXGBE_RSC_CB(skb)->delay_unmap = false;
1292 }
1293 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)
1294 rx_ring->rsc_count += skb_shinfo(skb)->nr_frags;
1295 else
1296 rx_ring->rsc_count++;
1297 rx_ring->rsc_flush++;
1298 }
1299 rx_ring->stats.packets++;
1300 rx_ring->stats.bytes += skb->len;
1301 } else {
1302 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
1303 rx_buffer_info->skb = next_buffer->skb;
1304 rx_buffer_info->dma = next_buffer->dma;
1305 next_buffer->skb = skb;
1306 next_buffer->dma = 0;
1307 } else {
1308 skb->next = next_buffer->skb;
1309 skb->next->prev = skb;
1310 }
1311 rx_ring->non_eop_descs++;
1312 goto next_desc;
1313 }
1314
1315 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
1316 dev_kfree_skb_irq(skb);
1317 goto next_desc;
1318 }
1319
1320 ixgbe_rx_checksum(adapter, rx_desc, skb);
1321
1322 /* probably a little skewed due to removing CRC */
1323 total_rx_bytes += skb->len;
1324 total_rx_packets++;
1325
1326 skb->protocol = eth_type_trans(skb, adapter->netdev);
1327 #ifdef IXGBE_FCOE
1328 /* if ddp, not passing to ULD unless for FCP_RSP or error */
1329 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
1330 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
1331 if (!ddp_bytes)
1332 goto next_desc;
1333 }
1334 #endif /* IXGBE_FCOE */
1335 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
1336
1337 next_desc:
1338 rx_desc->wb.upper.status_error = 0;
1339
1340 /* return some buffers to hardware, one at a time is too slow */
1341 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1342 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
1343 cleaned_count = 0;
1344 }
1345
1346 /* use prefetched values */
1347 rx_desc = next_rxd;
1348 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1349
1350 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1351 }
1352
1353 rx_ring->next_to_clean = i;
1354 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
1355
1356 if (cleaned_count)
1357 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
1358
1359 #ifdef IXGBE_FCOE
1360 /* include DDPed FCoE data */
1361 if (ddp_bytes > 0) {
1362 unsigned int mss;
1363
1364 mss = adapter->netdev->mtu - sizeof(struct fcoe_hdr) -
1365 sizeof(struct fc_frame_header) -
1366 sizeof(struct fcoe_crc_eof);
1367 if (mss > 512)
1368 mss &= ~511;
1369 total_rx_bytes += ddp_bytes;
1370 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1371 }
1372 #endif /* IXGBE_FCOE */
1373
1374 rx_ring->total_packets += total_rx_packets;
1375 rx_ring->total_bytes += total_rx_bytes;
1376 netdev->stats.rx_bytes += total_rx_bytes;
1377 netdev->stats.rx_packets += total_rx_packets;
1378
1379 return cleaned;
1380 }
1381
1382 static int ixgbe_clean_rxonly(struct napi_struct *, int);
1383 /**
1384 * ixgbe_configure_msix - Configure MSI-X hardware
1385 * @adapter: board private structure
1386 *
1387 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1388 * interrupts.
1389 **/
1390 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1391 {
1392 struct ixgbe_q_vector *q_vector;
1393 int i, j, q_vectors, v_idx, r_idx;
1394 u32 mask;
1395
1396 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1397
1398 /*
1399 * Populate the IVAR table and set the ITR values to the
1400 * corresponding register.
1401 */
1402 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
1403 q_vector = adapter->q_vector[v_idx];
1404 r_idx = find_first_bit(q_vector->rxr_idx,
1405 adapter->num_rx_queues);
1406
1407 for (i = 0; i < q_vector->rxr_count; i++) {
1408 j = adapter->rx_ring[r_idx]->reg_idx;
1409 ixgbe_set_ivar(adapter, 0, j, v_idx);
1410 r_idx = find_next_bit(q_vector->rxr_idx,
1411 adapter->num_rx_queues,
1412 r_idx + 1);
1413 }
1414 r_idx = find_first_bit(q_vector->txr_idx,
1415 adapter->num_tx_queues);
1416
1417 for (i = 0; i < q_vector->txr_count; i++) {
1418 j = adapter->tx_ring[r_idx]->reg_idx;
1419 ixgbe_set_ivar(adapter, 1, j, v_idx);
1420 r_idx = find_next_bit(q_vector->txr_idx,
1421 adapter->num_tx_queues,
1422 r_idx + 1);
1423 }
1424
1425 if (q_vector->txr_count && !q_vector->rxr_count)
1426 /* tx only */
1427 q_vector->eitr = adapter->tx_eitr_param;
1428 else if (q_vector->rxr_count)
1429 /* rx or mixed */
1430 q_vector->eitr = adapter->rx_eitr_param;
1431
1432 ixgbe_write_eitr(q_vector);
1433 }
1434
1435 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
1436 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1437 v_idx);
1438 else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
1439 ixgbe_set_ivar(adapter, -1, 1, v_idx);
1440 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1441
1442 /* set up to autoclear timer, and the vectors */
1443 mask = IXGBE_EIMS_ENABLE_MASK;
1444 if (adapter->num_vfs)
1445 mask &= ~(IXGBE_EIMS_OTHER |
1446 IXGBE_EIMS_MAILBOX |
1447 IXGBE_EIMS_LSC);
1448 else
1449 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
1450 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
1451 }
1452
1453 enum latency_range {
1454 lowest_latency = 0,
1455 low_latency = 1,
1456 bulk_latency = 2,
1457 latency_invalid = 255
1458 };
1459
1460 /**
1461 * ixgbe_update_itr - update the dynamic ITR value based on statistics
1462 * @adapter: pointer to adapter
1463 * @eitr: eitr setting (ints per sec) to give last timeslice
1464 * @itr_setting: current throttle rate in ints/second
1465 * @packets: the number of packets during this measurement interval
1466 * @bytes: the number of bytes during this measurement interval
1467 *
1468 * Stores a new ITR value based on packets and byte
1469 * counts during the last interrupt. The advantage of per interrupt
1470 * computation is faster updates and more accurate ITR for the current
1471 * traffic pattern. Constants in this function were computed
1472 * based on theoretical maximum wire speed and thresholds were set based
1473 * on testing data as well as attempting to minimize response time
1474 * while increasing bulk throughput.
1475 * this functionality is controlled by the InterruptThrottleRate module
1476 * parameter (see ixgbe_param.c)
1477 **/
1478 static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
1479 u32 eitr, u8 itr_setting,
1480 int packets, int bytes)
1481 {
1482 unsigned int retval = itr_setting;
1483 u32 timepassed_us;
1484 u64 bytes_perint;
1485
1486 if (packets == 0)
1487 goto update_itr_done;
1488
1489
1490 /* simple throttlerate management
1491 * 0-20MB/s lowest (100000 ints/s)
1492 * 20-100MB/s low (20000 ints/s)
1493 * 100-1249MB/s bulk (8000 ints/s)
1494 */
1495 /* what was last interrupt timeslice? */
1496 timepassed_us = 1000000/eitr;
1497 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1498
1499 switch (itr_setting) {
1500 case lowest_latency:
1501 if (bytes_perint > adapter->eitr_low)
1502 retval = low_latency;
1503 break;
1504 case low_latency:
1505 if (bytes_perint > adapter->eitr_high)
1506 retval = bulk_latency;
1507 else if (bytes_perint <= adapter->eitr_low)
1508 retval = lowest_latency;
1509 break;
1510 case bulk_latency:
1511 if (bytes_perint <= adapter->eitr_high)
1512 retval = low_latency;
1513 break;
1514 }
1515
1516 update_itr_done:
1517 return retval;
1518 }
1519
1520 /**
1521 * ixgbe_write_eitr - write EITR register in hardware specific way
1522 * @q_vector: structure containing interrupt and ring information
1523 *
1524 * This function is made to be called by ethtool and by the driver
1525 * when it needs to update EITR registers at runtime. Hardware
1526 * specific quirks/differences are taken care of here.
1527 */
1528 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1529 {
1530 struct ixgbe_adapter *adapter = q_vector->adapter;
1531 struct ixgbe_hw *hw = &adapter->hw;
1532 int v_idx = q_vector->v_idx;
1533 u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1534
1535 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1536 /* must write high and low 16 bits to reset counter */
1537 itr_reg |= (itr_reg << 16);
1538 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1539 /*
1540 * 82599 can support a value of zero, so allow it for
1541 * max interrupt rate, but there is an errata where it can
1542 * not be zero with RSC
1543 */
1544 if (itr_reg == 8 &&
1545 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
1546 itr_reg = 0;
1547
1548 /*
1549 * set the WDIS bit to not clear the timer bits and cause an
1550 * immediate assertion of the interrupt
1551 */
1552 itr_reg |= IXGBE_EITR_CNT_WDIS;
1553 }
1554 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1555 }
1556
1557 static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1558 {
1559 struct ixgbe_adapter *adapter = q_vector->adapter;
1560 u32 new_itr;
1561 u8 current_itr, ret_itr;
1562 int i, r_idx;
1563 struct ixgbe_ring *rx_ring, *tx_ring;
1564
1565 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1566 for (i = 0; i < q_vector->txr_count; i++) {
1567 tx_ring = adapter->tx_ring[r_idx];
1568 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1569 q_vector->tx_itr,
1570 tx_ring->total_packets,
1571 tx_ring->total_bytes);
1572 /* if the result for this queue would decrease interrupt
1573 * rate for this vector then use that result */
1574 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
1575 q_vector->tx_itr - 1 : ret_itr);
1576 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1577 r_idx + 1);
1578 }
1579
1580 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1581 for (i = 0; i < q_vector->rxr_count; i++) {
1582 rx_ring = adapter->rx_ring[r_idx];
1583 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1584 q_vector->rx_itr,
1585 rx_ring->total_packets,
1586 rx_ring->total_bytes);
1587 /* if the result for this queue would decrease interrupt
1588 * rate for this vector then use that result */
1589 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
1590 q_vector->rx_itr - 1 : ret_itr);
1591 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1592 r_idx + 1);
1593 }
1594
1595 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1596
1597 switch (current_itr) {
1598 /* counts and packets in update_itr are dependent on these numbers */
1599 case lowest_latency:
1600 new_itr = 100000;
1601 break;
1602 case low_latency:
1603 new_itr = 20000; /* aka hwitr = ~200 */
1604 break;
1605 case bulk_latency:
1606 default:
1607 new_itr = 8000;
1608 break;
1609 }
1610
1611 if (new_itr != q_vector->eitr) {
1612 /* do an exponential smoothing */
1613 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1614
1615 /* save the algorithm value here, not the smoothed one */
1616 q_vector->eitr = new_itr;
1617
1618 ixgbe_write_eitr(q_vector);
1619 }
1620 }
1621
1622 /**
1623 * ixgbe_check_overtemp_task - worker thread to check over tempurature
1624 * @work: pointer to work_struct containing our data
1625 **/
1626 static void ixgbe_check_overtemp_task(struct work_struct *work)
1627 {
1628 struct ixgbe_adapter *adapter = container_of(work,
1629 struct ixgbe_adapter,
1630 check_overtemp_task);
1631 struct ixgbe_hw *hw = &adapter->hw;
1632 u32 eicr = adapter->interrupt_event;
1633
1634 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
1635 switch (hw->device_id) {
1636 case IXGBE_DEV_ID_82599_T3_LOM: {
1637 u32 autoneg;
1638 bool link_up = false;
1639
1640 if (hw->mac.ops.check_link)
1641 hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1642
1643 if (((eicr & IXGBE_EICR_GPI_SDP0) && (!link_up)) ||
1644 (eicr & IXGBE_EICR_LSC))
1645 /* Check if this is due to overtemp */
1646 if (hw->phy.ops.check_overtemp(hw) == IXGBE_ERR_OVERTEMP)
1647 break;
1648 }
1649 return;
1650 default:
1651 if (!(eicr & IXGBE_EICR_GPI_SDP0))
1652 return;
1653 break;
1654 }
1655 e_crit(drv, "Network adapter has been stopped because it has "
1656 "over heated. Restart the computer. If the problem "
1657 "persists, power off the system and replace the "
1658 "adapter\n");
1659 /* write to clear the interrupt */
1660 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP0);
1661 }
1662 }
1663
1664 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1665 {
1666 struct ixgbe_hw *hw = &adapter->hw;
1667
1668 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1669 (eicr & IXGBE_EICR_GPI_SDP1)) {
1670 e_crit(probe, "Fan has stopped, replace the adapter\n");
1671 /* write to clear the interrupt */
1672 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1673 }
1674 }
1675
1676 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1677 {
1678 struct ixgbe_hw *hw = &adapter->hw;
1679
1680 if (eicr & IXGBE_EICR_GPI_SDP1) {
1681 /* Clear the interrupt */
1682 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1683 schedule_work(&adapter->multispeed_fiber_task);
1684 } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1685 /* Clear the interrupt */
1686 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1687 schedule_work(&adapter->sfp_config_module_task);
1688 } else {
1689 /* Interrupt isn't for us... */
1690 return;
1691 }
1692 }
1693
1694 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1695 {
1696 struct ixgbe_hw *hw = &adapter->hw;
1697
1698 adapter->lsc_int++;
1699 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1700 adapter->link_check_timeout = jiffies;
1701 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1702 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1703 IXGBE_WRITE_FLUSH(hw);
1704 schedule_work(&adapter->watchdog_task);
1705 }
1706 }
1707
1708 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1709 {
1710 struct net_device *netdev = data;
1711 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1712 struct ixgbe_hw *hw = &adapter->hw;
1713 u32 eicr;
1714
1715 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1716 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1717
1718 if (eicr & IXGBE_EICR_LSC)
1719 ixgbe_check_lsc(adapter);
1720
1721 if (eicr & IXGBE_EICR_MAILBOX)
1722 ixgbe_msg_task(adapter);
1723
1724 if (hw->mac.type == ixgbe_mac_82598EB)
1725 ixgbe_check_fan_failure(adapter, eicr);
1726
1727 if (hw->mac.type == ixgbe_mac_82599EB) {
1728 ixgbe_check_sfp_event(adapter, eicr);
1729 adapter->interrupt_event = eicr;
1730 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1731 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)))
1732 schedule_work(&adapter->check_overtemp_task);
1733
1734 /* Handle Flow Director Full threshold interrupt */
1735 if (eicr & IXGBE_EICR_FLOW_DIR) {
1736 int i;
1737 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1738 /* Disable transmits before FDIR Re-initialization */
1739 netif_tx_stop_all_queues(netdev);
1740 for (i = 0; i < adapter->num_tx_queues; i++) {
1741 struct ixgbe_ring *tx_ring =
1742 adapter->tx_ring[i];
1743 if (test_and_clear_bit(__IXGBE_FDIR_INIT_DONE,
1744 &tx_ring->reinit_state))
1745 schedule_work(&adapter->fdir_reinit_task);
1746 }
1747 }
1748 }
1749 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1750 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
1751
1752 return IRQ_HANDLED;
1753 }
1754
1755 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1756 u64 qmask)
1757 {
1758 u32 mask;
1759
1760 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1761 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1762 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1763 } else {
1764 mask = (qmask & 0xFFFFFFFF);
1765 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1766 mask = (qmask >> 32);
1767 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1768 }
1769 /* skip the flush */
1770 }
1771
1772 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1773 u64 qmask)
1774 {
1775 u32 mask;
1776
1777 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1778 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1779 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask);
1780 } else {
1781 mask = (qmask & 0xFFFFFFFF);
1782 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), mask);
1783 mask = (qmask >> 32);
1784 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), mask);
1785 }
1786 /* skip the flush */
1787 }
1788
1789 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1790 {
1791 struct ixgbe_q_vector *q_vector = data;
1792 struct ixgbe_adapter *adapter = q_vector->adapter;
1793 struct ixgbe_ring *tx_ring;
1794 int i, r_idx;
1795
1796 if (!q_vector->txr_count)
1797 return IRQ_HANDLED;
1798
1799 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1800 for (i = 0; i < q_vector->txr_count; i++) {
1801 tx_ring = adapter->tx_ring[r_idx];
1802 tx_ring->total_bytes = 0;
1803 tx_ring->total_packets = 0;
1804 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1805 r_idx + 1);
1806 }
1807
1808 /* EIAM disabled interrupts (on this vector) for us */
1809 napi_schedule(&q_vector->napi);
1810
1811 return IRQ_HANDLED;
1812 }
1813
1814 /**
1815 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1816 * @irq: unused
1817 * @data: pointer to our q_vector struct for this interrupt vector
1818 **/
1819 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1820 {
1821 struct ixgbe_q_vector *q_vector = data;
1822 struct ixgbe_adapter *adapter = q_vector->adapter;
1823 struct ixgbe_ring *rx_ring;
1824 int r_idx;
1825 int i;
1826
1827 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1828 for (i = 0; i < q_vector->rxr_count; i++) {
1829 rx_ring = adapter->rx_ring[r_idx];
1830 rx_ring->total_bytes = 0;
1831 rx_ring->total_packets = 0;
1832 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1833 r_idx + 1);
1834 }
1835
1836 if (!q_vector->rxr_count)
1837 return IRQ_HANDLED;
1838
1839 /* disable interrupts on this vector only */
1840 /* EIAM disabled interrupts (on this vector) for us */
1841 napi_schedule(&q_vector->napi);
1842
1843 return IRQ_HANDLED;
1844 }
1845
1846 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1847 {
1848 struct ixgbe_q_vector *q_vector = data;
1849 struct ixgbe_adapter *adapter = q_vector->adapter;
1850 struct ixgbe_ring *ring;
1851 int r_idx;
1852 int i;
1853
1854 if (!q_vector->txr_count && !q_vector->rxr_count)
1855 return IRQ_HANDLED;
1856
1857 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1858 for (i = 0; i < q_vector->txr_count; i++) {
1859 ring = adapter->tx_ring[r_idx];
1860 ring->total_bytes = 0;
1861 ring->total_packets = 0;
1862 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1863 r_idx + 1);
1864 }
1865
1866 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1867 for (i = 0; i < q_vector->rxr_count; i++) {
1868 ring = adapter->rx_ring[r_idx];
1869 ring->total_bytes = 0;
1870 ring->total_packets = 0;
1871 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1872 r_idx + 1);
1873 }
1874
1875 /* EIAM disabled interrupts (on this vector) for us */
1876 napi_schedule(&q_vector->napi);
1877
1878 return IRQ_HANDLED;
1879 }
1880
1881 /**
1882 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1883 * @napi: napi struct with our devices info in it
1884 * @budget: amount of work driver is allowed to do this pass, in packets
1885 *
1886 * This function is optimized for cleaning one queue only on a single
1887 * q_vector!!!
1888 **/
1889 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1890 {
1891 struct ixgbe_q_vector *q_vector =
1892 container_of(napi, struct ixgbe_q_vector, napi);
1893 struct ixgbe_adapter *adapter = q_vector->adapter;
1894 struct ixgbe_ring *rx_ring = NULL;
1895 int work_done = 0;
1896 long r_idx;
1897
1898 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1899 rx_ring = adapter->rx_ring[r_idx];
1900 #ifdef CONFIG_IXGBE_DCA
1901 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1902 ixgbe_update_rx_dca(adapter, rx_ring);
1903 #endif
1904
1905 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
1906
1907 /* If all Rx work done, exit the polling mode */
1908 if (work_done < budget) {
1909 napi_complete(napi);
1910 if (adapter->rx_itr_setting & 1)
1911 ixgbe_set_itr_msix(q_vector);
1912 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1913 ixgbe_irq_enable_queues(adapter,
1914 ((u64)1 << q_vector->v_idx));
1915 }
1916
1917 return work_done;
1918 }
1919
1920 /**
1921 * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
1922 * @napi: napi struct with our devices info in it
1923 * @budget: amount of work driver is allowed to do this pass, in packets
1924 *
1925 * This function will clean more than one rx queue associated with a
1926 * q_vector.
1927 **/
1928 static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
1929 {
1930 struct ixgbe_q_vector *q_vector =
1931 container_of(napi, struct ixgbe_q_vector, napi);
1932 struct ixgbe_adapter *adapter = q_vector->adapter;
1933 struct ixgbe_ring *ring = NULL;
1934 int work_done = 0, i;
1935 long r_idx;
1936 bool tx_clean_complete = true;
1937
1938 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1939 for (i = 0; i < q_vector->txr_count; i++) {
1940 ring = adapter->tx_ring[r_idx];
1941 #ifdef CONFIG_IXGBE_DCA
1942 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1943 ixgbe_update_tx_dca(adapter, ring);
1944 #endif
1945 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
1946 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1947 r_idx + 1);
1948 }
1949
1950 /* attempt to distribute budget to each queue fairly, but don't allow
1951 * the budget to go below 1 because we'll exit polling */
1952 budget /= (q_vector->rxr_count ?: 1);
1953 budget = max(budget, 1);
1954 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1955 for (i = 0; i < q_vector->rxr_count; i++) {
1956 ring = adapter->rx_ring[r_idx];
1957 #ifdef CONFIG_IXGBE_DCA
1958 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1959 ixgbe_update_rx_dca(adapter, ring);
1960 #endif
1961 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
1962 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1963 r_idx + 1);
1964 }
1965
1966 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1967 ring = adapter->rx_ring[r_idx];
1968 /* If all Rx work done, exit the polling mode */
1969 if (work_done < budget) {
1970 napi_complete(napi);
1971 if (adapter->rx_itr_setting & 1)
1972 ixgbe_set_itr_msix(q_vector);
1973 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1974 ixgbe_irq_enable_queues(adapter,
1975 ((u64)1 << q_vector->v_idx));
1976 return 0;
1977 }
1978
1979 return work_done;
1980 }
1981
1982 /**
1983 * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
1984 * @napi: napi struct with our devices info in it
1985 * @budget: amount of work driver is allowed to do this pass, in packets
1986 *
1987 * This function is optimized for cleaning one queue only on a single
1988 * q_vector!!!
1989 **/
1990 static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
1991 {
1992 struct ixgbe_q_vector *q_vector =
1993 container_of(napi, struct ixgbe_q_vector, napi);
1994 struct ixgbe_adapter *adapter = q_vector->adapter;
1995 struct ixgbe_ring *tx_ring = NULL;
1996 int work_done = 0;
1997 long r_idx;
1998
1999 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2000 tx_ring = adapter->tx_ring[r_idx];
2001 #ifdef CONFIG_IXGBE_DCA
2002 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2003 ixgbe_update_tx_dca(adapter, tx_ring);
2004 #endif
2005
2006 if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
2007 work_done = budget;
2008
2009 /* If all Tx work done, exit the polling mode */
2010 if (work_done < budget) {
2011 napi_complete(napi);
2012 if (adapter->tx_itr_setting & 1)
2013 ixgbe_set_itr_msix(q_vector);
2014 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2015 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
2016 }
2017
2018 return work_done;
2019 }
2020
2021 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
2022 int r_idx)
2023 {
2024 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2025
2026 set_bit(r_idx, q_vector->rxr_idx);
2027 q_vector->rxr_count++;
2028 }
2029
2030 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
2031 int t_idx)
2032 {
2033 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2034
2035 set_bit(t_idx, q_vector->txr_idx);
2036 q_vector->txr_count++;
2037 }
2038
2039 /**
2040 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2041 * @adapter: board private structure to initialize
2042 * @vectors: allotted vector count for descriptor rings
2043 *
2044 * This function maps descriptor rings to the queue-specific vectors
2045 * we were allotted through the MSI-X enabling code. Ideally, we'd have
2046 * one vector per ring/queue, but on a constrained vector budget, we
2047 * group the rings as "efficiently" as possible. You would add new
2048 * mapping configurations in here.
2049 **/
2050 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
2051 int vectors)
2052 {
2053 int v_start = 0;
2054 int rxr_idx = 0, txr_idx = 0;
2055 int rxr_remaining = adapter->num_rx_queues;
2056 int txr_remaining = adapter->num_tx_queues;
2057 int i, j;
2058 int rqpv, tqpv;
2059 int err = 0;
2060
2061 /* No mapping required if MSI-X is disabled. */
2062 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2063 goto out;
2064
2065 /*
2066 * The ideal configuration...
2067 * We have enough vectors to map one per queue.
2068 */
2069 if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
2070 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
2071 map_vector_to_rxq(adapter, v_start, rxr_idx);
2072
2073 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
2074 map_vector_to_txq(adapter, v_start, txr_idx);
2075
2076 goto out;
2077 }
2078
2079 /*
2080 * If we don't have enough vectors for a 1-to-1
2081 * mapping, we'll have to group them so there are
2082 * multiple queues per vector.
2083 */
2084 /* Re-adjusting *qpv takes care of the remainder. */
2085 for (i = v_start; i < vectors; i++) {
2086 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
2087 for (j = 0; j < rqpv; j++) {
2088 map_vector_to_rxq(adapter, i, rxr_idx);
2089 rxr_idx++;
2090 rxr_remaining--;
2091 }
2092 }
2093 for (i = v_start; i < vectors; i++) {
2094 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
2095 for (j = 0; j < tqpv; j++) {
2096 map_vector_to_txq(adapter, i, txr_idx);
2097 txr_idx++;
2098 txr_remaining--;
2099 }
2100 }
2101
2102 out:
2103 return err;
2104 }
2105
2106 /**
2107 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2108 * @adapter: board private structure
2109 *
2110 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2111 * interrupts from the kernel.
2112 **/
2113 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2114 {
2115 struct net_device *netdev = adapter->netdev;
2116 irqreturn_t (*handler)(int, void *);
2117 int i, vector, q_vectors, err;
2118 int ri=0, ti=0;
2119
2120 /* Decrement for Other and TCP Timer vectors */
2121 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2122
2123 /* Map the Tx/Rx rings to the vectors we were allotted. */
2124 err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
2125 if (err)
2126 goto out;
2127
2128 #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
2129 (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
2130 &ixgbe_msix_clean_many)
2131 for (vector = 0; vector < q_vectors; vector++) {
2132 handler = SET_HANDLER(adapter->q_vector[vector]);
2133
2134 if(handler == &ixgbe_msix_clean_rx) {
2135 sprintf(adapter->name[vector], "%s-%s-%d",
2136 netdev->name, "rx", ri++);
2137 }
2138 else if(handler == &ixgbe_msix_clean_tx) {
2139 sprintf(adapter->name[vector], "%s-%s-%d",
2140 netdev->name, "tx", ti++);
2141 }
2142 else
2143 sprintf(adapter->name[vector], "%s-%s-%d",
2144 netdev->name, "TxRx", vector);
2145
2146 err = request_irq(adapter->msix_entries[vector].vector,
2147 handler, 0, adapter->name[vector],
2148 adapter->q_vector[vector]);
2149 if (err) {
2150 e_err(probe, "request_irq failed for MSIX interrupt "
2151 "Error: %d\n", err);
2152 goto free_queue_irqs;
2153 }
2154 }
2155
2156 sprintf(adapter->name[vector], "%s:lsc", netdev->name);
2157 err = request_irq(adapter->msix_entries[vector].vector,
2158 ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
2159 if (err) {
2160 e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
2161 goto free_queue_irqs;
2162 }
2163
2164 return 0;
2165
2166 free_queue_irqs:
2167 for (i = vector - 1; i >= 0; i--)
2168 free_irq(adapter->msix_entries[--vector].vector,
2169 adapter->q_vector[i]);
2170 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2171 pci_disable_msix(adapter->pdev);
2172 kfree(adapter->msix_entries);
2173 adapter->msix_entries = NULL;
2174 out:
2175 return err;
2176 }
2177
2178 static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
2179 {
2180 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2181 u8 current_itr;
2182 u32 new_itr = q_vector->eitr;
2183 struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
2184 struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
2185
2186 q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
2187 q_vector->tx_itr,
2188 tx_ring->total_packets,
2189 tx_ring->total_bytes);
2190 q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
2191 q_vector->rx_itr,
2192 rx_ring->total_packets,
2193 rx_ring->total_bytes);
2194
2195 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
2196
2197 switch (current_itr) {
2198 /* counts and packets in update_itr are dependent on these numbers */
2199 case lowest_latency:
2200 new_itr = 100000;
2201 break;
2202 case low_latency:
2203 new_itr = 20000; /* aka hwitr = ~200 */
2204 break;
2205 case bulk_latency:
2206 new_itr = 8000;
2207 break;
2208 default:
2209 break;
2210 }
2211
2212 if (new_itr != q_vector->eitr) {
2213 /* do an exponential smoothing */
2214 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
2215
2216 /* save the algorithm value here, not the smoothed one */
2217 q_vector->eitr = new_itr;
2218
2219 ixgbe_write_eitr(q_vector);
2220 }
2221 }
2222
2223 /**
2224 * ixgbe_irq_enable - Enable default interrupt generation settings
2225 * @adapter: board private structure
2226 **/
2227 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
2228 {
2229 u32 mask;
2230
2231 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
2232 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2233 mask |= IXGBE_EIMS_GPI_SDP0;
2234 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2235 mask |= IXGBE_EIMS_GPI_SDP1;
2236 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2237 mask |= IXGBE_EIMS_ECC;
2238 mask |= IXGBE_EIMS_GPI_SDP1;
2239 mask |= IXGBE_EIMS_GPI_SDP2;
2240 if (adapter->num_vfs)
2241 mask |= IXGBE_EIMS_MAILBOX;
2242 }
2243 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
2244 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
2245 mask |= IXGBE_EIMS_FLOW_DIR;
2246
2247 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2248 ixgbe_irq_enable_queues(adapter, ~0);
2249 IXGBE_WRITE_FLUSH(&adapter->hw);
2250
2251 if (adapter->num_vfs > 32) {
2252 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2253 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2254 }
2255 }
2256
2257 /**
2258 * ixgbe_intr - legacy mode Interrupt Handler
2259 * @irq: interrupt number
2260 * @data: pointer to a network interface device structure
2261 **/
2262 static irqreturn_t ixgbe_intr(int irq, void *data)
2263 {
2264 struct net_device *netdev = data;
2265 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2266 struct ixgbe_hw *hw = &adapter->hw;
2267 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2268 u32 eicr;
2269
2270 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2271
2272 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2273 * therefore no explict interrupt disable is necessary */
2274 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2275 if (!eicr) {
2276 /* shared interrupt alert!
2277 * make sure interrupts are enabled because the read will
2278 * have disabled interrupts due to EIAM */
2279 ixgbe_irq_enable(adapter);
2280 return IRQ_NONE; /* Not our interrupt */
2281 }
2282
2283 if (eicr & IXGBE_EICR_LSC)
2284 ixgbe_check_lsc(adapter);
2285
2286 if (hw->mac.type == ixgbe_mac_82599EB)
2287 ixgbe_check_sfp_event(adapter, eicr);
2288
2289 ixgbe_check_fan_failure(adapter, eicr);
2290 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2291 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)))
2292 schedule_work(&adapter->check_overtemp_task);
2293
2294 if (napi_schedule_prep(&(q_vector->napi))) {
2295 adapter->tx_ring[0]->total_packets = 0;
2296 adapter->tx_ring[0]->total_bytes = 0;
2297 adapter->rx_ring[0]->total_packets = 0;
2298 adapter->rx_ring[0]->total_bytes = 0;
2299 /* would disable interrupts here but EIAM disabled it */
2300 __napi_schedule(&(q_vector->napi));
2301 }
2302
2303 return IRQ_HANDLED;
2304 }
2305
2306 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2307 {
2308 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2309
2310 for (i = 0; i < q_vectors; i++) {
2311 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
2312 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
2313 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
2314 q_vector->rxr_count = 0;
2315 q_vector->txr_count = 0;
2316 }
2317 }
2318
2319 /**
2320 * ixgbe_request_irq - initialize interrupts
2321 * @adapter: board private structure
2322 *
2323 * Attempts to configure interrupts using the best available
2324 * capabilities of the hardware and kernel.
2325 **/
2326 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2327 {
2328 struct net_device *netdev = adapter->netdev;
2329 int err;
2330
2331 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2332 err = ixgbe_request_msix_irqs(adapter);
2333 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
2334 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2335 netdev->name, netdev);
2336 } else {
2337 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2338 netdev->name, netdev);
2339 }
2340
2341 if (err)
2342 e_err(probe, "request_irq failed, Error %d\n", err);
2343
2344 return err;
2345 }
2346
2347 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2348 {
2349 struct net_device *netdev = adapter->netdev;
2350
2351 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2352 int i, q_vectors;
2353
2354 q_vectors = adapter->num_msix_vectors;
2355
2356 i = q_vectors - 1;
2357 free_irq(adapter->msix_entries[i].vector, netdev);
2358
2359 i--;
2360 for (; i >= 0; i--) {
2361 free_irq(adapter->msix_entries[i].vector,
2362 adapter->q_vector[i]);
2363 }
2364
2365 ixgbe_reset_q_vectors(adapter);
2366 } else {
2367 free_irq(adapter->pdev->irq, netdev);
2368 }
2369 }
2370
2371 /**
2372 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2373 * @adapter: board private structure
2374 **/
2375 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2376 {
2377 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2378 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2379 } else {
2380 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2381 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
2382 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
2383 if (adapter->num_vfs > 32)
2384 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
2385 }
2386 IXGBE_WRITE_FLUSH(&adapter->hw);
2387 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2388 int i;
2389 for (i = 0; i < adapter->num_msix_vectors; i++)
2390 synchronize_irq(adapter->msix_entries[i].vector);
2391 } else {
2392 synchronize_irq(adapter->pdev->irq);
2393 }
2394 }
2395
2396 /**
2397 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2398 *
2399 **/
2400 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2401 {
2402 struct ixgbe_hw *hw = &adapter->hw;
2403
2404 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
2405 EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
2406
2407 ixgbe_set_ivar(adapter, 0, 0, 0);
2408 ixgbe_set_ivar(adapter, 1, 0, 0);
2409
2410 map_vector_to_rxq(adapter, 0, 0);
2411 map_vector_to_txq(adapter, 0, 0);
2412
2413 e_info(hw, "Legacy interrupt IVAR setup done\n");
2414 }
2415
2416 /**
2417 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2418 * @adapter: board private structure
2419 *
2420 * Configure the Tx unit of the MAC after a reset.
2421 **/
2422 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2423 {
2424 u64 tdba;
2425 struct ixgbe_hw *hw = &adapter->hw;
2426 u32 i, j, tdlen, txctrl;
2427
2428 /* Setup the HW Tx Head and Tail descriptor pointers */
2429 for (i = 0; i < adapter->num_tx_queues; i++) {
2430 struct ixgbe_ring *ring = adapter->tx_ring[i];
2431 j = ring->reg_idx;
2432 tdba = ring->dma;
2433 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
2434 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
2435 (tdba & DMA_BIT_MASK(32)));
2436 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
2437 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
2438 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
2439 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
2440 adapter->tx_ring[i]->head = IXGBE_TDH(j);
2441 adapter->tx_ring[i]->tail = IXGBE_TDT(j);
2442 /*
2443 * Disable Tx Head Writeback RO bit, since this hoses
2444 * bookkeeping if things aren't delivered in order.
2445 */
2446 switch (hw->mac.type) {
2447 case ixgbe_mac_82598EB:
2448 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
2449 break;
2450 case ixgbe_mac_82599EB:
2451 default:
2452 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(j));
2453 break;
2454 }
2455 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
2456 switch (hw->mac.type) {
2457 case ixgbe_mac_82598EB:
2458 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
2459 break;
2460 case ixgbe_mac_82599EB:
2461 default:
2462 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(j), txctrl);
2463 break;
2464 }
2465 }
2466
2467 if (hw->mac.type == ixgbe_mac_82599EB) {
2468 u32 rttdcs;
2469 u32 mask;
2470
2471 /* disable the arbiter while setting MTQC */
2472 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2473 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2474 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2475
2476 /* set transmit pool layout */
2477 mask = (IXGBE_FLAG_SRIOV_ENABLED | IXGBE_FLAG_DCB_ENABLED);
2478 switch (adapter->flags & mask) {
2479
2480 case (IXGBE_FLAG_SRIOV_ENABLED):
2481 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2482 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2483 break;
2484
2485 case (IXGBE_FLAG_DCB_ENABLED):
2486 /* We enable 8 traffic classes, DCB only */
2487 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2488 (IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ));
2489 break;
2490
2491 default:
2492 IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB);
2493 break;
2494 }
2495
2496 /* re-eable the arbiter */
2497 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2498 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2499 }
2500 }
2501
2502 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2503
2504 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2505 struct ixgbe_ring *rx_ring)
2506 {
2507 u32 srrctl;
2508 int index;
2509 struct ixgbe_ring_feature *feature = adapter->ring_feature;
2510
2511 index = rx_ring->reg_idx;
2512 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2513 unsigned long mask;
2514 mask = (unsigned long) feature[RING_F_RSS].mask;
2515 index = index & mask;
2516 }
2517 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
2518
2519 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2520 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2521
2522 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2523 IXGBE_SRRCTL_BSIZEHDR_MASK;
2524
2525 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
2526 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2527 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2528 #else
2529 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2530 #endif
2531 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2532 } else {
2533 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2534 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2535 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
2536 }
2537
2538 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
2539 }
2540
2541 static u32 ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2542 {
2543 u32 mrqc = 0;
2544 int mask;
2545
2546 if (!(adapter->hw.mac.type == ixgbe_mac_82599EB))
2547 return mrqc;
2548
2549 mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2550 #ifdef CONFIG_IXGBE_DCB
2551 | IXGBE_FLAG_DCB_ENABLED
2552 #endif
2553 | IXGBE_FLAG_SRIOV_ENABLED
2554 );
2555
2556 switch (mask) {
2557 case (IXGBE_FLAG_RSS_ENABLED):
2558 mrqc = IXGBE_MRQC_RSSEN;
2559 break;
2560 case (IXGBE_FLAG_SRIOV_ENABLED):
2561 mrqc = IXGBE_MRQC_VMDQEN;
2562 break;
2563 #ifdef CONFIG_IXGBE_DCB
2564 case (IXGBE_FLAG_DCB_ENABLED):
2565 mrqc = IXGBE_MRQC_RT8TCEN;
2566 break;
2567 #endif /* CONFIG_IXGBE_DCB */
2568 default:
2569 break;
2570 }
2571
2572 return mrqc;
2573 }
2574
2575 /**
2576 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2577 * @adapter: address of board private structure
2578 * @index: index of ring to set
2579 **/
2580 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, int index)
2581 {
2582 struct ixgbe_ring *rx_ring;
2583 struct ixgbe_hw *hw = &adapter->hw;
2584 int j;
2585 u32 rscctrl;
2586 int rx_buf_len;
2587
2588 rx_ring = adapter->rx_ring[index];
2589 j = rx_ring->reg_idx;
2590 rx_buf_len = rx_ring->rx_buf_len;
2591 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(j));
2592 rscctrl |= IXGBE_RSCCTL_RSCEN;
2593 /*
2594 * we must limit the number of descriptors so that the
2595 * total size of max desc * buf_len is not greater
2596 * than 65535
2597 */
2598 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
2599 #if (MAX_SKB_FRAGS > 16)
2600 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2601 #elif (MAX_SKB_FRAGS > 8)
2602 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2603 #elif (MAX_SKB_FRAGS > 4)
2604 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2605 #else
2606 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2607 #endif
2608 } else {
2609 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2610 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2611 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2612 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2613 else
2614 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2615 }
2616 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(j), rscctrl);
2617 }
2618
2619 /**
2620 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
2621 * @adapter: board private structure
2622 *
2623 * Configure the Rx unit of the MAC after a reset.
2624 **/
2625 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
2626 {
2627 u64 rdba;
2628 struct ixgbe_hw *hw = &adapter->hw;
2629 struct ixgbe_ring *rx_ring;
2630 struct net_device *netdev = adapter->netdev;
2631 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2632 int i, j;
2633 u32 rdlen, rxctrl, rxcsum;
2634 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2635 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2636 0x6A3E67EA, 0x14364D17, 0x3BED200D};
2637 u32 fctrl, hlreg0;
2638 u32 reta = 0, mrqc = 0;
2639 u32 rdrxctl;
2640 int rx_buf_len;
2641
2642 /* Decide whether to use packet split mode or not */
2643 /* On by default */
2644 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
2645
2646 /* Do not use packet split if we're in SR-IOV Mode */
2647 if (adapter->num_vfs)
2648 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
2649
2650 /* Disable packet split due to 82599 erratum #45 */
2651 if (hw->mac.type == ixgbe_mac_82599EB)
2652 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
2653
2654 /* Set the RX buffer length according to the mode */
2655 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
2656 rx_buf_len = IXGBE_RX_HDR_SIZE;
2657 if (hw->mac.type == ixgbe_mac_82599EB) {
2658 /* PSRTYPE must be initialized in 82599 */
2659 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
2660 IXGBE_PSRTYPE_UDPHDR |
2661 IXGBE_PSRTYPE_IPV4HDR |
2662 IXGBE_PSRTYPE_IPV6HDR |
2663 IXGBE_PSRTYPE_L2HDR;
2664 IXGBE_WRITE_REG(hw,
2665 IXGBE_PSRTYPE(adapter->num_vfs),
2666 psrtype);
2667 }
2668 } else {
2669 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
2670 (netdev->mtu <= ETH_DATA_LEN))
2671 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
2672 else
2673 rx_buf_len = ALIGN(max_frame, 1024);
2674 }
2675
2676 fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
2677 fctrl |= IXGBE_FCTRL_BAM;
2678 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
2679 fctrl |= IXGBE_FCTRL_PMCF;
2680 IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
2681
2682 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2683 if (adapter->netdev->mtu <= ETH_DATA_LEN)
2684 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
2685 else
2686 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2687 #ifdef IXGBE_FCOE
2688 if (netdev->features & NETIF_F_FCOE_MTU)
2689 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2690 #endif
2691 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2692
2693 rdlen = adapter->rx_ring[0]->count * sizeof(union ixgbe_adv_rx_desc);
2694 /* disable receives while setting up the descriptors */
2695 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2696 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2697
2698 /*
2699 * Setup the HW Rx Head and Tail Descriptor Pointers and
2700 * the Base and Length of the Rx Descriptor Ring
2701 */
2702 for (i = 0; i < adapter->num_rx_queues; i++) {
2703 rx_ring = adapter->rx_ring[i];
2704 rdba = rx_ring->dma;
2705 j = rx_ring->reg_idx;
2706 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_BIT_MASK(32)));
2707 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
2708 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
2709 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
2710 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
2711 rx_ring->head = IXGBE_RDH(j);
2712 rx_ring->tail = IXGBE_RDT(j);
2713 rx_ring->rx_buf_len = rx_buf_len;
2714
2715 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
2716 rx_ring->flags |= IXGBE_RING_RX_PS_ENABLED;
2717 else
2718 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2719
2720 #ifdef IXGBE_FCOE
2721 if (netdev->features & NETIF_F_FCOE_MTU) {
2722 struct ixgbe_ring_feature *f;
2723 f = &adapter->ring_feature[RING_F_FCOE];
2724 if ((i >= f->mask) && (i < f->mask + f->indices)) {
2725 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2726 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
2727 rx_ring->rx_buf_len =
2728 IXGBE_FCOE_JUMBO_FRAME_SIZE;
2729 }
2730 }
2731
2732 #endif /* IXGBE_FCOE */
2733 ixgbe_configure_srrctl(adapter, rx_ring);
2734 }
2735
2736 if (hw->mac.type == ixgbe_mac_82598EB) {
2737 /*
2738 * For VMDq support of different descriptor types or
2739 * buffer sizes through the use of multiple SRRCTL
2740 * registers, RDRXCTL.MVMEN must be set to 1
2741 *
2742 * also, the manual doesn't mention it clearly but DCA hints
2743 * will only use queue 0's tags unless this bit is set. Side
2744 * effects of setting this bit are only that SRRCTL must be
2745 * fully programmed [0..15]
2746 */
2747 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2748 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
2749 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2750 }
2751
2752 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2753 u32 vt_reg_bits;
2754 u32 reg_offset, vf_shift;
2755 u32 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2756 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN
2757 | IXGBE_VT_CTL_REPLEN;
2758 vt_reg_bits |= (adapter->num_vfs <<
2759 IXGBE_VT_CTL_POOL_SHIFT);
2760 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
2761 IXGBE_WRITE_REG(hw, IXGBE_MRQC, 0);
2762
2763 vf_shift = adapter->num_vfs % 32;
2764 reg_offset = adapter->num_vfs / 32;
2765 IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), 0);
2766 IXGBE_WRITE_REG(hw, IXGBE_VFRE(1), 0);
2767 IXGBE_WRITE_REG(hw, IXGBE_VFTE(0), 0);
2768 IXGBE_WRITE_REG(hw, IXGBE_VFTE(1), 0);
2769 /* Enable only the PF's pool for Tx/Rx */
2770 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
2771 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
2772 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2773 ixgbe_set_vmolr(hw, adapter->num_vfs, true);
2774 }
2775
2776 /* Program MRQC for the distribution of queues */
2777 mrqc = ixgbe_setup_mrqc(adapter);
2778
2779 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
2780 /* Fill out redirection table */
2781 for (i = 0, j = 0; i < 128; i++, j++) {
2782 if (j == adapter->ring_feature[RING_F_RSS].indices)
2783 j = 0;
2784 /* reta = 4-byte sliding window of
2785 * 0x00..(indices-1)(indices-1)00..etc. */
2786 reta = (reta << 8) | (j * 0x11);
2787 if ((i & 3) == 3)
2788 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2789 }
2790
2791 /* Fill out hash function seeds */
2792 for (i = 0; i < 10; i++)
2793 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2794
2795 if (hw->mac.type == ixgbe_mac_82598EB)
2796 mrqc |= IXGBE_MRQC_RSSEN;
2797 /* Perform hash on these packet types */
2798 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2799 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2800 | IXGBE_MRQC_RSS_FIELD_IPV6
2801 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2802 }
2803 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2804
2805 if (adapter->num_vfs) {
2806 u32 reg;
2807
2808 /* Map PF MAC address in RAR Entry 0 to first pool
2809 * following VFs */
2810 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
2811
2812 /* Set up VF register offsets for selected VT Mode, i.e.
2813 * 64 VFs for SR-IOV */
2814 reg = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
2815 reg |= IXGBE_GCR_EXT_SRIOV;
2816 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, reg);
2817 }
2818
2819 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2820
2821 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
2822 adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
2823 /* Disable indicating checksum in descriptor, enables
2824 * RSS hash */
2825 rxcsum |= IXGBE_RXCSUM_PCSD;
2826 }
2827 if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
2828 /* Enable IPv4 payload checksum for UDP fragments
2829 * if PCSD is not set */
2830 rxcsum |= IXGBE_RXCSUM_IPPCSE;
2831 }
2832
2833 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2834
2835 if (hw->mac.type == ixgbe_mac_82599EB) {
2836 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2837 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
2838 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
2839 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2840 }
2841
2842 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
2843 /* Enable 82599 HW-RSC */
2844 for (i = 0; i < adapter->num_rx_queues; i++)
2845 ixgbe_configure_rscctl(adapter, i);
2846
2847 /* Disable RSC for ACK packets */
2848 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
2849 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
2850 }
2851 }
2852
2853 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
2854 {
2855 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2856 struct ixgbe_hw *hw = &adapter->hw;
2857 int pool_ndx = adapter->num_vfs;
2858
2859 /* add VID to filter table */
2860 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
2861 }
2862
2863 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
2864 {
2865 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2866 struct ixgbe_hw *hw = &adapter->hw;
2867 int pool_ndx = adapter->num_vfs;
2868
2869 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2870 ixgbe_irq_disable(adapter);
2871
2872 vlan_group_set_device(adapter->vlgrp, vid, NULL);
2873
2874 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2875 ixgbe_irq_enable(adapter);
2876
2877 /* remove VID from filter table */
2878 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
2879 }
2880
2881 /**
2882 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
2883 * @adapter: driver data
2884 */
2885 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
2886 {
2887 struct ixgbe_hw *hw = &adapter->hw;
2888 u32 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2889 int i, j;
2890
2891 switch (hw->mac.type) {
2892 case ixgbe_mac_82598EB:
2893 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
2894 #ifdef CONFIG_IXGBE_DCB
2895 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
2896 vlnctrl &= ~IXGBE_VLNCTRL_VME;
2897 #endif
2898 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2899 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2900 break;
2901 case ixgbe_mac_82599EB:
2902 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
2903 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2904 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2905 #ifdef CONFIG_IXGBE_DCB
2906 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
2907 break;
2908 #endif
2909 for (i = 0; i < adapter->num_rx_queues; i++) {
2910 j = adapter->rx_ring[i]->reg_idx;
2911 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2912 vlnctrl &= ~IXGBE_RXDCTL_VME;
2913 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2914 }
2915 break;
2916 default:
2917 break;
2918 }
2919 }
2920
2921 /**
2922 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
2923 * @adapter: driver data
2924 */
2925 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
2926 {
2927 struct ixgbe_hw *hw = &adapter->hw;
2928 u32 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2929 int i, j;
2930
2931 switch (hw->mac.type) {
2932 case ixgbe_mac_82598EB:
2933 vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2934 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2935 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2936 break;
2937 case ixgbe_mac_82599EB:
2938 vlnctrl |= IXGBE_VLNCTRL_VFE;
2939 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2940 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2941 for (i = 0; i < adapter->num_rx_queues; i++) {
2942 j = adapter->rx_ring[i]->reg_idx;
2943 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2944 vlnctrl |= IXGBE_RXDCTL_VME;
2945 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2946 }
2947 break;
2948 default:
2949 break;
2950 }
2951 }
2952
2953 static void ixgbe_vlan_rx_register(struct net_device *netdev,
2954 struct vlan_group *grp)
2955 {
2956 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2957
2958 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2959 ixgbe_irq_disable(adapter);
2960 adapter->vlgrp = grp;
2961
2962 /*
2963 * For a DCB driver, always enable VLAN tag stripping so we can
2964 * still receive traffic from a DCB-enabled host even if we're
2965 * not in DCB mode.
2966 */
2967 ixgbe_vlan_filter_enable(adapter);
2968
2969 ixgbe_vlan_rx_add_vid(netdev, 0);
2970
2971 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2972 ixgbe_irq_enable(adapter);
2973 }
2974
2975 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
2976 {
2977 ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
2978
2979 if (adapter->vlgrp) {
2980 u16 vid;
2981 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
2982 if (!vlan_group_get_device(adapter->vlgrp, vid))
2983 continue;
2984 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
2985 }
2986 }
2987 }
2988
2989 /**
2990 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
2991 * @netdev: network interface device structure
2992 *
2993 * Writes unicast address list to the RAR table.
2994 * Returns: -ENOMEM on failure/insufficient address space
2995 * 0 on no addresses written
2996 * X on writing X addresses to the RAR table
2997 **/
2998 static int ixgbe_write_uc_addr_list(struct net_device *netdev)
2999 {
3000 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3001 struct ixgbe_hw *hw = &adapter->hw;
3002 unsigned int vfn = adapter->num_vfs;
3003 unsigned int rar_entries = hw->mac.num_rar_entries - (vfn + 1);
3004 int count = 0;
3005
3006 /* return ENOMEM indicating insufficient memory for addresses */
3007 if (netdev_uc_count(netdev) > rar_entries)
3008 return -ENOMEM;
3009
3010 if (!netdev_uc_empty(netdev) && rar_entries) {
3011 struct netdev_hw_addr *ha;
3012 /* return error if we do not support writing to RAR table */
3013 if (!hw->mac.ops.set_rar)
3014 return -ENOMEM;
3015
3016 netdev_for_each_uc_addr(ha, netdev) {
3017 if (!rar_entries)
3018 break;
3019 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3020 vfn, IXGBE_RAH_AV);
3021 count++;
3022 }
3023 }
3024 /* write the addresses in reverse order to avoid write combining */
3025 for (; rar_entries > 0 ; rar_entries--)
3026 hw->mac.ops.clear_rar(hw, rar_entries);
3027
3028 return count;
3029 }
3030
3031 /**
3032 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
3033 * @netdev: network interface device structure
3034 *
3035 * The set_rx_method entry point is called whenever the unicast/multicast
3036 * address list or the network interface flags are updated. This routine is
3037 * responsible for configuring the hardware for proper unicast, multicast and
3038 * promiscuous mode.
3039 **/
3040 void ixgbe_set_rx_mode(struct net_device *netdev)
3041 {
3042 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3043 struct ixgbe_hw *hw = &adapter->hw;
3044 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3045 int count;
3046
3047 /* Check for Promiscuous and All Multicast modes */
3048
3049 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3050
3051 /* clear the bits we are changing the status of */
3052 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3053
3054 if (netdev->flags & IFF_PROMISC) {
3055 hw->addr_ctrl.user_set_promisc = true;
3056 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3057 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
3058 /* don't hardware filter vlans in promisc mode */
3059 ixgbe_vlan_filter_disable(adapter);
3060 } else {
3061 if (netdev->flags & IFF_ALLMULTI) {
3062 fctrl |= IXGBE_FCTRL_MPE;
3063 vmolr |= IXGBE_VMOLR_MPE;
3064 } else {
3065 /*
3066 * Write addresses to the MTA, if the attempt fails
3067 * then we should just turn on promiscous mode so
3068 * that we can at least receive multicast traffic
3069 */
3070 hw->mac.ops.update_mc_addr_list(hw, netdev);
3071 vmolr |= IXGBE_VMOLR_ROMPE;
3072 }
3073 ixgbe_vlan_filter_enable(adapter);
3074 hw->addr_ctrl.user_set_promisc = false;
3075 /*
3076 * Write addresses to available RAR registers, if there is not
3077 * sufficient space to store all the addresses then enable
3078 * unicast promiscous mode
3079 */
3080 count = ixgbe_write_uc_addr_list(netdev);
3081 if (count < 0) {
3082 fctrl |= IXGBE_FCTRL_UPE;
3083 vmolr |= IXGBE_VMOLR_ROPE;
3084 }
3085 }
3086
3087 if (adapter->num_vfs) {
3088 ixgbe_restore_vf_multicasts(adapter);
3089 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3090 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3091 IXGBE_VMOLR_ROPE);
3092 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3093 }
3094
3095 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3096 }
3097
3098 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3099 {
3100 int q_idx;
3101 struct ixgbe_q_vector *q_vector;
3102 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3103
3104 /* legacy and MSI only use one vector */
3105 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3106 q_vectors = 1;
3107
3108 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3109 struct napi_struct *napi;
3110 q_vector = adapter->q_vector[q_idx];
3111 napi = &q_vector->napi;
3112 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3113 if (!q_vector->rxr_count || !q_vector->txr_count) {
3114 if (q_vector->txr_count == 1)
3115 napi->poll = &ixgbe_clean_txonly;
3116 else if (q_vector->rxr_count == 1)
3117 napi->poll = &ixgbe_clean_rxonly;
3118 }
3119 }
3120
3121 napi_enable(napi);
3122 }
3123 }
3124
3125 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3126 {
3127 int q_idx;
3128 struct ixgbe_q_vector *q_vector;
3129 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3130
3131 /* legacy and MSI only use one vector */
3132 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3133 q_vectors = 1;
3134
3135 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3136 q_vector = adapter->q_vector[q_idx];
3137 napi_disable(&q_vector->napi);
3138 }
3139 }
3140
3141 #ifdef CONFIG_IXGBE_DCB
3142 /*
3143 * ixgbe_configure_dcb - Configure DCB hardware
3144 * @adapter: ixgbe adapter struct
3145 *
3146 * This is called by the driver on open to configure the DCB hardware.
3147 * This is also called by the gennetlink interface when reconfiguring
3148 * the DCB state.
3149 */
3150 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3151 {
3152 struct ixgbe_hw *hw = &adapter->hw;
3153 u32 txdctl;
3154 int i, j;
3155
3156 ixgbe_dcb_check_config(&adapter->dcb_cfg);
3157 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
3158 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
3159
3160 /* reconfigure the hardware */
3161 ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
3162
3163 for (i = 0; i < adapter->num_tx_queues; i++) {
3164 j = adapter->tx_ring[i]->reg_idx;
3165 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3166 txdctl |= 32;
3167 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
3168 }
3169 /* Enable VLAN tag insert/strip */
3170 ixgbe_vlan_filter_enable(adapter);
3171
3172 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
3173 }
3174
3175 #endif
3176 static void ixgbe_configure(struct ixgbe_adapter *adapter)
3177 {
3178 struct net_device *netdev = adapter->netdev;
3179 struct ixgbe_hw *hw = &adapter->hw;
3180 int i;
3181
3182 ixgbe_set_rx_mode(netdev);
3183
3184 ixgbe_restore_vlan(adapter);
3185 #ifdef CONFIG_IXGBE_DCB
3186 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3187 if (hw->mac.type == ixgbe_mac_82598EB)
3188 netif_set_gso_max_size(netdev, 32768);
3189 else
3190 netif_set_gso_max_size(netdev, 65536);
3191 ixgbe_configure_dcb(adapter);
3192 } else {
3193 netif_set_gso_max_size(netdev, 65536);
3194 }
3195 #else
3196 netif_set_gso_max_size(netdev, 65536);
3197 #endif
3198
3199 #ifdef IXGBE_FCOE
3200 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3201 ixgbe_configure_fcoe(adapter);
3202
3203 #endif /* IXGBE_FCOE */
3204 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3205 for (i = 0; i < adapter->num_tx_queues; i++)
3206 adapter->tx_ring[i]->atr_sample_rate =
3207 adapter->atr_sample_rate;
3208 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
3209 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3210 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
3211 }
3212
3213 ixgbe_configure_tx(adapter);
3214 ixgbe_configure_rx(adapter);
3215 for (i = 0; i < adapter->num_rx_queues; i++)
3216 ixgbe_alloc_rx_buffers(adapter, adapter->rx_ring[i],
3217 (adapter->rx_ring[i]->count - 1));
3218 }
3219
3220 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3221 {
3222 switch (hw->phy.type) {
3223 case ixgbe_phy_sfp_avago:
3224 case ixgbe_phy_sfp_ftl:
3225 case ixgbe_phy_sfp_intel:
3226 case ixgbe_phy_sfp_unknown:
3227 case ixgbe_phy_sfp_passive_tyco:
3228 case ixgbe_phy_sfp_passive_unknown:
3229 case ixgbe_phy_sfp_active_unknown:
3230 case ixgbe_phy_sfp_ftl_active:
3231 return true;
3232 default:
3233 return false;
3234 }
3235 }
3236
3237 /**
3238 * ixgbe_sfp_link_config - set up SFP+ link
3239 * @adapter: pointer to private adapter struct
3240 **/
3241 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3242 {
3243 struct ixgbe_hw *hw = &adapter->hw;
3244
3245 if (hw->phy.multispeed_fiber) {
3246 /*
3247 * In multispeed fiber setups, the device may not have
3248 * had a physical connection when the driver loaded.
3249 * If that's the case, the initial link configuration
3250 * couldn't get the MAC into 10G or 1G mode, so we'll
3251 * never have a link status change interrupt fire.
3252 * We need to try and force an autonegotiation
3253 * session, then bring up link.
3254 */
3255 hw->mac.ops.setup_sfp(hw);
3256 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
3257 schedule_work(&adapter->multispeed_fiber_task);
3258 } else {
3259 /*
3260 * Direct Attach Cu and non-multispeed fiber modules
3261 * still need to be configured properly prior to
3262 * attempting link.
3263 */
3264 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
3265 schedule_work(&adapter->sfp_config_module_task);
3266 }
3267 }
3268
3269 /**
3270 * ixgbe_non_sfp_link_config - set up non-SFP+ link
3271 * @hw: pointer to private hardware struct
3272 *
3273 * Returns 0 on success, negative on failure
3274 **/
3275 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
3276 {
3277 u32 autoneg;
3278 bool negotiation, link_up = false;
3279 u32 ret = IXGBE_ERR_LINK_SETUP;
3280
3281 if (hw->mac.ops.check_link)
3282 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3283
3284 if (ret)
3285 goto link_cfg_out;
3286
3287 if (hw->mac.ops.get_link_capabilities)
3288 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
3289 if (ret)
3290 goto link_cfg_out;
3291
3292 if (hw->mac.ops.setup_link)
3293 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
3294 link_cfg_out:
3295 return ret;
3296 }
3297
3298 #define IXGBE_MAX_RX_DESC_POLL 10
3299 static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3300 int rxr)
3301 {
3302 int j = adapter->rx_ring[rxr]->reg_idx;
3303 int k;
3304
3305 for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) {
3306 if (IXGBE_READ_REG(&adapter->hw,
3307 IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
3308 break;
3309 else
3310 msleep(1);
3311 }
3312 if (k >= IXGBE_MAX_RX_DESC_POLL) {
3313 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3314 "the polling period\n", rxr);
3315 }
3316 ixgbe_release_rx_desc(&adapter->hw, adapter->rx_ring[rxr],
3317 (adapter->rx_ring[rxr]->count - 1));
3318 }
3319
3320 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
3321 {
3322 struct net_device *netdev = adapter->netdev;
3323 struct ixgbe_hw *hw = &adapter->hw;
3324 int i, j = 0;
3325 int num_rx_rings = adapter->num_rx_queues;
3326 int err;
3327 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3328 u32 txdctl, rxdctl, mhadd;
3329 u32 dmatxctl;
3330 u32 gpie;
3331 u32 ctrl_ext;
3332
3333 ixgbe_get_hw_control(adapter);
3334
3335 if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
3336 (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
3337 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3338 gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
3339 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
3340 } else {
3341 /* MSI only */
3342 gpie = 0;
3343 }
3344 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3345 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3346 gpie |= IXGBE_GPIE_VTMODE_64;
3347 }
3348 /* gpie |= IXGBE_GPIE_EIMEN; */
3349 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3350 }
3351
3352 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3353 /*
3354 * use EIAM to auto-mask when MSI-X interrupt is asserted
3355 * this saves a register write for every interrupt
3356 */
3357 switch (hw->mac.type) {
3358 case ixgbe_mac_82598EB:
3359 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3360 break;
3361 default:
3362 case ixgbe_mac_82599EB:
3363 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3364 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3365 break;
3366 }
3367 } else {
3368 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3369 * specifically only auto mask tx and rx interrupts */
3370 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3371 }
3372
3373 /* Enable Thermal over heat sensor interrupt */
3374 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
3375 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
3376 gpie |= IXGBE_SDP0_GPIEN;
3377 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3378 }
3379
3380 /* Enable fan failure interrupt if media type is copper */
3381 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3382 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
3383 gpie |= IXGBE_SDP1_GPIEN;
3384 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3385 }
3386
3387 if (hw->mac.type == ixgbe_mac_82599EB) {
3388 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
3389 gpie |= IXGBE_SDP1_GPIEN;
3390 gpie |= IXGBE_SDP2_GPIEN;
3391 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3392 }
3393
3394 #ifdef IXGBE_FCOE
3395 /* adjust max frame to be able to do baby jumbo for FCoE */
3396 if ((netdev->features & NETIF_F_FCOE_MTU) &&
3397 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3398 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3399
3400 #endif /* IXGBE_FCOE */
3401 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3402 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3403 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3404 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3405
3406 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3407 }
3408
3409 for (i = 0; i < adapter->num_tx_queues; i++) {
3410 j = adapter->tx_ring[i]->reg_idx;
3411 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3412 if (adapter->rx_itr_setting == 0) {
3413 /* cannot set wthresh when itr==0 */
3414 txdctl &= ~0x007F0000;
3415 } else {
3416 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
3417 txdctl |= (8 << 16);
3418 }
3419 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
3420 }
3421
3422 if (hw->mac.type == ixgbe_mac_82599EB) {
3423 /* DMATXCTL.EN must be set after all Tx queue config is done */
3424 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
3425 dmatxctl |= IXGBE_DMATXCTL_TE;
3426 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
3427 }
3428 for (i = 0; i < adapter->num_tx_queues; i++) {
3429 j = adapter->tx_ring[i]->reg_idx;
3430 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3431 txdctl |= IXGBE_TXDCTL_ENABLE;
3432 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
3433 if (hw->mac.type == ixgbe_mac_82599EB) {
3434 int wait_loop = 10;
3435 /* poll for Tx Enable ready */
3436 do {
3437 msleep(1);
3438 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3439 } while (--wait_loop &&
3440 !(txdctl & IXGBE_TXDCTL_ENABLE));
3441 if (!wait_loop)
3442 e_err(drv, "Could not enable Tx Queue %d\n", j);
3443 }
3444 }
3445
3446 for (i = 0; i < num_rx_rings; i++) {
3447 j = adapter->rx_ring[i]->reg_idx;
3448 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3449 /* enable PTHRESH=32 descriptors (half the internal cache)
3450 * and HTHRESH=0 descriptors (to minimize latency on fetch),
3451 * this also removes a pesky rx_no_buffer_count increment */
3452 rxdctl |= 0x0020;
3453 rxdctl |= IXGBE_RXDCTL_ENABLE;
3454 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
3455 if (hw->mac.type == ixgbe_mac_82599EB)
3456 ixgbe_rx_desc_queue_enable(adapter, i);
3457 }
3458 /* enable all receives */
3459 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3460 if (hw->mac.type == ixgbe_mac_82598EB)
3461 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
3462 else
3463 rxdctl |= IXGBE_RXCTRL_RXEN;
3464 hw->mac.ops.enable_rx_dma(hw, rxdctl);
3465
3466 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3467 ixgbe_configure_msix(adapter);
3468 else
3469 ixgbe_configure_msi_and_legacy(adapter);
3470
3471 /* enable the optics */
3472 if (hw->phy.multispeed_fiber)
3473 hw->mac.ops.enable_tx_laser(hw);
3474
3475 clear_bit(__IXGBE_DOWN, &adapter->state);
3476 ixgbe_napi_enable_all(adapter);
3477
3478 /* clear any pending interrupts, may auto mask */
3479 IXGBE_READ_REG(hw, IXGBE_EICR);
3480
3481 ixgbe_irq_enable(adapter);
3482
3483 /*
3484 * If this adapter has a fan, check to see if we had a failure
3485 * before we enabled the interrupt.
3486 */
3487 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3488 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3489 if (esdp & IXGBE_ESDP_SDP1)
3490 e_crit(drv, "Fan has stopped, replace the adapter\n");
3491 }
3492
3493 /*
3494 * For hot-pluggable SFP+ devices, a new SFP+ module may have
3495 * arrived before interrupts were enabled but after probe. Such
3496 * devices wouldn't have their type identified yet. We need to
3497 * kick off the SFP+ module setup first, then try to bring up link.
3498 * If we're not hot-pluggable SFP+, we just need to configure link
3499 * and bring it up.
3500 */
3501 if (hw->phy.type == ixgbe_phy_unknown) {
3502 err = hw->phy.ops.identify(hw);
3503 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
3504 /*
3505 * Take the device down and schedule the sfp tasklet
3506 * which will unregister_netdev and log it.
3507 */
3508 ixgbe_down(adapter);
3509 schedule_work(&adapter->sfp_config_module_task);
3510 return err;
3511 }
3512 }
3513
3514 if (ixgbe_is_sfp(hw)) {
3515 ixgbe_sfp_link_config(adapter);
3516 } else {
3517 err = ixgbe_non_sfp_link_config(hw);
3518 if (err)
3519 e_err(probe, "link_config FAILED %d\n", err);
3520 }
3521
3522 for (i = 0; i < adapter->num_tx_queues; i++)
3523 set_bit(__IXGBE_FDIR_INIT_DONE,
3524 &(adapter->tx_ring[i]->reinit_state));
3525
3526 /* enable transmits */
3527 netif_tx_start_all_queues(netdev);
3528
3529 /* bring the link up in the watchdog, this could race with our first
3530 * link up interrupt but shouldn't be a problem */
3531 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3532 adapter->link_check_timeout = jiffies;
3533 mod_timer(&adapter->watchdog_timer, jiffies);
3534
3535 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3536 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3537 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3538 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3539
3540 return 0;
3541 }
3542
3543 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3544 {
3545 WARN_ON(in_interrupt());
3546 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
3547 msleep(1);
3548 ixgbe_down(adapter);
3549 /*
3550 * If SR-IOV enabled then wait a bit before bringing the adapter
3551 * back up to give the VFs time to respond to the reset. The
3552 * two second wait is based upon the watchdog timer cycle in
3553 * the VF driver.
3554 */
3555 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3556 msleep(2000);
3557 ixgbe_up(adapter);
3558 clear_bit(__IXGBE_RESETTING, &adapter->state);
3559 }
3560
3561 int ixgbe_up(struct ixgbe_adapter *adapter)
3562 {
3563 /* hardware has been reset, we need to reload some things */
3564 ixgbe_configure(adapter);
3565
3566 return ixgbe_up_complete(adapter);
3567 }
3568
3569 void ixgbe_reset(struct ixgbe_adapter *adapter)
3570 {
3571 struct ixgbe_hw *hw = &adapter->hw;
3572 int err;
3573
3574 err = hw->mac.ops.init_hw(hw);
3575 switch (err) {
3576 case 0:
3577 case IXGBE_ERR_SFP_NOT_PRESENT:
3578 break;
3579 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
3580 e_dev_err("master disable timed out\n");
3581 break;
3582 case IXGBE_ERR_EEPROM_VERSION:
3583 /* We are running on a pre-production device, log a warning */
3584 e_dev_warn("This device is a pre-production adapter/LOM. "
3585 "Please be aware there may be issuesassociated with "
3586 "your hardware. If you are experiencing problems "
3587 "please contact your Intel or hardware "
3588 "representative who provided you with this "
3589 "hardware.\n");
3590 break;
3591 default:
3592 e_dev_err("Hardware Error: %d\n", err);
3593 }
3594
3595 /* reprogram the RAR[0] in case user changed it. */
3596 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3597 IXGBE_RAH_AV);
3598 }
3599
3600 /**
3601 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
3602 * @adapter: board private structure
3603 * @rx_ring: ring to free buffers from
3604 **/
3605 static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
3606 struct ixgbe_ring *rx_ring)
3607 {
3608 struct pci_dev *pdev = adapter->pdev;
3609 unsigned long size;
3610 unsigned int i;
3611
3612 /* Free all the Rx ring sk_buffs */
3613
3614 for (i = 0; i < rx_ring->count; i++) {
3615 struct ixgbe_rx_buffer *rx_buffer_info;
3616
3617 rx_buffer_info = &rx_ring->rx_buffer_info[i];
3618 if (rx_buffer_info->dma) {
3619 dma_unmap_single(&pdev->dev, rx_buffer_info->dma,
3620 rx_ring->rx_buf_len,
3621 DMA_FROM_DEVICE);
3622 rx_buffer_info->dma = 0;
3623 }
3624 if (rx_buffer_info->skb) {
3625 struct sk_buff *skb = rx_buffer_info->skb;
3626 rx_buffer_info->skb = NULL;
3627 do {
3628 struct sk_buff *this = skb;
3629 if (IXGBE_RSC_CB(this)->delay_unmap) {
3630 dma_unmap_single(&pdev->dev,
3631 IXGBE_RSC_CB(this)->dma,
3632 rx_ring->rx_buf_len,
3633 DMA_FROM_DEVICE);
3634 IXGBE_RSC_CB(this)->dma = 0;
3635 IXGBE_RSC_CB(skb)->delay_unmap = false;
3636 }
3637 skb = skb->prev;
3638 dev_kfree_skb(this);
3639 } while (skb);
3640 }
3641 if (!rx_buffer_info->page)
3642 continue;
3643 if (rx_buffer_info->page_dma) {
3644 dma_unmap_page(&pdev->dev, rx_buffer_info->page_dma,
3645 PAGE_SIZE / 2, DMA_FROM_DEVICE);
3646 rx_buffer_info->page_dma = 0;
3647 }
3648 put_page(rx_buffer_info->page);
3649 rx_buffer_info->page = NULL;
3650 rx_buffer_info->page_offset = 0;
3651 }
3652
3653 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3654 memset(rx_ring->rx_buffer_info, 0, size);
3655
3656 /* Zero out the descriptor ring */
3657 memset(rx_ring->desc, 0, rx_ring->size);
3658
3659 rx_ring->next_to_clean = 0;
3660 rx_ring->next_to_use = 0;
3661
3662 if (rx_ring->head)
3663 writel(0, adapter->hw.hw_addr + rx_ring->head);
3664 if (rx_ring->tail)
3665 writel(0, adapter->hw.hw_addr + rx_ring->tail);
3666 }
3667
3668 /**
3669 * ixgbe_clean_tx_ring - Free Tx Buffers
3670 * @adapter: board private structure
3671 * @tx_ring: ring to be cleaned
3672 **/
3673 static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
3674 struct ixgbe_ring *tx_ring)
3675 {
3676 struct ixgbe_tx_buffer *tx_buffer_info;
3677 unsigned long size;
3678 unsigned int i;
3679
3680 /* Free all the Tx ring sk_buffs */
3681
3682 for (i = 0; i < tx_ring->count; i++) {
3683 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3684 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
3685 }
3686
3687 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3688 memset(tx_ring->tx_buffer_info, 0, size);
3689
3690 /* Zero out the descriptor ring */
3691 memset(tx_ring->desc, 0, tx_ring->size);
3692
3693 tx_ring->next_to_use = 0;
3694 tx_ring->next_to_clean = 0;
3695
3696 if (tx_ring->head)
3697 writel(0, adapter->hw.hw_addr + tx_ring->head);
3698 if (tx_ring->tail)
3699 writel(0, adapter->hw.hw_addr + tx_ring->tail);
3700 }
3701
3702 /**
3703 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
3704 * @adapter: board private structure
3705 **/
3706 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
3707 {
3708 int i;
3709
3710 for (i = 0; i < adapter->num_rx_queues; i++)
3711 ixgbe_clean_rx_ring(adapter, adapter->rx_ring[i]);
3712 }
3713
3714 /**
3715 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
3716 * @adapter: board private structure
3717 **/
3718 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
3719 {
3720 int i;
3721
3722 for (i = 0; i < adapter->num_tx_queues; i++)
3723 ixgbe_clean_tx_ring(adapter, adapter->tx_ring[i]);
3724 }
3725
3726 void ixgbe_down(struct ixgbe_adapter *adapter)
3727 {
3728 struct net_device *netdev = adapter->netdev;
3729 struct ixgbe_hw *hw = &adapter->hw;
3730 u32 rxctrl;
3731 u32 txdctl;
3732 int i, j;
3733
3734 /* signal that we are down to the interrupt handler */
3735 set_bit(__IXGBE_DOWN, &adapter->state);
3736
3737 /* disable receive for all VFs and wait one second */
3738 if (adapter->num_vfs) {
3739 /* ping all the active vfs to let them know we are going down */
3740 ixgbe_ping_all_vfs(adapter);
3741
3742 /* Disable all VFTE/VFRE TX/RX */
3743 ixgbe_disable_tx_rx(adapter);
3744
3745 /* Mark all the VFs as inactive */
3746 for (i = 0 ; i < adapter->num_vfs; i++)
3747 adapter->vfinfo[i].clear_to_send = 0;
3748 }
3749
3750 /* disable receives */
3751 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3752 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3753
3754 IXGBE_WRITE_FLUSH(hw);
3755 msleep(10);
3756
3757 netif_tx_stop_all_queues(netdev);
3758
3759 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3760 del_timer_sync(&adapter->sfp_timer);
3761 del_timer_sync(&adapter->watchdog_timer);
3762 cancel_work_sync(&adapter->watchdog_task);
3763
3764 netif_carrier_off(netdev);
3765 netif_tx_disable(netdev);
3766
3767 ixgbe_irq_disable(adapter);
3768
3769 ixgbe_napi_disable_all(adapter);
3770
3771 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3772 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3773 cancel_work_sync(&adapter->fdir_reinit_task);
3774
3775 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
3776 cancel_work_sync(&adapter->check_overtemp_task);
3777
3778 /* disable transmits in the hardware now that interrupts are off */
3779 for (i = 0; i < adapter->num_tx_queues; i++) {
3780 j = adapter->tx_ring[i]->reg_idx;
3781 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3782 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
3783 (txdctl & ~IXGBE_TXDCTL_ENABLE));
3784 }
3785 /* Disable the Tx DMA engine on 82599 */
3786 if (hw->mac.type == ixgbe_mac_82599EB)
3787 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
3788 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
3789 ~IXGBE_DMATXCTL_TE));
3790
3791 /* power down the optics */
3792 if (hw->phy.multispeed_fiber)
3793 hw->mac.ops.disable_tx_laser(hw);
3794
3795 /* clear n-tuple filters that are cached */
3796 ethtool_ntuple_flush(netdev);
3797
3798 if (!pci_channel_offline(adapter->pdev))
3799 ixgbe_reset(adapter);
3800 ixgbe_clean_all_tx_rings(adapter);
3801 ixgbe_clean_all_rx_rings(adapter);
3802
3803 #ifdef CONFIG_IXGBE_DCA
3804 /* since we reset the hardware DCA settings were cleared */
3805 ixgbe_setup_dca(adapter);
3806 #endif
3807 }
3808
3809 /**
3810 * ixgbe_poll - NAPI Rx polling callback
3811 * @napi: structure for representing this polling device
3812 * @budget: how many packets driver is allowed to clean
3813 *
3814 * This function is used for legacy and MSI, NAPI mode
3815 **/
3816 static int ixgbe_poll(struct napi_struct *napi, int budget)
3817 {
3818 struct ixgbe_q_vector *q_vector =
3819 container_of(napi, struct ixgbe_q_vector, napi);
3820 struct ixgbe_adapter *adapter = q_vector->adapter;
3821 int tx_clean_complete, work_done = 0;
3822
3823 #ifdef CONFIG_IXGBE_DCA
3824 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
3825 ixgbe_update_tx_dca(adapter, adapter->tx_ring[0]);
3826 ixgbe_update_rx_dca(adapter, adapter->rx_ring[0]);
3827 }
3828 #endif
3829
3830 tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring[0]);
3831 ixgbe_clean_rx_irq(q_vector, adapter->rx_ring[0], &work_done, budget);
3832
3833 if (!tx_clean_complete)
3834 work_done = budget;
3835
3836 /* If budget not fully consumed, exit the polling mode */
3837 if (work_done < budget) {
3838 napi_complete(napi);
3839 if (adapter->rx_itr_setting & 1)
3840 ixgbe_set_itr(adapter);
3841 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3842 ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
3843 }
3844 return work_done;
3845 }
3846
3847 /**
3848 * ixgbe_tx_timeout - Respond to a Tx Hang
3849 * @netdev: network interface device structure
3850 **/
3851 static void ixgbe_tx_timeout(struct net_device *netdev)
3852 {
3853 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3854
3855 /* Do the reset outside of interrupt context */
3856 schedule_work(&adapter->reset_task);
3857 }
3858
3859 static void ixgbe_reset_task(struct work_struct *work)
3860 {
3861 struct ixgbe_adapter *adapter;
3862 adapter = container_of(work, struct ixgbe_adapter, reset_task);
3863
3864 /* If we're already down or resetting, just bail */
3865 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
3866 test_bit(__IXGBE_RESETTING, &adapter->state))
3867 return;
3868
3869 adapter->tx_timeout_count++;
3870
3871 ixgbe_dump(adapter);
3872 netdev_err(adapter->netdev, "Reset adapter\n");
3873 ixgbe_reinit_locked(adapter);
3874 }
3875
3876 #ifdef CONFIG_IXGBE_DCB
3877 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
3878 {
3879 bool ret = false;
3880 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
3881
3882 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
3883 return ret;
3884
3885 f->mask = 0x7 << 3;
3886 adapter->num_rx_queues = f->indices;
3887 adapter->num_tx_queues = f->indices;
3888 ret = true;
3889
3890 return ret;
3891 }
3892 #endif
3893
3894 /**
3895 * ixgbe_set_rss_queues: Allocate queues for RSS
3896 * @adapter: board private structure to initialize
3897 *
3898 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
3899 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
3900 *
3901 **/
3902 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
3903 {
3904 bool ret = false;
3905 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
3906
3907 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3908 f->mask = 0xF;
3909 adapter->num_rx_queues = f->indices;
3910 adapter->num_tx_queues = f->indices;
3911 ret = true;
3912 } else {
3913 ret = false;
3914 }
3915
3916 return ret;
3917 }
3918
3919 /**
3920 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
3921 * @adapter: board private structure to initialize
3922 *
3923 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
3924 * to the original CPU that initiated the Tx session. This runs in addition
3925 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
3926 * Rx load across CPUs using RSS.
3927 *
3928 **/
3929 static bool inline ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
3930 {
3931 bool ret = false;
3932 struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
3933
3934 f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
3935 f_fdir->mask = 0;
3936
3937 /* Flow Director must have RSS enabled */
3938 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3939 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3940 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
3941 adapter->num_tx_queues = f_fdir->indices;
3942 adapter->num_rx_queues = f_fdir->indices;
3943 ret = true;
3944 } else {
3945 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3946 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3947 }
3948 return ret;
3949 }
3950
3951 #ifdef IXGBE_FCOE
3952 /**
3953 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
3954 * @adapter: board private structure to initialize
3955 *
3956 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
3957 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
3958 * rx queues out of the max number of rx queues, instead, it is used as the
3959 * index of the first rx queue used by FCoE.
3960 *
3961 **/
3962 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
3963 {
3964 bool ret = false;
3965 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3966
3967 f->indices = min((int)num_online_cpus(), f->indices);
3968 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
3969 adapter->num_rx_queues = 1;
3970 adapter->num_tx_queues = 1;
3971 #ifdef CONFIG_IXGBE_DCB
3972 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3973 e_info(probe, "FCoE enabled with DCB\n");
3974 ixgbe_set_dcb_queues(adapter);
3975 }
3976 #endif
3977 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3978 e_info(probe, "FCoE enabled with RSS\n");
3979 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3980 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3981 ixgbe_set_fdir_queues(adapter);
3982 else
3983 ixgbe_set_rss_queues(adapter);
3984 }
3985 /* adding FCoE rx rings to the end */
3986 f->mask = adapter->num_rx_queues;
3987 adapter->num_rx_queues += f->indices;
3988 adapter->num_tx_queues += f->indices;
3989
3990 ret = true;
3991 }
3992
3993 return ret;
3994 }
3995
3996 #endif /* IXGBE_FCOE */
3997 /**
3998 * ixgbe_set_sriov_queues: Allocate queues for IOV use
3999 * @adapter: board private structure to initialize
4000 *
4001 * IOV doesn't actually use anything, so just NAK the
4002 * request for now and let the other queue routines
4003 * figure out what to do.
4004 */
4005 static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
4006 {
4007 return false;
4008 }
4009
4010 /*
4011 * ixgbe_set_num_queues: Allocate queues for device, feature dependant
4012 * @adapter: board private structure to initialize
4013 *
4014 * This is the top level queue allocation routine. The order here is very
4015 * important, starting with the "most" number of features turned on at once,
4016 * and ending with the smallest set of features. This way large combinations
4017 * can be allocated if they're turned on, and smaller combinations are the
4018 * fallthrough conditions.
4019 *
4020 **/
4021 static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
4022 {
4023 /* Start with base case */
4024 adapter->num_rx_queues = 1;
4025 adapter->num_tx_queues = 1;
4026 adapter->num_rx_pools = adapter->num_rx_queues;
4027 adapter->num_rx_queues_per_pool = 1;
4028
4029 if (ixgbe_set_sriov_queues(adapter))
4030 return;
4031
4032 #ifdef IXGBE_FCOE
4033 if (ixgbe_set_fcoe_queues(adapter))
4034 goto done;
4035
4036 #endif /* IXGBE_FCOE */
4037 #ifdef CONFIG_IXGBE_DCB
4038 if (ixgbe_set_dcb_queues(adapter))
4039 goto done;
4040
4041 #endif
4042 if (ixgbe_set_fdir_queues(adapter))
4043 goto done;
4044
4045 if (ixgbe_set_rss_queues(adapter))
4046 goto done;
4047
4048 /* fallback to base case */
4049 adapter->num_rx_queues = 1;
4050 adapter->num_tx_queues = 1;
4051
4052 done:
4053 /* Notify the stack of the (possibly) reduced Tx Queue count. */
4054 netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
4055 }
4056
4057 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
4058 int vectors)
4059 {
4060 int err, vector_threshold;
4061
4062 /* We'll want at least 3 (vector_threshold):
4063 * 1) TxQ[0] Cleanup
4064 * 2) RxQ[0] Cleanup
4065 * 3) Other (Link Status Change, etc.)
4066 * 4) TCP Timer (optional)
4067 */
4068 vector_threshold = MIN_MSIX_COUNT;
4069
4070 /* The more we get, the more we will assign to Tx/Rx Cleanup
4071 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4072 * Right now, we simply care about how many we'll get; we'll
4073 * set them up later while requesting irq's.
4074 */
4075 while (vectors >= vector_threshold) {
4076 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
4077 vectors);
4078 if (!err) /* Success in acquiring all requested vectors. */
4079 break;
4080 else if (err < 0)
4081 vectors = 0; /* Nasty failure, quit now */
4082 else /* err == number of vectors we should try again with */
4083 vectors = err;
4084 }
4085
4086 if (vectors < vector_threshold) {
4087 /* Can't allocate enough MSI-X interrupts? Oh well.
4088 * This just means we'll go with either a single MSI
4089 * vector or fall back to legacy interrupts.
4090 */
4091 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4092 "Unable to allocate MSI-X interrupts\n");
4093 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4094 kfree(adapter->msix_entries);
4095 adapter->msix_entries = NULL;
4096 } else {
4097 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
4098 /*
4099 * Adjust for only the vectors we'll use, which is minimum
4100 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4101 * vectors we were allocated.
4102 */
4103 adapter->num_msix_vectors = min(vectors,
4104 adapter->max_msix_q_vectors + NON_Q_VECTORS);
4105 }
4106 }
4107
4108 /**
4109 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
4110 * @adapter: board private structure to initialize
4111 *
4112 * Cache the descriptor ring offsets for RSS to the assigned rings.
4113 *
4114 **/
4115 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
4116 {
4117 int i;
4118 bool ret = false;
4119
4120 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4121 for (i = 0; i < adapter->num_rx_queues; i++)
4122 adapter->rx_ring[i]->reg_idx = i;
4123 for (i = 0; i < adapter->num_tx_queues; i++)
4124 adapter->tx_ring[i]->reg_idx = i;
4125 ret = true;
4126 } else {
4127 ret = false;
4128 }
4129
4130 return ret;
4131 }
4132
4133 #ifdef CONFIG_IXGBE_DCB
4134 /**
4135 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4136 * @adapter: board private structure to initialize
4137 *
4138 * Cache the descriptor ring offsets for DCB to the assigned rings.
4139 *
4140 **/
4141 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4142 {
4143 int i;
4144 bool ret = false;
4145 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
4146
4147 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4148 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
4149 /* the number of queues is assumed to be symmetric */
4150 for (i = 0; i < dcb_i; i++) {
4151 adapter->rx_ring[i]->reg_idx = i << 3;
4152 adapter->tx_ring[i]->reg_idx = i << 2;
4153 }
4154 ret = true;
4155 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
4156 if (dcb_i == 8) {
4157 /*
4158 * Tx TC0 starts at: descriptor queue 0
4159 * Tx TC1 starts at: descriptor queue 32
4160 * Tx TC2 starts at: descriptor queue 64
4161 * Tx TC3 starts at: descriptor queue 80
4162 * Tx TC4 starts at: descriptor queue 96
4163 * Tx TC5 starts at: descriptor queue 104
4164 * Tx TC6 starts at: descriptor queue 112
4165 * Tx TC7 starts at: descriptor queue 120
4166 *
4167 * Rx TC0-TC7 are offset by 16 queues each
4168 */
4169 for (i = 0; i < 3; i++) {
4170 adapter->tx_ring[i]->reg_idx = i << 5;
4171 adapter->rx_ring[i]->reg_idx = i << 4;
4172 }
4173 for ( ; i < 5; i++) {
4174 adapter->tx_ring[i]->reg_idx =
4175 ((i + 2) << 4);
4176 adapter->rx_ring[i]->reg_idx = i << 4;
4177 }
4178 for ( ; i < dcb_i; i++) {
4179 adapter->tx_ring[i]->reg_idx =
4180 ((i + 8) << 3);
4181 adapter->rx_ring[i]->reg_idx = i << 4;
4182 }
4183
4184 ret = true;
4185 } else if (dcb_i == 4) {
4186 /*
4187 * Tx TC0 starts at: descriptor queue 0
4188 * Tx TC1 starts at: descriptor queue 64
4189 * Tx TC2 starts at: descriptor queue 96
4190 * Tx TC3 starts at: descriptor queue 112
4191 *
4192 * Rx TC0-TC3 are offset by 32 queues each
4193 */
4194 adapter->tx_ring[0]->reg_idx = 0;
4195 adapter->tx_ring[1]->reg_idx = 64;
4196 adapter->tx_ring[2]->reg_idx = 96;
4197 adapter->tx_ring[3]->reg_idx = 112;
4198 for (i = 0 ; i < dcb_i; i++)
4199 adapter->rx_ring[i]->reg_idx = i << 5;
4200
4201 ret = true;
4202 } else {
4203 ret = false;
4204 }
4205 } else {
4206 ret = false;
4207 }
4208 } else {
4209 ret = false;
4210 }
4211
4212 return ret;
4213 }
4214 #endif
4215
4216 /**
4217 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4218 * @adapter: board private structure to initialize
4219 *
4220 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4221 *
4222 **/
4223 static bool inline ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
4224 {
4225 int i;
4226 bool ret = false;
4227
4228 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4229 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4230 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
4231 for (i = 0; i < adapter->num_rx_queues; i++)
4232 adapter->rx_ring[i]->reg_idx = i;
4233 for (i = 0; i < adapter->num_tx_queues; i++)
4234 adapter->tx_ring[i]->reg_idx = i;
4235 ret = true;
4236 }
4237
4238 return ret;
4239 }
4240
4241 #ifdef IXGBE_FCOE
4242 /**
4243 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4244 * @adapter: board private structure to initialize
4245 *
4246 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4247 *
4248 */
4249 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4250 {
4251 int i, fcoe_rx_i = 0, fcoe_tx_i = 0;
4252 bool ret = false;
4253 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4254
4255 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4256 #ifdef CONFIG_IXGBE_DCB
4257 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4258 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
4259
4260 ixgbe_cache_ring_dcb(adapter);
4261 /* find out queues in TC for FCoE */
4262 fcoe_rx_i = adapter->rx_ring[fcoe->tc]->reg_idx + 1;
4263 fcoe_tx_i = adapter->tx_ring[fcoe->tc]->reg_idx + 1;
4264 /*
4265 * In 82599, the number of Tx queues for each traffic
4266 * class for both 8-TC and 4-TC modes are:
4267 * TCs : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
4268 * 8 TCs: 32 32 16 16 8 8 8 8
4269 * 4 TCs: 64 64 32 32
4270 * We have max 8 queues for FCoE, where 8 the is
4271 * FCoE redirection table size. If TC for FCoE is
4272 * less than or equal to TC3, we have enough queues
4273 * to add max of 8 queues for FCoE, so we start FCoE
4274 * tx descriptor from the next one, i.e., reg_idx + 1.
4275 * If TC for FCoE is above TC3, implying 8 TC mode,
4276 * and we need 8 for FCoE, we have to take all queues
4277 * in that traffic class for FCoE.
4278 */
4279 if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3))
4280 fcoe_tx_i--;
4281 }
4282 #endif /* CONFIG_IXGBE_DCB */
4283 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4284 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4285 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4286 ixgbe_cache_ring_fdir(adapter);
4287 else
4288 ixgbe_cache_ring_rss(adapter);
4289
4290 fcoe_rx_i = f->mask;
4291 fcoe_tx_i = f->mask;
4292 }
4293 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4294 adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4295 adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
4296 }
4297 ret = true;
4298 }
4299 return ret;
4300 }
4301
4302 #endif /* IXGBE_FCOE */
4303 /**
4304 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4305 * @adapter: board private structure to initialize
4306 *
4307 * SR-IOV doesn't use any descriptor rings but changes the default if
4308 * no other mapping is used.
4309 *
4310 */
4311 static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4312 {
4313 adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4314 adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
4315 if (adapter->num_vfs)
4316 return true;
4317 else
4318 return false;
4319 }
4320
4321 /**
4322 * ixgbe_cache_ring_register - Descriptor ring to register mapping
4323 * @adapter: board private structure to initialize
4324 *
4325 * Once we know the feature-set enabled for the device, we'll cache
4326 * the register offset the descriptor ring is assigned to.
4327 *
4328 * Note, the order the various feature calls is important. It must start with
4329 * the "most" features enabled at the same time, then trickle down to the
4330 * least amount of features turned on at once.
4331 **/
4332 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4333 {
4334 /* start with default case */
4335 adapter->rx_ring[0]->reg_idx = 0;
4336 adapter->tx_ring[0]->reg_idx = 0;
4337
4338 if (ixgbe_cache_ring_sriov(adapter))
4339 return;
4340
4341 #ifdef IXGBE_FCOE
4342 if (ixgbe_cache_ring_fcoe(adapter))
4343 return;
4344
4345 #endif /* IXGBE_FCOE */
4346 #ifdef CONFIG_IXGBE_DCB
4347 if (ixgbe_cache_ring_dcb(adapter))
4348 return;
4349
4350 #endif
4351 if (ixgbe_cache_ring_fdir(adapter))
4352 return;
4353
4354 if (ixgbe_cache_ring_rss(adapter))
4355 return;
4356 }
4357
4358 /**
4359 * ixgbe_alloc_queues - Allocate memory for all rings
4360 * @adapter: board private structure to initialize
4361 *
4362 * We allocate one ring per queue at run-time since we don't know the
4363 * number of queues at compile-time. The polling_netdev array is
4364 * intended for Multiqueue, but should work fine with a single queue.
4365 **/
4366 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
4367 {
4368 int i;
4369 int orig_node = adapter->node;
4370
4371 for (i = 0; i < adapter->num_tx_queues; i++) {
4372 struct ixgbe_ring *ring = adapter->tx_ring[i];
4373 if (orig_node == -1) {
4374 int cur_node = next_online_node(adapter->node);
4375 if (cur_node == MAX_NUMNODES)
4376 cur_node = first_online_node;
4377 adapter->node = cur_node;
4378 }
4379 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
4380 adapter->node);
4381 if (!ring)
4382 ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
4383 if (!ring)
4384 goto err_tx_ring_allocation;
4385 ring->count = adapter->tx_ring_count;
4386 ring->queue_index = i;
4387 ring->numa_node = adapter->node;
4388
4389 adapter->tx_ring[i] = ring;
4390 }
4391
4392 /* Restore the adapter's original node */
4393 adapter->node = orig_node;
4394
4395 for (i = 0; i < adapter->num_rx_queues; i++) {
4396 struct ixgbe_ring *ring = adapter->rx_ring[i];
4397 if (orig_node == -1) {
4398 int cur_node = next_online_node(adapter->node);
4399 if (cur_node == MAX_NUMNODES)
4400 cur_node = first_online_node;
4401 adapter->node = cur_node;
4402 }
4403 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
4404 adapter->node);
4405 if (!ring)
4406 ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
4407 if (!ring)
4408 goto err_rx_ring_allocation;
4409 ring->count = adapter->rx_ring_count;
4410 ring->queue_index = i;
4411 ring->numa_node = adapter->node;
4412
4413 adapter->rx_ring[i] = ring;
4414 }
4415
4416 /* Restore the adapter's original node */
4417 adapter->node = orig_node;
4418
4419 ixgbe_cache_ring_register(adapter);
4420
4421 return 0;
4422
4423 err_rx_ring_allocation:
4424 for (i = 0; i < adapter->num_tx_queues; i++)
4425 kfree(adapter->tx_ring[i]);
4426 err_tx_ring_allocation:
4427 return -ENOMEM;
4428 }
4429
4430 /**
4431 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4432 * @adapter: board private structure to initialize
4433 *
4434 * Attempt to configure the interrupts using the best available
4435 * capabilities of the hardware and the kernel.
4436 **/
4437 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
4438 {
4439 struct ixgbe_hw *hw = &adapter->hw;
4440 int err = 0;
4441 int vector, v_budget;
4442
4443 /*
4444 * It's easy to be greedy for MSI-X vectors, but it really
4445 * doesn't do us much good if we have a lot more vectors
4446 * than CPU's. So let's be conservative and only ask for
4447 * (roughly) the same number of vectors as there are CPU's.
4448 */
4449 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
4450 (int)num_online_cpus()) + NON_Q_VECTORS;
4451
4452 /*
4453 * At the same time, hardware can only support a maximum of
4454 * hw.mac->max_msix_vectors vectors. With features
4455 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4456 * descriptor queues supported by our device. Thus, we cap it off in
4457 * those rare cases where the cpu count also exceeds our vector limit.
4458 */
4459 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
4460
4461 /* A failure in MSI-X entry allocation isn't fatal, but it does
4462 * mean we disable MSI-X capabilities of the adapter. */
4463 adapter->msix_entries = kcalloc(v_budget,
4464 sizeof(struct msix_entry), GFP_KERNEL);
4465 if (adapter->msix_entries) {
4466 for (vector = 0; vector < v_budget; vector++)
4467 adapter->msix_entries[vector].entry = vector;
4468
4469 ixgbe_acquire_msix_vectors(adapter, v_budget);
4470
4471 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4472 goto out;
4473 }
4474
4475 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4476 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
4477 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4478 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4479 adapter->atr_sample_rate = 0;
4480 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4481 ixgbe_disable_sriov(adapter);
4482
4483 ixgbe_set_num_queues(adapter);
4484
4485 err = pci_enable_msi(adapter->pdev);
4486 if (!err) {
4487 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4488 } else {
4489 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4490 "Unable to allocate MSI interrupt, "
4491 "falling back to legacy. Error: %d\n", err);
4492 /* reset err */
4493 err = 0;
4494 }
4495
4496 out:
4497 return err;
4498 }
4499
4500 /**
4501 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4502 * @adapter: board private structure to initialize
4503 *
4504 * We allocate one q_vector per queue interrupt. If allocation fails we
4505 * return -ENOMEM.
4506 **/
4507 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4508 {
4509 int q_idx, num_q_vectors;
4510 struct ixgbe_q_vector *q_vector;
4511 int napi_vectors;
4512 int (*poll)(struct napi_struct *, int);
4513
4514 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4515 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4516 napi_vectors = adapter->num_rx_queues;
4517 poll = &ixgbe_clean_rxtx_many;
4518 } else {
4519 num_q_vectors = 1;
4520 napi_vectors = 1;
4521 poll = &ixgbe_poll;
4522 }
4523
4524 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4525 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
4526 GFP_KERNEL, adapter->node);
4527 if (!q_vector)
4528 q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
4529 GFP_KERNEL);
4530 if (!q_vector)
4531 goto err_out;
4532 q_vector->adapter = adapter;
4533 if (q_vector->txr_count && !q_vector->rxr_count)
4534 q_vector->eitr = adapter->tx_eitr_param;
4535 else
4536 q_vector->eitr = adapter->rx_eitr_param;
4537 q_vector->v_idx = q_idx;
4538 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
4539 adapter->q_vector[q_idx] = q_vector;
4540 }
4541
4542 return 0;
4543
4544 err_out:
4545 while (q_idx) {
4546 q_idx--;
4547 q_vector = adapter->q_vector[q_idx];
4548 netif_napi_del(&q_vector->napi);
4549 kfree(q_vector);
4550 adapter->q_vector[q_idx] = NULL;
4551 }
4552 return -ENOMEM;
4553 }
4554
4555 /**
4556 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4557 * @adapter: board private structure to initialize
4558 *
4559 * This function frees the memory allocated to the q_vectors. In addition if
4560 * NAPI is enabled it will delete any references to the NAPI struct prior
4561 * to freeing the q_vector.
4562 **/
4563 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
4564 {
4565 int q_idx, num_q_vectors;
4566
4567 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4568 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4569 else
4570 num_q_vectors = 1;
4571
4572 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4573 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
4574 adapter->q_vector[q_idx] = NULL;
4575 netif_napi_del(&q_vector->napi);
4576 kfree(q_vector);
4577 }
4578 }
4579
4580 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
4581 {
4582 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4583 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4584 pci_disable_msix(adapter->pdev);
4585 kfree(adapter->msix_entries);
4586 adapter->msix_entries = NULL;
4587 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
4588 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
4589 pci_disable_msi(adapter->pdev);
4590 }
4591 }
4592
4593 /**
4594 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4595 * @adapter: board private structure to initialize
4596 *
4597 * We determine which interrupt scheme to use based on...
4598 * - Kernel support (MSI, MSI-X)
4599 * - which can be user-defined (via MODULE_PARAM)
4600 * - Hardware queue count (num_*_queues)
4601 * - defined by miscellaneous hardware support/features (RSS, etc.)
4602 **/
4603 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
4604 {
4605 int err;
4606
4607 /* Number of supported queues */
4608 ixgbe_set_num_queues(adapter);
4609
4610 err = ixgbe_set_interrupt_capability(adapter);
4611 if (err) {
4612 e_dev_err("Unable to setup interrupt capabilities\n");
4613 goto err_set_interrupt;
4614 }
4615
4616 err = ixgbe_alloc_q_vectors(adapter);
4617 if (err) {
4618 e_dev_err("Unable to allocate memory for queue vectors\n");
4619 goto err_alloc_q_vectors;
4620 }
4621
4622 err = ixgbe_alloc_queues(adapter);
4623 if (err) {
4624 e_dev_err("Unable to allocate memory for queues\n");
4625 goto err_alloc_queues;
4626 }
4627
4628 e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
4629 (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
4630 adapter->num_rx_queues, adapter->num_tx_queues);
4631
4632 set_bit(__IXGBE_DOWN, &adapter->state);
4633
4634 return 0;
4635
4636 err_alloc_queues:
4637 ixgbe_free_q_vectors(adapter);
4638 err_alloc_q_vectors:
4639 ixgbe_reset_interrupt_capability(adapter);
4640 err_set_interrupt:
4641 return err;
4642 }
4643
4644 /**
4645 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
4646 * @adapter: board private structure to clear interrupt scheme on
4647 *
4648 * We go through and clear interrupt specific resources and reset the structure
4649 * to pre-load conditions
4650 **/
4651 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
4652 {
4653 int i;
4654
4655 for (i = 0; i < adapter->num_tx_queues; i++) {
4656 kfree(adapter->tx_ring[i]);
4657 adapter->tx_ring[i] = NULL;
4658 }
4659 for (i = 0; i < adapter->num_rx_queues; i++) {
4660 kfree(adapter->rx_ring[i]);
4661 adapter->rx_ring[i] = NULL;
4662 }
4663
4664 ixgbe_free_q_vectors(adapter);
4665 ixgbe_reset_interrupt_capability(adapter);
4666 }
4667
4668 /**
4669 * ixgbe_sfp_timer - worker thread to find a missing module
4670 * @data: pointer to our adapter struct
4671 **/
4672 static void ixgbe_sfp_timer(unsigned long data)
4673 {
4674 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
4675
4676 /*
4677 * Do the sfp_timer outside of interrupt context due to the
4678 * delays that sfp+ detection requires
4679 */
4680 schedule_work(&adapter->sfp_task);
4681 }
4682
4683 /**
4684 * ixgbe_sfp_task - worker thread to find a missing module
4685 * @work: pointer to work_struct containing our data
4686 **/
4687 static void ixgbe_sfp_task(struct work_struct *work)
4688 {
4689 struct ixgbe_adapter *adapter = container_of(work,
4690 struct ixgbe_adapter,
4691 sfp_task);
4692 struct ixgbe_hw *hw = &adapter->hw;
4693
4694 if ((hw->phy.type == ixgbe_phy_nl) &&
4695 (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
4696 s32 ret = hw->phy.ops.identify_sfp(hw);
4697 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
4698 goto reschedule;
4699 ret = hw->phy.ops.reset(hw);
4700 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4701 e_dev_err("failed to initialize because an unsupported "
4702 "SFP+ module type was detected.\n");
4703 e_dev_err("Reload the driver after installing a "
4704 "supported module.\n");
4705 unregister_netdev(adapter->netdev);
4706 } else {
4707 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
4708 }
4709 /* don't need this routine any more */
4710 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4711 }
4712 return;
4713 reschedule:
4714 if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
4715 mod_timer(&adapter->sfp_timer,
4716 round_jiffies(jiffies + (2 * HZ)));
4717 }
4718
4719 /**
4720 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4721 * @adapter: board private structure to initialize
4722 *
4723 * ixgbe_sw_init initializes the Adapter private data structure.
4724 * Fields are initialized based on PCI device information and
4725 * OS network device settings (MTU size).
4726 **/
4727 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4728 {
4729 struct ixgbe_hw *hw = &adapter->hw;
4730 struct pci_dev *pdev = adapter->pdev;
4731 struct net_device *dev = adapter->netdev;
4732 unsigned int rss;
4733 #ifdef CONFIG_IXGBE_DCB
4734 int j;
4735 struct tc_configuration *tc;
4736 #endif
4737
4738 /* PCI config space info */
4739
4740 hw->vendor_id = pdev->vendor;
4741 hw->device_id = pdev->device;
4742 hw->revision_id = pdev->revision;
4743 hw->subsystem_vendor_id = pdev->subsystem_vendor;
4744 hw->subsystem_device_id = pdev->subsystem_device;
4745
4746 /* Set capability flags */
4747 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
4748 adapter->ring_feature[RING_F_RSS].indices = rss;
4749 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
4750 adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
4751 if (hw->mac.type == ixgbe_mac_82598EB) {
4752 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4753 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
4754 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
4755 } else if (hw->mac.type == ixgbe_mac_82599EB) {
4756 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
4757 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4758 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
4759 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
4760 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4761 if (dev->features & NETIF_F_NTUPLE) {
4762 /* Flow Director perfect filter enabled */
4763 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4764 adapter->atr_sample_rate = 0;
4765 spin_lock_init(&adapter->fdir_perfect_lock);
4766 } else {
4767 /* Flow Director hash filters enabled */
4768 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
4769 adapter->atr_sample_rate = 20;
4770 }
4771 adapter->ring_feature[RING_F_FDIR].indices =
4772 IXGBE_MAX_FDIR_INDICES;
4773 adapter->fdir_pballoc = 0;
4774 #ifdef IXGBE_FCOE
4775 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4776 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4777 adapter->ring_feature[RING_F_FCOE].indices = 0;
4778 #ifdef CONFIG_IXGBE_DCB
4779 /* Default traffic class to use for FCoE */
4780 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
4781 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
4782 #endif
4783 #endif /* IXGBE_FCOE */
4784 }
4785
4786 #ifdef CONFIG_IXGBE_DCB
4787 /* Configure DCB traffic classes */
4788 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4789 tc = &adapter->dcb_cfg.tc_config[j];
4790 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4791 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4792 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4793 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4794 tc->dcb_pfc = pfc_disabled;
4795 }
4796 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4797 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
4798 adapter->dcb_cfg.rx_pba_cfg = pba_equal;
4799 adapter->dcb_cfg.pfc_mode_enable = false;
4800 adapter->dcb_cfg.round_robin_enable = false;
4801 adapter->dcb_set_bitmap = 0x00;
4802 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
4803 adapter->ring_feature[RING_F_DCB].indices);
4804
4805 #endif
4806
4807 /* default flow control settings */
4808 hw->fc.requested_mode = ixgbe_fc_full;
4809 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
4810 #ifdef CONFIG_DCB
4811 adapter->last_lfc_mode = hw->fc.current_mode;
4812 #endif
4813 hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
4814 hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
4815 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4816 hw->fc.send_xon = true;
4817 hw->fc.disable_fc_autoneg = false;
4818
4819 /* enable itr by default in dynamic mode */
4820 adapter->rx_itr_setting = 1;
4821 adapter->rx_eitr_param = 20000;
4822 adapter->tx_itr_setting = 1;
4823 adapter->tx_eitr_param = 10000;
4824
4825 /* set defaults for eitr in MegaBytes */
4826 adapter->eitr_low = 10;
4827 adapter->eitr_high = 20;
4828
4829 /* set default ring sizes */
4830 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4831 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4832
4833 /* initialize eeprom parameters */
4834 if (ixgbe_init_eeprom_params_generic(hw)) {
4835 e_dev_err("EEPROM initialization failed\n");
4836 return -EIO;
4837 }
4838
4839 /* enable rx csum by default */
4840 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
4841
4842 /* get assigned NUMA node */
4843 adapter->node = dev_to_node(&pdev->dev);
4844
4845 set_bit(__IXGBE_DOWN, &adapter->state);
4846
4847 return 0;
4848 }
4849
4850 /**
4851 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
4852 * @adapter: board private structure
4853 * @tx_ring: tx descriptor ring (for a specific queue) to setup
4854 *
4855 * Return 0 on success, negative on failure
4856 **/
4857 int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
4858 struct ixgbe_ring *tx_ring)
4859 {
4860 struct pci_dev *pdev = adapter->pdev;
4861 int size;
4862
4863 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4864 tx_ring->tx_buffer_info = vmalloc_node(size, tx_ring->numa_node);
4865 if (!tx_ring->tx_buffer_info)
4866 tx_ring->tx_buffer_info = vmalloc(size);
4867 if (!tx_ring->tx_buffer_info)
4868 goto err;
4869 memset(tx_ring->tx_buffer_info, 0, size);
4870
4871 /* round up to nearest 4K */
4872 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
4873 tx_ring->size = ALIGN(tx_ring->size, 4096);
4874
4875 tx_ring->desc = dma_alloc_coherent(&pdev->dev, tx_ring->size,
4876 &tx_ring->dma, GFP_KERNEL);
4877 if (!tx_ring->desc)
4878 goto err;
4879
4880 tx_ring->next_to_use = 0;
4881 tx_ring->next_to_clean = 0;
4882 tx_ring->work_limit = tx_ring->count;
4883 return 0;
4884
4885 err:
4886 vfree(tx_ring->tx_buffer_info);
4887 tx_ring->tx_buffer_info = NULL;
4888 e_err(probe, "Unable to allocate memory for the Tx descriptor ring\n");
4889 return -ENOMEM;
4890 }
4891
4892 /**
4893 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4894 * @adapter: board private structure
4895 *
4896 * If this function returns with an error, then it's possible one or
4897 * more of the rings is populated (while the rest are not). It is the
4898 * callers duty to clean those orphaned rings.
4899 *
4900 * Return 0 on success, negative on failure
4901 **/
4902 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
4903 {
4904 int i, err = 0;
4905
4906 for (i = 0; i < adapter->num_tx_queues; i++) {
4907 err = ixgbe_setup_tx_resources(adapter, adapter->tx_ring[i]);
4908 if (!err)
4909 continue;
4910 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
4911 break;
4912 }
4913
4914 return err;
4915 }
4916
4917 /**
4918 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
4919 * @adapter: board private structure
4920 * @rx_ring: rx descriptor ring (for a specific queue) to setup
4921 *
4922 * Returns 0 on success, negative on failure
4923 **/
4924 int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
4925 struct ixgbe_ring *rx_ring)
4926 {
4927 struct pci_dev *pdev = adapter->pdev;
4928 int size;
4929
4930 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4931 rx_ring->rx_buffer_info = vmalloc_node(size, adapter->node);
4932 if (!rx_ring->rx_buffer_info)
4933 rx_ring->rx_buffer_info = vmalloc(size);
4934 if (!rx_ring->rx_buffer_info) {
4935 e_err(probe, "vmalloc allocation failed for the Rx "
4936 "descriptor ring\n");
4937 goto alloc_failed;
4938 }
4939 memset(rx_ring->rx_buffer_info, 0, size);
4940
4941 /* Round up to nearest 4K */
4942 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
4943 rx_ring->size = ALIGN(rx_ring->size, 4096);
4944
4945 rx_ring->desc = dma_alloc_coherent(&pdev->dev, rx_ring->size,
4946 &rx_ring->dma, GFP_KERNEL);
4947
4948 if (!rx_ring->desc) {
4949 e_err(probe, "Memory allocation failed for the Rx "
4950 "descriptor ring\n");
4951 vfree(rx_ring->rx_buffer_info);
4952 goto alloc_failed;
4953 }
4954
4955 rx_ring->next_to_clean = 0;
4956 rx_ring->next_to_use = 0;
4957
4958 return 0;
4959
4960 alloc_failed:
4961 return -ENOMEM;
4962 }
4963
4964 /**
4965 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4966 * @adapter: board private structure
4967 *
4968 * If this function returns with an error, then it's possible one or
4969 * more of the rings is populated (while the rest are not). It is the
4970 * callers duty to clean those orphaned rings.
4971 *
4972 * Return 0 on success, negative on failure
4973 **/
4974
4975 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
4976 {
4977 int i, err = 0;
4978
4979 for (i = 0; i < adapter->num_rx_queues; i++) {
4980 err = ixgbe_setup_rx_resources(adapter, adapter->rx_ring[i]);
4981 if (!err)
4982 continue;
4983 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
4984 break;
4985 }
4986
4987 return err;
4988 }
4989
4990 /**
4991 * ixgbe_free_tx_resources - Free Tx Resources per Queue
4992 * @adapter: board private structure
4993 * @tx_ring: Tx descriptor ring for a specific queue
4994 *
4995 * Free all transmit software resources
4996 **/
4997 void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
4998 struct ixgbe_ring *tx_ring)
4999 {
5000 struct pci_dev *pdev = adapter->pdev;
5001
5002 ixgbe_clean_tx_ring(adapter, tx_ring);
5003
5004 vfree(tx_ring->tx_buffer_info);
5005 tx_ring->tx_buffer_info = NULL;
5006
5007 dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc,
5008 tx_ring->dma);
5009
5010 tx_ring->desc = NULL;
5011 }
5012
5013 /**
5014 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5015 * @adapter: board private structure
5016 *
5017 * Free all transmit software resources
5018 **/
5019 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5020 {
5021 int i;
5022
5023 for (i = 0; i < adapter->num_tx_queues; i++)
5024 if (adapter->tx_ring[i]->desc)
5025 ixgbe_free_tx_resources(adapter, adapter->tx_ring[i]);
5026 }
5027
5028 /**
5029 * ixgbe_free_rx_resources - Free Rx Resources
5030 * @adapter: board private structure
5031 * @rx_ring: ring to clean the resources from
5032 *
5033 * Free all receive software resources
5034 **/
5035 void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
5036 struct ixgbe_ring *rx_ring)
5037 {
5038 struct pci_dev *pdev = adapter->pdev;
5039
5040 ixgbe_clean_rx_ring(adapter, rx_ring);
5041
5042 vfree(rx_ring->rx_buffer_info);
5043 rx_ring->rx_buffer_info = NULL;
5044
5045 dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc,
5046 rx_ring->dma);
5047
5048 rx_ring->desc = NULL;
5049 }
5050
5051 /**
5052 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5053 * @adapter: board private structure
5054 *
5055 * Free all receive software resources
5056 **/
5057 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5058 {
5059 int i;
5060
5061 for (i = 0; i < adapter->num_rx_queues; i++)
5062 if (adapter->rx_ring[i]->desc)
5063 ixgbe_free_rx_resources(adapter, adapter->rx_ring[i]);
5064 }
5065
5066 /**
5067 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5068 * @netdev: network interface device structure
5069 * @new_mtu: new value for maximum frame size
5070 *
5071 * Returns 0 on success, negative on failure
5072 **/
5073 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5074 {
5075 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5076 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5077
5078 /* MTU < 68 is an error and causes problems on some kernels */
5079 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5080 return -EINVAL;
5081
5082 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5083 /* must set new MTU before calling down or up */
5084 netdev->mtu = new_mtu;
5085
5086 if (netif_running(netdev))
5087 ixgbe_reinit_locked(adapter);
5088
5089 return 0;
5090 }
5091
5092 /**
5093 * ixgbe_open - Called when a network interface is made active
5094 * @netdev: network interface device structure
5095 *
5096 * Returns 0 on success, negative value on failure
5097 *
5098 * The open entry point is called when a network interface is made
5099 * active by the system (IFF_UP). At this point all resources needed
5100 * for transmit and receive operations are allocated, the interrupt
5101 * handler is registered with the OS, the watchdog timer is started,
5102 * and the stack is notified that the interface is ready.
5103 **/
5104 static int ixgbe_open(struct net_device *netdev)
5105 {
5106 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5107 int err;
5108
5109 /* disallow open during test */
5110 if (test_bit(__IXGBE_TESTING, &adapter->state))
5111 return -EBUSY;
5112
5113 netif_carrier_off(netdev);
5114
5115 /* allocate transmit descriptors */
5116 err = ixgbe_setup_all_tx_resources(adapter);
5117 if (err)
5118 goto err_setup_tx;
5119
5120 /* allocate receive descriptors */
5121 err = ixgbe_setup_all_rx_resources(adapter);
5122 if (err)
5123 goto err_setup_rx;
5124
5125 ixgbe_configure(adapter);
5126
5127 err = ixgbe_request_irq(adapter);
5128 if (err)
5129 goto err_req_irq;
5130
5131 err = ixgbe_up_complete(adapter);
5132 if (err)
5133 goto err_up;
5134
5135 netif_tx_start_all_queues(netdev);
5136
5137 return 0;
5138
5139 err_up:
5140 ixgbe_release_hw_control(adapter);
5141 ixgbe_free_irq(adapter);
5142 err_req_irq:
5143 err_setup_rx:
5144 ixgbe_free_all_rx_resources(adapter);
5145 err_setup_tx:
5146 ixgbe_free_all_tx_resources(adapter);
5147 ixgbe_reset(adapter);
5148
5149 return err;
5150 }
5151
5152 /**
5153 * ixgbe_close - Disables a network interface
5154 * @netdev: network interface device structure
5155 *
5156 * Returns 0, this is not allowed to fail
5157 *
5158 * The close entry point is called when an interface is de-activated
5159 * by the OS. The hardware is still under the drivers control, but
5160 * needs to be disabled. A global MAC reset is issued to stop the
5161 * hardware, and all transmit and receive resources are freed.
5162 **/
5163 static int ixgbe_close(struct net_device *netdev)
5164 {
5165 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5166
5167 ixgbe_down(adapter);
5168 ixgbe_free_irq(adapter);
5169
5170 ixgbe_free_all_tx_resources(adapter);
5171 ixgbe_free_all_rx_resources(adapter);
5172
5173 ixgbe_release_hw_control(adapter);
5174
5175 return 0;
5176 }
5177
5178 #ifdef CONFIG_PM
5179 static int ixgbe_resume(struct pci_dev *pdev)
5180 {
5181 struct net_device *netdev = pci_get_drvdata(pdev);
5182 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5183 u32 err;
5184
5185 pci_set_power_state(pdev, PCI_D0);
5186 pci_restore_state(pdev);
5187 /*
5188 * pci_restore_state clears dev->state_saved so call
5189 * pci_save_state to restore it.
5190 */
5191 pci_save_state(pdev);
5192
5193 err = pci_enable_device_mem(pdev);
5194 if (err) {
5195 e_dev_err("Cannot enable PCI device from suspend\n");
5196 return err;
5197 }
5198 pci_set_master(pdev);
5199
5200 pci_wake_from_d3(pdev, false);
5201
5202 err = ixgbe_init_interrupt_scheme(adapter);
5203 if (err) {
5204 e_dev_err("Cannot initialize interrupts for device\n");
5205 return err;
5206 }
5207
5208 ixgbe_reset(adapter);
5209
5210 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5211
5212 if (netif_running(netdev)) {
5213 err = ixgbe_open(adapter->netdev);
5214 if (err)
5215 return err;
5216 }
5217
5218 netif_device_attach(netdev);
5219
5220 return 0;
5221 }
5222 #endif /* CONFIG_PM */
5223
5224 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
5225 {
5226 struct net_device *netdev = pci_get_drvdata(pdev);
5227 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5228 struct ixgbe_hw *hw = &adapter->hw;
5229 u32 ctrl, fctrl;
5230 u32 wufc = adapter->wol;
5231 #ifdef CONFIG_PM
5232 int retval = 0;
5233 #endif
5234
5235 netif_device_detach(netdev);
5236
5237 if (netif_running(netdev)) {
5238 ixgbe_down(adapter);
5239 ixgbe_free_irq(adapter);
5240 ixgbe_free_all_tx_resources(adapter);
5241 ixgbe_free_all_rx_resources(adapter);
5242 }
5243
5244 #ifdef CONFIG_PM
5245 retval = pci_save_state(pdev);
5246 if (retval)
5247 return retval;
5248
5249 #endif
5250 if (wufc) {
5251 ixgbe_set_rx_mode(netdev);
5252
5253 /* turn on all-multi mode if wake on multicast is enabled */
5254 if (wufc & IXGBE_WUFC_MC) {
5255 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5256 fctrl |= IXGBE_FCTRL_MPE;
5257 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5258 }
5259
5260 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5261 ctrl |= IXGBE_CTRL_GIO_DIS;
5262 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5263
5264 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5265 } else {
5266 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5267 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5268 }
5269
5270 if (wufc && hw->mac.type == ixgbe_mac_82599EB)
5271 pci_wake_from_d3(pdev, true);
5272 else
5273 pci_wake_from_d3(pdev, false);
5274
5275 *enable_wake = !!wufc;
5276
5277 ixgbe_clear_interrupt_scheme(adapter);
5278
5279 ixgbe_release_hw_control(adapter);
5280
5281 pci_disable_device(pdev);
5282
5283 return 0;
5284 }
5285
5286 #ifdef CONFIG_PM
5287 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5288 {
5289 int retval;
5290 bool wake;
5291
5292 retval = __ixgbe_shutdown(pdev, &wake);
5293 if (retval)
5294 return retval;
5295
5296 if (wake) {
5297 pci_prepare_to_sleep(pdev);
5298 } else {
5299 pci_wake_from_d3(pdev, false);
5300 pci_set_power_state(pdev, PCI_D3hot);
5301 }
5302
5303 return 0;
5304 }
5305 #endif /* CONFIG_PM */
5306
5307 static void ixgbe_shutdown(struct pci_dev *pdev)
5308 {
5309 bool wake;
5310
5311 __ixgbe_shutdown(pdev, &wake);
5312
5313 if (system_state == SYSTEM_POWER_OFF) {
5314 pci_wake_from_d3(pdev, wake);
5315 pci_set_power_state(pdev, PCI_D3hot);
5316 }
5317 }
5318
5319 /**
5320 * ixgbe_update_stats - Update the board statistics counters.
5321 * @adapter: board private structure
5322 **/
5323 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5324 {
5325 struct net_device *netdev = adapter->netdev;
5326 struct ixgbe_hw *hw = &adapter->hw;
5327 u64 total_mpc = 0;
5328 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5329 u64 non_eop_descs = 0, restart_queue = 0;
5330
5331 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5332 test_bit(__IXGBE_RESETTING, &adapter->state))
5333 return;
5334
5335 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
5336 u64 rsc_count = 0;
5337 u64 rsc_flush = 0;
5338 for (i = 0; i < 16; i++)
5339 adapter->hw_rx_no_dma_resources +=
5340 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5341 for (i = 0; i < adapter->num_rx_queues; i++) {
5342 rsc_count += adapter->rx_ring[i]->rsc_count;
5343 rsc_flush += adapter->rx_ring[i]->rsc_flush;
5344 }
5345 adapter->rsc_total_count = rsc_count;
5346 adapter->rsc_total_flush = rsc_flush;
5347 }
5348
5349 /* gather some stats to the adapter struct that are per queue */
5350 for (i = 0; i < adapter->num_tx_queues; i++)
5351 restart_queue += adapter->tx_ring[i]->restart_queue;
5352 adapter->restart_queue = restart_queue;
5353
5354 for (i = 0; i < adapter->num_rx_queues; i++)
5355 non_eop_descs += adapter->rx_ring[i]->non_eop_descs;
5356 adapter->non_eop_descs = non_eop_descs;
5357
5358 adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
5359 for (i = 0; i < 8; i++) {
5360 /* for packet buffers not used, the register should read 0 */
5361 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5362 missed_rx += mpc;
5363 adapter->stats.mpc[i] += mpc;
5364 total_mpc += adapter->stats.mpc[i];
5365 if (hw->mac.type == ixgbe_mac_82598EB)
5366 adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5367 adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5368 adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5369 adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5370 adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
5371 if (hw->mac.type == ixgbe_mac_82599EB) {
5372 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
5373 IXGBE_PXONRXCNT(i));
5374 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
5375 IXGBE_PXOFFRXCNT(i));
5376 adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5377 } else {
5378 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
5379 IXGBE_PXONRXC(i));
5380 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
5381 IXGBE_PXOFFRXC(i));
5382 }
5383 adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw,
5384 IXGBE_PXONTXC(i));
5385 adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw,
5386 IXGBE_PXOFFTXC(i));
5387 }
5388 adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5389 adapter->stats.gprc -= missed_rx;
5390
5391 /* 82598 hardware only has a 32 bit counter in the high register */
5392 if (hw->mac.type == ixgbe_mac_82599EB) {
5393 u64 tmp;
5394 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
5395 tmp = IXGBE_READ_REG(hw, IXGBE_GORCH) & 0xF; /* 4 high bits of GORC */
5396 adapter->stats.gorc += (tmp << 32);
5397 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
5398 tmp = IXGBE_READ_REG(hw, IXGBE_GOTCH) & 0xF; /* 4 high bits of GOTC */
5399 adapter->stats.gotc += (tmp << 32);
5400 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL);
5401 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
5402 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5403 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
5404 adapter->stats.fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5405 adapter->stats.fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
5406 #ifdef IXGBE_FCOE
5407 adapter->stats.fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5408 adapter->stats.fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5409 adapter->stats.fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5410 adapter->stats.fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5411 adapter->stats.fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5412 adapter->stats.fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5413 #endif /* IXGBE_FCOE */
5414 } else {
5415 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5416 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
5417 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5418 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5419 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5420 }
5421 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
5422 adapter->stats.bprc += bprc;
5423 adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
5424 if (hw->mac.type == ixgbe_mac_82598EB)
5425 adapter->stats.mprc -= bprc;
5426 adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5427 adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5428 adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5429 adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5430 adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5431 adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5432 adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5433 adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
5434 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
5435 adapter->stats.lxontxc += lxon;
5436 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
5437 adapter->stats.lxofftxc += lxoff;
5438 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5439 adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5440 adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
5441 /*
5442 * 82598 errata - tx of flow control packets is included in tx counters
5443 */
5444 xon_off_tot = lxon + lxoff;
5445 adapter->stats.gptc -= xon_off_tot;
5446 adapter->stats.mptc -= xon_off_tot;
5447 adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5448 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5449 adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5450 adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5451 adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5452 adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5453 adapter->stats.ptc64 -= xon_off_tot;
5454 adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5455 adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5456 adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5457 adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5458 adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5459 adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
5460
5461 /* Fill out the OS statistics structure */
5462 netdev->stats.multicast = adapter->stats.mprc;
5463
5464 /* Rx Errors */
5465 netdev->stats.rx_errors = adapter->stats.crcerrs +
5466 adapter->stats.rlec;
5467 netdev->stats.rx_dropped = 0;
5468 netdev->stats.rx_length_errors = adapter->stats.rlec;
5469 netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
5470 netdev->stats.rx_missed_errors = total_mpc;
5471 }
5472
5473 /**
5474 * ixgbe_watchdog - Timer Call-back
5475 * @data: pointer to adapter cast into an unsigned long
5476 **/
5477 static void ixgbe_watchdog(unsigned long data)
5478 {
5479 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
5480 struct ixgbe_hw *hw = &adapter->hw;
5481 u64 eics = 0;
5482 int i;
5483
5484 /*
5485 * Do the watchdog outside of interrupt context due to the lovely
5486 * delays that some of the newer hardware requires
5487 */
5488
5489 if (test_bit(__IXGBE_DOWN, &adapter->state))
5490 goto watchdog_short_circuit;
5491
5492 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5493 /*
5494 * for legacy and MSI interrupts don't set any bits
5495 * that are enabled for EIAM, because this operation
5496 * would set *both* EIMS and EICS for any bit in EIAM
5497 */
5498 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5499 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5500 goto watchdog_reschedule;
5501 }
5502
5503 /* get one bit for every active tx/rx interrupt vector */
5504 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5505 struct ixgbe_q_vector *qv = adapter->q_vector[i];
5506 if (qv->rxr_count || qv->txr_count)
5507 eics |= ((u64)1 << i);
5508 }
5509
5510 /* Cause software interrupt to ensure rx rings are cleaned */
5511 ixgbe_irq_rearm_queues(adapter, eics);
5512
5513 watchdog_reschedule:
5514 /* Reset the timer */
5515 mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
5516
5517 watchdog_short_circuit:
5518 schedule_work(&adapter->watchdog_task);
5519 }
5520
5521 /**
5522 * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
5523 * @work: pointer to work_struct containing our data
5524 **/
5525 static void ixgbe_multispeed_fiber_task(struct work_struct *work)
5526 {
5527 struct ixgbe_adapter *adapter = container_of(work,
5528 struct ixgbe_adapter,
5529 multispeed_fiber_task);
5530 struct ixgbe_hw *hw = &adapter->hw;
5531 u32 autoneg;
5532 bool negotiation;
5533
5534 adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
5535 autoneg = hw->phy.autoneg_advertised;
5536 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
5537 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
5538 hw->mac.autotry_restart = false;
5539 if (hw->mac.ops.setup_link)
5540 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
5541 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5542 adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
5543 }
5544
5545 /**
5546 * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
5547 * @work: pointer to work_struct containing our data
5548 **/
5549 static void ixgbe_sfp_config_module_task(struct work_struct *work)
5550 {
5551 struct ixgbe_adapter *adapter = container_of(work,
5552 struct ixgbe_adapter,
5553 sfp_config_module_task);
5554 struct ixgbe_hw *hw = &adapter->hw;
5555 u32 err;
5556
5557 adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
5558
5559 /* Time for electrical oscillations to settle down */
5560 msleep(100);
5561 err = hw->phy.ops.identify_sfp(hw);
5562
5563 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5564 e_dev_err("failed to initialize because an unsupported SFP+ "
5565 "module type was detected.\n");
5566 e_dev_err("Reload the driver after installing a supported "
5567 "module.\n");
5568 unregister_netdev(adapter->netdev);
5569 return;
5570 }
5571 hw->mac.ops.setup_sfp(hw);
5572
5573 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
5574 /* This will also work for DA Twinax connections */
5575 schedule_work(&adapter->multispeed_fiber_task);
5576 adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
5577 }
5578
5579 /**
5580 * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
5581 * @work: pointer to work_struct containing our data
5582 **/
5583 static void ixgbe_fdir_reinit_task(struct work_struct *work)
5584 {
5585 struct ixgbe_adapter *adapter = container_of(work,
5586 struct ixgbe_adapter,
5587 fdir_reinit_task);
5588 struct ixgbe_hw *hw = &adapter->hw;
5589 int i;
5590
5591 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5592 for (i = 0; i < adapter->num_tx_queues; i++)
5593 set_bit(__IXGBE_FDIR_INIT_DONE,
5594 &(adapter->tx_ring[i]->reinit_state));
5595 } else {
5596 e_err(probe, "failed to finish FDIR re-initialization, "
5597 "ignored adding FDIR ATR filters\n");
5598 }
5599 /* Done FDIR Re-initialization, enable transmits */
5600 netif_tx_start_all_queues(adapter->netdev);
5601 }
5602
5603 static DEFINE_MUTEX(ixgbe_watchdog_lock);
5604
5605 /**
5606 * ixgbe_watchdog_task - worker thread to bring link up
5607 * @work: pointer to work_struct containing our data
5608 **/
5609 static void ixgbe_watchdog_task(struct work_struct *work)
5610 {
5611 struct ixgbe_adapter *adapter = container_of(work,
5612 struct ixgbe_adapter,
5613 watchdog_task);
5614 struct net_device *netdev = adapter->netdev;
5615 struct ixgbe_hw *hw = &adapter->hw;
5616 u32 link_speed;
5617 bool link_up;
5618 int i;
5619 struct ixgbe_ring *tx_ring;
5620 int some_tx_pending = 0;
5621
5622 mutex_lock(&ixgbe_watchdog_lock);
5623
5624 link_up = adapter->link_up;
5625 link_speed = adapter->link_speed;
5626
5627 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
5628 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
5629 if (link_up) {
5630 #ifdef CONFIG_DCB
5631 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5632 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
5633 hw->mac.ops.fc_enable(hw, i);
5634 } else {
5635 hw->mac.ops.fc_enable(hw, 0);
5636 }
5637 #else
5638 hw->mac.ops.fc_enable(hw, 0);
5639 #endif
5640 }
5641
5642 if (link_up ||
5643 time_after(jiffies, (adapter->link_check_timeout +
5644 IXGBE_TRY_LINK_TIMEOUT))) {
5645 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5646 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5647 }
5648 adapter->link_up = link_up;
5649 adapter->link_speed = link_speed;
5650 }
5651
5652 if (link_up) {
5653 if (!netif_carrier_ok(netdev)) {
5654 bool flow_rx, flow_tx;
5655
5656 if (hw->mac.type == ixgbe_mac_82599EB) {
5657 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5658 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5659 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5660 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5661 } else {
5662 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5663 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5664 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5665 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5666 }
5667
5668 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
5669 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5670 "10 Gbps" :
5671 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5672 "1 Gbps" : "unknown speed")),
5673 ((flow_rx && flow_tx) ? "RX/TX" :
5674 (flow_rx ? "RX" :
5675 (flow_tx ? "TX" : "None"))));
5676
5677 netif_carrier_on(netdev);
5678 } else {
5679 /* Force detection of hung controller */
5680 adapter->detect_tx_hung = true;
5681 }
5682 } else {
5683 adapter->link_up = false;
5684 adapter->link_speed = 0;
5685 if (netif_carrier_ok(netdev)) {
5686 e_info(drv, "NIC Link is Down\n");
5687 netif_carrier_off(netdev);
5688 }
5689 }
5690
5691 if (!netif_carrier_ok(netdev)) {
5692 for (i = 0; i < adapter->num_tx_queues; i++) {
5693 tx_ring = adapter->tx_ring[i];
5694 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5695 some_tx_pending = 1;
5696 break;
5697 }
5698 }
5699
5700 if (some_tx_pending) {
5701 /* We've lost link, so the controller stops DMA,
5702 * but we've got queued Tx work that's never going
5703 * to get done, so reset controller to flush Tx.
5704 * (Do the reset outside of interrupt context).
5705 */
5706 schedule_work(&adapter->reset_task);
5707 }
5708 }
5709
5710 ixgbe_update_stats(adapter);
5711 mutex_unlock(&ixgbe_watchdog_lock);
5712 }
5713
5714 static int ixgbe_tso(struct ixgbe_adapter *adapter,
5715 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
5716 u32 tx_flags, u8 *hdr_len)
5717 {
5718 struct ixgbe_adv_tx_context_desc *context_desc;
5719 unsigned int i;
5720 int err;
5721 struct ixgbe_tx_buffer *tx_buffer_info;
5722 u32 vlan_macip_lens = 0, type_tucmd_mlhl;
5723 u32 mss_l4len_idx, l4len;
5724
5725 if (skb_is_gso(skb)) {
5726 if (skb_header_cloned(skb)) {
5727 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
5728 if (err)
5729 return err;
5730 }
5731 l4len = tcp_hdrlen(skb);
5732 *hdr_len += l4len;
5733
5734 if (skb->protocol == htons(ETH_P_IP)) {
5735 struct iphdr *iph = ip_hdr(skb);
5736 iph->tot_len = 0;
5737 iph->check = 0;
5738 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5739 iph->daddr, 0,
5740 IPPROTO_TCP,
5741 0);
5742 } else if (skb_is_gso_v6(skb)) {
5743 ipv6_hdr(skb)->payload_len = 0;
5744 tcp_hdr(skb)->check =
5745 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
5746 &ipv6_hdr(skb)->daddr,
5747 0, IPPROTO_TCP, 0);
5748 }
5749
5750 i = tx_ring->next_to_use;
5751
5752 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5753 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
5754
5755 /* VLAN MACLEN IPLEN */
5756 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5757 vlan_macip_lens |=
5758 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5759 vlan_macip_lens |= ((skb_network_offset(skb)) <<
5760 IXGBE_ADVTXD_MACLEN_SHIFT);
5761 *hdr_len += skb_network_offset(skb);
5762 vlan_macip_lens |=
5763 (skb_transport_header(skb) - skb_network_header(skb));
5764 *hdr_len +=
5765 (skb_transport_header(skb) - skb_network_header(skb));
5766 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5767 context_desc->seqnum_seed = 0;
5768
5769 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
5770 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
5771 IXGBE_ADVTXD_DTYP_CTXT);
5772
5773 if (skb->protocol == htons(ETH_P_IP))
5774 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
5775 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5776 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
5777
5778 /* MSS L4LEN IDX */
5779 mss_l4len_idx =
5780 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
5781 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
5782 /* use index 1 for TSO */
5783 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
5784 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
5785
5786 tx_buffer_info->time_stamp = jiffies;
5787 tx_buffer_info->next_to_watch = i;
5788
5789 i++;
5790 if (i == tx_ring->count)
5791 i = 0;
5792 tx_ring->next_to_use = i;
5793
5794 return true;
5795 }
5796 return false;
5797 }
5798
5799 static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
5800 struct ixgbe_ring *tx_ring,
5801 struct sk_buff *skb, u32 tx_flags)
5802 {
5803 struct ixgbe_adv_tx_context_desc *context_desc;
5804 unsigned int i;
5805 struct ixgbe_tx_buffer *tx_buffer_info;
5806 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
5807
5808 if (skb->ip_summed == CHECKSUM_PARTIAL ||
5809 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
5810 i = tx_ring->next_to_use;
5811 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5812 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
5813
5814 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5815 vlan_macip_lens |=
5816 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5817 vlan_macip_lens |= (skb_network_offset(skb) <<
5818 IXGBE_ADVTXD_MACLEN_SHIFT);
5819 if (skb->ip_summed == CHECKSUM_PARTIAL)
5820 vlan_macip_lens |= (skb_transport_header(skb) -
5821 skb_network_header(skb));
5822
5823 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5824 context_desc->seqnum_seed = 0;
5825
5826 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
5827 IXGBE_ADVTXD_DTYP_CTXT);
5828
5829 if (skb->ip_summed == CHECKSUM_PARTIAL) {
5830 __be16 protocol;
5831
5832 if (skb->protocol == cpu_to_be16(ETH_P_8021Q)) {
5833 const struct vlan_ethhdr *vhdr =
5834 (const struct vlan_ethhdr *)skb->data;
5835
5836 protocol = vhdr->h_vlan_encapsulated_proto;
5837 } else {
5838 protocol = skb->protocol;
5839 }
5840
5841 switch (protocol) {
5842 case cpu_to_be16(ETH_P_IP):
5843 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
5844 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
5845 type_tucmd_mlhl |=
5846 IXGBE_ADVTXD_TUCMD_L4T_TCP;
5847 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
5848 type_tucmd_mlhl |=
5849 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
5850 break;
5851 case cpu_to_be16(ETH_P_IPV6):
5852 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
5853 type_tucmd_mlhl |=
5854 IXGBE_ADVTXD_TUCMD_L4T_TCP;
5855 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
5856 type_tucmd_mlhl |=
5857 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
5858 break;
5859 default:
5860 if (unlikely(net_ratelimit())) {
5861 e_warn(probe, "partial checksum "
5862 "but proto=%x!\n",
5863 skb->protocol);
5864 }
5865 break;
5866 }
5867 }
5868
5869 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
5870 /* use index zero for tx checksum offload */
5871 context_desc->mss_l4len_idx = 0;
5872
5873 tx_buffer_info->time_stamp = jiffies;
5874 tx_buffer_info->next_to_watch = i;
5875
5876 i++;
5877 if (i == tx_ring->count)
5878 i = 0;
5879 tx_ring->next_to_use = i;
5880
5881 return true;
5882 }
5883
5884 return false;
5885 }
5886
5887 static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
5888 struct ixgbe_ring *tx_ring,
5889 struct sk_buff *skb, u32 tx_flags,
5890 unsigned int first)
5891 {
5892 struct pci_dev *pdev = adapter->pdev;
5893 struct ixgbe_tx_buffer *tx_buffer_info;
5894 unsigned int len;
5895 unsigned int total = skb->len;
5896 unsigned int offset = 0, size, count = 0, i;
5897 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
5898 unsigned int f;
5899
5900 i = tx_ring->next_to_use;
5901
5902 if (tx_flags & IXGBE_TX_FLAGS_FCOE)
5903 /* excluding fcoe_crc_eof for FCoE */
5904 total -= sizeof(struct fcoe_crc_eof);
5905
5906 len = min(skb_headlen(skb), total);
5907 while (len) {
5908 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5909 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
5910
5911 tx_buffer_info->length = size;
5912 tx_buffer_info->mapped_as_page = false;
5913 tx_buffer_info->dma = dma_map_single(&pdev->dev,
5914 skb->data + offset,
5915 size, DMA_TO_DEVICE);
5916 if (dma_mapping_error(&pdev->dev, tx_buffer_info->dma))
5917 goto dma_error;
5918 tx_buffer_info->time_stamp = jiffies;
5919 tx_buffer_info->next_to_watch = i;
5920
5921 len -= size;
5922 total -= size;
5923 offset += size;
5924 count++;
5925
5926 if (len) {
5927 i++;
5928 if (i == tx_ring->count)
5929 i = 0;
5930 }
5931 }
5932
5933 for (f = 0; f < nr_frags; f++) {
5934 struct skb_frag_struct *frag;
5935
5936 frag = &skb_shinfo(skb)->frags[f];
5937 len = min((unsigned int)frag->size, total);
5938 offset = frag->page_offset;
5939
5940 while (len) {
5941 i++;
5942 if (i == tx_ring->count)
5943 i = 0;
5944
5945 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5946 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
5947
5948 tx_buffer_info->length = size;
5949 tx_buffer_info->dma = dma_map_page(&adapter->pdev->dev,
5950 frag->page,
5951 offset, size,
5952 DMA_TO_DEVICE);
5953 tx_buffer_info->mapped_as_page = true;
5954 if (dma_mapping_error(&pdev->dev, tx_buffer_info->dma))
5955 goto dma_error;
5956 tx_buffer_info->time_stamp = jiffies;
5957 tx_buffer_info->next_to_watch = i;
5958
5959 len -= size;
5960 total -= size;
5961 offset += size;
5962 count++;
5963 }
5964 if (total == 0)
5965 break;
5966 }
5967
5968 tx_ring->tx_buffer_info[i].skb = skb;
5969 tx_ring->tx_buffer_info[first].next_to_watch = i;
5970
5971 return count;
5972
5973 dma_error:
5974 e_dev_err("TX DMA map failed\n");
5975
5976 /* clear timestamp and dma mappings for failed tx_buffer_info map */
5977 tx_buffer_info->dma = 0;
5978 tx_buffer_info->time_stamp = 0;
5979 tx_buffer_info->next_to_watch = 0;
5980 if (count)
5981 count--;
5982
5983 /* clear timestamp and dma mappings for remaining portion of packet */
5984 while (count--) {
5985 if (i==0)
5986 i += tx_ring->count;
5987 i--;
5988 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5989 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
5990 }
5991
5992 return 0;
5993 }
5994
5995 static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
5996 struct ixgbe_ring *tx_ring,
5997 int tx_flags, int count, u32 paylen, u8 hdr_len)
5998 {
5999 union ixgbe_adv_tx_desc *tx_desc = NULL;
6000 struct ixgbe_tx_buffer *tx_buffer_info;
6001 u32 olinfo_status = 0, cmd_type_len = 0;
6002 unsigned int i;
6003 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
6004
6005 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
6006
6007 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
6008
6009 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6010 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
6011
6012 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
6013 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6014
6015 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
6016 IXGBE_ADVTXD_POPTS_SHIFT;
6017
6018 /* use index 1 context for tso */
6019 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6020 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6021 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
6022 IXGBE_ADVTXD_POPTS_SHIFT;
6023
6024 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6025 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
6026 IXGBE_ADVTXD_POPTS_SHIFT;
6027
6028 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6029 olinfo_status |= IXGBE_ADVTXD_CC;
6030 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6031 if (tx_flags & IXGBE_TX_FLAGS_FSO)
6032 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6033 }
6034
6035 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
6036
6037 i = tx_ring->next_to_use;
6038 while (count--) {
6039 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6040 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
6041 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
6042 tx_desc->read.cmd_type_len =
6043 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
6044 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
6045 i++;
6046 if (i == tx_ring->count)
6047 i = 0;
6048 }
6049
6050 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
6051
6052 /*
6053 * Force memory writes to complete before letting h/w
6054 * know there are new descriptors to fetch. (Only
6055 * applicable for weak-ordered memory model archs,
6056 * such as IA-64).
6057 */
6058 wmb();
6059
6060 tx_ring->next_to_use = i;
6061 writel(i, adapter->hw.hw_addr + tx_ring->tail);
6062 }
6063
6064 static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb,
6065 int queue, u32 tx_flags)
6066 {
6067 struct ixgbe_atr_input atr_input;
6068 struct tcphdr *th;
6069 struct iphdr *iph = ip_hdr(skb);
6070 struct ethhdr *eth = (struct ethhdr *)skb->data;
6071 u16 vlan_id, src_port, dst_port, flex_bytes;
6072 u32 src_ipv4_addr, dst_ipv4_addr;
6073 u8 l4type = 0;
6074
6075 /* Right now, we support IPv4 only */
6076 if (skb->protocol != htons(ETH_P_IP))
6077 return;
6078 /* check if we're UDP or TCP */
6079 if (iph->protocol == IPPROTO_TCP) {
6080 th = tcp_hdr(skb);
6081 src_port = th->source;
6082 dst_port = th->dest;
6083 l4type |= IXGBE_ATR_L4TYPE_TCP;
6084 /* l4type IPv4 type is 0, no need to assign */
6085 } else {
6086 /* Unsupported L4 header, just bail here */
6087 return;
6088 }
6089
6090 memset(&atr_input, 0, sizeof(struct ixgbe_atr_input));
6091
6092 vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >>
6093 IXGBE_TX_FLAGS_VLAN_SHIFT;
6094 src_ipv4_addr = iph->saddr;
6095 dst_ipv4_addr = iph->daddr;
6096 flex_bytes = eth->h_proto;
6097
6098 ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id);
6099 ixgbe_atr_set_src_port_82599(&atr_input, dst_port);
6100 ixgbe_atr_set_dst_port_82599(&atr_input, src_port);
6101 ixgbe_atr_set_flex_byte_82599(&atr_input, flex_bytes);
6102 ixgbe_atr_set_l4type_82599(&atr_input, l4type);
6103 /* src and dst are inverted, think how the receiver sees them */
6104 ixgbe_atr_set_src_ipv4_82599(&atr_input, dst_ipv4_addr);
6105 ixgbe_atr_set_dst_ipv4_82599(&atr_input, src_ipv4_addr);
6106
6107 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6108 ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue);
6109 }
6110
6111 static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
6112 struct ixgbe_ring *tx_ring, int size)
6113 {
6114 netif_stop_subqueue(netdev, tx_ring->queue_index);
6115 /* Herbert's original patch had:
6116 * smp_mb__after_netif_stop_queue();
6117 * but since that doesn't exist yet, just open code it. */
6118 smp_mb();
6119
6120 /* We need to check again in a case another CPU has just
6121 * made room available. */
6122 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
6123 return -EBUSY;
6124
6125 /* A reprieve! - use start_queue because it doesn't call schedule */
6126 netif_start_subqueue(netdev, tx_ring->queue_index);
6127 ++tx_ring->restart_queue;
6128 return 0;
6129 }
6130
6131 static int ixgbe_maybe_stop_tx(struct net_device *netdev,
6132 struct ixgbe_ring *tx_ring, int size)
6133 {
6134 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
6135 return 0;
6136 return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
6137 }
6138
6139 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6140 {
6141 struct ixgbe_adapter *adapter = netdev_priv(dev);
6142 int txq = smp_processor_id();
6143
6144 #ifdef IXGBE_FCOE
6145 if ((skb->protocol == htons(ETH_P_FCOE)) ||
6146 (skb->protocol == htons(ETH_P_FIP))) {
6147 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
6148 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6149 txq += adapter->ring_feature[RING_F_FCOE].mask;
6150 return txq;
6151 #ifdef CONFIG_IXGBE_DCB
6152 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6153 txq = adapter->fcoe.up;
6154 return txq;
6155 #endif
6156 }
6157 }
6158 #endif
6159
6160 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6161 while (unlikely(txq >= dev->real_num_tx_queues))
6162 txq -= dev->real_num_tx_queues;
6163 return txq;
6164 }
6165
6166 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6167 if (skb->priority == TC_PRIO_CONTROL)
6168 txq = adapter->ring_feature[RING_F_DCB].indices-1;
6169 else
6170 txq = (skb->vlan_tci & IXGBE_TX_FLAGS_VLAN_PRIO_MASK)
6171 >> 13;
6172 return txq;
6173 }
6174
6175 return skb_tx_hash(dev, skb);
6176 }
6177
6178 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
6179 struct net_device *netdev)
6180 {
6181 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6182 struct ixgbe_ring *tx_ring;
6183 struct netdev_queue *txq;
6184 unsigned int first;
6185 unsigned int tx_flags = 0;
6186 u8 hdr_len = 0;
6187 int tso;
6188 int count = 0;
6189 unsigned int f;
6190
6191 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
6192 tx_flags |= vlan_tx_tag_get(skb);
6193 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6194 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
6195 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
6196 }
6197 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6198 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6199 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED &&
6200 skb->priority != TC_PRIO_CONTROL) {
6201 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
6202 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6203 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6204 }
6205
6206 tx_ring = adapter->tx_ring[skb->queue_mapping];
6207
6208 #ifdef IXGBE_FCOE
6209 /* for FCoE with DCB, we force the priority to what
6210 * was specified by the switch */
6211 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED &&
6212 (skb->protocol == htons(ETH_P_FCOE) ||
6213 skb->protocol == htons(ETH_P_FIP))) {
6214 #ifdef CONFIG_IXGBE_DCB
6215 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6216 tx_flags &= ~(IXGBE_TX_FLAGS_VLAN_PRIO_MASK
6217 << IXGBE_TX_FLAGS_VLAN_SHIFT);
6218 tx_flags |= ((adapter->fcoe.up << 13)
6219 << IXGBE_TX_FLAGS_VLAN_SHIFT);
6220 }
6221 #endif
6222 /* flag for FCoE offloads */
6223 if (skb->protocol == htons(ETH_P_FCOE))
6224 tx_flags |= IXGBE_TX_FLAGS_FCOE;
6225 }
6226 #endif
6227
6228 /* four things can cause us to need a context descriptor */
6229 if (skb_is_gso(skb) ||
6230 (skb->ip_summed == CHECKSUM_PARTIAL) ||
6231 (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
6232 (tx_flags & IXGBE_TX_FLAGS_FCOE))
6233 count++;
6234
6235 count += TXD_USE_COUNT(skb_headlen(skb));
6236 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6237 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6238
6239 if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
6240 adapter->tx_busy++;
6241 return NETDEV_TX_BUSY;
6242 }
6243
6244 first = tx_ring->next_to_use;
6245 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6246 #ifdef IXGBE_FCOE
6247 /* setup tx offload for FCoE */
6248 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
6249 if (tso < 0) {
6250 dev_kfree_skb_any(skb);
6251 return NETDEV_TX_OK;
6252 }
6253 if (tso)
6254 tx_flags |= IXGBE_TX_FLAGS_FSO;
6255 #endif /* IXGBE_FCOE */
6256 } else {
6257 if (skb->protocol == htons(ETH_P_IP))
6258 tx_flags |= IXGBE_TX_FLAGS_IPV4;
6259 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
6260 if (tso < 0) {
6261 dev_kfree_skb_any(skb);
6262 return NETDEV_TX_OK;
6263 }
6264
6265 if (tso)
6266 tx_flags |= IXGBE_TX_FLAGS_TSO;
6267 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
6268 (skb->ip_summed == CHECKSUM_PARTIAL))
6269 tx_flags |= IXGBE_TX_FLAGS_CSUM;
6270 }
6271
6272 count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first);
6273 if (count) {
6274 /* add the ATR filter if ATR is on */
6275 if (tx_ring->atr_sample_rate) {
6276 ++tx_ring->atr_count;
6277 if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) &&
6278 test_bit(__IXGBE_FDIR_INIT_DONE,
6279 &tx_ring->reinit_state)) {
6280 ixgbe_atr(adapter, skb, tx_ring->queue_index,
6281 tx_flags);
6282 tx_ring->atr_count = 0;
6283 }
6284 }
6285 txq = netdev_get_tx_queue(netdev, tx_ring->queue_index);
6286 txq->tx_bytes += skb->len;
6287 txq->tx_packets++;
6288 ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len,
6289 hdr_len);
6290 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
6291
6292 } else {
6293 dev_kfree_skb_any(skb);
6294 tx_ring->tx_buffer_info[first].time_stamp = 0;
6295 tx_ring->next_to_use = first;
6296 }
6297
6298 return NETDEV_TX_OK;
6299 }
6300
6301 /**
6302 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6303 * @netdev: network interface device structure
6304 * @p: pointer to an address structure
6305 *
6306 * Returns 0 on success, negative on failure
6307 **/
6308 static int ixgbe_set_mac(struct net_device *netdev, void *p)
6309 {
6310 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6311 struct ixgbe_hw *hw = &adapter->hw;
6312 struct sockaddr *addr = p;
6313
6314 if (!is_valid_ether_addr(addr->sa_data))
6315 return -EADDRNOTAVAIL;
6316
6317 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
6318 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
6319
6320 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6321 IXGBE_RAH_AV);
6322
6323 return 0;
6324 }
6325
6326 static int
6327 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6328 {
6329 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6330 struct ixgbe_hw *hw = &adapter->hw;
6331 u16 value;
6332 int rc;
6333
6334 if (prtad != hw->phy.mdio.prtad)
6335 return -EINVAL;
6336 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6337 if (!rc)
6338 rc = value;
6339 return rc;
6340 }
6341
6342 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6343 u16 addr, u16 value)
6344 {
6345 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6346 struct ixgbe_hw *hw = &adapter->hw;
6347
6348 if (prtad != hw->phy.mdio.prtad)
6349 return -EINVAL;
6350 return hw->phy.ops.write_reg(hw, addr, devad, value);
6351 }
6352
6353 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6354 {
6355 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6356
6357 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6358 }
6359
6360 /**
6361 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
6362 * netdev->dev_addrs
6363 * @netdev: network interface device structure
6364 *
6365 * Returns non-zero on failure
6366 **/
6367 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6368 {
6369 int err = 0;
6370 struct ixgbe_adapter *adapter = netdev_priv(dev);
6371 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6372
6373 if (is_valid_ether_addr(mac->san_addr)) {
6374 rtnl_lock();
6375 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6376 rtnl_unlock();
6377 }
6378 return err;
6379 }
6380
6381 /**
6382 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
6383 * netdev->dev_addrs
6384 * @netdev: network interface device structure
6385 *
6386 * Returns non-zero on failure
6387 **/
6388 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6389 {
6390 int err = 0;
6391 struct ixgbe_adapter *adapter = netdev_priv(dev);
6392 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6393
6394 if (is_valid_ether_addr(mac->san_addr)) {
6395 rtnl_lock();
6396 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6397 rtnl_unlock();
6398 }
6399 return err;
6400 }
6401
6402 #ifdef CONFIG_NET_POLL_CONTROLLER
6403 /*
6404 * Polling 'interrupt' - used by things like netconsole to send skbs
6405 * without having to re-enable interrupts. It's not called while
6406 * the interrupt routine is executing.
6407 */
6408 static void ixgbe_netpoll(struct net_device *netdev)
6409 {
6410 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6411 int i;
6412
6413 /* if interface is down do nothing */
6414 if (test_bit(__IXGBE_DOWN, &adapter->state))
6415 return;
6416
6417 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
6418 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
6419 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
6420 for (i = 0; i < num_q_vectors; i++) {
6421 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
6422 ixgbe_msix_clean_many(0, q_vector);
6423 }
6424 } else {
6425 ixgbe_intr(adapter->pdev->irq, netdev);
6426 }
6427 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
6428 }
6429 #endif
6430
6431 static const struct net_device_ops ixgbe_netdev_ops = {
6432 .ndo_open = ixgbe_open,
6433 .ndo_stop = ixgbe_close,
6434 .ndo_start_xmit = ixgbe_xmit_frame,
6435 .ndo_select_queue = ixgbe_select_queue,
6436 .ndo_set_rx_mode = ixgbe_set_rx_mode,
6437 .ndo_set_multicast_list = ixgbe_set_rx_mode,
6438 .ndo_validate_addr = eth_validate_addr,
6439 .ndo_set_mac_address = ixgbe_set_mac,
6440 .ndo_change_mtu = ixgbe_change_mtu,
6441 .ndo_tx_timeout = ixgbe_tx_timeout,
6442 .ndo_vlan_rx_register = ixgbe_vlan_rx_register,
6443 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
6444 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6445 .ndo_do_ioctl = ixgbe_ioctl,
6446 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
6447 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
6448 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
6449 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
6450 #ifdef CONFIG_NET_POLL_CONTROLLER
6451 .ndo_poll_controller = ixgbe_netpoll,
6452 #endif
6453 #ifdef IXGBE_FCOE
6454 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
6455 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
6456 .ndo_fcoe_enable = ixgbe_fcoe_enable,
6457 .ndo_fcoe_disable = ixgbe_fcoe_disable,
6458 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
6459 #endif /* IXGBE_FCOE */
6460 };
6461
6462 static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
6463 const struct ixgbe_info *ii)
6464 {
6465 #ifdef CONFIG_PCI_IOV
6466 struct ixgbe_hw *hw = &adapter->hw;
6467 int err;
6468
6469 if (hw->mac.type != ixgbe_mac_82599EB || !max_vfs)
6470 return;
6471
6472 /* The 82599 supports up to 64 VFs per physical function
6473 * but this implementation limits allocation to 63 so that
6474 * basic networking resources are still available to the
6475 * physical function
6476 */
6477 adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
6478 adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED;
6479 err = pci_enable_sriov(adapter->pdev, adapter->num_vfs);
6480 if (err) {
6481 e_err(probe, "Failed to enable PCI sriov: %d\n", err);
6482 goto err_novfs;
6483 }
6484 /* If call to enable VFs succeeded then allocate memory
6485 * for per VF control structures.
6486 */
6487 adapter->vfinfo =
6488 kcalloc(adapter->num_vfs,
6489 sizeof(struct vf_data_storage), GFP_KERNEL);
6490 if (adapter->vfinfo) {
6491 /* Now that we're sure SR-IOV is enabled
6492 * and memory allocated set up the mailbox parameters
6493 */
6494 ixgbe_init_mbx_params_pf(hw);
6495 memcpy(&hw->mbx.ops, ii->mbx_ops,
6496 sizeof(hw->mbx.ops));
6497
6498 /* Disable RSC when in SR-IOV mode */
6499 adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE |
6500 IXGBE_FLAG2_RSC_ENABLED);
6501 return;
6502 }
6503
6504 /* Oh oh */
6505 e_err(probe, "Unable to allocate memory for VF Data Storage - "
6506 "SRIOV disabled\n");
6507 pci_disable_sriov(adapter->pdev);
6508
6509 err_novfs:
6510 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
6511 adapter->num_vfs = 0;
6512 #endif /* CONFIG_PCI_IOV */
6513 }
6514
6515 /**
6516 * ixgbe_probe - Device Initialization Routine
6517 * @pdev: PCI device information struct
6518 * @ent: entry in ixgbe_pci_tbl
6519 *
6520 * Returns 0 on success, negative on failure
6521 *
6522 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
6523 * The OS initialization, configuring of the adapter private structure,
6524 * and a hardware reset occur.
6525 **/
6526 static int __devinit ixgbe_probe(struct pci_dev *pdev,
6527 const struct pci_device_id *ent)
6528 {
6529 struct net_device *netdev;
6530 struct ixgbe_adapter *adapter = NULL;
6531 struct ixgbe_hw *hw;
6532 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
6533 static int cards_found;
6534 int i, err, pci_using_dac;
6535 unsigned int indices = num_possible_cpus();
6536 #ifdef IXGBE_FCOE
6537 u16 device_caps;
6538 #endif
6539 u32 part_num, eec;
6540
6541 /* Catch broken hardware that put the wrong VF device ID in
6542 * the PCIe SR-IOV capability.
6543 */
6544 if (pdev->is_virtfn) {
6545 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
6546 pci_name(pdev), pdev->vendor, pdev->device);
6547 return -EINVAL;
6548 }
6549
6550 err = pci_enable_device_mem(pdev);
6551 if (err)
6552 return err;
6553
6554 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
6555 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
6556 pci_using_dac = 1;
6557 } else {
6558 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
6559 if (err) {
6560 err = dma_set_coherent_mask(&pdev->dev,
6561 DMA_BIT_MASK(32));
6562 if (err) {
6563 dev_err(&pdev->dev,
6564 "No usable DMA configuration, aborting\n");
6565 goto err_dma;
6566 }
6567 }
6568 pci_using_dac = 0;
6569 }
6570
6571 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
6572 IORESOURCE_MEM), ixgbe_driver_name);
6573 if (err) {
6574 dev_err(&pdev->dev,
6575 "pci_request_selected_regions failed 0x%x\n", err);
6576 goto err_pci_reg;
6577 }
6578
6579 pci_enable_pcie_error_reporting(pdev);
6580
6581 pci_set_master(pdev);
6582 pci_save_state(pdev);
6583
6584 if (ii->mac == ixgbe_mac_82598EB)
6585 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
6586 else
6587 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
6588
6589 indices = max_t(unsigned int, indices, IXGBE_MAX_DCB_INDICES);
6590 #ifdef IXGBE_FCOE
6591 indices += min_t(unsigned int, num_possible_cpus(),
6592 IXGBE_MAX_FCOE_INDICES);
6593 #endif
6594 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
6595 if (!netdev) {
6596 err = -ENOMEM;
6597 goto err_alloc_etherdev;
6598 }
6599
6600 SET_NETDEV_DEV(netdev, &pdev->dev);
6601
6602 pci_set_drvdata(pdev, netdev);
6603 adapter = netdev_priv(netdev);
6604
6605 adapter->netdev = netdev;
6606 adapter->pdev = pdev;
6607 hw = &adapter->hw;
6608 hw->back = adapter;
6609 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
6610
6611 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
6612 pci_resource_len(pdev, 0));
6613 if (!hw->hw_addr) {
6614 err = -EIO;
6615 goto err_ioremap;
6616 }
6617
6618 for (i = 1; i <= 5; i++) {
6619 if (pci_resource_len(pdev, i) == 0)
6620 continue;
6621 }
6622
6623 netdev->netdev_ops = &ixgbe_netdev_ops;
6624 ixgbe_set_ethtool_ops(netdev);
6625 netdev->watchdog_timeo = 5 * HZ;
6626 strcpy(netdev->name, pci_name(pdev));
6627
6628 adapter->bd_number = cards_found;
6629
6630 /* Setup hw api */
6631 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
6632 hw->mac.type = ii->mac;
6633
6634 /* EEPROM */
6635 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
6636 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
6637 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
6638 if (!(eec & (1 << 8)))
6639 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
6640
6641 /* PHY */
6642 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
6643 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6644 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
6645 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
6646 hw->phy.mdio.mmds = 0;
6647 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
6648 hw->phy.mdio.dev = netdev;
6649 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
6650 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
6651
6652 /* set up this timer and work struct before calling get_invariants
6653 * which might start the timer
6654 */
6655 init_timer(&adapter->sfp_timer);
6656 adapter->sfp_timer.function = &ixgbe_sfp_timer;
6657 adapter->sfp_timer.data = (unsigned long) adapter;
6658
6659 INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
6660
6661 /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
6662 INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
6663
6664 /* a new SFP+ module arrival, called from GPI SDP2 context */
6665 INIT_WORK(&adapter->sfp_config_module_task,
6666 ixgbe_sfp_config_module_task);
6667
6668 ii->get_invariants(hw);
6669
6670 /* setup the private structure */
6671 err = ixgbe_sw_init(adapter);
6672 if (err)
6673 goto err_sw_init;
6674
6675 /* Make it possible the adapter to be woken up via WOL */
6676 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
6677 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6678
6679 /*
6680 * If there is a fan on this device and it has failed log the
6681 * failure.
6682 */
6683 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
6684 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
6685 if (esdp & IXGBE_ESDP_SDP1)
6686 e_crit(probe, "Fan has stopped, replace the adapter\n");
6687 }
6688
6689 /* reset_hw fills in the perm_addr as well */
6690 hw->phy.reset_if_overtemp = true;
6691 err = hw->mac.ops.reset_hw(hw);
6692 hw->phy.reset_if_overtemp = false;
6693 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
6694 hw->mac.type == ixgbe_mac_82598EB) {
6695 /*
6696 * Start a kernel thread to watch for a module to arrive.
6697 * Only do this for 82598, since 82599 will generate
6698 * interrupts on module arrival.
6699 */
6700 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6701 mod_timer(&adapter->sfp_timer,
6702 round_jiffies(jiffies + (2 * HZ)));
6703 err = 0;
6704 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
6705 e_dev_err("failed to initialize because an unsupported SFP+ "
6706 "module type was detected.\n");
6707 e_dev_err("Reload the driver after installing a supported "
6708 "module.\n");
6709 goto err_sw_init;
6710 } else if (err) {
6711 e_dev_err("HW Init failed: %d\n", err);
6712 goto err_sw_init;
6713 }
6714
6715 ixgbe_probe_vf(adapter, ii);
6716
6717 netdev->features = NETIF_F_SG |
6718 NETIF_F_IP_CSUM |
6719 NETIF_F_HW_VLAN_TX |
6720 NETIF_F_HW_VLAN_RX |
6721 NETIF_F_HW_VLAN_FILTER;
6722
6723 netdev->features |= NETIF_F_IPV6_CSUM;
6724 netdev->features |= NETIF_F_TSO;
6725 netdev->features |= NETIF_F_TSO6;
6726 netdev->features |= NETIF_F_GRO;
6727
6728 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
6729 netdev->features |= NETIF_F_SCTP_CSUM;
6730
6731 netdev->vlan_features |= NETIF_F_TSO;
6732 netdev->vlan_features |= NETIF_F_TSO6;
6733 netdev->vlan_features |= NETIF_F_IP_CSUM;
6734 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
6735 netdev->vlan_features |= NETIF_F_SG;
6736
6737 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6738 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
6739 IXGBE_FLAG_DCB_ENABLED);
6740 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
6741 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
6742
6743 #ifdef CONFIG_IXGBE_DCB
6744 netdev->dcbnl_ops = &dcbnl_ops;
6745 #endif
6746
6747 #ifdef IXGBE_FCOE
6748 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
6749 if (hw->mac.ops.get_device_caps) {
6750 hw->mac.ops.get_device_caps(hw, &device_caps);
6751 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
6752 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
6753 }
6754 }
6755 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
6756 netdev->vlan_features |= NETIF_F_FCOE_CRC;
6757 netdev->vlan_features |= NETIF_F_FSO;
6758 netdev->vlan_features |= NETIF_F_FCOE_MTU;
6759 }
6760 #endif /* IXGBE_FCOE */
6761 if (pci_using_dac)
6762 netdev->features |= NETIF_F_HIGHDMA;
6763
6764 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
6765 netdev->features |= NETIF_F_LRO;
6766
6767 /* make sure the EEPROM is good */
6768 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
6769 e_dev_err("The EEPROM Checksum Is Not Valid\n");
6770 err = -EIO;
6771 goto err_eeprom;
6772 }
6773
6774 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
6775 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
6776
6777 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
6778 e_dev_err("invalid MAC address\n");
6779 err = -EIO;
6780 goto err_eeprom;
6781 }
6782
6783 /* power down the optics */
6784 if (hw->phy.multispeed_fiber)
6785 hw->mac.ops.disable_tx_laser(hw);
6786
6787 init_timer(&adapter->watchdog_timer);
6788 adapter->watchdog_timer.function = &ixgbe_watchdog;
6789 adapter->watchdog_timer.data = (unsigned long)adapter;
6790
6791 INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
6792 INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
6793
6794 err = ixgbe_init_interrupt_scheme(adapter);
6795 if (err)
6796 goto err_sw_init;
6797
6798 switch (pdev->device) {
6799 case IXGBE_DEV_ID_82599_KX4:
6800 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
6801 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
6802 break;
6803 default:
6804 adapter->wol = 0;
6805 break;
6806 }
6807 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
6808
6809 /* pick up the PCI bus settings for reporting later */
6810 hw->mac.ops.get_bus_info(hw);
6811
6812 /* print bus type/speed/width info */
6813 e_dev_info("(PCI Express:%s:%s) %pM\n",
6814 ((hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0Gb/s":
6815 (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5Gb/s":"Unknown"),
6816 ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" :
6817 (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" :
6818 (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" :
6819 "Unknown"),
6820 netdev->dev_addr);
6821 ixgbe_read_pba_num_generic(hw, &part_num);
6822 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
6823 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, "
6824 "PBA No: %06x-%03x\n",
6825 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
6826 (part_num >> 8), (part_num & 0xff));
6827 else
6828 e_dev_info("MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
6829 hw->mac.type, hw->phy.type,
6830 (part_num >> 8), (part_num & 0xff));
6831
6832 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
6833 e_dev_warn("PCI-Express bandwidth available for this card is "
6834 "not sufficient for optimal performance.\n");
6835 e_dev_warn("For optimal performance a x8 PCI-Express slot "
6836 "is required.\n");
6837 }
6838
6839 /* save off EEPROM version number */
6840 hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
6841
6842 /* reset the hardware with the new settings */
6843 err = hw->mac.ops.start_hw(hw);
6844
6845 if (err == IXGBE_ERR_EEPROM_VERSION) {
6846 /* We are running on a pre-production device, log a warning */
6847 e_dev_warn("This device is a pre-production adapter/LOM. "
6848 "Please be aware there may be issues associated "
6849 "with your hardware. If you are experiencing "
6850 "problems please contact your Intel or hardware "
6851 "representative who provided you with this "
6852 "hardware.\n");
6853 }
6854 strcpy(netdev->name, "eth%d");
6855 err = register_netdev(netdev);
6856 if (err)
6857 goto err_register;
6858
6859 /* carrier off reporting is important to ethtool even BEFORE open */
6860 netif_carrier_off(netdev);
6861
6862 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
6863 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
6864 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
6865
6866 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
6867 INIT_WORK(&adapter->check_overtemp_task, ixgbe_check_overtemp_task);
6868 #ifdef CONFIG_IXGBE_DCA
6869 if (dca_add_requester(&pdev->dev) == 0) {
6870 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
6871 ixgbe_setup_dca(adapter);
6872 }
6873 #endif
6874 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
6875 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
6876 for (i = 0; i < adapter->num_vfs; i++)
6877 ixgbe_vf_configuration(pdev, (i | 0x10000000));
6878 }
6879
6880 /* add san mac addr to netdev */
6881 ixgbe_add_sanmac_netdev(netdev);
6882
6883 e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
6884 cards_found++;
6885 return 0;
6886
6887 err_register:
6888 ixgbe_release_hw_control(adapter);
6889 ixgbe_clear_interrupt_scheme(adapter);
6890 err_sw_init:
6891 err_eeprom:
6892 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6893 ixgbe_disable_sriov(adapter);
6894 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6895 del_timer_sync(&adapter->sfp_timer);
6896 cancel_work_sync(&adapter->sfp_task);
6897 cancel_work_sync(&adapter->multispeed_fiber_task);
6898 cancel_work_sync(&adapter->sfp_config_module_task);
6899 iounmap(hw->hw_addr);
6900 err_ioremap:
6901 free_netdev(netdev);
6902 err_alloc_etherdev:
6903 pci_release_selected_regions(pdev, pci_select_bars(pdev,
6904 IORESOURCE_MEM));
6905 err_pci_reg:
6906 err_dma:
6907 pci_disable_device(pdev);
6908 return err;
6909 }
6910
6911 /**
6912 * ixgbe_remove - Device Removal Routine
6913 * @pdev: PCI device information struct
6914 *
6915 * ixgbe_remove is called by the PCI subsystem to alert the driver
6916 * that it should release a PCI device. The could be caused by a
6917 * Hot-Plug event, or because the driver is going to be removed from
6918 * memory.
6919 **/
6920 static void __devexit ixgbe_remove(struct pci_dev *pdev)
6921 {
6922 struct net_device *netdev = pci_get_drvdata(pdev);
6923 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6924
6925 set_bit(__IXGBE_DOWN, &adapter->state);
6926 /* clear the module not found bit to make sure the worker won't
6927 * reschedule
6928 */
6929 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6930 del_timer_sync(&adapter->watchdog_timer);
6931
6932 del_timer_sync(&adapter->sfp_timer);
6933 cancel_work_sync(&adapter->watchdog_task);
6934 cancel_work_sync(&adapter->sfp_task);
6935 cancel_work_sync(&adapter->multispeed_fiber_task);
6936 cancel_work_sync(&adapter->sfp_config_module_task);
6937 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
6938 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
6939 cancel_work_sync(&adapter->fdir_reinit_task);
6940 flush_scheduled_work();
6941
6942 #ifdef CONFIG_IXGBE_DCA
6943 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
6944 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
6945 dca_remove_requester(&pdev->dev);
6946 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
6947 }
6948
6949 #endif
6950 #ifdef IXGBE_FCOE
6951 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
6952 ixgbe_cleanup_fcoe(adapter);
6953
6954 #endif /* IXGBE_FCOE */
6955
6956 /* remove the added san mac */
6957 ixgbe_del_sanmac_netdev(netdev);
6958
6959 if (netdev->reg_state == NETREG_REGISTERED)
6960 unregister_netdev(netdev);
6961
6962 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6963 ixgbe_disable_sriov(adapter);
6964
6965 ixgbe_clear_interrupt_scheme(adapter);
6966
6967 ixgbe_release_hw_control(adapter);
6968
6969 iounmap(adapter->hw.hw_addr);
6970 pci_release_selected_regions(pdev, pci_select_bars(pdev,
6971 IORESOURCE_MEM));
6972
6973 e_dev_info("complete\n");
6974
6975 free_netdev(netdev);
6976
6977 pci_disable_pcie_error_reporting(pdev);
6978
6979 pci_disable_device(pdev);
6980 }
6981
6982 /**
6983 * ixgbe_io_error_detected - called when PCI error is detected
6984 * @pdev: Pointer to PCI device
6985 * @state: The current pci connection state
6986 *
6987 * This function is called after a PCI bus error affecting
6988 * this device has been detected.
6989 */
6990 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
6991 pci_channel_state_t state)
6992 {
6993 struct net_device *netdev = pci_get_drvdata(pdev);
6994 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6995
6996 netif_device_detach(netdev);
6997
6998 if (state == pci_channel_io_perm_failure)
6999 return PCI_ERS_RESULT_DISCONNECT;
7000
7001 if (netif_running(netdev))
7002 ixgbe_down(adapter);
7003 pci_disable_device(pdev);
7004
7005 /* Request a slot reset. */
7006 return PCI_ERS_RESULT_NEED_RESET;
7007 }
7008
7009 /**
7010 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7011 * @pdev: Pointer to PCI device
7012 *
7013 * Restart the card from scratch, as if from a cold-boot.
7014 */
7015 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7016 {
7017 struct net_device *netdev = pci_get_drvdata(pdev);
7018 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7019 pci_ers_result_t result;
7020 int err;
7021
7022 if (pci_enable_device_mem(pdev)) {
7023 e_err(probe, "Cannot re-enable PCI device after reset.\n");
7024 result = PCI_ERS_RESULT_DISCONNECT;
7025 } else {
7026 pci_set_master(pdev);
7027 pci_restore_state(pdev);
7028 pci_save_state(pdev);
7029
7030 pci_wake_from_d3(pdev, false);
7031
7032 ixgbe_reset(adapter);
7033 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7034 result = PCI_ERS_RESULT_RECOVERED;
7035 }
7036
7037 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7038 if (err) {
7039 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7040 "failed 0x%0x\n", err);
7041 /* non-fatal, continue */
7042 }
7043
7044 return result;
7045 }
7046
7047 /**
7048 * ixgbe_io_resume - called when traffic can start flowing again.
7049 * @pdev: Pointer to PCI device
7050 *
7051 * This callback is called when the error recovery driver tells us that
7052 * its OK to resume normal operation.
7053 */
7054 static void ixgbe_io_resume(struct pci_dev *pdev)
7055 {
7056 struct net_device *netdev = pci_get_drvdata(pdev);
7057 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7058
7059 if (netif_running(netdev)) {
7060 if (ixgbe_up(adapter)) {
7061 e_info(probe, "ixgbe_up failed after reset\n");
7062 return;
7063 }
7064 }
7065
7066 netif_device_attach(netdev);
7067 }
7068
7069 static struct pci_error_handlers ixgbe_err_handler = {
7070 .error_detected = ixgbe_io_error_detected,
7071 .slot_reset = ixgbe_io_slot_reset,
7072 .resume = ixgbe_io_resume,
7073 };
7074
7075 static struct pci_driver ixgbe_driver = {
7076 .name = ixgbe_driver_name,
7077 .id_table = ixgbe_pci_tbl,
7078 .probe = ixgbe_probe,
7079 .remove = __devexit_p(ixgbe_remove),
7080 #ifdef CONFIG_PM
7081 .suspend = ixgbe_suspend,
7082 .resume = ixgbe_resume,
7083 #endif
7084 .shutdown = ixgbe_shutdown,
7085 .err_handler = &ixgbe_err_handler
7086 };
7087
7088 /**
7089 * ixgbe_init_module - Driver Registration Routine
7090 *
7091 * ixgbe_init_module is the first routine called when the driver is
7092 * loaded. All it does is register with the PCI subsystem.
7093 **/
7094 static int __init ixgbe_init_module(void)
7095 {
7096 int ret;
7097 pr_info("%s - version %s\n", ixgbe_driver_string,
7098 ixgbe_driver_version);
7099 pr_info("%s\n", ixgbe_copyright);
7100
7101 #ifdef CONFIG_IXGBE_DCA
7102 dca_register_notify(&dca_notifier);
7103 #endif
7104
7105 ret = pci_register_driver(&ixgbe_driver);
7106 return ret;
7107 }
7108
7109 module_init(ixgbe_init_module);
7110
7111 /**
7112 * ixgbe_exit_module - Driver Exit Cleanup Routine
7113 *
7114 * ixgbe_exit_module is called just before the driver is removed
7115 * from memory.
7116 **/
7117 static void __exit ixgbe_exit_module(void)
7118 {
7119 #ifdef CONFIG_IXGBE_DCA
7120 dca_unregister_notify(&dca_notifier);
7121 #endif
7122 pci_unregister_driver(&ixgbe_driver);
7123 }
7124
7125 #ifdef CONFIG_IXGBE_DCA
7126 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
7127 void *p)
7128 {
7129 int ret_val;
7130
7131 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
7132 __ixgbe_notify_dca);
7133
7134 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7135 }
7136
7137 #endif /* CONFIG_IXGBE_DCA */
7138
7139 /**
7140 * ixgbe_get_hw_dev return device
7141 * used by hardware layer to print debugging information
7142 **/
7143 struct net_device *ixgbe_get_hw_dev(struct ixgbe_hw *hw)
7144 {
7145 struct ixgbe_adapter *adapter = hw->back;
7146 return adapter->netdev;
7147 }
7148
7149 module_exit(ixgbe_exit_module);
7150
7151 /* ixgbe_main.c */
Tomato firmware and modifications.