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GUI: Fix Tomato RAF theme for all builds. Compilation typo.
[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / drivers / net / ixgbe / ixgbe_ethtool.c
blobdcebc82c6f4de3a4ae0134f802cbf5c7f8e8d302
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2010 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 /* ethtool support for ixgbe */
29
30 #include <linux/types.h>
31 #include <linux/module.h>
32 #include <linux/slab.h>
33 #include <linux/pci.h>
34 #include <linux/netdevice.h>
35 #include <linux/ethtool.h>
36 #include <linux/vmalloc.h>
37 #include <linux/uaccess.h>
38
39 #include "ixgbe.h"
40
41
42 #define IXGBE_ALL_RAR_ENTRIES 16
43
44 enum {NETDEV_STATS, IXGBE_STATS};
45
46 struct ixgbe_stats {
47 char stat_string[ETH_GSTRING_LEN];
48 int type;
49 int sizeof_stat;
50 int stat_offset;
51 };
52
53 #define IXGBE_STAT(m) IXGBE_STATS, \
54 sizeof(((struct ixgbe_adapter *)0)->m), \
55 offsetof(struct ixgbe_adapter, m)
56 #define IXGBE_NETDEV_STAT(m) NETDEV_STATS, \
57 sizeof(((struct rtnl_link_stats64 *)0)->m), \
58 offsetof(struct rtnl_link_stats64, m)
59
60 static struct ixgbe_stats ixgbe_gstrings_stats[] = {
61 {"rx_packets", IXGBE_NETDEV_STAT(rx_packets)},
62 {"tx_packets", IXGBE_NETDEV_STAT(tx_packets)},
63 {"rx_bytes", IXGBE_NETDEV_STAT(rx_bytes)},
64 {"tx_bytes", IXGBE_NETDEV_STAT(tx_bytes)},
65 {"rx_pkts_nic", IXGBE_STAT(stats.gprc)},
66 {"tx_pkts_nic", IXGBE_STAT(stats.gptc)},
67 {"rx_bytes_nic", IXGBE_STAT(stats.gorc)},
68 {"tx_bytes_nic", IXGBE_STAT(stats.gotc)},
69 {"lsc_int", IXGBE_STAT(lsc_int)},
70 {"tx_busy", IXGBE_STAT(tx_busy)},
71 {"non_eop_descs", IXGBE_STAT(non_eop_descs)},
72 {"rx_errors", IXGBE_NETDEV_STAT(rx_errors)},
73 {"tx_errors", IXGBE_NETDEV_STAT(tx_errors)},
74 {"rx_dropped", IXGBE_NETDEV_STAT(rx_dropped)},
75 {"tx_dropped", IXGBE_NETDEV_STAT(tx_dropped)},
76 {"multicast", IXGBE_NETDEV_STAT(multicast)},
77 {"broadcast", IXGBE_STAT(stats.bprc)},
78 {"rx_no_buffer_count", IXGBE_STAT(stats.rnbc[0]) },
79 {"collisions", IXGBE_NETDEV_STAT(collisions)},
80 {"rx_over_errors", IXGBE_NETDEV_STAT(rx_over_errors)},
81 {"rx_crc_errors", IXGBE_NETDEV_STAT(rx_crc_errors)},
82 {"rx_frame_errors", IXGBE_NETDEV_STAT(rx_frame_errors)},
83 {"hw_rsc_aggregated", IXGBE_STAT(rsc_total_count)},
84 {"hw_rsc_flushed", IXGBE_STAT(rsc_total_flush)},
85 {"fdir_match", IXGBE_STAT(stats.fdirmatch)},
86 {"fdir_miss", IXGBE_STAT(stats.fdirmiss)},
87 {"rx_fifo_errors", IXGBE_NETDEV_STAT(rx_fifo_errors)},
88 {"rx_missed_errors", IXGBE_NETDEV_STAT(rx_missed_errors)},
89 {"tx_aborted_errors", IXGBE_NETDEV_STAT(tx_aborted_errors)},
90 {"tx_carrier_errors", IXGBE_NETDEV_STAT(tx_carrier_errors)},
91 {"tx_fifo_errors", IXGBE_NETDEV_STAT(tx_fifo_errors)},
92 {"tx_heartbeat_errors", IXGBE_NETDEV_STAT(tx_heartbeat_errors)},
93 {"tx_timeout_count", IXGBE_STAT(tx_timeout_count)},
94 {"tx_restart_queue", IXGBE_STAT(restart_queue)},
95 {"rx_long_length_errors", IXGBE_STAT(stats.roc)},
96 {"rx_short_length_errors", IXGBE_STAT(stats.ruc)},
97 {"tx_flow_control_xon", IXGBE_STAT(stats.lxontxc)},
98 {"rx_flow_control_xon", IXGBE_STAT(stats.lxonrxc)},
99 {"tx_flow_control_xoff", IXGBE_STAT(stats.lxofftxc)},
100 {"rx_flow_control_xoff", IXGBE_STAT(stats.lxoffrxc)},
101 {"rx_csum_offload_errors", IXGBE_STAT(hw_csum_rx_error)},
102 {"alloc_rx_page_failed", IXGBE_STAT(alloc_rx_page_failed)},
103 {"alloc_rx_buff_failed", IXGBE_STAT(alloc_rx_buff_failed)},
104 {"rx_no_dma_resources", IXGBE_STAT(hw_rx_no_dma_resources)},
105 #ifdef IXGBE_FCOE
106 {"fcoe_bad_fccrc", IXGBE_STAT(stats.fccrc)},
107 {"rx_fcoe_dropped", IXGBE_STAT(stats.fcoerpdc)},
108 {"rx_fcoe_packets", IXGBE_STAT(stats.fcoeprc)},
109 {"rx_fcoe_dwords", IXGBE_STAT(stats.fcoedwrc)},
110 {"tx_fcoe_packets", IXGBE_STAT(stats.fcoeptc)},
111 {"tx_fcoe_dwords", IXGBE_STAT(stats.fcoedwtc)},
112 #endif /* IXGBE_FCOE */
113 };
114
115 #define IXGBE_QUEUE_STATS_LEN \
116 ((((struct ixgbe_adapter *)netdev_priv(netdev))->num_tx_queues + \
117 ((struct ixgbe_adapter *)netdev_priv(netdev))->num_rx_queues) * \
118 (sizeof(struct ixgbe_queue_stats) / sizeof(u64)))
119 #define IXGBE_GLOBAL_STATS_LEN ARRAY_SIZE(ixgbe_gstrings_stats)
120 #define IXGBE_PB_STATS_LEN ( \
121 (((struct ixgbe_adapter *)netdev_priv(netdev))->flags & \
122 IXGBE_FLAG_DCB_ENABLED) ? \
123 (sizeof(((struct ixgbe_adapter *)0)->stats.pxonrxc) + \
124 sizeof(((struct ixgbe_adapter *)0)->stats.pxontxc) + \
125 sizeof(((struct ixgbe_adapter *)0)->stats.pxoffrxc) + \
126 sizeof(((struct ixgbe_adapter *)0)->stats.pxofftxc)) \
127 / sizeof(u64) : 0)
128 #define IXGBE_STATS_LEN (IXGBE_GLOBAL_STATS_LEN + \
129 IXGBE_PB_STATS_LEN + \
130 IXGBE_QUEUE_STATS_LEN)
131
132 static const char ixgbe_gstrings_test[][ETH_GSTRING_LEN] = {
133 "Register test (offline)", "Eeprom test (offline)",
134 "Interrupt test (offline)", "Loopback test (offline)",
135 "Link test (on/offline)"
136 };
137 #define IXGBE_TEST_LEN sizeof(ixgbe_gstrings_test) / ETH_GSTRING_LEN
138
139 static int ixgbe_get_settings(struct net_device *netdev,
140 struct ethtool_cmd *ecmd)
141 {
142 struct ixgbe_adapter *adapter = netdev_priv(netdev);
143 struct ixgbe_hw *hw = &adapter->hw;
144 u32 link_speed = 0;
145 bool link_up;
146
147 ecmd->supported = SUPPORTED_10000baseT_Full;
148 ecmd->autoneg = AUTONEG_ENABLE;
149 ecmd->transceiver = XCVR_EXTERNAL;
150 if ((hw->phy.media_type == ixgbe_media_type_copper) ||
151 (hw->phy.multispeed_fiber)) {
152 ecmd->supported |= (SUPPORTED_1000baseT_Full |
153 SUPPORTED_Autoneg);
154
155 ecmd->advertising = ADVERTISED_Autoneg;
156 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
157 ecmd->advertising |= ADVERTISED_10000baseT_Full;
158 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
159 ecmd->advertising |= ADVERTISED_1000baseT_Full;
160 /*
161 * It's possible that phy.autoneg_advertised may not be
162 * set yet. If so display what the default would be -
163 * both 1G and 10G supported.
164 */
165 if (!(ecmd->advertising & (ADVERTISED_1000baseT_Full |
166 ADVERTISED_10000baseT_Full)))
167 ecmd->advertising |= (ADVERTISED_10000baseT_Full |
168 ADVERTISED_1000baseT_Full);
169
170 if (hw->phy.media_type == ixgbe_media_type_copper) {
171 ecmd->supported |= SUPPORTED_TP;
172 ecmd->advertising |= ADVERTISED_TP;
173 ecmd->port = PORT_TP;
174 } else {
175 ecmd->supported |= SUPPORTED_FIBRE;
176 ecmd->advertising |= ADVERTISED_FIBRE;
177 ecmd->port = PORT_FIBRE;
178 }
179 } else if (hw->phy.media_type == ixgbe_media_type_backplane) {
180 /* Set as FIBRE until SERDES defined in kernel */
181 if (hw->device_id == IXGBE_DEV_ID_82598_BX) {
182 ecmd->supported = (SUPPORTED_1000baseT_Full |
183 SUPPORTED_FIBRE);
184 ecmd->advertising = (ADVERTISED_1000baseT_Full |
185 ADVERTISED_FIBRE);
186 ecmd->port = PORT_FIBRE;
187 ecmd->autoneg = AUTONEG_DISABLE;
188 } else {
189 ecmd->supported |= (SUPPORTED_1000baseT_Full |
190 SUPPORTED_FIBRE);
191 ecmd->advertising = (ADVERTISED_10000baseT_Full |
192 ADVERTISED_1000baseT_Full |
193 ADVERTISED_FIBRE);
194 ecmd->port = PORT_FIBRE;
195 }
196 } else {
197 ecmd->supported |= SUPPORTED_FIBRE;
198 ecmd->advertising = (ADVERTISED_10000baseT_Full |
199 ADVERTISED_FIBRE);
200 ecmd->port = PORT_FIBRE;
201 ecmd->autoneg = AUTONEG_DISABLE;
202 }
203
204 /* Get PHY type */
205 switch (adapter->hw.phy.type) {
206 case ixgbe_phy_tn:
207 case ixgbe_phy_cu_unknown:
208 /* Copper 10G-BASET */
209 ecmd->port = PORT_TP;
210 break;
211 case ixgbe_phy_qt:
212 ecmd->port = PORT_FIBRE;
213 break;
214 case ixgbe_phy_nl:
215 case ixgbe_phy_sfp_passive_tyco:
216 case ixgbe_phy_sfp_passive_unknown:
217 case ixgbe_phy_sfp_ftl:
218 case ixgbe_phy_sfp_avago:
219 case ixgbe_phy_sfp_intel:
220 case ixgbe_phy_sfp_unknown:
221 switch (adapter->hw.phy.sfp_type) {
222 /* SFP+ devices, further checking needed */
223 case ixgbe_sfp_type_da_cu:
224 case ixgbe_sfp_type_da_cu_core0:
225 case ixgbe_sfp_type_da_cu_core1:
226 ecmd->port = PORT_DA;
227 break;
228 case ixgbe_sfp_type_sr:
229 case ixgbe_sfp_type_lr:
230 case ixgbe_sfp_type_srlr_core0:
231 case ixgbe_sfp_type_srlr_core1:
232 ecmd->port = PORT_FIBRE;
233 break;
234 case ixgbe_sfp_type_not_present:
235 ecmd->port = PORT_NONE;
236 break;
237 case ixgbe_sfp_type_1g_cu_core0:
238 case ixgbe_sfp_type_1g_cu_core1:
239 ecmd->port = PORT_TP;
240 ecmd->supported = SUPPORTED_TP;
241 ecmd->advertising = (ADVERTISED_1000baseT_Full |
242 ADVERTISED_TP);
243 break;
244 case ixgbe_sfp_type_unknown:
245 default:
246 ecmd->port = PORT_OTHER;
247 break;
248 }
249 break;
250 case ixgbe_phy_xaui:
251 ecmd->port = PORT_NONE;
252 break;
253 case ixgbe_phy_unknown:
254 case ixgbe_phy_generic:
255 case ixgbe_phy_sfp_unsupported:
256 default:
257 ecmd->port = PORT_OTHER;
258 break;
259 }
260
261 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
262 if (link_up) {
263 ecmd->speed = (link_speed == IXGBE_LINK_SPEED_10GB_FULL) ?
264 SPEED_10000 : SPEED_1000;
265 ecmd->duplex = DUPLEX_FULL;
266 } else {
267 ecmd->speed = -1;
268 ecmd->duplex = -1;
269 }
270
271 return 0;
272 }
273
274 static int ixgbe_set_settings(struct net_device *netdev,
275 struct ethtool_cmd *ecmd)
276 {
277 struct ixgbe_adapter *adapter = netdev_priv(netdev);
278 struct ixgbe_hw *hw = &adapter->hw;
279 u32 advertised, old;
280 s32 err = 0;
281
282 if ((hw->phy.media_type == ixgbe_media_type_copper) ||
283 (hw->phy.multispeed_fiber)) {
284 /* 10000/copper and 1000/copper must autoneg
285 * this function does not support any duplex forcing, but can
286 * limit the advertising of the adapter to only 10000 or 1000 */
287 if (ecmd->autoneg == AUTONEG_DISABLE)
288 return -EINVAL;
289
290 old = hw->phy.autoneg_advertised;
291 advertised = 0;
292 if (ecmd->advertising & ADVERTISED_10000baseT_Full)
293 advertised |= IXGBE_LINK_SPEED_10GB_FULL;
294
295 if (ecmd->advertising & ADVERTISED_1000baseT_Full)
296 advertised |= IXGBE_LINK_SPEED_1GB_FULL;
297
298 if (old == advertised)
299 return err;
300 /* this sets the link speed and restarts auto-neg */
301 hw->mac.autotry_restart = true;
302 err = hw->mac.ops.setup_link(hw, advertised, true, true);
303 if (err) {
304 e_info(probe, "setup link failed with code %d\n", err);
305 hw->mac.ops.setup_link(hw, old, true, true);
306 }
307 } else {
308 /* in this case we currently only support 10Gb/FULL */
309 if ((ecmd->autoneg == AUTONEG_ENABLE) ||
310 (ecmd->advertising != ADVERTISED_10000baseT_Full) ||
311 (ecmd->speed + ecmd->duplex != SPEED_10000 + DUPLEX_FULL))
312 return -EINVAL;
313 }
314
315 return err;
316 }
317
318 static void ixgbe_get_pauseparam(struct net_device *netdev,
319 struct ethtool_pauseparam *pause)
320 {
321 struct ixgbe_adapter *adapter = netdev_priv(netdev);
322 struct ixgbe_hw *hw = &adapter->hw;
323
324 /*
325 * Flow Control Autoneg isn't on if
326 * - we didn't ask for it OR
327 * - it failed, we know this by tx & rx being off
328 */
329 if (hw->fc.disable_fc_autoneg ||
330 (hw->fc.current_mode == ixgbe_fc_none))
331 pause->autoneg = 0;
332 else
333 pause->autoneg = 1;
334
335 #ifdef CONFIG_DCB
336 if (hw->fc.current_mode == ixgbe_fc_pfc) {
337 pause->rx_pause = 0;
338 pause->tx_pause = 0;
339 }
340
341 #endif
342 if (hw->fc.current_mode == ixgbe_fc_rx_pause) {
343 pause->rx_pause = 1;
344 } else if (hw->fc.current_mode == ixgbe_fc_tx_pause) {
345 pause->tx_pause = 1;
346 } else if (hw->fc.current_mode == ixgbe_fc_full) {
347 pause->rx_pause = 1;
348 pause->tx_pause = 1;
349 }
350 }
351
352 static int ixgbe_set_pauseparam(struct net_device *netdev,
353 struct ethtool_pauseparam *pause)
354 {
355 struct ixgbe_adapter *adapter = netdev_priv(netdev);
356 struct ixgbe_hw *hw = &adapter->hw;
357 struct ixgbe_fc_info fc;
358
359 #ifdef CONFIG_DCB
360 if (adapter->dcb_cfg.pfc_mode_enable ||
361 ((hw->mac.type == ixgbe_mac_82598EB) &&
362 (adapter->flags & IXGBE_FLAG_DCB_ENABLED)))
363 return -EINVAL;
364
365 #endif
366
367 fc = hw->fc;
368
369 if (pause->autoneg != AUTONEG_ENABLE)
370 fc.disable_fc_autoneg = true;
371 else
372 fc.disable_fc_autoneg = false;
373
374 if ((pause->rx_pause && pause->tx_pause) || pause->autoneg)
375 fc.requested_mode = ixgbe_fc_full;
376 else if (pause->rx_pause && !pause->tx_pause)
377 fc.requested_mode = ixgbe_fc_rx_pause;
378 else if (!pause->rx_pause && pause->tx_pause)
379 fc.requested_mode = ixgbe_fc_tx_pause;
380 else if (!pause->rx_pause && !pause->tx_pause)
381 fc.requested_mode = ixgbe_fc_none;
382 else
383 return -EINVAL;
384
385 #ifdef CONFIG_DCB
386 adapter->last_lfc_mode = fc.requested_mode;
387 #endif
388
389 /* if the thing changed then we'll update and use new autoneg */
390 if (memcmp(&fc, &hw->fc, sizeof(struct ixgbe_fc_info))) {
391 hw->fc = fc;
392 if (netif_running(netdev))
393 ixgbe_reinit_locked(adapter);
394 else
395 ixgbe_reset(adapter);
396 }
397
398 return 0;
399 }
400
401 static u32 ixgbe_get_rx_csum(struct net_device *netdev)
402 {
403 struct ixgbe_adapter *adapter = netdev_priv(netdev);
404 return (adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED);
405 }
406
407 static int ixgbe_set_rx_csum(struct net_device *netdev, u32 data)
408 {
409 struct ixgbe_adapter *adapter = netdev_priv(netdev);
410 if (data)
411 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
412 else
413 adapter->flags &= ~IXGBE_FLAG_RX_CSUM_ENABLED;
414
415 if (netif_running(netdev))
416 ixgbe_reinit_locked(adapter);
417 else
418 ixgbe_reset(adapter);
419
420 return 0;
421 }
422
423 static u32 ixgbe_get_tx_csum(struct net_device *netdev)
424 {
425 return (netdev->features & NETIF_F_IP_CSUM) != 0;
426 }
427
428 static int ixgbe_set_tx_csum(struct net_device *netdev, u32 data)
429 {
430 struct ixgbe_adapter *adapter = netdev_priv(netdev);
431
432 if (data) {
433 netdev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
434 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
435 netdev->features |= NETIF_F_SCTP_CSUM;
436 } else {
437 netdev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
438 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
439 netdev->features &= ~NETIF_F_SCTP_CSUM;
440 }
441
442 return 0;
443 }
444
445 static int ixgbe_set_tso(struct net_device *netdev, u32 data)
446 {
447 if (data) {
448 netdev->features |= NETIF_F_TSO;
449 netdev->features |= NETIF_F_TSO6;
450 } else {
451 netdev->features &= ~NETIF_F_TSO;
452 netdev->features &= ~NETIF_F_TSO6;
453 }
454 return 0;
455 }
456
457 static u32 ixgbe_get_msglevel(struct net_device *netdev)
458 {
459 struct ixgbe_adapter *adapter = netdev_priv(netdev);
460 return adapter->msg_enable;
461 }
462
463 static void ixgbe_set_msglevel(struct net_device *netdev, u32 data)
464 {
465 struct ixgbe_adapter *adapter = netdev_priv(netdev);
466 adapter->msg_enable = data;
467 }
468
469 static int ixgbe_get_regs_len(struct net_device *netdev)
470 {
471 #define IXGBE_REGS_LEN 1128
472 return IXGBE_REGS_LEN * sizeof(u32);
473 }
474
475 #define IXGBE_GET_STAT(_A_, _R_) _A_->stats._R_
476
477 static void ixgbe_get_regs(struct net_device *netdev,
478 struct ethtool_regs *regs, void *p)
479 {
480 struct ixgbe_adapter *adapter = netdev_priv(netdev);
481 struct ixgbe_hw *hw = &adapter->hw;
482 u32 *regs_buff = p;
483 u8 i;
484
485 memset(p, 0, IXGBE_REGS_LEN * sizeof(u32));
486
487 regs->version = (1 << 24) | hw->revision_id << 16 | hw->device_id;
488
489 /* General Registers */
490 regs_buff[0] = IXGBE_READ_REG(hw, IXGBE_CTRL);
491 regs_buff[1] = IXGBE_READ_REG(hw, IXGBE_STATUS);
492 regs_buff[2] = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
493 regs_buff[3] = IXGBE_READ_REG(hw, IXGBE_ESDP);
494 regs_buff[4] = IXGBE_READ_REG(hw, IXGBE_EODSDP);
495 regs_buff[5] = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
496 regs_buff[6] = IXGBE_READ_REG(hw, IXGBE_FRTIMER);
497 regs_buff[7] = IXGBE_READ_REG(hw, IXGBE_TCPTIMER);
498
499 /* NVM Register */
500 regs_buff[8] = IXGBE_READ_REG(hw, IXGBE_EEC);
501 regs_buff[9] = IXGBE_READ_REG(hw, IXGBE_EERD);
502 regs_buff[10] = IXGBE_READ_REG(hw, IXGBE_FLA);
503 regs_buff[11] = IXGBE_READ_REG(hw, IXGBE_EEMNGCTL);
504 regs_buff[12] = IXGBE_READ_REG(hw, IXGBE_EEMNGDATA);
505 regs_buff[13] = IXGBE_READ_REG(hw, IXGBE_FLMNGCTL);
506 regs_buff[14] = IXGBE_READ_REG(hw, IXGBE_FLMNGDATA);
507 regs_buff[15] = IXGBE_READ_REG(hw, IXGBE_FLMNGCNT);
508 regs_buff[16] = IXGBE_READ_REG(hw, IXGBE_FLOP);
509 regs_buff[17] = IXGBE_READ_REG(hw, IXGBE_GRC);
510
511 /* Interrupt */
512 /* don't read EICR because it can clear interrupt causes, instead
513 * read EICS which is a shadow but doesn't clear EICR */
514 regs_buff[18] = IXGBE_READ_REG(hw, IXGBE_EICS);
515 regs_buff[19] = IXGBE_READ_REG(hw, IXGBE_EICS);
516 regs_buff[20] = IXGBE_READ_REG(hw, IXGBE_EIMS);
517 regs_buff[21] = IXGBE_READ_REG(hw, IXGBE_EIMC);
518 regs_buff[22] = IXGBE_READ_REG(hw, IXGBE_EIAC);
519 regs_buff[23] = IXGBE_READ_REG(hw, IXGBE_EIAM);
520 regs_buff[24] = IXGBE_READ_REG(hw, IXGBE_EITR(0));
521 regs_buff[25] = IXGBE_READ_REG(hw, IXGBE_IVAR(0));
522 regs_buff[26] = IXGBE_READ_REG(hw, IXGBE_MSIXT);
523 regs_buff[27] = IXGBE_READ_REG(hw, IXGBE_MSIXPBA);
524 regs_buff[28] = IXGBE_READ_REG(hw, IXGBE_PBACL(0));
525 regs_buff[29] = IXGBE_READ_REG(hw, IXGBE_GPIE);
526
527 /* Flow Control */
528 regs_buff[30] = IXGBE_READ_REG(hw, IXGBE_PFCTOP);
529 regs_buff[31] = IXGBE_READ_REG(hw, IXGBE_FCTTV(0));
530 regs_buff[32] = IXGBE_READ_REG(hw, IXGBE_FCTTV(1));
531 regs_buff[33] = IXGBE_READ_REG(hw, IXGBE_FCTTV(2));
532 regs_buff[34] = IXGBE_READ_REG(hw, IXGBE_FCTTV(3));
533 for (i = 0; i < 8; i++)
534 regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL(i));
535 for (i = 0; i < 8; i++)
536 regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH(i));
537 regs_buff[51] = IXGBE_READ_REG(hw, IXGBE_FCRTV);
538 regs_buff[52] = IXGBE_READ_REG(hw, IXGBE_TFCS);
539
540 /* Receive DMA */
541 for (i = 0; i < 64; i++)
542 regs_buff[53 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
543 for (i = 0; i < 64; i++)
544 regs_buff[117 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
545 for (i = 0; i < 64; i++)
546 regs_buff[181 + i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
547 for (i = 0; i < 64; i++)
548 regs_buff[245 + i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
549 for (i = 0; i < 64; i++)
550 regs_buff[309 + i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
551 for (i = 0; i < 64; i++)
552 regs_buff[373 + i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
553 for (i = 0; i < 16; i++)
554 regs_buff[437 + i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
555 for (i = 0; i < 16; i++)
556 regs_buff[453 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
557 regs_buff[469] = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
558 for (i = 0; i < 8; i++)
559 regs_buff[470 + i] = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
560 regs_buff[478] = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
561 regs_buff[479] = IXGBE_READ_REG(hw, IXGBE_DROPEN);
562
563 /* Receive */
564 regs_buff[480] = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
565 regs_buff[481] = IXGBE_READ_REG(hw, IXGBE_RFCTL);
566 for (i = 0; i < 16; i++)
567 regs_buff[482 + i] = IXGBE_READ_REG(hw, IXGBE_RAL(i));
568 for (i = 0; i < 16; i++)
569 regs_buff[498 + i] = IXGBE_READ_REG(hw, IXGBE_RAH(i));
570 regs_buff[514] = IXGBE_READ_REG(hw, IXGBE_PSRTYPE(0));
571 regs_buff[515] = IXGBE_READ_REG(hw, IXGBE_FCTRL);
572 regs_buff[516] = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
573 regs_buff[517] = IXGBE_READ_REG(hw, IXGBE_MCSTCTRL);
574 regs_buff[518] = IXGBE_READ_REG(hw, IXGBE_MRQC);
575 regs_buff[519] = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
576 for (i = 0; i < 8; i++)
577 regs_buff[520 + i] = IXGBE_READ_REG(hw, IXGBE_IMIR(i));
578 for (i = 0; i < 8; i++)
579 regs_buff[528 + i] = IXGBE_READ_REG(hw, IXGBE_IMIREXT(i));
580 regs_buff[536] = IXGBE_READ_REG(hw, IXGBE_IMIRVP);
581
582 /* Transmit */
583 for (i = 0; i < 32; i++)
584 regs_buff[537 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
585 for (i = 0; i < 32; i++)
586 regs_buff[569 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
587 for (i = 0; i < 32; i++)
588 regs_buff[601 + i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
589 for (i = 0; i < 32; i++)
590 regs_buff[633 + i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
591 for (i = 0; i < 32; i++)
592 regs_buff[665 + i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
593 for (i = 0; i < 32; i++)
594 regs_buff[697 + i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
595 for (i = 0; i < 32; i++)
596 regs_buff[729 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAL(i));
597 for (i = 0; i < 32; i++)
598 regs_buff[761 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAH(i));
599 regs_buff[793] = IXGBE_READ_REG(hw, IXGBE_DTXCTL);
600 for (i = 0; i < 16; i++)
601 regs_buff[794 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));
602 regs_buff[810] = IXGBE_READ_REG(hw, IXGBE_TIPG);
603 for (i = 0; i < 8; i++)
604 regs_buff[811 + i] = IXGBE_READ_REG(hw, IXGBE_TXPBSIZE(i));
605 regs_buff[819] = IXGBE_READ_REG(hw, IXGBE_MNGTXMAP);
606
607 /* Wake Up */
608 regs_buff[820] = IXGBE_READ_REG(hw, IXGBE_WUC);
609 regs_buff[821] = IXGBE_READ_REG(hw, IXGBE_WUFC);
610 regs_buff[822] = IXGBE_READ_REG(hw, IXGBE_WUS);
611 regs_buff[823] = IXGBE_READ_REG(hw, IXGBE_IPAV);
612 regs_buff[824] = IXGBE_READ_REG(hw, IXGBE_IP4AT);
613 regs_buff[825] = IXGBE_READ_REG(hw, IXGBE_IP6AT);
614 regs_buff[826] = IXGBE_READ_REG(hw, IXGBE_WUPL);
615 regs_buff[827] = IXGBE_READ_REG(hw, IXGBE_WUPM);
616 regs_buff[828] = IXGBE_READ_REG(hw, IXGBE_FHFT(0));
617
618 regs_buff[829] = IXGBE_READ_REG(hw, IXGBE_RMCS);
619 regs_buff[830] = IXGBE_READ_REG(hw, IXGBE_DPMCS);
620 regs_buff[831] = IXGBE_READ_REG(hw, IXGBE_PDPMCS);
621 regs_buff[832] = IXGBE_READ_REG(hw, IXGBE_RUPPBMR);
622 for (i = 0; i < 8; i++)
623 regs_buff[833 + i] = IXGBE_READ_REG(hw, IXGBE_RT2CR(i));
624 for (i = 0; i < 8; i++)
625 regs_buff[841 + i] = IXGBE_READ_REG(hw, IXGBE_RT2SR(i));
626 for (i = 0; i < 8; i++)
627 regs_buff[849 + i] = IXGBE_READ_REG(hw, IXGBE_TDTQ2TCCR(i));
628 for (i = 0; i < 8; i++)
629 regs_buff[857 + i] = IXGBE_READ_REG(hw, IXGBE_TDTQ2TCSR(i));
630 for (i = 0; i < 8; i++)
631 regs_buff[865 + i] = IXGBE_READ_REG(hw, IXGBE_TDPT2TCCR(i));
632 for (i = 0; i < 8; i++)
633 regs_buff[873 + i] = IXGBE_READ_REG(hw, IXGBE_TDPT2TCSR(i));
634
635 /* Statistics */
636 regs_buff[881] = IXGBE_GET_STAT(adapter, crcerrs);
637 regs_buff[882] = IXGBE_GET_STAT(adapter, illerrc);
638 regs_buff[883] = IXGBE_GET_STAT(adapter, errbc);
639 regs_buff[884] = IXGBE_GET_STAT(adapter, mspdc);
640 for (i = 0; i < 8; i++)
641 regs_buff[885 + i] = IXGBE_GET_STAT(adapter, mpc[i]);
642 regs_buff[893] = IXGBE_GET_STAT(adapter, mlfc);
643 regs_buff[894] = IXGBE_GET_STAT(adapter, mrfc);
644 regs_buff[895] = IXGBE_GET_STAT(adapter, rlec);
645 regs_buff[896] = IXGBE_GET_STAT(adapter, lxontxc);
646 regs_buff[897] = IXGBE_GET_STAT(adapter, lxonrxc);
647 regs_buff[898] = IXGBE_GET_STAT(adapter, lxofftxc);
648 regs_buff[899] = IXGBE_GET_STAT(adapter, lxoffrxc);
649 for (i = 0; i < 8; i++)
650 regs_buff[900 + i] = IXGBE_GET_STAT(adapter, pxontxc[i]);
651 for (i = 0; i < 8; i++)
652 regs_buff[908 + i] = IXGBE_GET_STAT(adapter, pxonrxc[i]);
653 for (i = 0; i < 8; i++)
654 regs_buff[916 + i] = IXGBE_GET_STAT(adapter, pxofftxc[i]);
655 for (i = 0; i < 8; i++)
656 regs_buff[924 + i] = IXGBE_GET_STAT(adapter, pxoffrxc[i]);
657 regs_buff[932] = IXGBE_GET_STAT(adapter, prc64);
658 regs_buff[933] = IXGBE_GET_STAT(adapter, prc127);
659 regs_buff[934] = IXGBE_GET_STAT(adapter, prc255);
660 regs_buff[935] = IXGBE_GET_STAT(adapter, prc511);
661 regs_buff[936] = IXGBE_GET_STAT(adapter, prc1023);
662 regs_buff[937] = IXGBE_GET_STAT(adapter, prc1522);
663 regs_buff[938] = IXGBE_GET_STAT(adapter, gprc);
664 regs_buff[939] = IXGBE_GET_STAT(adapter, bprc);
665 regs_buff[940] = IXGBE_GET_STAT(adapter, mprc);
666 regs_buff[941] = IXGBE_GET_STAT(adapter, gptc);
667 regs_buff[942] = IXGBE_GET_STAT(adapter, gorc);
668 regs_buff[944] = IXGBE_GET_STAT(adapter, gotc);
669 for (i = 0; i < 8; i++)
670 regs_buff[946 + i] = IXGBE_GET_STAT(adapter, rnbc[i]);
671 regs_buff[954] = IXGBE_GET_STAT(adapter, ruc);
672 regs_buff[955] = IXGBE_GET_STAT(adapter, rfc);
673 regs_buff[956] = IXGBE_GET_STAT(adapter, roc);
674 regs_buff[957] = IXGBE_GET_STAT(adapter, rjc);
675 regs_buff[958] = IXGBE_GET_STAT(adapter, mngprc);
676 regs_buff[959] = IXGBE_GET_STAT(adapter, mngpdc);
677 regs_buff[960] = IXGBE_GET_STAT(adapter, mngptc);
678 regs_buff[961] = IXGBE_GET_STAT(adapter, tor);
679 regs_buff[963] = IXGBE_GET_STAT(adapter, tpr);
680 regs_buff[964] = IXGBE_GET_STAT(adapter, tpt);
681 regs_buff[965] = IXGBE_GET_STAT(adapter, ptc64);
682 regs_buff[966] = IXGBE_GET_STAT(adapter, ptc127);
683 regs_buff[967] = IXGBE_GET_STAT(adapter, ptc255);
684 regs_buff[968] = IXGBE_GET_STAT(adapter, ptc511);
685 regs_buff[969] = IXGBE_GET_STAT(adapter, ptc1023);
686 regs_buff[970] = IXGBE_GET_STAT(adapter, ptc1522);
687 regs_buff[971] = IXGBE_GET_STAT(adapter, mptc);
688 regs_buff[972] = IXGBE_GET_STAT(adapter, bptc);
689 regs_buff[973] = IXGBE_GET_STAT(adapter, xec);
690 for (i = 0; i < 16; i++)
691 regs_buff[974 + i] = IXGBE_GET_STAT(adapter, qprc[i]);
692 for (i = 0; i < 16; i++)
693 regs_buff[990 + i] = IXGBE_GET_STAT(adapter, qptc[i]);
694 for (i = 0; i < 16; i++)
695 regs_buff[1006 + i] = IXGBE_GET_STAT(adapter, qbrc[i]);
696 for (i = 0; i < 16; i++)
697 regs_buff[1022 + i] = IXGBE_GET_STAT(adapter, qbtc[i]);
698
699 /* MAC */
700 regs_buff[1038] = IXGBE_READ_REG(hw, IXGBE_PCS1GCFIG);
701 regs_buff[1039] = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
702 regs_buff[1040] = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
703 regs_buff[1041] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG0);
704 regs_buff[1042] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG1);
705 regs_buff[1043] = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
706 regs_buff[1044] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
707 regs_buff[1045] = IXGBE_READ_REG(hw, IXGBE_PCS1GANNP);
708 regs_buff[1046] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLPNP);
709 regs_buff[1047] = IXGBE_READ_REG(hw, IXGBE_HLREG0);
710 regs_buff[1048] = IXGBE_READ_REG(hw, IXGBE_HLREG1);
711 regs_buff[1049] = IXGBE_READ_REG(hw, IXGBE_PAP);
712 regs_buff[1050] = IXGBE_READ_REG(hw, IXGBE_MACA);
713 regs_buff[1051] = IXGBE_READ_REG(hw, IXGBE_APAE);
714 regs_buff[1052] = IXGBE_READ_REG(hw, IXGBE_ARD);
715 regs_buff[1053] = IXGBE_READ_REG(hw, IXGBE_AIS);
716 regs_buff[1054] = IXGBE_READ_REG(hw, IXGBE_MSCA);
717 regs_buff[1055] = IXGBE_READ_REG(hw, IXGBE_MSRWD);
718 regs_buff[1056] = IXGBE_READ_REG(hw, IXGBE_MLADD);
719 regs_buff[1057] = IXGBE_READ_REG(hw, IXGBE_MHADD);
720 regs_buff[1058] = IXGBE_READ_REG(hw, IXGBE_TREG);
721 regs_buff[1059] = IXGBE_READ_REG(hw, IXGBE_PCSS1);
722 regs_buff[1060] = IXGBE_READ_REG(hw, IXGBE_PCSS2);
723 regs_buff[1061] = IXGBE_READ_REG(hw, IXGBE_XPCSS);
724 regs_buff[1062] = IXGBE_READ_REG(hw, IXGBE_SERDESC);
725 regs_buff[1063] = IXGBE_READ_REG(hw, IXGBE_MACS);
726 regs_buff[1064] = IXGBE_READ_REG(hw, IXGBE_AUTOC);
727 regs_buff[1065] = IXGBE_READ_REG(hw, IXGBE_LINKS);
728 regs_buff[1066] = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
729 regs_buff[1067] = IXGBE_READ_REG(hw, IXGBE_AUTOC3);
730 regs_buff[1068] = IXGBE_READ_REG(hw, IXGBE_ANLP1);
731 regs_buff[1069] = IXGBE_READ_REG(hw, IXGBE_ANLP2);
732 regs_buff[1070] = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);
733
734 /* Diagnostic */
735 regs_buff[1071] = IXGBE_READ_REG(hw, IXGBE_RDSTATCTL);
736 for (i = 0; i < 8; i++)
737 regs_buff[1072 + i] = IXGBE_READ_REG(hw, IXGBE_RDSTAT(i));
738 regs_buff[1080] = IXGBE_READ_REG(hw, IXGBE_RDHMPN);
739 for (i = 0; i < 4; i++)
740 regs_buff[1081 + i] = IXGBE_READ_REG(hw, IXGBE_RIC_DW(i));
741 regs_buff[1085] = IXGBE_READ_REG(hw, IXGBE_RDPROBE);
742 regs_buff[1086] = IXGBE_READ_REG(hw, IXGBE_TDSTATCTL);
743 for (i = 0; i < 8; i++)
744 regs_buff[1087 + i] = IXGBE_READ_REG(hw, IXGBE_TDSTAT(i));
745 regs_buff[1095] = IXGBE_READ_REG(hw, IXGBE_TDHMPN);
746 for (i = 0; i < 4; i++)
747 regs_buff[1096 + i] = IXGBE_READ_REG(hw, IXGBE_TIC_DW(i));
748 regs_buff[1100] = IXGBE_READ_REG(hw, IXGBE_TDPROBE);
749 regs_buff[1101] = IXGBE_READ_REG(hw, IXGBE_TXBUFCTRL);
750 regs_buff[1102] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA0);
751 regs_buff[1103] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA1);
752 regs_buff[1104] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA2);
753 regs_buff[1105] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA3);
754 regs_buff[1106] = IXGBE_READ_REG(hw, IXGBE_RXBUFCTRL);
755 regs_buff[1107] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA0);
756 regs_buff[1108] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA1);
757 regs_buff[1109] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA2);
758 regs_buff[1110] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA3);
759 for (i = 0; i < 8; i++)
760 regs_buff[1111 + i] = IXGBE_READ_REG(hw, IXGBE_PCIE_DIAG(i));
761 regs_buff[1119] = IXGBE_READ_REG(hw, IXGBE_RFVAL);
762 regs_buff[1120] = IXGBE_READ_REG(hw, IXGBE_MDFTC1);
763 regs_buff[1121] = IXGBE_READ_REG(hw, IXGBE_MDFTC2);
764 regs_buff[1122] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO1);
765 regs_buff[1123] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO2);
766 regs_buff[1124] = IXGBE_READ_REG(hw, IXGBE_MDFTS);
767 regs_buff[1125] = IXGBE_READ_REG(hw, IXGBE_PCIEECCCTL);
768 regs_buff[1126] = IXGBE_READ_REG(hw, IXGBE_PBTXECC);
769 regs_buff[1127] = IXGBE_READ_REG(hw, IXGBE_PBRXECC);
770 }
771
772 static int ixgbe_get_eeprom_len(struct net_device *netdev)
773 {
774 struct ixgbe_adapter *adapter = netdev_priv(netdev);
775 return adapter->hw.eeprom.word_size * 2;
776 }
777
778 static int ixgbe_get_eeprom(struct net_device *netdev,
779 struct ethtool_eeprom *eeprom, u8 *bytes)
780 {
781 struct ixgbe_adapter *adapter = netdev_priv(netdev);
782 struct ixgbe_hw *hw = &adapter->hw;
783 u16 *eeprom_buff;
784 int first_word, last_word, eeprom_len;
785 int ret_val = 0;
786 u16 i;
787
788 if (eeprom->len == 0)
789 return -EINVAL;
790
791 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
792
793 first_word = eeprom->offset >> 1;
794 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
795 eeprom_len = last_word - first_word + 1;
796
797 eeprom_buff = kmalloc(sizeof(u16) * eeprom_len, GFP_KERNEL);
798 if (!eeprom_buff)
799 return -ENOMEM;
800
801 for (i = 0; i < eeprom_len; i++) {
802 if ((ret_val = hw->eeprom.ops.read(hw, first_word + i,
803 &eeprom_buff[i])))
804 break;
805 }
806
807 /* Device's eeprom is always little-endian, word addressable */
808 for (i = 0; i < eeprom_len; i++)
809 le16_to_cpus(&eeprom_buff[i]);
810
811 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1), eeprom->len);
812 kfree(eeprom_buff);
813
814 return ret_val;
815 }
816
817 static void ixgbe_get_drvinfo(struct net_device *netdev,
818 struct ethtool_drvinfo *drvinfo)
819 {
820 struct ixgbe_adapter *adapter = netdev_priv(netdev);
821 char firmware_version[32];
822
823 strncpy(drvinfo->driver, ixgbe_driver_name, 32);
824 strncpy(drvinfo->version, ixgbe_driver_version, 32);
825
826 sprintf(firmware_version, "%d.%d-%d",
827 (adapter->eeprom_version & 0xF000) >> 12,
828 (adapter->eeprom_version & 0x0FF0) >> 4,
829 adapter->eeprom_version & 0x000F);
830
831 strncpy(drvinfo->fw_version, firmware_version, 32);
832 strncpy(drvinfo->bus_info, pci_name(adapter->pdev), 32);
833 drvinfo->n_stats = IXGBE_STATS_LEN;
834 drvinfo->testinfo_len = IXGBE_TEST_LEN;
835 drvinfo->regdump_len = ixgbe_get_regs_len(netdev);
836 }
837
838 static void ixgbe_get_ringparam(struct net_device *netdev,
839 struct ethtool_ringparam *ring)
840 {
841 struct ixgbe_adapter *adapter = netdev_priv(netdev);
842 struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
843 struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
844
845 ring->rx_max_pending = IXGBE_MAX_RXD;
846 ring->tx_max_pending = IXGBE_MAX_TXD;
847 ring->rx_mini_max_pending = 0;
848 ring->rx_jumbo_max_pending = 0;
849 ring->rx_pending = rx_ring->count;
850 ring->tx_pending = tx_ring->count;
851 ring->rx_mini_pending = 0;
852 ring->rx_jumbo_pending = 0;
853 }
854
855 static int ixgbe_set_ringparam(struct net_device *netdev,
856 struct ethtool_ringparam *ring)
857 {
858 struct ixgbe_adapter *adapter = netdev_priv(netdev);
859 struct ixgbe_ring *temp_tx_ring, *temp_rx_ring;
860 int i, err = 0;
861 u32 new_rx_count, new_tx_count;
862 bool need_update = false;
863
864 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
865 return -EINVAL;
866
867 new_rx_count = max(ring->rx_pending, (u32)IXGBE_MIN_RXD);
868 new_rx_count = min(new_rx_count, (u32)IXGBE_MAX_RXD);
869 new_rx_count = ALIGN(new_rx_count, IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE);
870
871 new_tx_count = max(ring->tx_pending, (u32)IXGBE_MIN_TXD);
872 new_tx_count = min(new_tx_count, (u32)IXGBE_MAX_TXD);
873 new_tx_count = ALIGN(new_tx_count, IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE);
874
875 if ((new_tx_count == adapter->tx_ring[0]->count) &&
876 (new_rx_count == adapter->rx_ring[0]->count)) {
877 /* nothing to do */
878 return 0;
879 }
880
881 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
882 msleep(1);
883
884 if (!netif_running(adapter->netdev)) {
885 for (i = 0; i < adapter->num_tx_queues; i++)
886 adapter->tx_ring[i]->count = new_tx_count;
887 for (i = 0; i < adapter->num_rx_queues; i++)
888 adapter->rx_ring[i]->count = new_rx_count;
889 adapter->tx_ring_count = new_tx_count;
890 adapter->rx_ring_count = new_rx_count;
891 goto clear_reset;
892 }
893
894 temp_tx_ring = vmalloc(adapter->num_tx_queues * sizeof(struct ixgbe_ring));
895 if (!temp_tx_ring) {
896 err = -ENOMEM;
897 goto clear_reset;
898 }
899
900 if (new_tx_count != adapter->tx_ring_count) {
901 for (i = 0; i < adapter->num_tx_queues; i++) {
902 memcpy(&temp_tx_ring[i], adapter->tx_ring[i],
903 sizeof(struct ixgbe_ring));
904 temp_tx_ring[i].count = new_tx_count;
905 err = ixgbe_setup_tx_resources(adapter,
906 &temp_tx_ring[i]);
907 if (err) {
908 while (i) {
909 i--;
910 ixgbe_free_tx_resources(adapter,
911 &temp_tx_ring[i]);
912 }
913 goto clear_reset;
914 }
915 }
916 need_update = true;
917 }
918
919 temp_rx_ring = vmalloc(adapter->num_rx_queues * sizeof(struct ixgbe_ring));
920 if (!temp_rx_ring) {
921 err = -ENOMEM;
922 goto err_setup;
923 }
924
925 if (new_rx_count != adapter->rx_ring_count) {
926 for (i = 0; i < adapter->num_rx_queues; i++) {
927 memcpy(&temp_rx_ring[i], adapter->rx_ring[i],
928 sizeof(struct ixgbe_ring));
929 temp_rx_ring[i].count = new_rx_count;
930 err = ixgbe_setup_rx_resources(adapter,
931 &temp_rx_ring[i]);
932 if (err) {
933 while (i) {
934 i--;
935 ixgbe_free_rx_resources(adapter,
936 &temp_rx_ring[i]);
937 }
938 goto err_setup;
939 }
940 }
941 need_update = true;
942 }
943
944 /* if rings need to be updated, here's the place to do it in one shot */
945 if (need_update) {
946 ixgbe_down(adapter);
947
948 /* tx */
949 if (new_tx_count != adapter->tx_ring_count) {
950 for (i = 0; i < adapter->num_tx_queues; i++) {
951 ixgbe_free_tx_resources(adapter,
952 adapter->tx_ring[i]);
953 memcpy(adapter->tx_ring[i], &temp_tx_ring[i],
954 sizeof(struct ixgbe_ring));
955 }
956 adapter->tx_ring_count = new_tx_count;
957 }
958
959 /* rx */
960 if (new_rx_count != adapter->rx_ring_count) {
961 for (i = 0; i < adapter->num_rx_queues; i++) {
962 ixgbe_free_rx_resources(adapter,
963 adapter->rx_ring[i]);
964 memcpy(adapter->rx_ring[i], &temp_rx_ring[i],
965 sizeof(struct ixgbe_ring));
966 }
967 adapter->rx_ring_count = new_rx_count;
968 }
969 ixgbe_up(adapter);
970 }
971
972 vfree(temp_rx_ring);
973 err_setup:
974 vfree(temp_tx_ring);
975 clear_reset:
976 clear_bit(__IXGBE_RESETTING, &adapter->state);
977 return err;
978 }
979
980 static int ixgbe_get_sset_count(struct net_device *netdev, int sset)
981 {
982 switch (sset) {
983 case ETH_SS_TEST:
984 return IXGBE_TEST_LEN;
985 case ETH_SS_STATS:
986 return IXGBE_STATS_LEN;
987 case ETH_SS_NTUPLE_FILTERS:
988 return (ETHTOOL_MAX_NTUPLE_LIST_ENTRY *
989 ETHTOOL_MAX_NTUPLE_STRING_PER_ENTRY);
990 default:
991 return -EOPNOTSUPP;
992 }
993 }
994
995 static void ixgbe_get_ethtool_stats(struct net_device *netdev,
996 struct ethtool_stats *stats, u64 *data)
997 {
998 struct ixgbe_adapter *adapter = netdev_priv(netdev);
999 u64 *queue_stat;
1000 int stat_count = sizeof(struct ixgbe_queue_stats) / sizeof(u64);
1001 struct rtnl_link_stats64 temp;
1002 const struct rtnl_link_stats64 *net_stats;
1003 int j, k;
1004 int i;
1005 char *p = NULL;
1006
1007 ixgbe_update_stats(adapter);
1008 net_stats = dev_get_stats(netdev, &temp);
1009 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) {
1010 switch (ixgbe_gstrings_stats[i].type) {
1011 case NETDEV_STATS:
1012 p = (char *) net_stats +
1013 ixgbe_gstrings_stats[i].stat_offset;
1014 break;
1015 case IXGBE_STATS:
1016 p = (char *) adapter +
1017 ixgbe_gstrings_stats[i].stat_offset;
1018 break;
1019 }
1020
1021 data[i] = (ixgbe_gstrings_stats[i].sizeof_stat ==
1022 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
1023 }
1024 for (j = 0; j < adapter->num_tx_queues; j++) {
1025 queue_stat = (u64 *)&adapter->tx_ring[j]->stats;
1026 for (k = 0; k < stat_count; k++)
1027 data[i + k] = queue_stat[k];
1028 i += k;
1029 }
1030 for (j = 0; j < adapter->num_rx_queues; j++) {
1031 queue_stat = (u64 *)&adapter->rx_ring[j]->stats;
1032 for (k = 0; k < stat_count; k++)
1033 data[i + k] = queue_stat[k];
1034 i += k;
1035 }
1036 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
1037 for (j = 0; j < MAX_TX_PACKET_BUFFERS; j++) {
1038 data[i++] = adapter->stats.pxontxc[j];
1039 data[i++] = adapter->stats.pxofftxc[j];
1040 }
1041 for (j = 0; j < MAX_RX_PACKET_BUFFERS; j++) {
1042 data[i++] = adapter->stats.pxonrxc[j];
1043 data[i++] = adapter->stats.pxoffrxc[j];
1044 }
1045 }
1046 }
1047
1048 static void ixgbe_get_strings(struct net_device *netdev, u32 stringset,
1049 u8 *data)
1050 {
1051 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1052 char *p = (char *)data;
1053 int i;
1054
1055 switch (stringset) {
1056 case ETH_SS_TEST:
1057 memcpy(data, *ixgbe_gstrings_test,
1058 IXGBE_TEST_LEN * ETH_GSTRING_LEN);
1059 break;
1060 case ETH_SS_STATS:
1061 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) {
1062 memcpy(p, ixgbe_gstrings_stats[i].stat_string,
1063 ETH_GSTRING_LEN);
1064 p += ETH_GSTRING_LEN;
1065 }
1066 for (i = 0; i < adapter->num_tx_queues; i++) {
1067 sprintf(p, "tx_queue_%u_packets", i);
1068 p += ETH_GSTRING_LEN;
1069 sprintf(p, "tx_queue_%u_bytes", i);
1070 p += ETH_GSTRING_LEN;
1071 }
1072 for (i = 0; i < adapter->num_rx_queues; i++) {
1073 sprintf(p, "rx_queue_%u_packets", i);
1074 p += ETH_GSTRING_LEN;
1075 sprintf(p, "rx_queue_%u_bytes", i);
1076 p += ETH_GSTRING_LEN;
1077 }
1078 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
1079 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
1080 sprintf(p, "tx_pb_%u_pxon", i);
1081 p += ETH_GSTRING_LEN;
1082 sprintf(p, "tx_pb_%u_pxoff", i);
1083 p += ETH_GSTRING_LEN;
1084 }
1085 for (i = 0; i < MAX_RX_PACKET_BUFFERS; i++) {
1086 sprintf(p, "rx_pb_%u_pxon", i);
1087 p += ETH_GSTRING_LEN;
1088 sprintf(p, "rx_pb_%u_pxoff", i);
1089 p += ETH_GSTRING_LEN;
1090 }
1091 }
1092 /* BUG_ON(p - data != IXGBE_STATS_LEN * ETH_GSTRING_LEN); */
1093 break;
1094 }
1095 }
1096
1097 static int ixgbe_link_test(struct ixgbe_adapter *adapter, u64 *data)
1098 {
1099 struct ixgbe_hw *hw = &adapter->hw;
1100 bool link_up;
1101 u32 link_speed = 0;
1102 *data = 0;
1103
1104 hw->mac.ops.check_link(hw, &link_speed, &link_up, true);
1105 if (link_up)
1106 return *data;
1107 else
1108 *data = 1;
1109 return *data;
1110 }
1111
1112 /* ethtool register test data */
1113 struct ixgbe_reg_test {
1114 u16 reg;
1115 u8 array_len;
1116 u8 test_type;
1117 u32 mask;
1118 u32 write;
1119 };
1120
1121 /* In the hardware, registers are laid out either singly, in arrays
1122 * spaced 0x40 bytes apart, or in contiguous tables. We assume
1123 * most tests take place on arrays or single registers (handled
1124 * as a single-element array) and special-case the tables.
1125 * Table tests are always pattern tests.
1126 *
1127 * We also make provision for some required setup steps by specifying
1128 * registers to be written without any read-back testing.
1129 */
1130
1131 #define PATTERN_TEST 1
1132 #define SET_READ_TEST 2
1133 #define WRITE_NO_TEST 3
1134 #define TABLE32_TEST 4
1135 #define TABLE64_TEST_LO 5
1136 #define TABLE64_TEST_HI 6
1137
1138 /* default 82599 register test */
1139 static struct ixgbe_reg_test reg_test_82599[] = {
1140 { IXGBE_FCRTL_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1141 { IXGBE_FCRTH_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1142 { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1143 { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 },
1144 { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFF80 },
1145 { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1146 { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1147 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE },
1148 { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1149 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 },
1150 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1151 { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1152 { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1153 { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1154 { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFF80 },
1155 { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000001, 0x00000001 },
1156 { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1157 { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x8001FFFF, 0x800CFFFF },
1158 { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1159 { 0, 0, 0, 0 }
1160 };
1161
1162 /* default 82598 register test */
1163 static struct ixgbe_reg_test reg_test_82598[] = {
1164 { IXGBE_FCRTL(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1165 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1166 { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1167 { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 },
1168 { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1169 { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1170 { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1171 /* Enable all four RX queues before testing. */
1172 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE },
1173 /* RDH is read-only for 82598, only test RDT. */
1174 { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1175 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 },
1176 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1177 { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1178 { IXGBE_TIPG, 1, PATTERN_TEST, 0x000000FF, 0x000000FF },
1179 { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1180 { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1181 { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1182 { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000003, 0x00000003 },
1183 { IXGBE_DTXCTL, 1, SET_READ_TEST, 0x00000005, 0x00000005 },
1184 { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1185 { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x800CFFFF, 0x800CFFFF },
1186 { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1187 { 0, 0, 0, 0 }
1188 };
1189
1190 #define REG_PATTERN_TEST(R, M, W) \
1191 { \
1192 u32 pat, val, before; \
1193 const u32 _test[] = {0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF}; \
1194 for (pat = 0; pat < ARRAY_SIZE(_test); pat++) { \
1195 before = readl(adapter->hw.hw_addr + R); \
1196 writel((_test[pat] & W), (adapter->hw.hw_addr + R)); \
1197 val = readl(adapter->hw.hw_addr + R); \
1198 if (val != (_test[pat] & W & M)) { \
1199 e_err(drv, "pattern test reg %04X failed: got " \
1200 "0x%08X expected 0x%08X\n", \
1201 R, val, (_test[pat] & W & M)); \
1202 *data = R; \
1203 writel(before, adapter->hw.hw_addr + R); \
1204 return 1; \
1205 } \
1206 writel(before, adapter->hw.hw_addr + R); \
1207 } \
1208 }
1209
1210 #define REG_SET_AND_CHECK(R, M, W) \
1211 { \
1212 u32 val, before; \
1213 before = readl(adapter->hw.hw_addr + R); \
1214 writel((W & M), (adapter->hw.hw_addr + R)); \
1215 val = readl(adapter->hw.hw_addr + R); \
1216 if ((W & M) != (val & M)) { \
1217 e_err(drv, "set/check reg %04X test failed: got 0x%08X " \
1218 "expected 0x%08X\n", R, (val & M), (W & M)); \
1219 *data = R; \
1220 writel(before, (adapter->hw.hw_addr + R)); \
1221 return 1; \
1222 } \
1223 writel(before, (adapter->hw.hw_addr + R)); \
1224 }
1225
1226 static int ixgbe_reg_test(struct ixgbe_adapter *adapter, u64 *data)
1227 {
1228 struct ixgbe_reg_test *test;
1229 u32 value, before, after;
1230 u32 i, toggle;
1231
1232 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1233 toggle = 0x7FFFF30F;
1234 test = reg_test_82599;
1235 } else {
1236 toggle = 0x7FFFF3FF;
1237 test = reg_test_82598;
1238 }
1239
1240 /*
1241 * Because the status register is such a special case,
1242 * we handle it separately from the rest of the register
1243 * tests. Some bits are read-only, some toggle, and some
1244 * are writeable on newer MACs.
1245 */
1246 before = IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS);
1247 value = (IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS) & toggle);
1248 IXGBE_WRITE_REG(&adapter->hw, IXGBE_STATUS, toggle);
1249 after = IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS) & toggle;
1250 if (value != after) {
1251 e_err(drv, "failed STATUS register test got: 0x%08X "
1252 "expected: 0x%08X\n", after, value);
1253 *data = 1;
1254 return 1;
1255 }
1256 /* restore previous status */
1257 IXGBE_WRITE_REG(&adapter->hw, IXGBE_STATUS, before);
1258
1259 /*
1260 * Perform the remainder of the register test, looping through
1261 * the test table until we either fail or reach the null entry.
1262 */
1263 while (test->reg) {
1264 for (i = 0; i < test->array_len; i++) {
1265 switch (test->test_type) {
1266 case PATTERN_TEST:
1267 REG_PATTERN_TEST(test->reg + (i * 0x40),
1268 test->mask,
1269 test->write);
1270 break;
1271 case SET_READ_TEST:
1272 REG_SET_AND_CHECK(test->reg + (i * 0x40),
1273 test->mask,
1274 test->write);
1275 break;
1276 case WRITE_NO_TEST:
1277 writel(test->write,
1278 (adapter->hw.hw_addr + test->reg)
1279 + (i * 0x40));
1280 break;
1281 case TABLE32_TEST:
1282 REG_PATTERN_TEST(test->reg + (i * 4),
1283 test->mask,
1284 test->write);
1285 break;
1286 case TABLE64_TEST_LO:
1287 REG_PATTERN_TEST(test->reg + (i * 8),
1288 test->mask,
1289 test->write);
1290 break;
1291 case TABLE64_TEST_HI:
1292 REG_PATTERN_TEST((test->reg + 4) + (i * 8),
1293 test->mask,
1294 test->write);
1295 break;
1296 }
1297 }
1298 test++;
1299 }
1300
1301 *data = 0;
1302 return 0;
1303 }
1304
1305 static int ixgbe_eeprom_test(struct ixgbe_adapter *adapter, u64 *data)
1306 {
1307 struct ixgbe_hw *hw = &adapter->hw;
1308 if (hw->eeprom.ops.validate_checksum(hw, NULL))
1309 *data = 1;
1310 else
1311 *data = 0;
1312 return *data;
1313 }
1314
1315 static irqreturn_t ixgbe_test_intr(int irq, void *data)
1316 {
1317 struct net_device *netdev = (struct net_device *) data;
1318 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1319
1320 adapter->test_icr |= IXGBE_READ_REG(&adapter->hw, IXGBE_EICR);
1321
1322 return IRQ_HANDLED;
1323 }
1324
1325 static int ixgbe_intr_test(struct ixgbe_adapter *adapter, u64 *data)
1326 {
1327 struct net_device *netdev = adapter->netdev;
1328 u32 mask, i = 0, shared_int = true;
1329 u32 irq = adapter->pdev->irq;
1330
1331 *data = 0;
1332
1333 /* Hook up test interrupt handler just for this test */
1334 if (adapter->msix_entries) {
1335 /* NOTE: we don't test MSI-X interrupts here, yet */
1336 return 0;
1337 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1338 shared_int = false;
1339 if (request_irq(irq, ixgbe_test_intr, 0, netdev->name,
1340 netdev)) {
1341 *data = 1;
1342 return -1;
1343 }
1344 } else if (!request_irq(irq, ixgbe_test_intr, IRQF_PROBE_SHARED,
1345 netdev->name, netdev)) {
1346 shared_int = false;
1347 } else if (request_irq(irq, ixgbe_test_intr, IRQF_SHARED,
1348 netdev->name, netdev)) {
1349 *data = 1;
1350 return -1;
1351 }
1352 e_info(hw, "testing %s interrupt\n", shared_int ?
1353 "shared" : "unshared");
1354
1355 /* Disable all the interrupts */
1356 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
1357 msleep(10);
1358
1359 /* Test each interrupt */
1360 for (; i < 10; i++) {
1361 /* Interrupt to test */
1362 mask = 1 << i;
1363
1364 if (!shared_int) {
1365 /*
1366 * Disable the interrupts to be reported in
1367 * the cause register and then force the same
1368 * interrupt and see if one gets posted. If
1369 * an interrupt was posted to the bus, the
1370 * test failed.
1371 */
1372 adapter->test_icr = 0;
1373 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,
1374 ~mask & 0x00007FFF);
1375 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
1376 ~mask & 0x00007FFF);
1377 msleep(10);
1378
1379 if (adapter->test_icr & mask) {
1380 *data = 3;
1381 break;
1382 }
1383 }
1384
1385 /*
1386 * Enable the interrupt to be reported in the cause
1387 * register and then force the same interrupt and see
1388 * if one gets posted. If an interrupt was not posted
1389 * to the bus, the test failed.
1390 */
1391 adapter->test_icr = 0;
1392 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1393 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
1394 msleep(10);
1395
1396 if (!(adapter->test_icr &mask)) {
1397 *data = 4;
1398 break;
1399 }
1400
1401 if (!shared_int) {
1402 /*
1403 * Disable the other interrupts to be reported in
1404 * the cause register and then force the other
1405 * interrupts and see if any get posted. If
1406 * an interrupt was posted to the bus, the
1407 * test failed.
1408 */
1409 adapter->test_icr = 0;
1410 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,
1411 ~mask & 0x00007FFF);
1412 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
1413 ~mask & 0x00007FFF);
1414 msleep(10);
1415
1416 if (adapter->test_icr) {
1417 *data = 5;
1418 break;
1419 }
1420 }
1421 }
1422
1423 /* Disable all the interrupts */
1424 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
1425 msleep(10);
1426
1427 /* Unhook test interrupt handler */
1428 free_irq(irq, netdev);
1429
1430 return *data;
1431 }
1432
1433 static void ixgbe_free_desc_rings(struct ixgbe_adapter *adapter)
1434 {
1435 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1436 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
1437 struct ixgbe_hw *hw = &adapter->hw;
1438 struct pci_dev *pdev = adapter->pdev;
1439 u32 reg_ctl;
1440 int i;
1441
1442 /* shut down the DMA engines now so they can be reinitialized later */
1443
1444 /* first Rx */
1445 reg_ctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1446 reg_ctl &= ~IXGBE_RXCTRL_RXEN;
1447 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg_ctl);
1448 reg_ctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(0));
1449 reg_ctl &= ~IXGBE_RXDCTL_ENABLE;
1450 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(0), reg_ctl);
1451
1452 /* now Tx */
1453 reg_ctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(0));
1454 reg_ctl &= ~IXGBE_TXDCTL_ENABLE;
1455 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(0), reg_ctl);
1456 if (hw->mac.type == ixgbe_mac_82599EB) {
1457 reg_ctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1458 reg_ctl &= ~IXGBE_DMATXCTL_TE;
1459 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg_ctl);
1460 }
1461
1462 ixgbe_reset(adapter);
1463
1464 if (tx_ring->desc && tx_ring->tx_buffer_info) {
1465 for (i = 0; i < tx_ring->count; i++) {
1466 struct ixgbe_tx_buffer *buf =
1467 &(tx_ring->tx_buffer_info[i]);
1468 if (buf->dma)
1469 dma_unmap_single(&pdev->dev, buf->dma,
1470 buf->length, DMA_TO_DEVICE);
1471 if (buf->skb)
1472 dev_kfree_skb(buf->skb);
1473 }
1474 }
1475
1476 if (rx_ring->desc && rx_ring->rx_buffer_info) {
1477 for (i = 0; i < rx_ring->count; i++) {
1478 struct ixgbe_rx_buffer *buf =
1479 &(rx_ring->rx_buffer_info[i]);
1480 if (buf->dma)
1481 dma_unmap_single(&pdev->dev, buf->dma,
1482 IXGBE_RXBUFFER_2048,
1483 DMA_FROM_DEVICE);
1484 if (buf->skb)
1485 dev_kfree_skb(buf->skb);
1486 }
1487 }
1488
1489 if (tx_ring->desc) {
1490 dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc,
1491 tx_ring->dma);
1492 tx_ring->desc = NULL;
1493 }
1494 if (rx_ring->desc) {
1495 dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc,
1496 rx_ring->dma);
1497 rx_ring->desc = NULL;
1498 }
1499
1500 kfree(tx_ring->tx_buffer_info);
1501 tx_ring->tx_buffer_info = NULL;
1502 kfree(rx_ring->rx_buffer_info);
1503 rx_ring->rx_buffer_info = NULL;
1504 }
1505
1506 static int ixgbe_setup_desc_rings(struct ixgbe_adapter *adapter)
1507 {
1508 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1509 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
1510 struct pci_dev *pdev = adapter->pdev;
1511 u32 rctl, reg_data;
1512 int i, ret_val;
1513
1514 /* Setup Tx descriptor ring and Tx buffers */
1515
1516 if (!tx_ring->count)
1517 tx_ring->count = IXGBE_DEFAULT_TXD;
1518
1519 tx_ring->tx_buffer_info = kcalloc(tx_ring->count,
1520 sizeof(struct ixgbe_tx_buffer),
1521 GFP_KERNEL);
1522 if (!(tx_ring->tx_buffer_info)) {
1523 ret_val = 1;
1524 goto err_nomem;
1525 }
1526
1527 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
1528 tx_ring->size = ALIGN(tx_ring->size, 4096);
1529 tx_ring->desc = dma_alloc_coherent(&pdev->dev, tx_ring->size,
1530 &tx_ring->dma, GFP_KERNEL);
1531 if (!(tx_ring->desc)) {
1532 ret_val = 2;
1533 goto err_nomem;
1534 }
1535 tx_ring->next_to_use = tx_ring->next_to_clean = 0;
1536
1537 IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDBAL(0),
1538 ((u64) tx_ring->dma & 0x00000000FFFFFFFF));
1539 IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDBAH(0),
1540 ((u64) tx_ring->dma >> 32));
1541 IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDLEN(0),
1542 tx_ring->count * sizeof(union ixgbe_adv_tx_desc));
1543 IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDH(0), 0);
1544 IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDT(0), 0);
1545
1546 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);
1547 reg_data |= IXGBE_HLREG0_TXPADEN;
1548 IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);
1549
1550 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1551 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_DMATXCTL);
1552 reg_data |= IXGBE_DMATXCTL_TE;
1553 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DMATXCTL, reg_data);
1554 }
1555 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_TXDCTL(0));
1556 reg_data |= IXGBE_TXDCTL_ENABLE;
1557 IXGBE_WRITE_REG(&adapter->hw, IXGBE_TXDCTL(0), reg_data);
1558
1559 for (i = 0; i < tx_ring->count; i++) {
1560 union ixgbe_adv_tx_desc *desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
1561 struct sk_buff *skb;
1562 unsigned int size = 1024;
1563
1564 skb = alloc_skb(size, GFP_KERNEL);
1565 if (!skb) {
1566 ret_val = 3;
1567 goto err_nomem;
1568 }
1569 skb_put(skb, size);
1570 tx_ring->tx_buffer_info[i].skb = skb;
1571 tx_ring->tx_buffer_info[i].length = skb->len;
1572 tx_ring->tx_buffer_info[i].dma =
1573 dma_map_single(&pdev->dev, skb->data, skb->len,
1574 DMA_TO_DEVICE);
1575 desc->read.buffer_addr =
1576 cpu_to_le64(tx_ring->tx_buffer_info[i].dma);
1577 desc->read.cmd_type_len = cpu_to_le32(skb->len);
1578 desc->read.cmd_type_len |= cpu_to_le32(IXGBE_TXD_CMD_EOP |
1579 IXGBE_TXD_CMD_IFCS |
1580 IXGBE_TXD_CMD_RS);
1581 desc->read.olinfo_status = 0;
1582 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
1583 desc->read.olinfo_status |=
1584 (skb->len << IXGBE_ADVTXD_PAYLEN_SHIFT);
1585
1586 }
1587
1588 /* Setup Rx Descriptor ring and Rx buffers */
1589
1590 if (!rx_ring->count)
1591 rx_ring->count = IXGBE_DEFAULT_RXD;
1592
1593 rx_ring->rx_buffer_info = kcalloc(rx_ring->count,
1594 sizeof(struct ixgbe_rx_buffer),
1595 GFP_KERNEL);
1596 if (!(rx_ring->rx_buffer_info)) {
1597 ret_val = 4;
1598 goto err_nomem;
1599 }
1600
1601 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
1602 rx_ring->size = ALIGN(rx_ring->size, 4096);
1603 rx_ring->desc = dma_alloc_coherent(&pdev->dev, rx_ring->size,
1604 &rx_ring->dma, GFP_KERNEL);
1605 if (!(rx_ring->desc)) {
1606 ret_val = 5;
1607 goto err_nomem;
1608 }
1609 rx_ring->next_to_use = rx_ring->next_to_clean = 0;
1610
1611 rctl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXCTRL);
1612 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL, rctl & ~IXGBE_RXCTRL_RXEN);
1613 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDBAL(0),
1614 ((u64)rx_ring->dma & 0xFFFFFFFF));
1615 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDBAH(0),
1616 ((u64) rx_ring->dma >> 32));
1617 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDLEN(0), rx_ring->size);
1618 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDH(0), 0);
1619 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDT(0), 0);
1620
1621 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
1622 reg_data |= IXGBE_FCTRL_BAM | IXGBE_FCTRL_SBP | IXGBE_FCTRL_MPE;
1623 IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, reg_data);
1624
1625 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);
1626 reg_data &= ~IXGBE_HLREG0_LPBK;
1627 IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);
1628
1629 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_RDRXCTL);
1630 #define IXGBE_RDRXCTL_RDMTS_MASK 0x00000003 /* Receive Descriptor Minimum
1631 Threshold Size mask */
1632 reg_data &= ~IXGBE_RDRXCTL_RDMTS_MASK;
1633 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDRXCTL, reg_data);
1634
1635 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_MCSTCTRL);
1636 #define IXGBE_MCSTCTRL_MO_MASK 0x00000003 /* Multicast Offset mask */
1637 reg_data &= ~IXGBE_MCSTCTRL_MO_MASK;
1638 reg_data |= adapter->hw.mac.mc_filter_type;
1639 IXGBE_WRITE_REG(&adapter->hw, IXGBE_MCSTCTRL, reg_data);
1640
1641 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_RXDCTL(0));
1642 reg_data |= IXGBE_RXDCTL_ENABLE;
1643 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXDCTL(0), reg_data);
1644 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1645 int j = adapter->rx_ring[0]->reg_idx;
1646 u32 k;
1647 for (k = 0; k < 10; k++) {
1648 if (IXGBE_READ_REG(&adapter->hw,
1649 IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
1650 break;
1651 else
1652 msleep(1);
1653 }
1654 }
1655
1656 rctl |= IXGBE_RXCTRL_RXEN | IXGBE_RXCTRL_DMBYPS;
1657 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL, rctl);
1658
1659 for (i = 0; i < rx_ring->count; i++) {
1660 union ixgbe_adv_rx_desc *rx_desc =
1661 IXGBE_RX_DESC_ADV(*rx_ring, i);
1662 struct sk_buff *skb;
1663
1664 skb = alloc_skb(IXGBE_RXBUFFER_2048 + NET_IP_ALIGN, GFP_KERNEL);
1665 if (!skb) {
1666 ret_val = 6;
1667 goto err_nomem;
1668 }
1669 skb_reserve(skb, NET_IP_ALIGN);
1670 rx_ring->rx_buffer_info[i].skb = skb;
1671 rx_ring->rx_buffer_info[i].dma =
1672 dma_map_single(&pdev->dev, skb->data,
1673 IXGBE_RXBUFFER_2048, DMA_FROM_DEVICE);
1674 rx_desc->read.pkt_addr =
1675 cpu_to_le64(rx_ring->rx_buffer_info[i].dma);
1676 memset(skb->data, 0x00, skb->len);
1677 }
1678
1679 return 0;
1680
1681 err_nomem:
1682 ixgbe_free_desc_rings(adapter);
1683 return ret_val;
1684 }
1685
1686 static int ixgbe_setup_loopback_test(struct ixgbe_adapter *adapter)
1687 {
1688 struct ixgbe_hw *hw = &adapter->hw;
1689 u32 reg_data;
1690
1691 /* right now we only support MAC loopback in the driver */
1692
1693 /* Setup MAC loopback */
1694 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);
1695 reg_data |= IXGBE_HLREG0_LPBK;
1696 IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);
1697
1698 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_AUTOC);
1699 reg_data &= ~IXGBE_AUTOC_LMS_MASK;
1700 reg_data |= IXGBE_AUTOC_LMS_10G_LINK_NO_AN | IXGBE_AUTOC_FLU;
1701 IXGBE_WRITE_REG(&adapter->hw, IXGBE_AUTOC, reg_data);
1702
1703 /* Disable Atlas Tx lanes; re-enabled in reset path */
1704 if (hw->mac.type == ixgbe_mac_82598EB) {
1705 u8 atlas;
1706
1707 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &atlas);
1708 atlas |= IXGBE_ATLAS_PDN_TX_REG_EN;
1709 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, atlas);
1710
1711 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, &atlas);
1712 atlas |= IXGBE_ATLAS_PDN_TX_10G_QL_ALL;
1713 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, atlas);
1714
1715 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, &atlas);
1716 atlas |= IXGBE_ATLAS_PDN_TX_1G_QL_ALL;
1717 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, atlas);
1718
1719 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, &atlas);
1720 atlas |= IXGBE_ATLAS_PDN_TX_AN_QL_ALL;
1721 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, atlas);
1722 }
1723
1724 return 0;
1725 }
1726
1727 static void ixgbe_loopback_cleanup(struct ixgbe_adapter *adapter)
1728 {
1729 u32 reg_data;
1730
1731 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);
1732 reg_data &= ~IXGBE_HLREG0_LPBK;
1733 IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);
1734 }
1735
1736 static void ixgbe_create_lbtest_frame(struct sk_buff *skb,
1737 unsigned int frame_size)
1738 {
1739 memset(skb->data, 0xFF, frame_size);
1740 frame_size &= ~1;
1741 memset(&skb->data[frame_size / 2], 0xAA, frame_size / 2 - 1);
1742 memset(&skb->data[frame_size / 2 + 10], 0xBE, 1);
1743 memset(&skb->data[frame_size / 2 + 12], 0xAF, 1);
1744 }
1745
1746 static int ixgbe_check_lbtest_frame(struct sk_buff *skb,
1747 unsigned int frame_size)
1748 {
1749 frame_size &= ~1;
1750 if (*(skb->data + 3) == 0xFF) {
1751 if ((*(skb->data + frame_size / 2 + 10) == 0xBE) &&
1752 (*(skb->data + frame_size / 2 + 12) == 0xAF)) {
1753 return 0;
1754 }
1755 }
1756 return 13;
1757 }
1758
1759 static int ixgbe_run_loopback_test(struct ixgbe_adapter *adapter)
1760 {
1761 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1762 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
1763 struct pci_dev *pdev = adapter->pdev;
1764 int i, j, k, l, lc, good_cnt, ret_val = 0;
1765 unsigned long time;
1766
1767 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDT(0), rx_ring->count - 1);
1768
1769 /*
1770 * Calculate the loop count based on the largest descriptor ring
1771 * The idea is to wrap the largest ring a number of times using 64
1772 * send/receive pairs during each loop
1773 */
1774
1775 if (rx_ring->count <= tx_ring->count)
1776 lc = ((tx_ring->count / 64) * 2) + 1;
1777 else
1778 lc = ((rx_ring->count / 64) * 2) + 1;
1779
1780 k = l = 0;
1781 for (j = 0; j <= lc; j++) {
1782 for (i = 0; i < 64; i++) {
1783 ixgbe_create_lbtest_frame(
1784 tx_ring->tx_buffer_info[k].skb,
1785 1024);
1786 dma_sync_single_for_device(&pdev->dev,
1787 tx_ring->tx_buffer_info[k].dma,
1788 tx_ring->tx_buffer_info[k].length,
1789 DMA_TO_DEVICE);
1790 if (unlikely(++k == tx_ring->count))
1791 k = 0;
1792 }
1793 IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDT(0), k);
1794 msleep(200);
1795 /* set the start time for the receive */
1796 time = jiffies;
1797 good_cnt = 0;
1798 do {
1799 /* receive the sent packets */
1800 dma_sync_single_for_cpu(&pdev->dev,
1801 rx_ring->rx_buffer_info[l].dma,
1802 IXGBE_RXBUFFER_2048,
1803 DMA_FROM_DEVICE);
1804 ret_val = ixgbe_check_lbtest_frame(
1805 rx_ring->rx_buffer_info[l].skb, 1024);
1806 if (!ret_val)
1807 good_cnt++;
1808 if (++l == rx_ring->count)
1809 l = 0;
1810 /*
1811 * time + 20 msecs (200 msecs on 2.4) is more than
1812 * enough time to complete the receives, if it's
1813 * exceeded, break and error off
1814 */
1815 } while (good_cnt < 64 && jiffies < (time + 20));
1816 if (good_cnt != 64) {
1817 /* ret_val is the same as mis-compare */
1818 ret_val = 13;
1819 break;
1820 }
1821 if (jiffies >= (time + 20)) {
1822 /* Error code for time out error */
1823 ret_val = 14;
1824 break;
1825 }
1826 }
1827
1828 return ret_val;
1829 }
1830
1831 static int ixgbe_loopback_test(struct ixgbe_adapter *adapter, u64 *data)
1832 {
1833 *data = ixgbe_setup_desc_rings(adapter);
1834 if (*data)
1835 goto out;
1836 *data = ixgbe_setup_loopback_test(adapter);
1837 if (*data)
1838 goto err_loopback;
1839 *data = ixgbe_run_loopback_test(adapter);
1840 ixgbe_loopback_cleanup(adapter);
1841
1842 err_loopback:
1843 ixgbe_free_desc_rings(adapter);
1844 out:
1845 return *data;
1846 }
1847
1848 static void ixgbe_diag_test(struct net_device *netdev,
1849 struct ethtool_test *eth_test, u64 *data)
1850 {
1851 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1852 bool if_running = netif_running(netdev);
1853
1854 set_bit(__IXGBE_TESTING, &adapter->state);
1855 if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
1856 /* Offline tests */
1857
1858 e_info(hw, "offline testing starting\n");
1859
1860 /* Link test performed before hardware reset so autoneg doesn't
1861 * interfere with test result */
1862 if (ixgbe_link_test(adapter, &data[4]))
1863 eth_test->flags |= ETH_TEST_FL_FAILED;
1864
1865 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
1866 int i;
1867 for (i = 0; i < adapter->num_vfs; i++) {
1868 if (adapter->vfinfo[i].clear_to_send) {
1869 netdev_warn(netdev, "%s",
1870 "offline diagnostic is not "
1871 "supported when VFs are "
1872 "present\n");
1873 data[0] = 1;
1874 data[1] = 1;
1875 data[2] = 1;
1876 data[3] = 1;
1877 eth_test->flags |= ETH_TEST_FL_FAILED;
1878 clear_bit(__IXGBE_TESTING,
1879 &adapter->state);
1880 goto skip_ol_tests;
1881 }
1882 }
1883 }
1884
1885 if (if_running)
1886 /* indicate we're in test mode */
1887 dev_close(netdev);
1888 else
1889 ixgbe_reset(adapter);
1890
1891 e_info(hw, "register testing starting\n");
1892 if (ixgbe_reg_test(adapter, &data[0]))
1893 eth_test->flags |= ETH_TEST_FL_FAILED;
1894
1895 ixgbe_reset(adapter);
1896 e_info(hw, "eeprom testing starting\n");
1897 if (ixgbe_eeprom_test(adapter, &data[1]))
1898 eth_test->flags |= ETH_TEST_FL_FAILED;
1899
1900 ixgbe_reset(adapter);
1901 e_info(hw, "interrupt testing starting\n");
1902 if (ixgbe_intr_test(adapter, &data[2]))
1903 eth_test->flags |= ETH_TEST_FL_FAILED;
1904
1905 /* If SRIOV or VMDq is enabled then skip MAC
1906 * loopback diagnostic. */
1907 if (adapter->flags & (IXGBE_FLAG_SRIOV_ENABLED |
1908 IXGBE_FLAG_VMDQ_ENABLED)) {
1909 e_info(hw, "Skip MAC loopback diagnostic in VT "
1910 "mode\n");
1911 data[3] = 0;
1912 goto skip_loopback;
1913 }
1914
1915 ixgbe_reset(adapter);
1916 e_info(hw, "loopback testing starting\n");
1917 if (ixgbe_loopback_test(adapter, &data[3]))
1918 eth_test->flags |= ETH_TEST_FL_FAILED;
1919
1920 skip_loopback:
1921 ixgbe_reset(adapter);
1922
1923 clear_bit(__IXGBE_TESTING, &adapter->state);
1924 if (if_running)
1925 dev_open(netdev);
1926 } else {
1927 e_info(hw, "online testing starting\n");
1928 /* Online tests */
1929 if (ixgbe_link_test(adapter, &data[4]))
1930 eth_test->flags |= ETH_TEST_FL_FAILED;
1931
1932 /* Online tests aren't run; pass by default */
1933 data[0] = 0;
1934 data[1] = 0;
1935 data[2] = 0;
1936 data[3] = 0;
1937
1938 clear_bit(__IXGBE_TESTING, &adapter->state);
1939 }
1940 skip_ol_tests:
1941 msleep_interruptible(4 * 1000);
1942 }
1943
1944 static int ixgbe_wol_exclusion(struct ixgbe_adapter *adapter,
1945 struct ethtool_wolinfo *wol)
1946 {
1947 struct ixgbe_hw *hw = &adapter->hw;
1948 int retval = 1;
1949
1950 switch(hw->device_id) {
1951 case IXGBE_DEV_ID_82599_KX4:
1952 retval = 0;
1953 break;
1954 default:
1955 wol->supported = 0;
1956 }
1957
1958 return retval;
1959 }
1960
1961 static void ixgbe_get_wol(struct net_device *netdev,
1962 struct ethtool_wolinfo *wol)
1963 {
1964 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1965
1966 wol->supported = WAKE_UCAST | WAKE_MCAST |
1967 WAKE_BCAST | WAKE_MAGIC;
1968 wol->wolopts = 0;
1969
1970 if (ixgbe_wol_exclusion(adapter, wol) ||
1971 !device_can_wakeup(&adapter->pdev->dev))
1972 return;
1973
1974 if (adapter->wol & IXGBE_WUFC_EX)
1975 wol->wolopts |= WAKE_UCAST;
1976 if (adapter->wol & IXGBE_WUFC_MC)
1977 wol->wolopts |= WAKE_MCAST;
1978 if (adapter->wol & IXGBE_WUFC_BC)
1979 wol->wolopts |= WAKE_BCAST;
1980 if (adapter->wol & IXGBE_WUFC_MAG)
1981 wol->wolopts |= WAKE_MAGIC;
1982 }
1983
1984 static int ixgbe_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1985 {
1986 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1987
1988 if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE))
1989 return -EOPNOTSUPP;
1990
1991 if (ixgbe_wol_exclusion(adapter, wol))
1992 return wol->wolopts ? -EOPNOTSUPP : 0;
1993
1994 adapter->wol = 0;
1995
1996 if (wol->wolopts & WAKE_UCAST)
1997 adapter->wol |= IXGBE_WUFC_EX;
1998 if (wol->wolopts & WAKE_MCAST)
1999 adapter->wol |= IXGBE_WUFC_MC;
2000 if (wol->wolopts & WAKE_BCAST)
2001 adapter->wol |= IXGBE_WUFC_BC;
2002 if (wol->wolopts & WAKE_MAGIC)
2003 adapter->wol |= IXGBE_WUFC_MAG;
2004
2005 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
2006
2007 return 0;
2008 }
2009
2010 static int ixgbe_nway_reset(struct net_device *netdev)
2011 {
2012 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2013
2014 if (netif_running(netdev))
2015 ixgbe_reinit_locked(adapter);
2016
2017 return 0;
2018 }
2019
2020 static int ixgbe_phys_id(struct net_device *netdev, u32 data)
2021 {
2022 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2023 struct ixgbe_hw *hw = &adapter->hw;
2024 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
2025 u32 i;
2026
2027 if (!data || data > 300)
2028 data = 300;
2029
2030 for (i = 0; i < (data * 1000); i += 400) {
2031 hw->mac.ops.led_on(hw, IXGBE_LED_ON);
2032 msleep_interruptible(200);
2033 hw->mac.ops.led_off(hw, IXGBE_LED_ON);
2034 msleep_interruptible(200);
2035 }
2036
2037 /* Restore LED settings */
2038 IXGBE_WRITE_REG(&adapter->hw, IXGBE_LEDCTL, led_reg);
2039
2040 return 0;
2041 }
2042
2043 static int ixgbe_get_coalesce(struct net_device *netdev,
2044 struct ethtool_coalesce *ec)
2045 {
2046 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2047
2048 ec->tx_max_coalesced_frames_irq = adapter->tx_ring[0]->work_limit;
2049
2050 /* only valid if in constant ITR mode */
2051 switch (adapter->rx_itr_setting) {
2052 case 0:
2053 /* throttling disabled */
2054 ec->rx_coalesce_usecs = 0;
2055 break;
2056 case 1:
2057 /* dynamic ITR mode */
2058 ec->rx_coalesce_usecs = 1;
2059 break;
2060 default:
2061 /* fixed interrupt rate mode */
2062 ec->rx_coalesce_usecs = 1000000/adapter->rx_eitr_param;
2063 break;
2064 }
2065
2066 /* if in mixed tx/rx queues per vector mode, report only rx settings */
2067 if (adapter->q_vector[0]->txr_count && adapter->q_vector[0]->rxr_count)
2068 return 0;
2069
2070 /* only valid if in constant ITR mode */
2071 switch (adapter->tx_itr_setting) {
2072 case 0:
2073 /* throttling disabled */
2074 ec->tx_coalesce_usecs = 0;
2075 break;
2076 case 1:
2077 /* dynamic ITR mode */
2078 ec->tx_coalesce_usecs = 1;
2079 break;
2080 default:
2081 ec->tx_coalesce_usecs = 1000000/adapter->tx_eitr_param;
2082 break;
2083 }
2084
2085 return 0;
2086 }
2087
2088 static int ixgbe_set_coalesce(struct net_device *netdev,
2089 struct ethtool_coalesce *ec)
2090 {
2091 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2092 struct ixgbe_q_vector *q_vector;
2093 int i;
2094 bool need_reset = false;
2095
2096 /* don't accept tx specific changes if we've got mixed RxTx vectors */
2097 if (adapter->q_vector[0]->txr_count && adapter->q_vector[0]->rxr_count
2098 && ec->tx_coalesce_usecs)
2099 return -EINVAL;
2100
2101 if (ec->tx_max_coalesced_frames_irq)
2102 adapter->tx_ring[0]->work_limit = ec->tx_max_coalesced_frames_irq;
2103
2104 if (ec->rx_coalesce_usecs > 1) {
2105 u32 max_int;
2106 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
2107 max_int = IXGBE_MAX_RSC_INT_RATE;
2108 else
2109 max_int = IXGBE_MAX_INT_RATE;
2110
2111 /* check the limits */
2112 if ((1000000/ec->rx_coalesce_usecs > max_int) ||
2113 (1000000/ec->rx_coalesce_usecs < IXGBE_MIN_INT_RATE))
2114 return -EINVAL;
2115
2116 /* store the value in ints/second */
2117 adapter->rx_eitr_param = 1000000/ec->rx_coalesce_usecs;
2118
2119 /* static value of interrupt rate */
2120 adapter->rx_itr_setting = adapter->rx_eitr_param;
2121 /* clear the lower bit as its used for dynamic state */
2122 adapter->rx_itr_setting &= ~1;
2123 } else if (ec->rx_coalesce_usecs == 1) {
2124 /* 1 means dynamic mode */
2125 adapter->rx_eitr_param = 20000;
2126 adapter->rx_itr_setting = 1;
2127 } else {
2128 /*
2129 * any other value means disable eitr, which is best
2130 * served by setting the interrupt rate very high
2131 */
2132 adapter->rx_eitr_param = IXGBE_MAX_INT_RATE;
2133 adapter->rx_itr_setting = 0;
2134
2135 /*
2136 * if hardware RSC is enabled, disable it when
2137 * setting low latency mode, to avoid errata, assuming
2138 * that when the user set low latency mode they want
2139 * it at the cost of anything else
2140 */
2141 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
2142 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
2143 if (netdev->features & NETIF_F_LRO) {
2144 netdev->features &= ~NETIF_F_LRO;
2145 e_info(probe, "rx-usecs set to 0, "
2146 "disabling RSC\n");
2147 }
2148 need_reset = true;
2149 }
2150 }
2151
2152 if (ec->tx_coalesce_usecs > 1) {
2153 /*
2154 * don't have to worry about max_int as above because
2155 * tx vectors don't do hardware RSC (an rx function)
2156 */
2157 /* check the limits */
2158 if ((1000000/ec->tx_coalesce_usecs > IXGBE_MAX_INT_RATE) ||
2159 (1000000/ec->tx_coalesce_usecs < IXGBE_MIN_INT_RATE))
2160 return -EINVAL;
2161
2162 /* store the value in ints/second */
2163 adapter->tx_eitr_param = 1000000/ec->tx_coalesce_usecs;
2164
2165 /* static value of interrupt rate */
2166 adapter->tx_itr_setting = adapter->tx_eitr_param;
2167
2168 /* clear the lower bit as its used for dynamic state */
2169 adapter->tx_itr_setting &= ~1;
2170 } else if (ec->tx_coalesce_usecs == 1) {
2171 /* 1 means dynamic mode */
2172 adapter->tx_eitr_param = 10000;
2173 adapter->tx_itr_setting = 1;
2174 } else {
2175 adapter->tx_eitr_param = IXGBE_MAX_INT_RATE;
2176 adapter->tx_itr_setting = 0;
2177 }
2178
2179 /* MSI/MSIx Interrupt Mode */
2180 if (adapter->flags &
2181 (IXGBE_FLAG_MSIX_ENABLED | IXGBE_FLAG_MSI_ENABLED)) {
2182 int num_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2183 for (i = 0; i < num_vectors; i++) {
2184 q_vector = adapter->q_vector[i];
2185 if (q_vector->txr_count && !q_vector->rxr_count)
2186 /* tx only */
2187 q_vector->eitr = adapter->tx_eitr_param;
2188 else
2189 /* rx only or mixed */
2190 q_vector->eitr = adapter->rx_eitr_param;
2191 ixgbe_write_eitr(q_vector);
2192 }
2193 /* Legacy Interrupt Mode */
2194 } else {
2195 q_vector = adapter->q_vector[0];
2196 q_vector->eitr = adapter->rx_eitr_param;
2197 ixgbe_write_eitr(q_vector);
2198 }
2199
2200 /*
2201 * do reset here at the end to make sure EITR==0 case is handled
2202 * correctly w.r.t stopping tx, and changing TXDCTL.WTHRESH settings
2203 * also locks in RSC enable/disable which requires reset
2204 */
2205 if (need_reset) {
2206 if (netif_running(netdev))
2207 ixgbe_reinit_locked(adapter);
2208 else
2209 ixgbe_reset(adapter);
2210 }
2211
2212 return 0;
2213 }
2214
2215 static int ixgbe_set_flags(struct net_device *netdev, u32 data)
2216 {
2217 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2218 bool need_reset = false;
2219 int rc;
2220
2221 rc = ethtool_op_set_flags(netdev, data, ETH_FLAG_LRO | ETH_FLAG_NTUPLE);
2222 if (rc)
2223 return rc;
2224
2225 /* if state changes we need to update adapter->flags and reset */
2226 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) {
2227 /*
2228 * cast both to bool and verify if they are set the same
2229 * but only enable RSC if itr is non-zero, as
2230 * itr=0 and RSC are mutually exclusive
2231 */
2232 if (((!!(data & ETH_FLAG_LRO)) !=
2233 (!!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))) &&
2234 adapter->rx_itr_setting) {
2235 adapter->flags2 ^= IXGBE_FLAG2_RSC_ENABLED;
2236 switch (adapter->hw.mac.type) {
2237 case ixgbe_mac_82599EB:
2238 need_reset = true;
2239 break;
2240 default:
2241 break;
2242 }
2243 } else if (!adapter->rx_itr_setting) {
2244 netdev->features &= ~NETIF_F_LRO;
2245 if (data & ETH_FLAG_LRO)
2246 e_info(probe, "rx-usecs set to 0, "
2247 "LRO/RSC cannot be enabled.\n");
2248 }
2249 }
2250
2251 /*
2252 * Check if Flow Director n-tuple support was enabled or disabled. If
2253 * the state changed, we need to reset.
2254 */
2255 if ((adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) &&
2256 (!(data & ETH_FLAG_NTUPLE))) {
2257 /* turn off Flow Director perfect, set hash and reset */
2258 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
2259 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
2260 need_reset = true;
2261 } else if ((!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) &&
2262 (data & ETH_FLAG_NTUPLE)) {
2263 /* turn off Flow Director hash, enable perfect and reset */
2264 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
2265 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
2266 need_reset = true;
2267 } else {
2268 /* no state change */
2269 }
2270
2271 if (need_reset) {
2272 if (netif_running(netdev))
2273 ixgbe_reinit_locked(adapter);
2274 else
2275 ixgbe_reset(adapter);
2276 }
2277
2278 return 0;
2279 }
2280
2281 static int ixgbe_set_rx_ntuple(struct net_device *dev,
2282 struct ethtool_rx_ntuple *cmd)
2283 {
2284 struct ixgbe_adapter *adapter = netdev_priv(dev);
2285 struct ethtool_rx_ntuple_flow_spec fs = cmd->fs;
2286 struct ixgbe_atr_input input_struct;
2287 struct ixgbe_atr_input_masks input_masks;
2288 int target_queue;
2289
2290 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
2291 return -EOPNOTSUPP;
2292
2293 /*
2294 * Don't allow programming if the action is a queue greater than
2295 * the number of online Tx queues.
2296 */
2297 if ((fs.action >= adapter->num_tx_queues) ||
2298 (fs.action < ETHTOOL_RXNTUPLE_ACTION_DROP))
2299 return -EINVAL;
2300
2301 memset(&input_struct, 0, sizeof(struct ixgbe_atr_input));
2302 memset(&input_masks, 0, sizeof(struct ixgbe_atr_input_masks));
2303
2304 input_masks.src_ip_mask = fs.m_u.tcp_ip4_spec.ip4src;
2305 input_masks.dst_ip_mask = fs.m_u.tcp_ip4_spec.ip4dst;
2306 input_masks.src_port_mask = fs.m_u.tcp_ip4_spec.psrc;
2307 input_masks.dst_port_mask = fs.m_u.tcp_ip4_spec.pdst;
2308 input_masks.vlan_id_mask = fs.vlan_tag_mask;
2309 /* only use the lowest 2 bytes for flex bytes */
2310 input_masks.data_mask = (fs.data_mask & 0xffff);
2311
2312 switch (fs.flow_type) {
2313 case TCP_V4_FLOW:
2314 ixgbe_atr_set_l4type_82599(&input_struct, IXGBE_ATR_L4TYPE_TCP);
2315 break;
2316 case UDP_V4_FLOW:
2317 ixgbe_atr_set_l4type_82599(&input_struct, IXGBE_ATR_L4TYPE_UDP);
2318 break;
2319 case SCTP_V4_FLOW:
2320 ixgbe_atr_set_l4type_82599(&input_struct, IXGBE_ATR_L4TYPE_SCTP);
2321 break;
2322 default:
2323 return -1;
2324 }
2325
2326 /* Mask bits from the inputs based on user-supplied mask */
2327 ixgbe_atr_set_src_ipv4_82599(&input_struct,
2328 (fs.h_u.tcp_ip4_spec.ip4src & ~fs.m_u.tcp_ip4_spec.ip4src));
2329 ixgbe_atr_set_dst_ipv4_82599(&input_struct,
2330 (fs.h_u.tcp_ip4_spec.ip4dst & ~fs.m_u.tcp_ip4_spec.ip4dst));
2331 /* 82599 expects these to be byte-swapped for perfect filtering */
2332 ixgbe_atr_set_src_port_82599(&input_struct,
2333 ((ntohs(fs.h_u.tcp_ip4_spec.psrc)) & ~fs.m_u.tcp_ip4_spec.psrc));
2334 ixgbe_atr_set_dst_port_82599(&input_struct,
2335 ((ntohs(fs.h_u.tcp_ip4_spec.pdst)) & ~fs.m_u.tcp_ip4_spec.pdst));
2336
2337 /* VLAN and Flex bytes are either completely masked or not */
2338 if (!fs.vlan_tag_mask)
2339 ixgbe_atr_set_vlan_id_82599(&input_struct, fs.vlan_tag);
2340
2341 if (!input_masks.data_mask)
2342 /* make sure we only use the first 2 bytes of user data */
2343 ixgbe_atr_set_flex_byte_82599(&input_struct,
2344 (fs.data & 0xffff));
2345
2346 /* determine if we need to drop or route the packet */
2347 if (fs.action == ETHTOOL_RXNTUPLE_ACTION_DROP)
2348 target_queue = MAX_RX_QUEUES - 1;
2349 else
2350 target_queue = fs.action;
2351
2352 spin_lock(&adapter->fdir_perfect_lock);
2353 ixgbe_fdir_add_perfect_filter_82599(&adapter->hw, &input_struct,
2354 &input_masks, 0, target_queue);
2355 spin_unlock(&adapter->fdir_perfect_lock);
2356
2357 return 0;
2358 }
2359
2360 static const struct ethtool_ops ixgbe_ethtool_ops = {
2361 .get_settings = ixgbe_get_settings,
2362 .set_settings = ixgbe_set_settings,
2363 .get_drvinfo = ixgbe_get_drvinfo,
2364 .get_regs_len = ixgbe_get_regs_len,
2365 .get_regs = ixgbe_get_regs,
2366 .get_wol = ixgbe_get_wol,
2367 .set_wol = ixgbe_set_wol,
2368 .nway_reset = ixgbe_nway_reset,
2369 .get_link = ethtool_op_get_link,
2370 .get_eeprom_len = ixgbe_get_eeprom_len,
2371 .get_eeprom = ixgbe_get_eeprom,
2372 .get_ringparam = ixgbe_get_ringparam,
2373 .set_ringparam = ixgbe_set_ringparam,
2374 .get_pauseparam = ixgbe_get_pauseparam,
2375 .set_pauseparam = ixgbe_set_pauseparam,
2376 .get_rx_csum = ixgbe_get_rx_csum,
2377 .set_rx_csum = ixgbe_set_rx_csum,
2378 .get_tx_csum = ixgbe_get_tx_csum,
2379 .set_tx_csum = ixgbe_set_tx_csum,
2380 .get_sg = ethtool_op_get_sg,
2381 .set_sg = ethtool_op_set_sg,
2382 .get_msglevel = ixgbe_get_msglevel,
2383 .set_msglevel = ixgbe_set_msglevel,
2384 .get_tso = ethtool_op_get_tso,
2385 .set_tso = ixgbe_set_tso,
2386 .self_test = ixgbe_diag_test,
2387 .get_strings = ixgbe_get_strings,
2388 .phys_id = ixgbe_phys_id,
2389 .get_sset_count = ixgbe_get_sset_count,
2390 .get_ethtool_stats = ixgbe_get_ethtool_stats,
2391 .get_coalesce = ixgbe_get_coalesce,
2392 .set_coalesce = ixgbe_set_coalesce,
2393 .get_flags = ethtool_op_get_flags,
2394 .set_flags = ixgbe_set_flags,
2395 .set_rx_ntuple = ixgbe_set_rx_ntuple,
2396 };
2397
2398 void ixgbe_set_ethtool_ops(struct net_device *netdev)
2399 {
2400 SET_ETHTOOL_OPS(netdev, &ixgbe_ethtool_ops);
2401 }
Tomato firmware and modifications.